diff options
| author |   RajithaY <rajithax.yerrumsetty@intel.com> | 2017-04-25 03:31:15 -0700 |
|---|---|---|
| committer | Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> | 2017-05-22 06:48:08 +0000 |
| commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
| tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/arm/include | |
| parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) | |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/arm/include')
506 files changed, 0 insertions, 90697 deletions
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-a320/a320.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-a320/a320.h deleted file mode 100644 index f2db8e106..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-a320/a320.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __A320_H -#define __A320_H - -/* - * Hardware register bases - */ -#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ -#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ -#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ -#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ -#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ -#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ -#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ - -#endif /* __A320_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h deleted file mode 100644 index 763745754..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * clock.h - * - * clock header - * - * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CLOCKS_H_ -#define _CLOCKS_H_ - -#include <asm/arch/clocks_am33xx.h> - -#ifdef CONFIG_TI81XX -#include <asm/arch/clock_ti81xx.h> -#endif - -#define LDELAY 1000000 - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F - -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 m4; - s8 m5; - s8 m6; -}; - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_m4_dpll; - u32 cm_div_m5_dpll; - u32 cm_div_m6_dpll; -}; - -extern const struct dpll_regs dpll_mpu_regs; -extern const struct dpll_regs dpll_core_regs; -extern const struct dpll_regs dpll_per_regs; -extern const struct dpll_regs dpll_ddr_regs; - -extern struct cm_wkuppll *const cmwkup; - -const struct dpll_params *get_dpll_mpu_params(void); -const struct dpll_params *get_dpll_core_params(void); -const struct dpll_params *get_dpll_per_params(void); -const struct dpll_params *get_dpll_ddr_params(void); -void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); -void prcm_init(void); -void enable_basic_clocks(void); -void do_enable_clocks(u32 *const *, u32 *const *, u8); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h deleted file mode 100644 index f0699229a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * ti81xx.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - */ - -#ifndef _CLOCK_TI81XX_H_ -#define _CLOCK_TI81XX_H_ - -#define PRCM_MOD_EN 0x2 - -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkstctrl; -#elif defined(CONFIG_TI816X) - unsigned int ocmc1clkstctrl; -#endif - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; -#if defined(CONFIG_TI814X) - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; -#elif defined(CONFIG_TI816X) - unsigned int resv1[1]; - unsigned int timer1clkctrl; - unsigned int timer2clkctrl; - unsigned int timer3clkctrl; - unsigned int timer4clkctrl; - unsigned int timer5clkctrl; - unsigned int timer6clkctrl; - unsigned int timer7clkctrl; -#endif - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv3[2]; -#elif defined(CONFIG_TI816X) - unsigned int resv3[1]; - unsigned int sdioclkctrl; -#endif - unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkctrl; -#elif defined(CONFIG_TI816X) - unsigned int ocmc1clkctrl; -#endif - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; -#if defined(CONFIG_TI814X) - unsigned int debugssclkctrl; -#elif defined(CONFIG_TI816X) - unsigned int resv6[1]; -#endif - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv6[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -#elif defined(CONFIG_TI816X) - unsigned int sr0clkctrl; - unsigned int sr1clkctrl; -#endif -}; - -#endif /* _CLOCK_TI81XX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h deleted file mode 100644 index 4c9352a2e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * clocks_am33xx.h - * - * AM33xx clock define - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CLOCKS_AM33XX_H_ -#define _CLOCKS_AM33XX_H_ - -/* MAIN PLL Fdll supported frequencies */ -#define MPUPLL_M_1000 1000 -#define MPUPLL_M_800 800 -#define MPUPLL_M_720 720 -#define MPUPLL_M_600 600 -#define MPUPLL_M_550 550 -#define MPUPLL_M_300 300 - -/* MAIN PLL Fdll = 550 MHz, by default */ -#ifndef CONFIG_SYS_MPUCLK -#define CONFIG_SYS_MPUCLK MPUPLL_M_550 -#endif - -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -#define CM_DLL_CTRL_NO_OVERRIDE 0x0 -#define CM_DLL_READYST 0x4 - -extern void enable_dmm_clocks(void); -extern const struct dpll_params dpll_core_opp100; -extern struct dpll_params dpll_mpu_opp100; - -#endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h deleted file mode 100644 index d9f0306b0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h +++ /dev/null @@ -1,536 +0,0 @@ -/* - * cpu.h - * - * AM33xx specific header file - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _AM33XX_CPU_H -#define _AM33XX_CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <asm/arch/hardware.h> - -#define BIT(x) (1 << x) -#define CL_BIT(x) (0 << x) - -/* Timer register bits */ -#define TCLR_ST BIT(0) /* Start=1 Stop=0 */ -#define TCLR_AR BIT(1) /* Auto reload */ -#define TCLR_PRE BIT(5) /* Pre-scaler enable */ -#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ -#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ - -/* device type */ -#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* cpu-id for AM33XX and TI81XX family */ -#define AM335X 0xB944 -#define TI81XX 0xB81E -#define DEVICE_ID (CTRL_BASE + 0x0600) -#define DEVICE_ID_MASK 0x1FFF - -/* MPU max frequencies */ -#define AM335X_ZCZ_300 0x1FEF -#define AM335X_ZCZ_600 0x1FAF -#define AM335X_ZCZ_720 0x1F2F -#define AM335X_ZCZ_800 0x1E2F -#define AM335X_ZCZ_1000 0x1C2F -#define AM335X_ZCE_300 0x1FDF -#define AM335X_ZCE_600 0x1F9F - -/* This gives the status of the boot mode pins on the evm */ -#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ - | BIT(3) | BIT(4)) - -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST_WARM_RESET_MASK 0x232 - -/* - * Watchdog: - * Using the prescaler, the OMAP watchdog could go for many - * months before firing. These limits work without scaling, - * with the 60 second default assumed by most tools and docs. - */ -#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ -#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ -#define TIMER_MARGIN_MIN 1 - -#define PTV 0 /* prescale */ -#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) -#define WDT_WWPS_PEND_WCLR BIT(0) -#define WDT_WWPS_PEND_WLDR BIT(2) -#define WDT_WWPS_PEND_WTGR BIT(3) -#define WDT_WWPS_PEND_WSPR BIT(4) - -#define WDT_WCLR_PRE BIT(5) -#define WDT_WCLR_PTV_OFF 2 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ - - -#ifndef CONFIG_AM43XX -/* Encapsulating core pll registers */ -struct cm_wkuppll { - unsigned int wkclkstctrl; /* offset 0x00 */ - unsigned int wkctrlclkctrl; /* offset 0x04 */ - unsigned int wkgpio0clkctrl; /* offset 0x08 */ - unsigned int wkl4wkclkctrl; /* offset 0x0c */ - unsigned int resv2[4]; - unsigned int idlestdpllmpu; /* offset 0x20 */ - unsigned int resv3[2]; - unsigned int clkseldpllmpu; /* offset 0x2c */ - unsigned int resv4[1]; - unsigned int idlestdpllddr; /* offset 0x34 */ - unsigned int resv5[2]; - unsigned int clkseldpllddr; /* offset 0x40 */ - unsigned int resv6[4]; - unsigned int clkseldplldisp; /* offset 0x54 */ - unsigned int resv7[1]; - unsigned int idlestdpllcore; /* offset 0x5c */ - unsigned int resv8[2]; - unsigned int clkseldpllcore; /* offset 0x68 */ - unsigned int resv9[1]; - unsigned int idlestdpllper; /* offset 0x70 */ - unsigned int resv10[2]; - unsigned int clkdcoldodpllper; /* offset 0x7c */ - unsigned int divm4dpllcore; /* offset 0x80 */ - unsigned int divm5dpllcore; /* offset 0x84 */ - unsigned int clkmoddpllmpu; /* offset 0x88 */ - unsigned int clkmoddpllper; /* offset 0x8c */ - unsigned int clkmoddpllcore; /* offset 0x90 */ - unsigned int clkmoddpllddr; /* offset 0x94 */ - unsigned int clkmoddplldisp; /* offset 0x98 */ - unsigned int clkseldpllper; /* offset 0x9c */ - unsigned int divm2dpllddr; /* offset 0xA0 */ - unsigned int divm2dplldisp; /* offset 0xA4 */ - unsigned int divm2dpllmpu; /* offset 0xA8 */ - unsigned int divm2dpllper; /* offset 0xAC */ - unsigned int resv11[1]; - unsigned int wkup_uart0ctrl; /* offset 0xB4 */ - unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ - unsigned int wkup_adctscctrl; /* offset 0xBC */ - unsigned int resv12[6]; - unsigned int divm6dpllcore; /* offset 0xD8 */ -}; - -/** - * Encapsulating peripheral functional clocks - * pll registers - */ -struct cm_perpll { - unsigned int l4lsclkstctrl; /* offset 0x00 */ - unsigned int l3sclkstctrl; /* offset 0x04 */ - unsigned int l4fwclkstctrl; /* offset 0x08 */ - unsigned int l3clkstctrl; /* offset 0x0c */ - unsigned int resv1; - unsigned int cpgmac0clkctrl; /* offset 0x14 */ - unsigned int lcdclkctrl; /* offset 0x18 */ - unsigned int usb0clkctrl; /* offset 0x1C */ - unsigned int resv2; - unsigned int tptc0clkctrl; /* offset 0x24 */ - unsigned int emifclkctrl; /* offset 0x28 */ - unsigned int ocmcramclkctrl; /* offset 0x2c */ - unsigned int gpmcclkctrl; /* offset 0x30 */ - unsigned int mcasp0clkctrl; /* offset 0x34 */ - unsigned int uart5clkctrl; /* offset 0x38 */ - unsigned int mmc0clkctrl; /* offset 0x3C */ - unsigned int elmclkctrl; /* offset 0x40 */ - unsigned int i2c2clkctrl; /* offset 0x44 */ - unsigned int i2c1clkctrl; /* offset 0x48 */ - unsigned int spi0clkctrl; /* offset 0x4C */ - unsigned int spi1clkctrl; /* offset 0x50 */ - unsigned int resv3[3]; - unsigned int l4lsclkctrl; /* offset 0x60 */ - unsigned int l4fwclkctrl; /* offset 0x64 */ - unsigned int mcasp1clkctrl; /* offset 0x68 */ - unsigned int uart1clkctrl; /* offset 0x6C */ - unsigned int uart2clkctrl; /* offset 0x70 */ - unsigned int uart3clkctrl; /* offset 0x74 */ - unsigned int uart4clkctrl; /* offset 0x78 */ - unsigned int timer7clkctrl; /* offset 0x7C */ - unsigned int timer2clkctrl; /* offset 0x80 */ - unsigned int timer3clkctrl; /* offset 0x84 */ - unsigned int timer4clkctrl; /* offset 0x88 */ - unsigned int resv4[8]; - unsigned int gpio1clkctrl; /* offset 0xAC */ - unsigned int gpio2clkctrl; /* offset 0xB0 */ - unsigned int gpio3clkctrl; /* offset 0xB4 */ - unsigned int resv5; - unsigned int tpccclkctrl; /* offset 0xBC */ - unsigned int dcan0clkctrl; /* offset 0xC0 */ - unsigned int dcan1clkctrl; /* offset 0xC4 */ - unsigned int resv6; - unsigned int epwmss1clkctrl; /* offset 0xCC */ - unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int epwmss0clkctrl; /* offset 0xD4 */ - unsigned int epwmss2clkctrl; /* offset 0xD8 */ - unsigned int l3instrclkctrl; /* offset 0xDC */ - unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv8[4]; - unsigned int mmc1clkctrl; /* offset 0xF4 */ - unsigned int mmc2clkctrl; /* offset 0xF8 */ - unsigned int resv9[8]; - unsigned int l4hsclkstctrl; /* offset 0x11C */ - unsigned int l4hsclkctrl; /* offset 0x120 */ - unsigned int resv10[8]; - unsigned int cpswclkstctrl; /* offset 0x144 */ - unsigned int lcdcclkstctrl; /* offset 0x148 */ -}; - -/* Encapsulating Display pll registers */ -struct cm_dpll { - unsigned int resv1[2]; - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ -}; -#else -/* Encapsulating core pll registers */ -struct cm_wkuppll { - unsigned int resv0[136]; - unsigned int wkl4wkclkctrl; /* offset 0x220 */ - unsigned int resv1[55]; - unsigned int wkclkstctrl; /* offset 0x300 */ - unsigned int resv2[15]; - unsigned int wkup_i2c0ctrl; /* offset 0x340 */ - unsigned int resv3; - unsigned int wkup_uart0ctrl; /* offset 0x348 */ - unsigned int resv4[5]; - unsigned int wkctrlclkctrl; /* offset 0x360 */ - unsigned int resv5; - unsigned int wkgpio0clkctrl; /* offset 0x368 */ - - unsigned int resv6[109]; - unsigned int clkmoddpllcore; /* offset 0x520 */ - unsigned int idlestdpllcore; /* offset 0x524 */ - unsigned int resv61; - unsigned int clkseldpllcore; /* offset 0x52C */ - unsigned int resv7[2]; - unsigned int divm4dpllcore; /* offset 0x538 */ - unsigned int divm5dpllcore; /* offset 0x53C */ - unsigned int divm6dpllcore; /* offset 0x540 */ - - unsigned int resv8[7]; - unsigned int clkmoddpllmpu; /* offset 0x560 */ - unsigned int idlestdpllmpu; /* offset 0x564 */ - unsigned int resv9; - unsigned int clkseldpllmpu; /* offset 0x56c */ - unsigned int divm2dpllmpu; /* offset 0x570 */ - - unsigned int resv10[11]; - unsigned int clkmoddpllddr; /* offset 0x5A0 */ - unsigned int idlestdpllddr; /* offset 0x5A4 */ - unsigned int resv11; - unsigned int clkseldpllddr; /* offset 0x5AC */ - unsigned int divm2dpllddr; /* offset 0x5B0 */ - - unsigned int resv12[11]; - unsigned int clkmoddpllper; /* offset 0x5E0 */ - unsigned int idlestdpllper; /* offset 0x5E4 */ - unsigned int resv13; - unsigned int clkseldpllper; /* offset 0x5EC */ - unsigned int divm2dpllper; /* offset 0x5F0 */ - unsigned int resv14[8]; - unsigned int clkdcoldodpllper; /* offset 0x614 */ - - unsigned int resv15[2]; - unsigned int clkmoddplldisp; /* offset 0x620 */ - unsigned int resv16[2]; - unsigned int clkseldplldisp; /* offset 0x62C */ - unsigned int divm2dplldisp; /* offset 0x630 */ -}; - -/* - * Encapsulating peripheral functional clocks - * pll registers - */ -struct cm_perpll { - unsigned int l3clkstctrl; /* offset 0x00 */ - unsigned int resv0[7]; - unsigned int l3clkctrl; /* Offset 0x20 */ - unsigned int resv1[7]; - unsigned int l3instrclkctrl; /* offset 0x40 */ - unsigned int resv2[3]; - unsigned int ocmcramclkctrl; /* offset 0x50 */ - unsigned int resv3[9]; - unsigned int tpccclkctrl; /* offset 0x78 */ - unsigned int resv4; - unsigned int tptc0clkctrl; /* offset 0x80 */ - - unsigned int resv5[7]; - unsigned int l4hsclkctrl; /* offset 0x0A0 */ - unsigned int resv6; - unsigned int l4fwclkctrl; /* offset 0x0A8 */ - unsigned int resv7[85]; - unsigned int l3sclkstctrl; /* offset 0x200 */ - unsigned int resv8[7]; - unsigned int gpmcclkctrl; /* offset 0x220 */ - unsigned int resv9[5]; - unsigned int mcasp0clkctrl; /* offset 0x238 */ - unsigned int resv10; - unsigned int mcasp1clkctrl; /* offset 0x240 */ - unsigned int resv11; - unsigned int mmc2clkctrl; /* offset 0x248 */ - unsigned int resv12[3]; - unsigned int qspiclkctrl; /* offset 0x258 */ - unsigned int resv121; - unsigned int usb0clkctrl; /* offset 0x260 */ - unsigned int resv13[103]; - unsigned int l4lsclkstctrl; /* offset 0x400 */ - unsigned int resv14[7]; - unsigned int l4lsclkctrl; /* offset 0x420 */ - unsigned int resv15; - unsigned int dcan0clkctrl; /* offset 0x428 */ - unsigned int resv16; - unsigned int dcan1clkctrl; /* offset 0x430 */ - unsigned int resv17[13]; - unsigned int elmclkctrl; /* offset 0x468 */ - - unsigned int resv18[3]; - unsigned int gpio1clkctrl; /* offset 0x478 */ - unsigned int resv19; - unsigned int gpio2clkctrl; /* offset 0x480 */ - unsigned int resv20; - unsigned int gpio3clkctrl; /* offset 0x488 */ - unsigned int resv41; - unsigned int gpio4clkctrl; /* offset 0x490 */ - unsigned int resv42; - unsigned int gpio5clkctrl; /* offset 0x498 */ - unsigned int resv21[3]; - - unsigned int i2c1clkctrl; /* offset 0x4A8 */ - unsigned int resv22; - unsigned int i2c2clkctrl; /* offset 0x4B0 */ - unsigned int resv23[3]; - unsigned int mmc0clkctrl; /* offset 0x4C0 */ - unsigned int resv24; - unsigned int mmc1clkctrl; /* offset 0x4C8 */ - - unsigned int resv25[13]; - unsigned int spi0clkctrl; /* offset 0x500 */ - unsigned int resv26; - unsigned int spi1clkctrl; /* offset 0x508 */ - unsigned int resv27[9]; - unsigned int timer2clkctrl; /* offset 0x530 */ - unsigned int resv28; - unsigned int timer3clkctrl; /* offset 0x538 */ - unsigned int resv29; - unsigned int timer4clkctrl; /* offset 0x540 */ - unsigned int resv30[5]; - unsigned int timer7clkctrl; /* offset 0x558 */ - - unsigned int resv31[9]; - unsigned int uart1clkctrl; /* offset 0x580 */ - unsigned int resv32; - unsigned int uart2clkctrl; /* offset 0x588 */ - unsigned int resv33; - unsigned int uart3clkctrl; /* offset 0x590 */ - unsigned int resv34; - unsigned int uart4clkctrl; /* offset 0x598 */ - unsigned int resv35; - unsigned int uart5clkctrl; /* offset 0x5A0 */ - unsigned int resv36[87]; - - unsigned int emifclkstctrl; /* offset 0x700 */ - unsigned int resv361[7]; - unsigned int emifclkctrl; /* offset 0x720 */ - unsigned int resv37[3]; - unsigned int emiffwclkctrl; /* offset 0x730 */ - unsigned int resv371; - unsigned int otfaemifclkctrl; /* offset 0x738 */ - unsigned int resv38[57]; - unsigned int lcdclkctrl; /* offset 0x820 */ - unsigned int resv39[183]; - unsigned int cpswclkstctrl; /* offset 0xB00 */ - unsigned int resv40[7]; - unsigned int cpgmac0clkctrl; /* offset 0xB20 */ -}; - -struct cm_device_inst { - unsigned int cm_clkout1_ctrl; - unsigned int cm_dll_ctrl; -}; - -struct cm_dpll { - unsigned int resv1; - unsigned int clktimer2clk; /* offset 0x04 */ -}; -#endif /* CONFIG_AM43XX */ - -/* Control Module RTC registers */ -struct cm_rtc { - unsigned int rtcclkctrl; /* offset 0x0 */ - unsigned int clkstctrl; /* offset 0x4 */ -}; - -/* Watchdog timer registers */ -struct wd_timer { - unsigned int resv1[4]; - unsigned int wdtwdsc; /* offset 0x010 */ - unsigned int wdtwdst; /* offset 0x014 */ - unsigned int wdtwisr; /* offset 0x018 */ - unsigned int wdtwier; /* offset 0x01C */ - unsigned int wdtwwer; /* offset 0x020 */ - unsigned int wdtwclr; /* offset 0x024 */ - unsigned int wdtwcrr; /* offset 0x028 */ - unsigned int wdtwldr; /* offset 0x02C */ - unsigned int wdtwtgr; /* offset 0x030 */ - unsigned int wdtwwps; /* offset 0x034 */ - unsigned int resv2[3]; - unsigned int wdtwdly; /* offset 0x044 */ - unsigned int wdtwspr; /* offset 0x048 */ - unsigned int resv3[1]; - unsigned int wdtwqeoi; /* offset 0x050 */ - unsigned int wdtwqstar; /* offset 0x054 */ - unsigned int wdtwqsta; /* offset 0x058 */ - unsigned int wdtwqens; /* offset 0x05C */ - unsigned int wdtwqenc; /* offset 0x060 */ - unsigned int resv4[39]; - unsigned int wdt_unfr; /* offset 0x100 */ -}; - -/* Timer 32 bit registers */ -struct gptimer { - unsigned int tidr; /* offset 0x00 */ - unsigned char res1[12]; - unsigned int tiocp_cfg; /* offset 0x10 */ - unsigned char res2[12]; - unsigned int tier; /* offset 0x20 */ - unsigned int tistatr; /* offset 0x24 */ - unsigned int tistat; /* offset 0x28 */ - unsigned int tisr; /* offset 0x2c */ - unsigned int tcicr; /* offset 0x30 */ - unsigned int twer; /* offset 0x34 */ - unsigned int tclr; /* offset 0x38 */ - unsigned int tcrr; /* offset 0x3c */ - unsigned int tldr; /* offset 0x40 */ - unsigned int ttgr; /* offset 0x44 */ - unsigned int twpc; /* offset 0x48 */ - unsigned int tmar; /* offset 0x4c */ - unsigned int tcar1; /* offset 0x50 */ - unsigned int tscir; /* offset 0x54 */ - unsigned int tcar2; /* offset 0x58 */ -}; - -/* UART Registers */ -struct uart_sys { - unsigned int resv1[21]; - unsigned int uartsyscfg; /* offset 0x54 */ - unsigned int uartsyssts; /* offset 0x58 */ -}; - -/* VTP Registers */ -struct vtp_reg { - unsigned int vtp0ctrlreg; -}; - -/* Control Status Register */ -struct ctrl_stat { - unsigned int resv1[16]; - unsigned int statusreg; /* ofset 0x40 */ - unsigned int resv2[51]; - unsigned int secure_emif_sdram_config; /* offset 0x0110 */ - unsigned int resv3[319]; - unsigned int dev_attr; -}; - -/* AM33XX GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x002c -#define OMAP_GPIO_IRQSTATUS2 0x0030 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* Control Device Register */ -struct ctrl_dev { - unsigned int deviceid; /* offset 0x00 */ - unsigned int resv1[7]; - unsigned int usb_ctrl0; /* offset 0x20 */ - unsigned int resv2; - unsigned int usb_ctrl1; /* offset 0x28 */ - unsigned int resv3; - unsigned int macid0l; /* offset 0x30 */ - unsigned int macid0h; /* offset 0x34 */ - unsigned int macid1l; /* offset 0x38 */ - unsigned int macid1h; /* offset 0x3c */ - unsigned int resv4[4]; - unsigned int miisel; /* offset 0x50 */ - unsigned int resv5[106]; - unsigned int efuse_sma; /* offset 0x1FC */ -}; - -/* gmii_sel register defines */ -#define GMII1_SEL_MII 0x0 -#define GMII1_SEL_RMII 0x1 -#define GMII1_SEL_RGMII 0x2 -#define GMII2_SEL_MII 0x0 -#define GMII2_SEL_RMII 0x4 -#define GMII2_SEL_RGMII 0x8 -#define RGMII1_IDMODE BIT(4) -#define RGMII2_IDMODE BIT(5) -#define RMII1_IO_CLK_EN BIT(6) -#define RMII2_IO_CLK_EN BIT(7) - -#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) -#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) -#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) -#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) -#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) - -/* PWMSS */ -struct pwmss_regs { - unsigned int idver; - unsigned int sysconfig; - unsigned int clkconfig; - unsigned int clkstatus; -}; -#define ECAP_CLK_EN BIT(0) -#define ECAP_CLK_STOP_REQ BIT(1) - -struct pwmss_ecap_regs { - unsigned int tsctr; - unsigned int ctrphs; - unsigned int cap1; - unsigned int cap2; - unsigned int cap3; - unsigned int cap4; - unsigned int resv1[4]; - unsigned short ecctl1; - unsigned short ecctl2; -}; - -/* Capture Control register 2 */ -#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) -#define ECTRL2_MDSL_ECAP BIT(9) -#define ECTRL2_CTRSTP_FREERUN BIT(4) -#define ECTRL2_PLSL_LOW BIT(10) -#define ECTRL2_SYNC_EN BIT(5) - -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#endif /* _AM33XX_CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h deleted file mode 100644 index 4d899528f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * ddr_defs.h - * - * ddr specific header - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DDR_DEFS_H -#define _DDR_DEFS_H - -#include <asm/arch/hardware.h> -#include <asm/emif.h> - -/* AM335X EMIF Register values */ -#define VTP_CTRL_READY (0x1 << 5) -#define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_START_EN (0x1) -#ifdef CONFIG_AM43XX -#define DDR_CKE_CTRL_NORMAL 0x3 -#else -#define DDR_CKE_CTRL_NORMAL 0x1 -#endif -#define PHY_EN_DYN_PWRDN (0x1 << 20) - -/* Micron MT47H128M16RT-25E */ -#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 -#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 -#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA -#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F -#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 -#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a -#define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 -#define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_WR_DQS 0x00 -#define MT47H128M16RT25E_PHY_WRLVL 0x00 -#define MT47H128M16RT25E_PHY_GATELVL 0x00 -#define MT47H128M16RT25E_PHY_WR_DATA 0x40 -#define MT47H128M16RT25E_PHY_FIFO_WE 0x80 -#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B - -/* Micron MT41J128M16JT-125 */ -#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 -#define MT41J128MJT125_EMIF_TIM1 0x0888A39B -#define MT41J128MJT125_EMIF_TIM2 0x26337FDA -#define MT41J128MJT125_EMIF_TIM3 0x501F830F -#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 -#define MT41J128MJT125_EMIF_SDREF 0x0000093B -#define MT41J128MJT125_ZQ_CFG 0x50074BE4 -#define MT41J128MJT125_RATIO 0x40 -#define MT41J128MJT125_INVERT_CLKOUT 0x1 -#define MT41J128MJT125_RD_DQS 0x3B -#define MT41J128MJT125_WR_DQS 0x85 -#define MT41J128MJT125_PHY_WR_DATA 0xC1 -#define MT41J128MJT125_PHY_FIFO_WE 0x100 -#define MT41J128MJT125_IOCTRL_VALUE 0x18B - -/* Micron MT41K128M16JT-187E */ -#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 -#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB -#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA -#define MT41K128MJT187E_EMIF_TIM3 0x501F830F -#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 -#define MT41K128MJT187E_EMIF_SDREF 0x0000093B -#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 -#define MT41K128MJT187E_RATIO 0x40 -#define MT41K128MJT187E_INVERT_CLKOUT 0x1 -#define MT41K128MJT187E_RD_DQS 0x3B -#define MT41K128MJT187E_WR_DQS 0x85 -#define MT41K128MJT187E_PHY_WR_DATA 0xC1 -#define MT41K128MJT187E_PHY_FIFO_WE 0x100 -#define MT41K128MJT187E_IOCTRL_VALUE 0x18B - -/* Micron MT41J64M16JT-125 */ -#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 - -/* Micron MT41J256M16JT-125 */ -#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 - -/* Micron MT41J256M8HX-15E */ -#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 -#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B -#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA -#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F -#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 -#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B -#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 -#define MT41J256M8HX15E_RATIO 0x40 -#define MT41J256M8HX15E_INVERT_CLKOUT 0x1 -#define MT41J256M8HX15E_RD_DQS 0x3B -#define MT41J256M8HX15E_WR_DQS 0x85 -#define MT41J256M8HX15E_PHY_WR_DATA 0xC1 -#define MT41J256M8HX15E_PHY_FIFO_WE 0x100 -#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B - -/* Micron MT41K256M16HA-125E */ -#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 -#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB -#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA -#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F -#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 -#define MT41K256M16HA125E_EMIF_SDREF 0xC30 -#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 -#define MT41K256M16HA125E_RATIO 0x80 -#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 -#define MT41K256M16HA125E_RD_DQS 0x38 -#define MT41K256M16HA125E_WR_DQS 0x44 -#define MT41K256M16HA125E_PHY_WR_DATA 0x7D -#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 -#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B - -/* Micron MT41J512M8RH-125 on EVM v1.5 */ -#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 -#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B -#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA -#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF -#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 -#define MT41J512M8RH125_EMIF_SDREF 0x0000093B -#define MT41J512M8RH125_ZQ_CFG 0x50074BE4 -#define MT41J512M8RH125_RATIO 0x80 -#define MT41J512M8RH125_INVERT_CLKOUT 0x0 -#define MT41J512M8RH125_RD_DQS 0x3B -#define MT41J512M8RH125_WR_DQS 0x3C -#define MT41J512M8RH125_PHY_FIFO_WE 0xA5 -#define MT41J512M8RH125_PHY_WR_DATA 0x74 -#define MT41J512M8RH125_IOCTRL_VALUE 0x18B - -/* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 -#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B -#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA -#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF -#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 -#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 -#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 -#define K4B2G1646EBIH9_RATIO 0x80 -#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 -#define K4B2G1646EBIH9_RD_DQS 0x35 -#define K4B2G1646EBIH9_WR_DQS 0x3A -#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 -#define K4B2G1646EBIH9_PHY_WR_DATA 0x76 -#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B - -#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 -#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 -#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 -#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 -#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 -#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 -#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 - -#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 -#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 -#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 -#define DDR3_DATA0_IOCTRL_VALUE 0x84 -#define DDR3_DATA1_IOCTRL_VALUE 0x84 -#define DDR3_DATA2_IOCTRL_VALUE 0x84 -#define DDR3_DATA3_IOCTRL_VALUE 0x84 - -/** - * Configure DMM - */ -void config_dmm(const struct dmm_lisa_map_regs *regs); - -/** - * Configure SDRAM - */ -void config_sdram(const struct emif_regs *regs, int nr); -void config_sdram_emif4d5(const struct emif_regs *regs, int nr); - -/** - * Set SDRAM timings - */ -void set_sdram_timings(const struct emif_regs *regs, int nr); - -/** - * Configure DDR PHY - */ -void config_ddr_phy(const struct emif_regs *regs, int nr); - -struct ddr_cmd_regs { - unsigned int resv0[7]; - unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv1[3]; - unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv2[8]; - unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[3]; - unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv4[8]; - unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[3]; - unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv6[3]; -}; - -struct ddr_data_regs { - unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv1[4]; - unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv2[4]; - unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv3; - unsigned int dt0wimode0; /* offset 0x0F8 */ - unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv4; - unsigned int dt0gimode0; /* offset 0x104 */ - unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv5[4]; - unsigned int dt0dqoffset; /* offset 0x11C */ - unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv6[4]; - unsigned int dt0rdelays0; /* offset 0x134 */ - unsigned int dt0dldiff0; /* offset 0x138 */ - unsigned int resv7[12]; -}; - -/** - * This structure represents the DDR registers on AM33XX devices. - * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that - * correspond to DATA1 registers defined here. - */ -struct ddr_regs { - unsigned int resv0[3]; - unsigned int cm0config; /* offset 0x00C */ - unsigned int cm0configclk; /* offset 0x010 */ - unsigned int resv1[2]; - unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv2[3]; - unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv3[4]; - unsigned int cm1config; /* offset 0x040 */ - unsigned int cm1configclk; /* offset 0x044 */ - unsigned int resv4[2]; - unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv5[3]; - unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv6[4]; - unsigned int cm2config; /* offset 0x074 */ - unsigned int cm2configclk; /* offset 0x078 */ - unsigned int resv7[2]; - unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv8[3]; - unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv9[12]; - unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv10[4]; - unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv11[4]; - unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv12; - unsigned int dt0wimode0; /* offset 0x0F8 */ - unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv13; - unsigned int dt0gimode0; /* offset 0x104 */ - unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv14[4]; - unsigned int dt0dqoffset; /* offset 0x11C */ - unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv15[4]; - unsigned int dt0rdelays0; /* offset 0x134 */ - unsigned int dt0dldiff0; /* offset 0x138 */ -}; - -/** - * Encapsulates DDR CMD control registers. - */ -struct cmd_control { - unsigned long cmd0csratio; - unsigned long cmd0csforce; - unsigned long cmd0csdelay; - unsigned long cmd0iclkout; - unsigned long cmd1csratio; - unsigned long cmd1csforce; - unsigned long cmd1csdelay; - unsigned long cmd1iclkout; - unsigned long cmd2csratio; - unsigned long cmd2csforce; - unsigned long cmd2csdelay; - unsigned long cmd2iclkout; -}; - -/** - * Encapsulates DDR DATA registers. - */ -struct ddr_data { - unsigned long datardsratio0; - unsigned long datawdsratio0; - unsigned long datawiratio0; - unsigned long datagiratio0; - unsigned long datafwsratio0; - unsigned long datawrsratio0; -}; - -/** - * Configure DDR CMD control registers - */ -void config_cmd_ctrl(const struct cmd_control *cmd, int nr); - -/** - * Configure DDR DATA registers - */ -void config_ddr_data(const struct ddr_data *data, int nr); - -/** - * This structure represents the DDR io control on AM33XX devices. - */ -struct ddr_cmdtctrl { - unsigned int cm0ioctl; - unsigned int cm1ioctl; - unsigned int cm2ioctl; - unsigned int resv2[12]; - unsigned int dt0ioctl; - unsigned int dt1ioctl; - unsigned int dt2ioctrl; - unsigned int dt3ioctrl; - unsigned int resv3[4]; - unsigned int emif_sdram_config_ext; -}; - -struct ctrl_ioregs { - unsigned int cm0ioctl; - unsigned int cm1ioctl; - unsigned int cm2ioctl; - unsigned int dt0ioctl; - unsigned int dt1ioctl; - unsigned int dt2ioctrl; - unsigned int dt3ioctrl; - unsigned int emif_sdram_config_ext; -}; - -/** - * Configure DDR io control registers - */ -void config_io_ctrl(const struct ctrl_ioregs *ioregs); - -struct ddr_ctrl { - unsigned int ddrioctrl; - unsigned int resv1[325]; - unsigned int ddrckectrl; -}; - -void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, - const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, int nr); -void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); - -#endif /* _DDR_DEFS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h deleted file mode 100644 index 220603db5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _GPIO_AM33xx_H -#define _GPIO_AM33xx_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 128 - -#define AM33XX_GPIO0_BASE 0x44E07000 -#define AM33XX_GPIO1_BASE 0x4804C000 -#define AM33XX_GPIO2_BASE 0x481AC000 -#define AM33XX_GPIO3_BASE 0x481AE000 -#define AM33XX_GPIO4_BASE 0x48320000 -#define AM33XX_GPIO5_BASE 0x48322000 - -/* GPIO CTRL register */ -#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 -#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) -#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK - -/* GPIO OUTPUT ENABLE register */ -#define GPIO_OE_ENABLE(x) (1 << x) - -/* GPIO SETDATAOUT register */ -#define GPIO_SETDATAOUT(x) (1 << x) -#endif /* _GPIO_AM33xx_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h deleted file mode 100644 index dd950e5ac..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * hardware.h - * - * hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AM33XX_HARDWARE_H -#define __AM33XX_HARDWARE_H - -#include <config.h> -#include <asm/arch/omap.h> -#ifdef CONFIG_AM33XX -#include <asm/arch/hardware_am33xx.h> -#elif defined(CONFIG_TI816X) -#include <asm/arch/hardware_ti816x.h> -#elif defined(CONFIG_TI814X) -#include <asm/arch/hardware_ti814x.h> -#elif defined(CONFIG_AM43XX) -#include <asm/arch/hardware_am43xx.h> -#endif - -/* - * Common hardware definitions - */ - -/* DM Timer base addresses */ -#define DM_TIMER0_BASE 0x4802C000 -#define DM_TIMER1_BASE 0x4802E000 -#define DM_TIMER2_BASE 0x48040000 -#define DM_TIMER3_BASE 0x48042000 -#define DM_TIMER4_BASE 0x48044000 -#define DM_TIMER5_BASE 0x48046000 -#define DM_TIMER6_BASE 0x48048000 -#define DM_TIMER7_BASE 0x4804A000 - -/* GPIO Base address */ -#define GPIO0_BASE 0x48032000 -#define GPIO1_BASE 0x4804C000 - -/* BCH Error Location Module */ -#define ELM_BASE 0x48080000 - -/* EMIF Base address */ -#define EMIF4_0_CFG_BASE 0x4C000000 -#define EMIF4_1_CFG_BASE 0x4D000000 - -/* DDR Base address */ -#define DDR_CTRL_ADDR 0x44E10E04 -#define DDR_CONTROL_BASE_ADDR 0x44E11404 - -/* UART */ -#define DEFAULT_UART_BASE UART0_BASE - -/* GPMC Base address */ -#define GPMC_BASE 0x50000000 - -/* CPSW Config space */ -#define CPSW_BASE 0x4A100000 - -int clk_get(int clk); -#endif /* __AM33XX_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h deleted file mode 100644 index c67a0801a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * hardware_am33xx.h - * - * AM33xx hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AM33XX_HARDWARE_AM33XX_H -#define __AM33XX_HARDWARE_AM33XX_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x44E09000 - -/* GPIO Base address */ -#define GPIO2_BASE 0x481AC000 - -/* Watchdog Timer */ -#define WDT_BASE 0x44E35000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x44E10000 -#define CTRL_DEVICE_BASE 0x44E10600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x44E00000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 -#define CM_DPLL 0x44E00500 -#define CM_RTC 0x44E00800 - -#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x44E10E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x44E12000 -#define DDR_PHY_DATA_ADDR 0x44E120C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 2 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A101000 - -/* RTC base address */ -#define RTC_BASE 0x44E3E000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -/* LCD Controller */ -#define LCD_CNTL_BASE 0x4830E000 - -/* PWMSS */ -#define PWMSS0_BASE 0x48300000 -#define AM33XX_ECAP0_BASE 0x48300100 - -#endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h deleted file mode 100644 index 15399dcc7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * hardware_am43xx.h - * - * AM43xx hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AM43XX_HARDWARE_AM43XX_H -#define __AM43XX_HARDWARE_AM43XX_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x44E09000 - -/* GPIO Base address */ -#define GPIO2_BASE 0x481AC000 - -/* Watchdog Timer */ -#define WDT_BASE 0x44E35000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x44E10000 -#define CTRL_DEVICE_BASE 0x44E10600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x44DF0000 -#define CM_WKUP 0x44DF2800 -#define CM_PER 0x44DF8800 -#define CM_DPLL 0x44DF4200 -#define CM_RTC 0x44DF8500 - -#define PRM_RSTCTRL (PRCM_BASE + 0x4000) -#define PRM_RSTST (PRM_RSTCTRL + 4) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x44E10E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x44E12000 -#define DDR_PHY_DATA_ADDR 0x44E120C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 2 - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A101000 - -/* RTC base address */ -#define RTC_BASE 0x44E3E000 - -/* USB Clock Control */ -#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) -#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) -#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) -#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) - -#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) -#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) -#define USBPHYOCPSCP_MODULE_EN (1 << 1) -#define CM_DEVICE_INST 0x44df4100 - -/* Control status register */ -#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) -#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 -#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) -#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 -#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) -#define CTRL_SYSBOOT_15_14_SHIFT 22 - -#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 -#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 - -#define NUM_CRYSTAL_FREQ 0x4 - -#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h deleted file mode 100644 index 4509a237d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * hardware_ti814x.h - * - * TI814x hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AM33XX_HARDWARE_TI814X_H -#define __AM33XX_HARDWARE_TI814X_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x48020000 - -/* Watchdog Timer */ -#define WDT_BASE 0x481C7000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* PLL Subsystem Base Address */ -#define PLL_SUBSYS_BASE 0x481C5000 - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48140E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x47C0C400 -#define DDR_PHY_DATA_ADDR 0x47C0C4C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 4 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A100800 - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h deleted file mode 100644 index 3c680649a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * hardware_ti816x.h - * - * TI816x hardware specific header - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * Based on TI-PSP-04.00.02.14 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AM33XX_HARDWARE_TI816X_H -#define __AM33XX_HARDWARE_TI816X_H - -/* UART */ -#define UART0_BASE 0x48020000 -#define UART1_BASE 0x48022000 -#define UART2_BASE 0x48024000 - -/* Watchdog Timer */ -#define WDT_BASE 0x480C2000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48198358 -#define VTP1_CTRL_ADDR 0x4819A358 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x48198000 -#define DDR_PHY_DATA_ADDR 0x481980C8 -#define DDR_PHY_CMD_ADDR2 0x4819A000 -#define DDR_PHY_DATA_ADDR2 0x4819A0C8 -#define DDR_DATA_REGS_NR 4 - - -#define DDRPHY_0_CONFIG_BASE 0x48198000 -#define DDRPHY_1_CONFIG_BASE 0x4819A000 -#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ - DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h deleted file mode 100644 index 8642c8f87..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _I2C_AM33XX_H_ -#define _I2C_AM33XX_H_ - -#define I2C_BASE1 0x44E0B000 -#define I2C_BASE2 0x4802A000 -#define I2C_BASE3 0x4819C000 -#define I2C_BUS_MAX 3 - -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short revnb_lo; /* 0x00 */ - unsigned short res1; - unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[5]; - unsigned short sysc; /* 0x10 */ - unsigned short res3[9]; - unsigned short irqstatus_raw; /* 0x24 */ - unsigned short res4; - unsigned short stat; /* 0x28 */ - unsigned short res5; - unsigned short ie; /* 0x2C */ - unsigned short res6; - unsigned short irqenable_clr; /* 0x30 */ - unsigned short res7; - unsigned short iv; /* 0x34 */ - unsigned short res8[45]; - unsigned short syss; /* 0x90 */ - unsigned short res9; - unsigned short buf; /* 0x94 */ - unsigned short res10; - unsigned short cnt; /* 0x98 */ - unsigned short res11; - unsigned short data; /* 0x9C */ - unsigned short res13; - unsigned short res14; /* 0xA0 */ - unsigned short res15; - unsigned short con; /* 0xA4 */ - unsigned short res16; - unsigned short oa; /* 0xA8 */ - unsigned short res17; - unsigned short sa; /* 0xAC */ - unsigned short res18; - unsigned short psc; /* 0xB0 */ - unsigned short res19; - unsigned short scll; /* 0xB4 */ - unsigned short res20; - unsigned short sclh; /* 0xB8 */ - unsigned short res21; - unsigned short systest; /* 0xBC */ - unsigned short res22; - unsigned short bufstat; /* 0xC0 */ - unsigned short res23; -}; - -#define I2C_IP_CLK 48000000 -#define I2C_INTERNAL_SAMPLING_CLK 12000000 - -#endif /* _I2C_AM33XX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h deleted file mode 100644 index e7e8c58b0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * Author - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Richard Woodruff <r-woodruff2@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL - */ -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define M_NAND_GPMC_CONFIG1 0x00000800 -#define M_NAND_GPMC_CONFIG2 0x001e1e00 -#define M_NAND_GPMC_CONFIG3 0x001e1e00 -#define M_NAND_GPMC_CONFIG4 0x16051807 -#define M_NAND_GPMC_CONFIG5 0x00151e1e -#define M_NAND_GPMC_CONFIG6 0x16000f80 -#define M_NAND_GPMC_CONFIG7 0x00000008 - -#define STNOR_GPMC_CONFIG1 0x00001200 -#define STNOR_GPMC_CONFIG2 0x00101000 -#define STNOR_GPMC_CONFIG3 0x00030301 -#define STNOR_GPMC_CONFIG4 0x10041004 -#define STNOR_GPMC_CONFIG5 0x000C1010 -#define STNOR_GPMC_CONFIG6 0x08070280 -#define STNOR_GPMC_CONFIG7 0x00000F48 - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -#endif /* endif _MEM_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h deleted file mode 100644 index 724e25294..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * mmc_host_def.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC1_BASE 0x48060100 -#define OMAP_HSMMC2_BASE 0x481D8100 - -#if defined(CONFIG_TI814X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 192 /* MHz */ -#elif defined(CONFIG_TI816X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 48 /* MHz */ -#endif - -#endif /* MMC_HOST_DEF_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h deleted file mode 100644 index 324943726..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * mux.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_H_ -#define _MUX_H_ - -#include <common.h> -#include <asm/io.h> - -#ifdef CONFIG_AM33XX -#include <asm/arch/mux_am33xx.h> -#elif defined(CONFIG_TI814X) -#include <asm/arch/mux_ti814x.h> -#elif defined(CONFIG_TI816X) -#include <asm/arch/mux_ti816x.h> -#elif defined(CONFIG_AM43XX) -#include <asm/arch/mux_am43xx.h> -#endif - -struct module_pin_mux { - short reg_offset; - unsigned int val; -}; - -/* Pad control register offset */ -#define PAD_CTRL_BASE 0x800 -#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ - (PAD_CTRL_BASE))->x) - -/* - * Configure the pin mux for the module - */ -void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); - -#endif /* endif _MUX_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h deleted file mode 100644 index d5cab3e08..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * mux_am33xx.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_AM33XX_H_ -#define _MUX_AM33XX_H_ - -#include <common.h> -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 6) -#define RXACTIVE (0x1 << 5) -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; - int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; - int rsvd1; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int pmic_power_en; - int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; - int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; - int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; - int ddr_a0; - int ddr_a1; - int ddr_a2; - int ddr_a3; - int ddr_a4; - int ddr_a5; - int ddr_a6; - int ddr_a7; - int ddr_a8; - int ddr_a9; - int ddr_a10; - int ddr_a11; - int ddr_a12; - int ddr_a13; - int ddr_a14; - int ddr_a15; - int ddr_odt; - int ddr_d0; - int ddr_d1; - int ddr_d2; - int ddr_d3; - int ddr_d4; - int ddr_d5; - int ddr_d6; - int ddr_d7; - int ddr_d8; - int ddr_d9; - int ddr_d10; - int ddr_d11; - int ddr_d12; - int ddr_d13; - int ddr_d14; - int ddr_d15; - int ddr_dqm0; - int ddr_dqm1; - int ddr_dqs0; - int ddr_dqsn0; - int ddr_dqs1; - int ddr_dqsn1; - int ddr_vref; - int ddr_vtp; - int ddr_strben0; - int ddr_strben1; - int ain7; - int ain6; - int ain5; - int ain4; - int ain3; - int ain2; - int ain1; - int ain0; - int vrefp; - int vrefn; -}; - -#endif /* endif _MUX_AM33XX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h deleted file mode 100644 index 98fc2b50d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * mux_am43xx.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MUX_AM43XX_H_ -#define _MUX_AM43XX_H_ - -#include <common.h> -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 19) -#define RXACTIVE (0x1 << 18) -#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ -#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ -#define MODE(val) val /* used for Readability */ - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; - int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; - int rsvd1; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int pmic_power_en; - int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; - int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; - int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; -}; - -#endif /* _MUX_AM43XX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h deleted file mode 100644 index a26e5038f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * mux_ti814x.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI814X_H_ -#define _MUX_TI814X_H_ - -/* PAD Control Fields */ -#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ -#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -#define MUX_CFG(value, offset) \ -{ \ - int tmp; \ - tmp = __raw_readl(CTRL_BASE + offset); \ - tmp &= PINCNTL_RSV_MSK; \ - __raw_writel(tmp | value, (CTRL_BASE + offset));\ -} - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; -}; - -#endif /* endif _MUX_TI814X_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h deleted file mode 100644 index e4e5a48ad..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * mux_ti816x.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI816X_H_ -#define _MUX_TI816X_H_ - -#include <common.h> -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) (val) /* used for Readability */ - - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; - int pincntl271; - int pincntl272; - int pincntl273; - int pincntl274; - int pincntl275; - int pincntl276; - int pincntl277; - int pincntl278; - int pincntl279; - int pincntl280; - int pincntl281; - int pincntl282; - int pincntl283; - int pincntl284; - int pincntl285; - int pincntl286; - int pincntl287; - int pincntl288; - int pincntl289; - int pincntl290; - int pincntl291; - int pincntl292; - int pincntl293; - int pincntl294; - int pincntl295; - int pincntl296; - int pincntl297; - int pincntl298; - int pincntl299; - int pincntl300; - int pincntl301; - int pincntl302; - int pincntl303; - int pincntl304; - int pincntl305; - int pincntl306; - int pincntl307; - int pincntl308; - int pincntl309; - int pincntl310; - int pincntl311; - int pincntl312; - int pincntl313; - int pincntl314; - int pincntl315; - int pincntl316; - int pincntl317; - int pincntl318; - int pincntl319; - int pincntl320; - int pincntl321; - int pincntl322; - int pincntl323; -}; - -#endif /* endif _MUX_TI816X_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h deleted file mode 100644 index 0855d16ce..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * omap.h - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * Author: - * Chandan Nath <chandan.nath@ti.com> - * - * Derived from OMAP4 work by - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _OMAP_H_ -#define _OMAP_H_ - -#ifdef CONFIG_AM33XX -#define NON_SECURE_SRAM_START 0x402F0400 -#define NON_SECURE_SRAM_END 0x40310000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800 -#elif defined(CONFIG_TI81XX) -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 -#elif defined(CONFIG_AM43XX) -#define NON_SECURE_SRAM_START 0x402F0400 -#define NON_SECURE_SRAM_END 0x40340000 -#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 -#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR -#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC -#define QSPI_BASE 0x47900000 -#endif -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h deleted file mode 100644 index 8543f4399..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#if defined(CONFIG_TI816X) -#define BOOT_DEVICE_XIP 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_MMC1 6 -#define BOOT_DEVICE_MMC2 5 -#define BOOT_DEVICE_UART 0x43 -#elif defined(CONFIG_AM43XX) -#define BOOT_DEVICE_NOR 1 -#define BOOT_DEVICE_NAND 5 -#define BOOT_DEVICE_MMC1 7 -#define BOOT_DEVICE_MMC2 8 -#define BOOT_DEVICE_SPI 10 -#define BOOT_DEVICE_USB 13 -#define BOOT_DEVICE_UART 65 -#define BOOT_DEVICE_CPGMAC 71 -#else -#define BOOT_DEVICE_XIP 2 -#define BOOT_DEVICE_NAND 5 -#if defined(CONFIG_AM33XX) -#define BOOT_DEVICE_MMC1 8 -#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ -#elif defined(CONFIG_TI814X) -#define BOOT_DEVICE_MMC1 9 -#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */ -#endif -#define BOOT_DEVICE_SPI 11 -#define BOOT_DEVICE_UART 65 -#define BOOT_DEVICE_USBETH 68 -#define BOOT_DEVICE_CPGMAC 70 -#endif -#define BOOT_DEVICE_MMC2_2 0xFF - -#if defined(CONFIG_AM33XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#elif defined(CONFIG_AM43XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#ifdef CONFIG_SPL_USB_SUPPORT -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB -#else -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#endif -#elif defined(CONFIG_TI81XX) -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#endif -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h deleted file mode 100644 index 91ff2ad0e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * sys_proto.h - * - * System information header - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/cpu.h> - -#define BOARD_REV_ID 0x0 - -u32 get_cpu_rev(void); -u32 get_sysboot_value(void); - -extern struct ctrl_stat *cstat; -u32 get_device_type(void); -void save_omap_boot_params(void); -void setup_clocks_for_console(void); -void mpu_pll_config_val(int mpull_m); -void ddr_pll_config(unsigned int ddrpll_M); - -void sdelay(unsigned long); - -struct gpmc_cs; -void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size); -void omap_nand_switch_ecc(uint32_t, uint32_t); - -void set_uart_mux_conf(void); -void set_mux_conf_regs(void); -void sdram_init(void); -u32 wait_on_value(u32, u32, void *, u32); -#ifdef CONFIG_NOR_BOOT -void enable_norboot_pin_mux(void); -#endif -void am33xx_spl_board_init(void); -int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); -int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-arm720t/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-arm720t/hardware.h deleted file mode 100644 index 8ca42d9e7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-arm720t/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ARM7_HW_H -#define __ARM7_HW_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune <curt@cucy.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) -/* include IntegratorCP/CM720T specific hardware file if there was one */ -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ARM7_HW_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h deleted file mode 100644 index d9feb1608..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * Contributor: Mahavir Jain <mjain@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_ARMADA100_H -#define _ASM_ARCH_ARMADA100_H - -#if defined (CONFIG_ARMADA100) - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Fast Ethernet Controller Clock register definition */ -#define FE_CLK_RST 0x1 -#define FE_CLK_ENA 0x8 - -/* SSP2 Clock Control */ -#define SSP2_APBCLK 0x01 -#define SSP2_FNCLK 0x02 - -/* USB Clock/reset control bits */ -#define USB_SPH_AXICLK_EN 0x10 -#define USB_SPH_AXI_RST 0x02 - -/* MPMU Clocks */ -#define APB2_26M_EN (1 << 20) -#define AP_26M (1 << 4) - -/* Register Base Addresses */ -#define ARMD1_DRAM_BASE 0xB0000000 -#define ARMD1_FEC_BASE 0xC0800000 -#define ARMD1_TIMER_BASE 0xD4014000 -#define ARMD1_APBC1_BASE 0xD4015000 -#define ARMD1_APBC2_BASE 0xD4015800 -#define ARMD1_UART1_BASE 0xD4017000 -#define ARMD1_UART2_BASE 0xD4018000 -#define ARMD1_GPIO_BASE 0xD4019000 -#define ARMD1_SSP1_BASE 0xD401B000 -#define ARMD1_SSP2_BASE 0xD401C000 -#define ARMD1_MFPR_BASE 0xD401E000 -#define ARMD1_SSP3_BASE 0xD401F000 -#define ARMD1_SSP4_BASE 0xD4020000 -#define ARMD1_SSP5_BASE 0xD4021000 -#define ARMD1_UART3_BASE 0xD4026000 -#define ARMD1_MPMU_BASE 0xD4050000 -#define ARMD1_USB_HOST_BASE 0xD4209000 -#define ARMD1_APMU_BASE 0xD4282800 -#define ARMD1_CPU_BASE 0xD4282C00 - -#endif /* CONFIG_ARMADA100 */ -#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h deleted file mode 100644 index 532411e1c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file should be included in board config header file. - * - * It supports common definitions for Armada100 platform - */ - -#ifndef _ARMD1_CONFIG_H -#define _ARMD1_CONFIG_H - -#include <asm/arch/armada100.h> -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ -/* default Dcache Line length for armada100 */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE ARMD1_MFPR_BASE -#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ -/* - * I2C definition - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_NUM 2 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000} -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 0 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -#endif /* _ARMD1_CONFIG_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h deleted file mode 100644 index c1f190dbd..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ARMADA100CPU_H -#define _ARMADA100CPU_H - -#include <asm/io.h> -#include <asm/system.h> - -/* - * Main Power Management (MPMU) Registers - * Refer Datasheet Appendix A.8 - */ -struct armd1mpmu_registers { - u8 pad0[0x08 - 0x00]; - u32 fccr; /*0x0008*/ - u32 pocr; /*0x000c*/ - u32 posr; /*0x0010*/ - u32 succr; /*0x0014*/ - u8 pad1[0x030 - 0x014 - 4]; - u32 gpcr; /*0x0030*/ - u8 pad2[0x200 - 0x030 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad3[0x1000 - 0x200 - 4]; - u32 apcr; /*0x1000*/ - u32 apsr; /*0x1004*/ - u8 pad4[0x1020 - 0x1004 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ - u32 arsr; /*0x1028*/ -}; - -/* - * Application Subsystem Power Management - * Refer Datasheet Appendix A.9 - */ -struct armd1apmu_registers { - u32 pcr; /* 0x000 */ - u32 ccr; /* 0x004 */ - u32 pad1; - u32 ccsr; /* 0x00C */ - u32 fc_timer; /* 0x010 */ - u32 pad2; - u32 ideal_cfg; /* 0x018 */ - u8 pad3[0x04C - 0x018 - 4]; - u32 lcdcrc; /* 0x04C */ - u32 cciccrc; /* 0x050 */ - u32 sd1crc; /* 0x054 */ - u32 sd2crc; /* 0x058 */ - u32 usbcrc; /* 0x05C */ - u32 nfccrc; /* 0x060 */ - u32 dmacrc; /* 0x064 */ - u32 pad4; - u32 buscrc; /* 0x06C */ - u8 pad5[0x07C - 0x06C - 4]; - u32 wake_clr; /* 0x07C */ - u8 pad6[0x090 - 0x07C - 4]; - u32 core_status; /* 0x090 */ - u32 rfsc; /* 0x094 */ - u32 imr; /* 0x098 */ - u32 irwc; /* 0x09C */ - u32 isr; /* 0x0A0 */ - u8 pad7[0x0B0 - 0x0A0 - 4]; - u32 mhst; /* 0x0B0 */ - u32 msr; /* 0x0B4 */ - u8 pad8[0x0C0 - 0x0B4 - 4]; - u32 msst; /* 0x0C0 */ - u32 pllss; /* 0x0C4 */ - u32 smb; /* 0x0C8 */ - u32 gccrc; /* 0x0CC */ - u8 pad9[0x0D4 - 0x0CC - 4]; - u32 smccrc; /* 0x0D4 */ - u32 pad10; - u32 xdcrc; /* 0x0DC */ - u32 sd3crc; /* 0x0E0 */ - u32 sd4crc; /* 0x0E4 */ - u8 pad11[0x0F0 - 0x0E4 - 4]; - u32 cfcrc; /* 0x0F0 */ - u32 mspcrc; /* 0x0F4 */ - u32 cmucrc; /* 0x0F8 */ - u32 fecrc; /* 0x0FC */ - u32 pciecrc; /* 0x100 */ - u32 epdcrc; /* 0x104 */ -}; - -/* - * APB1 Clock Reset/Control Registers - * Refer Datasheet Appendix A.10 - */ -struct armd1apb1_registers { - u32 uart1; /*0x000*/ - u32 uart2; /*0x004*/ - u32 gpio; /*0x008*/ - u32 pwm1; /*0x00c*/ - u32 pwm2; /*0x010*/ - u32 pwm3; /*0x014*/ - u32 pwm4; /*0x018*/ - u8 pad0[0x028 - 0x018 - 4]; - u32 rtc; /*0x028*/ - u32 twsi0; /*0x02c*/ - u32 kpc; /*0x030*/ - u32 timers; /*0x034*/ - u8 pad1[0x03c - 0x034 - 4]; - u32 aib; /*0x03c*/ - u32 sw_jtag; /*0x040*/ - u32 timer1; /*0x044*/ - u32 onewire; /*0x048*/ - u8 pad2[0x050 - 0x048 - 4]; - u32 asfar; /*0x050 AIB Secure First Access Reg*/ - u32 assar; /*0x054 AIB Secure Second Access Reg*/ - u8 pad3[0x06c - 0x054 - 4]; - u32 twsi1; /*0x06c*/ - u32 uart3; /*0x070*/ - u8 pad4[0x07c - 0x070 - 4]; - u32 timer2; /*0x07C*/ - u8 pad5[0x084 - 0x07c - 4]; - u32 ac97; /*0x084*/ -}; - -/* -* APB2 Clock Reset/Control Registers -* Refer Datasheet Appendix A.11 -*/ -struct armd1apb2_registers { - u32 pad1[0x01C - 0x000]; - u32 ssp1_clkrst; /* 0x01C */ - u32 ssp2_clkrst; /* 0x020 */ - u32 pad2[0x04C - 0x020 - 4]; - u32 ssp3_clkrst; /* 0x04C */ - u32 pad3[0x058 - 0x04C - 4]; - u32 ssp4_clkrst; /* 0x058 */ - u32 ssp5_clkrst; /* 0x05C */ -}; - -/* - * CPU Interface Registers - * Refer Datasheet Appendix A.2 - */ -struct armd1cpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 armd1_sdram_base(int); -u32 armd1_sdram_size(int); - -#endif /* _ARMADA100CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h deleted file mode 100644 index 4927abea9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_GPIO_H -#define _ASM_ARCH_GPIO_H - -#include <asm/types.h> -#include <asm/arch/armada100.h> - -#define GPIO_HIGH 1 -#define GPIO_LOW 0 - -#define GPIO_TO_REG(gp) (gp >> 5) -#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) -#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) - -static inline void *get_gpio_base(int bank) -{ - const unsigned int offset[4] = {0, 4, 8, 0x100}; - /* gpio register bank offset - refer Appendix A.36 */ - return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); -} - -#endif /* _ASM_ARCH_GPIO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h deleted file mode 100644 index b918239e9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h - * (C) Copyright 2007 - * Marvell Semiconductor <www.marvell.com> - * 2007-08-21: eric miao <eric.miao@marvell.com> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * Contributor: Mahavir Jain <mjain@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARMADA100_MFP_H -#define __ARMADA100_MFP_H - -/* - * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART1 */ -#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) -#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) -#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* UART3 */ -#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* I2c */ -#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) -#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) - -/* Fast Ethernet */ -#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) -#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) - -/* SPI */ -#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) -#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ - -#define MFP_PIN_MAX 117 - -#endif /* __ARMADA100_MFP_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h deleted file mode 100644 index 9efa1bf1e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARMADA100_SPI_H_ -#define __ARMADA100_SPI_H_ - -#include <asm/arch/armada100.h> - -#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE -#define SSP_REG_BASE(x) CAT_BASE_ADDR(x) - -/* - * SSP Serial Port Registers - * refer Appendix A.26 - */ -struct ssp_reg { - u32 sscr0; /* SSP Control Register 0 - 0x000 */ - u32 sscr1; /* SSP Control Register 1 - 0x004 */ - u32 sssr; /* SSP Status Register - 0x008 */ - u32 ssitr; /* SSP Interrupt Test Register - 0x00C */ - u32 ssdr; /* SSP Data Register - 0x010 */ - u32 pad1[5]; - u32 ssto; /* SSP Timeout Register - 0x028 */ - u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */ - u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */ - u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */ - u32 sstss; /* SSP Timeslot Status Register - 0x038 */ -}; - -#define DEFAULT_WORD_LEN 8 -#define SSP_FLUSH_NUM 0x2000 -#define RX_THRESH_DEF 8 -#define TX_THRESH_DEF 8 -#define TIMEOUT_DEF 1000 - -#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ -#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ -#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ -#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity - setting */ -#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ -#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ -#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */ -#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */ - -#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */ -#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */ -#define SSCR1_TINTE (1 << 19) /* Receiver Time-out - Interrupt enable */ - -#define SSCR0_DSS 0x0f /* Data Size Select (mask) */ -#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */ -#define SSCR0_FRF 0x30 /* FRame Format (mask) */ -#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial - Peripheral Interface */ -#define SSCR0_TI (0x1 << 4) /* TI's Synchronous - Serial Protocol (SSP) */ -#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */ -#define SSCR0_ECS (1 << 6) /* External clock select */ -#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port - Enable */ - -#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ -#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ -#define SSSR_BSY (1 << 4) /* SSP Busy */ -#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ -#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ -#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ - -#endif /* __ARMADA100_SPI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h deleted file mode 100644 index 953dd4413..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __UTMI_ARMADA100__ -#define __UTMI_ARMADA100__ - -#define UTMI_PHY_BASE 0xD4206000 - -/* utmi_ctrl - bits */ -#define INPKT_DELAY_SOF (1 << 28) -#define PLL_PWR_UP 2 -#define PHY_PWR_UP 1 - -/* utmi_pll - bits */ -#define PLL_FBDIV_MASK 0x00000FF0 -#define PLL_FBDIV 4 -#define PLL_REFDIV_MASK 0x0000000F -#define PLL_REFDIV 0 -#define PLL_READY 0x800000 -#define VCOCAL_START (1 << 21) - -#define N_DIVIDER 0xEE -#define M_DIVIDER 0x0B - -/* utmi_tx - bits */ -#define CK60_PHSEL 17 -#define PHSEL_VAL 0x4 -#define RCAL_START (1 << 12) - -/* - * USB PHY registers - * Refer Datasheet Appendix A.21 - */ -struct armd1usb_phy_reg { - u32 utmi_rev; /* USB PHY Revision */ - u32 utmi_ctrl; /* USB PHY Control register */ - u32 utmi_pll; /* PLL register */ - u32 utmi_tx; /* Tx register */ - u32 utmi_rx; /* Rx register */ - u32 utmi_ivref; /* IVREF register */ - u32 utmi_tst_g0; /* Test group 0 register */ - u32 utmi_tst_g1; /* Test group 1 register */ - u32 utmi_tst_g2; /* Test group 2 register */ - u32 utmi_tst_g3; /* Test group 3 register */ - u32 utmi_tst_g4; /* Test group 4 register */ - u32 utmi_tst_g5; /* Test group 5 register */ - u32 utmi_reserve; /* Reserve Register */ - u32 utmi_usb_int; /* USB interuppt register */ - u32 utmi_dbg_ctl; /* Debug control register */ - u32 utmi_otg_addon; /* OTG addon register */ -}; - -int utmi_init(void); - -#endif /* __UTMI_ARMADA100__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h deleted file mode 100644 index 6a19950de..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _GLOBALTIMER_H_ -#define _GLOBALTIMER_H_ - -struct globaltimer { - u32 cnt_l; /* 0x00 */ - u32 cnt_h; - u32 ctl; - u32 stat; - u32 cmp_l; /* 0x10 */ - u32 cmp_h; - u32 inc; -}; - -#endif /* _GLOBALTIMER_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h deleted file mode 100644 index 34e88a8f2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2010 Linaro - * Matt Waddel, <matt.waddel@linaro.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _SYSCTRL_H_ -#define _SYSCTRL_H_ - -/* System controller (SP810) register definitions */ -#define SP810_TIMER0_ENSEL (1 << 15) -#define SP810_TIMER1_ENSEL (1 << 17) -#define SP810_TIMER2_ENSEL (1 << 19) -#define SP810_TIMER3_ENSEL (1 << 21) - -struct sysctrl { - u32 scctrl; /* 0x000 */ - u32 scsysstat; - u32 scimctrl; - u32 scimstat; - u32 scxtalctrl; - u32 scpllctrl; - u32 scpllfctrl; - u32 scperctrl0; - u32 scperctrl1; - u32 scperen; - u32 scperdis; - u32 scperclken; - u32 scperstat; - u32 res1[0x006]; - u32 scflashctrl; /* 0x04c */ - u32 res2[0x3a4]; - u32 scsysid0; /* 0xee0 */ - u32 scsysid1; - u32 scsysid2; - u32 scsysid3; - u32 scitcr; - u32 scitir0; - u32 scitir1; - u32 scitor; - u32 sccntctrl; - u32 sccntdata; - u32 sccntstep; - u32 res3[0x32]; - u32 scperiphid0; /* 0xfe0 */ - u32 scperiphid1; - u32 scperiphid2; - u32 scperiphid3; - u32 scpcellid0; - u32 scpcellid1; - u32 scpcellid2; - u32 scpcellid3; -}; -#endif /* _SYSCTRL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h deleted file mode 100644 index a0412bd34..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2010 Linaro - * Matt Waddel, <matt.waddel@linaro.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _SYSTIMER_H_ -#define _SYSTIMER_H_ - -/* AMBA timer register base address */ -#define SYSTIMER_BASE 0x10011000 - -#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */ -#define SYSTIMER_RELOAD 0xFFFFFFFF -#define SYSTIMER_EN (1 << 7) -#define SYSTIMER_32BIT (1 << 1) -#define SYSTIMER_PRESC_16 (1 << 2) -#define SYSTIMER_PRESC_256 (1 << 3) - -struct systimer { - u32 timer0load; /* 0x00 */ - u32 timer0value; - u32 timer0control; - u32 timer0intclr; - u32 timer0ris; - u32 timer0mis; - u32 timer0bgload; - u32 timer1load; /* 0x20 */ - u32 timer1value; - u32 timer1control; - u32 timer1intclr; - u32 timer1ris; - u32 timer1mis; - u32 timer1bgload; -}; -#endif /* _SYSTIMER_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h deleted file mode 100644 index 4483b1a34..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2010 - * Matt Waddel, <matt.waddel@linaro.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _WDT_H_ -#define _WDT_H_ - -/* Watchdog timer (SP805) register base address */ -#define WDT_BASE 0x100E5000 - -#define WDT_EN 0x2 -#define WDT_RESET_LOAD 0x0 - -struct wdt { - u32 wdogload; /* 0x000 */ - u32 wdogvalue; - u32 wdogcontrol; - u32 wdogintclr; - u32 wdogris; - u32 wdogmis; - u32 res1[0x2F9]; - u32 wdoglock; /* 0xC00 */ - u32 res2[0xBE]; - u32 wdogitcr; /* 0xF00 */ - u32 wdogitop; - u32 res3[0x35]; - u32 wdogperiphid0; /* 0xFE0 */ - u32 wdogperiphid1; - u32 wdogperiphid2; - u32 wdogperiphid3; - u32 wdogpcellid0; - u32 wdogpcellid1; - u32 wdogpcellid2; - u32 wdogpcellid3; -}; - -#endif /* _WDT_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_common.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_common.h deleted file mode 100644 index 59e2f4391..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_common.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_COMMON_H -#define AT91_COMMON_H - -void at91_can_hw_init(void); -void at91_gmac_hw_init(void); -void at91_macb_hw_init(void); -void at91_mci_hw_init(void); -void at91_serial0_hw_init(void); -void at91_serial1_hw_init(void); -void at91_serial2_hw_init(void); -void at91_seriald_hw_init(void); -void at91_spi0_hw_init(unsigned long cs_mask); -void at91_spi1_hw_init(unsigned long cs_mask); -void at91_udp_hw_init(void); -void at91_uhp_hw_init(void); -void at91_lcd_hw_init(void); -void at91_plla_init(u32 pllar); -void at91_mck_init(u32 mckr); -void at91_pmc_init(void); -void mem_init(void); -void at91_phy_reset(void); - -#endif /* AT91_COMMON_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h deleted file mode 100644 index 7346fc056..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Debug Unit - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_DBU_H -#define AT91_DBU_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_dbu { - u32 cr; /* Control Register WO */ - u32 mr; /* Mode Register RW */ - u32 ier; /* Interrupt Enable Register WO */ - u32 idr; /* Interrupt Disable Register WO */ - u32 imr; /* Interrupt Mask Register RO */ - u32 sr; /* Status Register RO */ - u32 rhr; /* Receive Holding Register RO */ - u32 thr; /* Transmit Holding Register WO */ - u32 brgr; /* Baud Rate Generator Register RW */ - u32 res1[7];/* 0x0024 - 0x003C Reserved */ - u32 cidr; /* Chip ID Register RO */ - u32 exid; /* Chip ID Extension Register RO */ - u32 fnr; /* Force NTRST Register RW */ -} at91_dbu_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_DBU_CID_ARCH_MASK 0x0ff00000 -#define AT91_DBU_CID_ARCH_9xx 0x01900000 -#define AT91_DBU_CID_ARCH_9XExx 0x02900000 - -#define AT91_DBU_CIDR_MASK 0x1f -#define AT91_DBU_CIDR 0x40 -#define AT91_DBU_EXID 0x44 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_eefc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_eefc.h deleted file mode 100644 index 7ffbaee27..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_eefc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Enhanced Embedded Flash Controller - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_EEFC_H -#define AT91_EEFC_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_eefc { - u32 fmr; /* Flash Mode Register RW */ - u32 fcr; /* Flash Command Register WO */ - u32 fsr; /* Flash Status Register RO */ - u32 frr; /* Flash Result Register RO */ -} at91_eefc_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_EEFC_FMR_FWS_MASK 0x00000f00 -#define AT91_EEFC_FMR_FRDY_BIT 0x00000001 - -#define AT91_EEFC_FCR_KEY 0x5a000000 -#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 -#define AT91_EEFC_FCR_FARG_SHIFT 8 -#define AT91_EEFC_FCR_FCMD_GETD 0x0 -#define AT91_EEFC_FCR_FCMD_WP 0x1 -#define AT91_EEFC_FCR_FCMD_WPL 0x2 -#define AT91_EEFC_FCR_FCMD_EWP 0x3 -#define AT91_EEFC_FCR_FCMD_EWPL 0x4 -#define AT91_EEFC_FCR_FCMD_EA 0x5 -#define AT91_EEFC_FCR_FCMD_SLB 0x8 -#define AT91_EEFC_FCR_FCMD_CLB 0x9 -#define AT91_EEFC_FCR_FCMD_GLB 0xA -#define AT91_EEFC_FCR_FCMD_SGPB 0xB -#define AT91_EEFC_FCR_FCMD_CGPB 0xC -#define AT91_EEFC_FCR_FCMD_GGPB 0xD - -#define AT91_EEFC_FSR_FRDY 1 -#define AT91_EEFC_FSR_FCMDE 2 -#define AT91_EEFC_FSR_FLOCKE 4 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_emac.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_emac.h deleted file mode 100644 index a0d74ab66..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_emac.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_H -#define AT91_H - -typedef struct at91_emac { - u32 ctl; - u32 cfg; - u32 sr; - u32 tar; - u32 tcr; - u32 tsr; - u32 rbqp; - u32 reserved0; - u32 rsr; - u32 isr; - u32 ier; - u32 idr; - u32 imr; - u32 man; - u32 reserved1[2]; - u32 fra; - u32 scol; - u32 mocl; - u32 ok; - u32 seqe; - u32 ale; - u32 dte; - u32 lcol; - u32 ecol; - u32 cse; - u32 tue; - u32 cde; - u32 elr; - u32 rjb; - u32 usf; - u32 sqee; - u32 drfc; - u32 reserved2[3]; - u32 hsh; - u32 hsl; - u32 sa1l; - u32 sa1h; - u32 sa2l; - u32 sa2h; - u32 sa3l; - u32 sa3h; - u32 sa4l; - u32 sa4h; -} at91_emac_t; - -#define AT91_EMAC_CTL_LB 0x0001 -#define AT91_EMAC_CTL_LBL 0x0002 -#define AT91_EMAC_CTL_RE 0x0004 -#define AT91_EMAC_CTL_TE 0x0008 -#define AT91_EMAC_CTL_MPE 0x0010 -#define AT91_EMAC_CTL_CSR 0x0020 -#define AT91_EMAC_CTL_ISR 0x0040 -#define AT91_EMAC_CTL_WES 0x0080 -#define AT91_EMAC_CTL_BP 0x1000 - -#define AT91_EMAC_CFG_SPD 0x0001 -#define AT91_EMAC_CFG_FD 0x0002 -#define AT91_EMAC_CFG_BR 0x0004 -#define AT91_EMAC_CFG_CAF 0x0010 -#define AT91_EMAC_CFG_NBC 0x0020 -#define AT91_EMAC_CFG_MTI 0x0040 -#define AT91_EMAC_CFG_UNI 0x0080 -#define AT91_EMAC_CFG_BIG 0x0100 -#define AT91_EMAC_CFG_EAE 0x0200 -#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF -#define AT91_EMAC_CFG_MCLK_8 0x0000 -#define AT91_EMAC_CFG_MCLK_16 0x0400 -#define AT91_EMAC_CFG_MCLK_32 0x0800 -#define AT91_EMAC_CFG_MCLK_64 0x0C00 -#define AT91_EMAC_CFG_RTY 0x1000 -#define AT91_EMAC_CFG_RMII 0x2000 - -#define AT91_EMAC_SR_LINK 0x0001 -#define AT91_EMAC_SR_MDIO 0x0002 -#define AT91_EMAC_SR_IDLE 0x0004 - -#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF) -#define AT91_EMAC_TCR_NCRC 0x8000 - -#define AT91_EMAC_TSR_OVR 0x0001 -#define AT91_EMAC_TSR_COL 0x0002 -#define AT91_EMAC_TSR_RLE 0x0004 -#define AT91_EMAC_TSR_TXIDLE 0x0008 -#define AT91_EMAC_TSR_BNQ 0x0010 -#define AT91_EMAC_TSR_COMP 0x0020 -#define AT91_EMAC_TSR_UND 0x0040 - -#define AT91_EMAC_RSR_BNA 0x0001 -#define AT91_EMAC_RSR_REC 0x0002 -#define AT91_EMAC_RSR_OVR 0x0004 - -/* ISR, IER, IDR, IMR use the same bits */ -#define AT91_EMAC_IxR_DONE 0x0001 -#define AT91_EMAC_IxR_RCOM 0x0002 -#define AT91_EMAC_IxR_RBNA 0x0004 -#define AT91_EMAC_IxR_TOVR 0x0008 -#define AT91_EMAC_IxR_TUND 0x0010 -#define AT91_EMAC_IxR_RTRY 0x0020 -#define AT91_EMAC_IxR_TBRE 0x0040 -#define AT91_EMAC_IxR_TCOM 0x0080 -#define AT91_EMAC_IxR_TIDLE 0x0100 -#define AT91_EMAC_IxR_LINK 0x0200 -#define AT91_EMAC_IxR_ROVR 0x0400 -#define AT91_EMAC_IxR_HRESP 0x0800 - -#define AT91_EMAC_MAN_DATA_MASK 0xFFFF -#define AT91_EMAC_MAN_CODE_802_3 0x00020000 -#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18) -#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23) -#define AT91_EMAC_MAN_RW_R 0x20000000 -#define AT91_EMAC_MAN_RW_W 0x10000000 -#define AT91_EMAC_MAN_HIGH 0x40000000 -#define AT91_EMAC_MAN_LOW 0x80000000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_gpbr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_gpbr.h deleted file mode 100644 index e781481e8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_gpbr.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * General Purpose Backup Registers - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_GPBR_H -#define AT91_GPBR_H - -/* - * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile - * 32 Bit registers (buffered by the Vbu power). - * - * Please consider carefully before using this resource for tasks - * that do not really need nonvolatile registers. Maybe you can - * store information in EEPROM or FLASH instead. - * - * However, if you use a GPBR please document its use here and - * reference the define in your code! - * - * known typical uses of the GPBRs: - * GPBR[0]: offset for RTT timekeeping (u-boot, kernel) - * GPBR[1]: unused - * GPBR[2]: unused - * GPBR[3]: bootcount (u-boot) - */ -#define AT91_GPBR_INDEX_TIMEOFF 0 -#define AT91_GPBR_INDEX_BOOTCOUNT 3 - -#ifndef __ASSEMBLY__ - -typedef struct at91_gpbr { - u32 reg[4]; -} at91_gpbr_t; - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_matrix.h deleted file mode 100644 index 2379dd40f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_matrix.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_MATRIX_H -#define AT91_MATRIX_H - -#ifdef __ASSEMBLY__ - -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) -#elif defined(CONFIG_AT91SAM9261) -#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) -#elif defined(CONFIG_AT91SAM9263) -#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) -#elif defined(CONFIG_AT91SAM9G45) -#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) -#else -#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU -#endif - -#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX - -#else -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#define AT91_MATRIX_MASTERS 6 -#define AT91_MATRIX_SLAVES 5 -#elif defined(CONFIG_AT91SAM9261) -#define AT91_MATRIX_MASTERS 1 -#define AT91_MATRIX_SLAVES 5 -#elif defined(CONFIG_AT91SAM9263) -#define AT91_MATRIX_MASTERS 9 -#define AT91_MATRIX_SLAVES 7 -#elif defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_MASTERS 11 -#define AT91_MATRIX_SLAVES 8 -#else -#error CPU not supported. Please update at91_matrix.h -#endif - -typedef struct at91_priority { - u32 a; - u32 b; -} at91_priority_t; - -typedef struct at91_matrix { - u32 mcfg[AT91_MATRIX_MASTERS]; -#if defined(CONFIG_AT91SAM9261) - u32 scfg[AT91_MATRIX_SLAVES]; - u32 res61_1[3]; - u32 tcr; - u32 res61_2[2]; - u32 csa; - u32 pucr; - u32 res61_3[114]; -#else - u32 reserve1[16 - AT91_MATRIX_MASTERS]; - u32 scfg[AT91_MATRIX_SLAVES]; - u32 reserve2[16 - AT91_MATRIX_SLAVES]; - at91_priority_t pr[AT91_MATRIX_SLAVES]; - u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; - u32 mrcr; /* 0x100 Master Remap Control */ - u32 reserve4[3]; -#if defined(CONFIG_AT91SAM9G45) - u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ - u32 womr; /* 0x1E4 Write Protect Mode */ - u32 wpsr; /* 0x1E8 Write Protect Status */ - u32 resg45_1[10]; -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) - u32 res60_1[3]; - u32 csa; - u32 res60_2[56]; -#elif defined(CONFIG_AT91SAM9263) - u32 res63_1; - u32 tcmr; - u32 res63_2[2]; - u32 csa[2]; - u32 res63_3[54]; -#else - u32 reserve5[60]; -#endif -#endif -} at91_matrix_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_CSA_DBPUC 0x00000100 -#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 -#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 - -#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 -#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 -#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 -#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 - -#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 - -#if defined CONFIG_AT91SAM9261 -/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_MCFG_RCB0 (1 << 0) -/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_MCFG_RCB1 (1 << 1) -#endif - -/* Undefined Length Burst Type */ -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ - defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 -#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 -#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 -#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 -#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 -#endif -#if defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 -#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 -#define AT91_MATRIX_MCFG_ULBT_128 0x00000007 -#endif - -/* Default Master Type */ -#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 -#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 -#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 - -/* Fixed Index of Default Master */ -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) -#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) -#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) -#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) -#endif - -/* Maximum Number of Allowed Cycles for a Burst */ -#if defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9263) -#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) -#endif - -/* Arbitration Type */ -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) -#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 -#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 -#endif - -/* Master Remap Control Register */ -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ - defined(CONFIG_AT91SAM9G45) -/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_MRCR_RCB0 (1 << 0) -/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_MRCR_RCB1 (1 << 1) -#endif -#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_MRCR_RCB2 0x00000004 -#define AT91_MATRIX_MRCR_RCB3 0x00000008 -#define AT91_MATRIX_MRCR_RCB4 0x00000010 -#define AT91_MATRIX_MRCR_RCB5 0x00000020 -#define AT91_MATRIX_MRCR_RCB6 0x00000040 -#define AT91_MATRIX_MRCR_RCB7 0x00000080 -#define AT91_MATRIX_MRCR_RCB8 0x00000100 -#endif -#if defined(CONFIG_AT91SAM9G45) -#define AT91_MATRIX_MRCR_RCB9 0x00000200 -#define AT91_MATRIX_MRCR_RCB10 0x00000400 -#define AT91_MATRIX_MRCR_RCB11 0x00000800 -#endif - -/* TCM Configuration Register */ -#if defined(CONFIG_AT91SAM9G45) -/* Size of ITCM enabled memory block */ -#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 -#define AT91_MATRIX_TCMR_ITCM_32 0x00000040 -/* Size of DTCM enabled memory block */ -#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 -#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 -#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 -/* Wait state TCM register */ -#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 -#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 -#endif -#if defined(CONFIG_AT91SAM9263) -/* Size of ITCM enabled memory block */ -#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 -#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 -#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 -/* Size of DTCM enabled memory block */ -#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 -#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 -#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 -#endif -#if defined(CONFIG_AT91SAM9261) -/* Size of ITCM enabled memory block */ -#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 -#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 -#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 -#define AT91_MATRIX_TCMR_ITCM_64 0x00000007 -/* Size of DTCM enabled memory block */ -#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 -#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 -#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 -#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 -#endif - -#if defined(CONFIG_AT91SAM9G45) -/* Video Mode Configuration Register */ -#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 -#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 -/* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 -#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 -#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ -/* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_NO_WPV 0x00000000 -#define AT91_MATRIX_WPSR_WPV 0x00000001 -#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ -#endif - -/* USB Pad Pull-Up Control Register */ -#if defined(CONFIG_AT91SAM9261) -#define AT91_MATRIX_USBPUCR_PUON 0x40000000 -#endif - -#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ -#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ -#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ -#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ -#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_mc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_mc.h deleted file mode 100644 index 2ace77931..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_mc.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_MC_H -#define AT91_MC_H - -#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60) -#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64) -#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70) -#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90) -#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94) -#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98) - -#ifndef __ASSEMBLY__ - -typedef struct at91_ebi { - u32 csa; /* 0x00 Chip Select Assignment Register */ - u32 cfgr; /* 0x04 Configuration Register */ - u32 reserved[2]; -} at91_ebi_t; - -#define AT91_EBI_CSA_CS0A 0x0001 -#define AT91_EBI_CSA_CS1A 0x0002 - -#define AT91_EBI_CSA_CS3A 0x0008 -#define AT91_EBI_CSA_CS4A 0x0010 - -typedef struct at91_sdramc { - u32 mr; /* 0x00 SDRAMC Mode Register */ - u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ - u32 cr; /* 0x08 SDRAMC Configuration Register */ - u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ - u32 lpr; /* 0x10 SDRAMC Low Power Register */ - u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ - u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ - u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ - u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ - u32 reserved[3]; -} at91_sdramc_t; - -typedef struct at91_smc { - u32 csr[8]; /* 0x00 SDRAMC Mode Register */ -} at91_smc_t; - -#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) -#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) -#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 -#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 -#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 -#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 -#define AT91_SMC_CSR_DRP 0x00008000 -#define AT91_SMC_CSR_DBW_8 0x00004000 -#define AT91_SMC_CSR_DBW_16 0x00002000 -#define AT91_SMC_CSR_BAT_8 0x00000000 -#define AT91_SMC_CSR_BAT_16 0x00001000 -#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) -#define AT91_SMC_CSR_WSEN 0x00000080 -#define AT91_SMC_CSR_NWS(x) (x & 0x7F) - -typedef struct at91_bfc { - u32 mr; /* 0x00 SDRAMC Mode Register */ -} at91_bfc_t; - -typedef struct at91_mc { - u32 rcr; /* 0x00 MC Remap Control Register */ - u32 asr; /* 0x04 MC Abort Status Register */ - u32 aasr; /* 0x08 MC Abort Address Status Reg */ - u32 mpr; /* 0x0C MC Master Priority Register */ - u32 reserved1[20]; /* 0x10-0x5C */ - at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ - at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ - at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ - at91_bfc_t bfc; /* 0xC0 BFC User Interface */ - u32 reserved2[15]; -} at91_mc_t; - -#endif -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pdc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pdc.h deleted file mode 100644 index 832ebb51c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pdc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_PDC_H -#define AT91_PDC_H - -typedef struct at91_pdc { - u32 rpr; /* 0x100 Receive Pointer Register */ - u32 rcr; /* 0x104 Receive Counter Register */ - u32 tpr; /* 0x108 Transmit Pointer Register */ - u32 tcr; /* 0x10C Transmit Counter Register */ - u32 pnpr; /* 0x110 Receive Next Pointer Register */ - u32 pncr; /* 0x114 Receive Next Counter Register */ - u32 tnpr; /* 0x118 Transmit Next Pointer Register */ - u32 tncr; /* 0x11C Transmit Next Counter Register */ - u32 ptcr; /* 0x120 Transfer Control Register */ - u32 ptsr; /* 0x124 Transfer Status Register */ -} at91_pdc_t; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pio.h deleted file mode 100644 index 50464ffe8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pio.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * Parallel I/O Controller (PIO) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_PIO_H -#define AT91_PIO_H - - -#define AT91_ASM_PIO_RANGE 0x200 -#define AT91_ASM_PIOC_ASR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) -#define AT91_ASM_PIOC_BSR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) -#define AT91_ASM_PIOC_PDR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) -#define AT91_ASM_PIOC_PUDR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) - -#define AT91_ASM_PIOD_PDR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) -#define AT91_ASM_PIOD_PUDR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) -#define AT91_ASM_PIOD_ASR \ - (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) - -#ifndef __ASSEMBLY__ - -typedef struct at91_port { - u32 per; /* 0x00 PIO Enable Register */ - u32 pdr; /* 0x04 PIO Disable Register */ - u32 psr; /* 0x08 PIO Status Register */ - u32 reserved0; - u32 oer; /* 0x10 Output Enable Register */ - u32 odr; /* 0x14 Output Disable Registerr */ - u32 osr; /* 0x18 Output Status Register */ - u32 reserved1; - u32 ifer; /* 0x20 Input Filter Enable Register */ - u32 ifdr; /* 0x24 Input Filter Disable Register */ - u32 ifsr; /* 0x28 Input Filter Status Register */ - u32 reserved2; - u32 sodr; /* 0x30 Set Output Data Register */ - u32 codr; /* 0x34 Clear Output Data Register */ - u32 odsr; /* 0x38 Output Data Status Register */ - u32 pdsr; /* 0x3C Pin Data Status Register */ - u32 ier; /* 0x40 Interrupt Enable Register */ - u32 idr; /* 0x44 Interrupt Disable Register */ - u32 imr; /* 0x48 Interrupt Mask Register */ - u32 isr; /* 0x4C Interrupt Status Register */ - u32 mder; /* 0x50 Multi-driver Enable Register */ - u32 mddr; /* 0x54 Multi-driver Disable Register */ - u32 mdsr; /* 0x58 Multi-driver Status Register */ - u32 reserved3; - u32 pudr; /* 0x60 Pull-up Disable Register */ - u32 puer; /* 0x64 Pull-up Enable Register */ - u32 pusr; /* 0x68 Pad Pull-up Status Register */ - u32 reserved4; -#if defined(CPU_HAS_PIO3) - u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ - u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ - u32 reserved5[2]; - u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ - u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ - u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ - u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ - u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ - u32 ppder; /* 0x94 Pad Pull-down Enable Register */ - u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ - u32 reserved6; /* */ -#else - u32 asr; /* 0x70 Select A Register */ - u32 bsr; /* 0x74 Select B Register */ - u32 absr; /* 0x78 AB Select Status Register */ - u32 reserved5[9]; /* */ -#endif - u32 ower; /* 0xA0 Output Write Enable Register */ - u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 Output Write Status Register */ -#if defined(CPU_HAS_PIO3) - u32 reserved7; /* */ - u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ - u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ - u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ - u32 reserved8; /* */ - u32 esr; /* 0xC0 Edge Select Register */ - u32 lsr; /* 0xC4 Level Select Register */ - u32 elsr; /* 0xC8 Edge/Level Status Register */ - u32 reserved9; /* 0xCC */ - u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ - u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ - u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ - u32 reserved10; /* */ - u32 locksr; /* 0xE0 Lock Status */ - u32 wpmr; /* 0xE4 Write Protect Mode Register */ - u32 wpsr; /* 0xE8 Write Protect Status Register */ - u32 reserved11[5]; /* */ - u32 schmitt; /* 0x100 Schmitt Trigger Register */ - u32 reserved12[63]; -#else - u32 reserved6[85]; -#endif -} at91_port_t; - -typedef union at91_pio { - struct { - at91_port_t pioa; - at91_port_t piob; - at91_port_t pioc; - #if (ATMEL_PIO_PORTS > 3) - at91_port_t piod; - #endif - #if (ATMEL_PIO_PORTS > 4) - at91_port_t pioe; - #endif - } ; - at91_port_t port[ATMEL_PIO_PORTS]; -} at91_pio_t; - -#ifdef CONFIG_AT91_GPIO -int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); -#if defined(CPU_HAS_PIO3) -int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); -int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); -int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); -#endif -int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); -int at91_set_pio_output(unsigned port, unsigned pin, int value); -int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); -int at91_set_pio_value(unsigned port, unsigned pin, int value); -int at91_get_pio_value(unsigned port, unsigned pin); -#endif -#endif - -#define AT91_PIO_PORTA 0x0 -#define AT91_PIO_PORTB 0x1 -#define AT91_PIO_PORTC 0x2 -#define AT91_PIO_PORTD 0x3 -#define AT91_PIO_PORTE 0x4 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pit.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pit.h deleted file mode 100644 index 56724f15e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pit.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Periodic Interval Timer (PIT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_PIT_H -#define AT91_PIT_H - -typedef struct at91_pit { - u32 mr; /* 0x00 Mode Register */ - u32 sr; /* 0x04 Status Register */ - u32 pivr; /* 0x08 Periodic Interval Value Register */ - u32 piir; /* 0x0C Periodic Interval Image Register */ -} at91_pit_t; - -#define AT91_PIT_MR_IEN 0x02000000 -#define AT91_PIT_MR_EN 0x01000000 -#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff) -#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pmc.h deleted file mode 100644 index 453560843..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pmc.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#ifdef __ASSEMBLY__ - -#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) -#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) -#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) -#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) -#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) - -#else - -#include <asm/types.h> - -typedef struct at91_pmc { - u32 scer; /* 0x00 System Clock Enable Register */ - u32 scdr; /* 0x04 System Clock Disable Register */ - u32 scsr; /* 0x08 System Clock Status Register */ - u32 reserved0; - u32 pcer; /* 0x10 Peripheral Clock Enable Register */ - u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ - u32 pcsr; /* 0x18 Peripheral Clock Status Register */ - u32 uckr; /* 0x1C UTMI Clock Register */ - u32 mor; /* 0x20 Main Oscilator Register */ - u32 mcfr; /* 0x24 Main Clock Frequency Register */ - u32 pllar; /* 0x28 PLL A Register */ - u32 pllbr; /* 0x2C PLL B Register */ - u32 mckr; /* 0x30 Master Clock Register */ - u32 reserved1; - u32 usb; /* 0x38 USB Clock Register */ - u32 reserved2; - u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ - u32 reserved3[4]; - u32 ier; /* 0x60 Interrupt Enable Register */ - u32 idr; /* 0x64 Interrupt Disable Register */ - u32 sr; /* 0x68 Status Register */ - u32 imr; /* 0x6C Interrupt Mask Register */ - u32 reserved4[4]; - u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ - u32 reserved5[21]; - u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ - u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ -#ifdef CONFIG_SAMA5D3 - u32 reserved6[8]; - u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */ - u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */ - u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */ - u32 pcr; /* 0x10c Periperial Control Register */ - u32 ocr; /* 0x110 Oscillator Calibration Register */ -#else - u32 reserved8[5]; -#endif -} at91_pmc_t; - -#endif /* end not assembly */ - -#define AT91_PMC_MOR_MOSCEN 0x01 -#define AT91_PMC_MOR_OSCBYPASS 0x02 -#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) - -#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) -#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) -#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#ifdef CONFIG_SAMA5D3 -#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) -#else -#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) -#endif -#define AT91_PMC_PLLAR_29 0x20000000 -#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 -#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 -#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 - -#define AT91_PMC_MCFR_MAINRDY 0x00010000 -#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF - -#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 -#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 -#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 -#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 -#define AT91_PMC_MCKR_CSS_MASK 0x00000003 - -#ifdef CONFIG_SAMA5D3 -#define AT91_PMC_MCKR_PRES_1 0x00000000 -#define AT91_PMC_MCKR_PRES_2 0x00000010 -#define AT91_PMC_MCKR_PRES_4 0x00000020 -#define AT91_PMC_MCKR_PRES_8 0x00000030 -#define AT91_PMC_MCKR_PRES_16 0x00000040 -#define AT91_PMC_MCKR_PRES_32 0x00000050 -#define AT91_PMC_MCKR_PRES_64 0x00000060 -#define AT91_PMC_MCKR_PRES_MASK 0x00000070 -#else -#define AT91_PMC_MCKR_PRES_1 0x00000000 -#define AT91_PMC_MCKR_PRES_2 0x00000004 -#define AT91_PMC_MCKR_PRES_4 0x00000008 -#define AT91_PMC_MCKR_PRES_8 0x0000000C -#define AT91_PMC_MCKR_PRES_16 0x00000010 -#define AT91_PMC_MCKR_PRES_32 0x00000014 -#define AT91_PMC_MCKR_PRES_64 0x00000018 -#define AT91_PMC_MCKR_PRES_MASK 0x0000001C -#endif - -#ifdef CONFIG_AT91RM9200 -#define AT91_PMC_MCKR_MDIV_1 0x00000000 -#define AT91_PMC_MCKR_MDIV_2 0x00000100 -#define AT91_PMC_MCKR_MDIV_3 0x00000200 -#define AT91_PMC_MCKR_MDIV_4 0x00000300 -#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 -#else -#define AT91_PMC_MCKR_MDIV_1 0x00000000 -#define AT91_PMC_MCKR_MDIV_2 0x00000100 -#ifdef CONFIG_SAMA5D3 -#define AT91_PMC_MCKR_MDIV_3 0x00000300 -#endif -#define AT91_PMC_MCKR_MDIV_4 0x00000200 -#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 -#endif - -#define AT91_PMC_MCKR_PLLADIV_1 0x00000000 -#define AT91_PMC_MCKR_PLLADIV_2 0x00001000 - -#define AT91_PMC_IXR_MOSCS 0x00000001 -#define AT91_PMC_IXR_LOCKA 0x00000002 -#define AT91_PMC_IXR_LOCKB 0x00000004 -#define AT91_PMC_IXR_MCKRDY 0x00000008 -#define AT91_PMC_IXR_LOCKU 0x00000040 -#define AT91_PMC_IXR_PCKRDY0 0x00000100 -#define AT91_PMC_IXR_PCKRDY1 0x00000200 -#define AT91_PMC_IXR_PCKRDY2 0x00000400 -#define AT91_PMC_IXR_PCKRDY3 0x00000800 - -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ - -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ - -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ - -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << 2) -#define AT91_PMC_PRES_2 (1 << 2) -#define AT91_PMC_PRES_4 (2 << 2) -#define AT91_PMC_PRES_8 (3 << 2) -#define AT91_PMC_PRES_16 (4 << 2) -#define AT91_PMC_PRES_32 (5 << 2) -#define AT91_PMC_PRES_64 (6 << 2) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_6 (3 << 8) -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) - -#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ -#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ -#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ -#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */ -#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ -#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ - -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ -#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ - -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rstc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rstc.h deleted file mode 100644 index a9423428e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rstc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Reset Controller (RSTC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_RSTC_H -#define AT91_RSTC_H - -#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08) - -#ifndef __ASSEMBLY__ - -typedef struct at91_rstc { - u32 cr; /* Reset Controller Control Register */ - u32 sr; /* Reset Controller Status Register */ - u32 mr; /* Reset Controller Mode Register */ -} at91_rstc_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_RSTC_KEY 0xA5000000 - -#define AT91_RSTC_CR_PROCRST 0x00000001 -#define AT91_RSTC_CR_PERRST 0x00000004 -#define AT91_RSTC_CR_EXTRST 0x00000008 - -#define AT91_RSTC_MR_URSTEN 0x00000001 -#define AT91_RSTC_MR_URSTIEN 0x00000010 -#define AT91_RSTC_MR_ERSTL(x) ((x & 0xf) << 8) -#define AT91_RSTC_MR_ERSTL_MASK 0x0000FF00 - -#define AT91_RSTC_SR_NRSTL 0x00010000 - -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rtt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rtt.h deleted file mode 100644 index fe7619a93..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rtt.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Real-time Timer - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_RTT_H -#define AT91_RTT_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_rtt { - u32 mr; /* Mode Register RW 0x00008000 */ - u32 ar; /* Alarm Register RW 0xFFFFFFFF */ - u32 vr; /* Value Register RO 0x00000000 */ - u32 sr; /* Status Register RO 0x00000000 */ -} at91_rtt_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_RTT_MR_RTPRES 0x0000ffff -#define AT91_RTT_MR_ALMIEN 0x00010000 -#define AT91_RTT_RTTINCIEN 0x00020000 -#define AT91_RTT_RTTRST 0x00040000 - -#define AT91_RTT_SR_ALMS 0x00000001 -#define AT91_RTT_SR_RTTINC 0x00000002 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_shdwn.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_shdwn.h deleted file mode 100644 index 18d9ea690..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_shdwn.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Shutdown Controller - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_SHDWN_H -#define AT91_SHDWN_H - -#ifndef __ASSEMBLY__ - -struct at91_shdwn { - u32 cr; /* Control Rer. WO */ - u32 mr; /* Mode Register RW 0x00000003 */ - u32 sr; /* Status Register RO 0x00000000 */ -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_SHDW_CR_KEY 0xa5000000 -#define AT91_SHDW_CR_SHDW 0x00000001 - -#define AT91_SHDW_MR_RTTWKEN 0x00010000 -#define AT91_SHDW_MR_CPTWK0 0x000000f0 -#define AT91_SHDW_MR_WKMODE0H2L 0x00000002 -#define AT91_SHDW_MR_WKMODE0L2H 0x00000001 - -#define AT91_SHDW_SR_RTTWK 0x00010000 -#define AT91_SHDW_SR_WAKEUP0 0x00000001 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_spi.h deleted file mode 100644 index b18665b62..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_spi.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Serial Peripheral Interface (SPI) registers. - * Based on AT91RM9200 datasheet revision E. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_SPI_H -#define AT91_SPI_H - -#include <asm/arch/at91_pdc.h> - -typedef struct at91_spi { - u32 cr; /* 0x00 Control Register */ - u32 mr; /* 0x04 Mode Register */ - u32 rdr; /* 0x08 Receive Data Register */ - u32 tdr; /* 0x0C Transmit Data Register */ - u32 sr; /* 0x10 Status Register */ - u32 ier; /* 0x14 Interrupt Enable Register */ - u32 idr; /* 0x18 Interrupt Disable Register */ - u32 imr; /* 0x1C Interrupt Mask Register */ - u32 reserve1[4]; - u32 csr[4]; /* 0x30 Chip Select Register 0-3 */ - u32 reserve2[48]; - at91_pdc_t pdc; -} at91_spi_t; - -#ifdef CONFIG_ATMEL_LEGACY - -#define AT91_SPI_CR 0x00 /* Control Register */ -#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ -#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ -#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ - -#define AT91_SPI_MR 0x04 /* Mode Register */ -#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ -#define AT91_SPI_PS (1 << 1) /* Peripheral Select */ -#define AT91_SPI_PS_FIXED (0 << 1) -#define AT91_SPI_PS_VARIABLE (1 << 1) -#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ -#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ -#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ -#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ -#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ - -#define AT91_SPI_RDR 0x08 /* Receive Data Register */ -#define AT91_SPI_RD (0xffff << 0) /* Receive Data */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ - -#define AT91_SPI_TDR 0x0c /* Transmit Data Register */ -#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ -#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ -#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ - -#define AT91_SPI_SR 0x10 /* Status Register */ -#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ -#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ -#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ -#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ -#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ -#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ -#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ -#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ -#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ -#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ -#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ - -#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ -#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ -#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ - -#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ -#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ -#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ -#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ -#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ -#define AT91_SPI_BITS_8 (0 << 4) -#define AT91_SPI_BITS_9 (1 << 4) -#define AT91_SPI_BITS_10 (2 << 4) -#define AT91_SPI_BITS_11 (3 << 4) -#define AT91_SPI_BITS_12 (4 << 4) -#define AT91_SPI_BITS_13 (5 << 4) -#define AT91_SPI_BITS_14 (6 << 4) -#define AT91_SPI_BITS_15 (7 << 4) -#define AT91_SPI_BITS_16 (8 << 4) -#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ -#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ -#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ - -#define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */ - -#define AT91_SPI_RCR 0x0104 /* Receive Counter Register */ - -#define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */ - -#define AT91_SPI_TCR 0x010c /* Transmit Counter Register */ - -#define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */ - -#define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */ - -#define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */ - -#define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */ - -#define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */ -#define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */ -#define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */ -#define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */ -#define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */ - -#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */ - -#endif /* CONFIG_ATMEL_LEGACY */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_st.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_st.h deleted file mode 100644 index b1ee1472e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_st.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_ST_H -#define AT91_ST_H - -typedef struct at91_st { - - u32 cr; - u32 pimr; - u32 wdmr; - u32 rtmr; - u32 sr; - u32 ier; - u32 idr; - u32 imr; - u32 rtar; - u32 crtr; -} at91_st_t ; - -#define AT91_ST_CR_WDRST 1 - -#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF) -#define AT91_ST_WDMR_RSTEN 0x00010000 -#define AT91_ST_WDMR_EXTEN 0x00020000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_tc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_tc.h deleted file mode 100644 index de0e26656..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_tc.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_TC_H -#define AT91_TC_H - -typedef struct at91_tcc { - u32 ccr; /* 0x00 Channel Control Register */ - u32 cmr; /* 0x04 Channel Mode Register */ - u32 reserved1[2]; - u32 cv; /* 0x10 Counter Value */ - u32 ra; /* 0x14 Register A */ - u32 rb; /* 0x18 Register B */ - u32 rc; /* 0x1C Register C */ - u32 sr; /* 0x20 Status Register */ - u32 ier; /* 0x24 Interrupt Enable Register */ - u32 idr; /* 0x28 Interrupt Disable Register */ - u32 imr; /* 0x2C Interrupt Mask Register */ - u32 reserved3[4]; -} at91_tcc_t; - -#define AT91_TC_CCR_CLKEN 0x00000001 -#define AT91_TC_CCR_CLKDIS 0x00000002 -#define AT91_TC_CCR_SWTRG 0x00000004 - -#define AT91_TC_CMR_CPCTRG 0x00004000 - -#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 -#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 -#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 -#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 -#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 -#define AT91_TC_CMR_TCCLKS_XC0 0x00000005 -#define AT91_TC_CMR_TCCLKS_XC1 0x00000006 -#define AT91_TC_CMR_TCCLKS_XC2 0x00000007 - -typedef struct at91_tc { - at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ - u32 bcr; /* 0xC0 TC Block Control Register */ - u32 bmr; /* 0xC4 TC Block Mode Register */ -} at91_tc_t; - -#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 -#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 -#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 -#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 - -#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 -#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 -#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 -#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C - -#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 -#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 -#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 -#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_wdt.h deleted file mode 100644 index 0644bbf3c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_wdt.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Watchdog Timer (WDT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_WDT_H -#define AT91_WDT_H - -#ifdef __ASSEMBLY__ - -#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04) - -#else - -typedef struct at91_wdt { - u32 cr; - u32 mr; - u32 sr; -} at91_wdt_t; - -#endif - -#define AT91_WDT_CR_WDRSTT 1 -#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ - -#define AT91_WDT_MR_WDV(x) (x & 0xfff) -#define AT91_WDT_MR_WDFIEN 0x00001000 -#define AT91_WDT_MR_WDRSTEN 0x00002000 -#define AT91_WDT_MR_WDRPROC 0x00004000 -#define AT91_WDT_MR_WDDIS 0x00008000 -#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) -#define AT91_WDT_MR_WDDBGHLT 0x10000000 -#define AT91_WDT_MR_WDIDLEHLT 0x20000000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9.h deleted file mode 100644 index 63870bc65..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h] - * - * Copyright (C) 2007 Stelian Pop <stelian@popies.net> - * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> - * Copyright (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91CAP9 datasheet revision B (Preliminary). - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91CAP9_H -#define AT91CAP9_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ -#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ -#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ -#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ -#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ -#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ -#define AT91CAP9_ID_US0 8 /* USART 0 */ -#define AT91CAP9_ID_US1 9 /* USART 1 */ -#define AT91CAP9_ID_US2 10 /* USART 2 */ -#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ -#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ -#define AT91CAP9_ID_CAN 13 /* CAN */ -#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ -#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ -#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ -#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ -#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ -#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ -#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ -#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ -#define AT91CAP9_ID_EMAC 22 /* Ethernet */ -#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ -#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ -#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ -#define AT91CAP9_ID_LCDC 26 /* LCD Controller */ -#define AT91CAP9_ID_DMA 27 /* DMA Controller */ -#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ -#define AT91CAP9_ID_UHP 29 /* USB Host Port */ -#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 - -/* - * Internal Memory. - */ -#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ -#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ - -#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ - -#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ -#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ - -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 - -/* - * Cpu Name - */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9" - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9_matrix.h deleted file mode 100644 index 009a19daf..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9_matrix.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h] - * - * Copyright (C) 2007 Stelian Pop <stelian@popies.net> - * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91CAP9 datasheet revision B (Preliminary). - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91CAP9_MATRIX_H -#define AT91CAP9_MATRIX_H - -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ -#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ -#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ -#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */ -#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) - -#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ -#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */ -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) - -#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */ -#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */ -#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91rm9200.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91rm9200.h deleted file mode 100644 index 25bb071e9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91rm9200.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AT91RM9200_H__ -#define __AT91RM9200_H__ - -#define CONFIG_AT91FAMILY /* it's a member of AT91 family */ -#define CONFIG_ARM920T /* it's an ARM920T Core */ -#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */ -#define CONFIG_AT91_GPIO /* and require always gpio features */ - -/* Periperial Identifiers */ - -#define ATMEL_ID_SYS 1 /* System Peripheral */ -#define ATMEL_ID_PIOA 2 /* PIO port A */ -#define ATMEL_ID_PIOB 3 /* PIO port B */ -#define ATMEL_ID_PIOC 4 /* PIO port C */ -#define ATMEL_ID_PIOD 5 /* PIO port D BGA only */ -#define ATMEL_ID_USART0 6 /* USART 0 */ -#define ATMEL_ID_USART1 7 /* USART 1 */ -#define ATMEL_ID_USART2 8 /* USART 2 */ -#define ATMEL_ID_USART3 9 /* USART 3 */ -#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ -#define ATMEL_ID_UDP 11 /* USB Device Port */ -#define ATMEL_ID_TWI 12 /* Two Wire Interface */ -#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ -#define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */ -#define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */ -#define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */ -#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ -#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ -#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ -#define ATMEL_ID_TC3 20 /* Timer Counter 3 */ -#define ATMEL_ID_TC4 21 /* Timer Counter 4 */ -#define ATMEL_ID_TC5 22 /* Timer Counter 5 */ -#define ATMEL_ID_UHP 23 /* OHCI USB Host Port */ -#define ATMEL_ID_EMAC 24 /* Ethernet MAC */ -#define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */ -#define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */ -#define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */ -#define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */ -#define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */ -#define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */ -#define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */ - -#define ATMEL_USB_HOST_BASE 0x00300000 - -#define ATMEL_BASE_TC 0xFFFA0000 -#define ATMEL_BASE_UDP 0xFFFB0000 -#define ATMEL_BASE_MCI 0xFFFB4000 -#define ATMEL_BASE_TWI 0xFFFB8000 -#define ATMEL_BASE_EMAC 0xFFFBC000 -#define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */ -#define ATMEL_BASE_USART0 ATMEL_BASE_USART -#define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000) -#define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000) -#define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000) - -#define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */ -#define ATMEL_BASE_SPI 0xFFFE0000 - -#define ATMEL_BASE_AIC 0xFFFFF000 -#define ATMEL_BASE_DBGU 0xFFFFF200 -#define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */ -#define ATMEL_BASE_PIOA 0xFFFFF400 -#define ATMEL_BASE_PIOB 0xFFFFF600 -#define ATMEL_BASE_PIOC 0xFFFFF800 -#define ATMEL_BASE_PIOD 0xFFFFFA00 -#define ATMEL_BASE_PMC 0xFFFFFC00 -#define ATMEL_BASE_ST 0xFFFFFD00 -#define ATMEL_BASE_RTC 0xFFFFFE00 -#define ATMEL_BASE_MC 0xFFFFFF00 - -#define AT91_PIO_BASE ATMEL_BASE_PIO - -/* AT91RM9200 Periperial Multiplexing A */ -/* Port A */ -#define ATMEL_PMX_AA_EREFCK 0x00000080 -#define ATMEL_PMX_AA_ETXCK 0x00000080 -#define ATMEL_PMX_AA_ETXEN 0x00000100 -#define ATMEL_PMX_AA_ETX0 0x00000200 -#define ATMEL_PMX_AA_ETX1 0x00000400 -#define ATMEL_PMX_AA_ECRS 0x00000800 -#define ATMEL_PMX_AA_ECRSDV 0x00000800 -#define ATMEL_PMX_AA_ERX0 0x00001000 -#define ATMEL_PMX_AA_ERX1 0x00002000 -#define ATMEL_PMX_AA_ERXER 0x00004000 -#define ATMEL_PMX_AA_EMDC 0x00008000 -#define ATMEL_PMX_AA_EMDIO 0x00010000 - -#define ATMEL_PMX_AA_TXD2 0x00800000 - -#define ATMEL_PMX_AA_TWD 0x02000000 -#define ATMEL_PMX_AA_TWCK 0x04000000 - -/* Port B */ -#define ATMEL_PMX_BA_ERXCK 0x00080000 -#define ATMEL_PMX_BA_ECOL 0x00040000 -#define ATMEL_PMX_BA_ERXDV 0x00020000 -#define ATMEL_PMX_BA_ERX3 0x00010000 -#define ATMEL_PMX_BA_ERX2 0x00008000 -#define ATMEL_PMX_BA_ETXER 0x00004000 -#define ATMEL_PMX_BA_ETX3 0x00002000 -#define ATMEL_PMX_BA_ETX2 0x00001000 - -/* Port B */ - -#define ATMEL_PMX_CA_BFCK 0x00000001 -#define ATMEL_PMX_CA_BFRDY 0x00000002 -#define ATMEL_PMX_CA_SMOE 0x00000002 -#define ATMEL_PMX_CA_BFAVD 0x00000004 -#define ATMEL_PMX_CA_BFBAA 0x00000008 -#define ATMEL_PMX_CA_SMWE 0x00000008 -#define ATMEL_PMX_CA_BFOE 0x00000010 -#define ATMEL_PMX_CA_BFWE 0x00000020 -#define ATMEL_PMX_CA_NWAIT 0x00000040 -#define ATMEL_PMX_CA_A23 0x00000080 -#define ATMEL_PMX_CA_A24 0x00000100 -#define ATMEL_PMX_CA_A25 0x00000200 -#define ATMEL_PMX_CA_CFRNW 0x00000200 -#define ATMEL_PMX_CA_NCS4 0x00000400 -#define ATMEL_PMX_CA_CFCS 0x00000400 -#define ATMEL_PMX_CA_NCS5 0x00000800 -#define ATMEL_PMX_CA_CFCE1 0x00001000 -#define ATMEL_PMX_CA_NCS6 0x00001000 -#define ATMEL_PMX_CA_CFCE2 0x00002000 -#define ATMEL_PMX_CA_NCS7 0x00002000 -#define ATMEL_PMX_CA_D16_31 0xFFFF0000 - -#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */ -#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP - -#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200" - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260.h deleted file mode 100644 index 2e902eef3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] - * - * (C) 2006 Andrew Victor - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * Definitions for the SoCs: - * AT91SAM9260, AT91SAM9G20, AT91SAM9XE - * - * Note that those SoCs are mostly software and pin compatible, - * therefore this file applies to all of them. Differences between - * those SoCs are concentrated at the end of this file. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * defines to be used in other places - */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Peripherals */ -#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ -#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ -#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ -#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */ -#define ATMEL_ID_USART0 6 /* USART 0 */ -#define ATMEL_ID_USART1 7 /* USART 1 */ -#define ATMEL_ID_USART2 8 /* USART 2 */ -#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ -#define ATMEL_ID_UDP 10 /* USB Device Port */ -#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ -#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -/* Reserved: 15 */ -/* Reserved: 16 */ -#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ -#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ -#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ -#define ATMEL_ID_UHP 20 /* USB Host port */ -#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */ -#define ATMEL_ID_ISI 22 /* Image Sensor Interface */ -#define ATMEL_ID_USART3 23 /* USART 3 */ -#define ATMEL_ID_USART4 24 /* USART 4 */ -/* USART5 or TWI1: 25 */ -#define ATMEL_ID_TC3 26 /* Timer Counter 3 */ -#define ATMEL_ID_TC4 27 /* Timer Counter 4 */ -#define ATMEL_ID_TC5 28 /* Timer Counter 5 */ -#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -/* - * User Peripherals physical base addresses. - */ -#define ATMEL_BASE_TCB0 0xfffa0000 -#define ATMEL_BASE_TC0 0xfffa0000 -#define ATMEL_BASE_TC1 0xfffa0040 -#define ATMEL_BASE_TC2 0xfffa0080 -#define ATMEL_BASE_UDP0 0xfffa4000 -#define ATMEL_BASE_MCI 0xfffa8000 -#define ATMEL_BASE_TWI0 0xfffac000 -#define ATMEL_BASE_USART0 0xfffb0000 -#define ATMEL_BASE_USART1 0xfffb4000 -#define ATMEL_BASE_USART2 0xfffb8000 -#define ATMEL_BASE_SSC0 0xfffbc000 -#define ATMEL_BASE_ISI0 0xfffc0000 -#define ATMEL_BASE_EMAC0 0xfffc4000 -#define ATMEL_BASE_SPI0 0xfffc8000 -#define ATMEL_BASE_SPI1 0xfffcc000 -#define ATMEL_BASE_USART3 0xfffd0000 -#define ATMEL_BASE_USART4 0xfffd4000 -/* USART5 or TWI1: 0xfffd8000 */ -#define ATMEL_BASE_TCB1 0xfffdc000 -#define ATMEL_BASE_TC3 0xfffdc000 -#define ATMEL_BASE_TC4 0xfffdc040 -#define ATMEL_BASE_TC5 0xfffdc080 -#define ATMEL_BASE_ADC 0xfffe0000 -/* Reserved: 0xfffe4000 - 0xffffe7ff */ - -/* - * System Peripherals physical base addresses. - */ -#define ATMEL_BASE_SYS 0xffffe800 -#define ATMEL_BASE_SDRAMC 0xffffea00 -#define ATMEL_BASE_SMC 0xffffec00 -#define ATMEL_BASE_MATRIX 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_DBGU 0xfffff200 -#define ATMEL_BASE_PIOA 0xfffff400 -#define ATMEL_BASE_PIOB 0xfffff600 -#define ATMEL_BASE_PIOC 0xfffff800 -/* EEFC: 0xfffffa00 */ -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffd00 -#define ATMEL_BASE_SHDWN 0xfffffd10 -#define ATMEL_BASE_RTT 0xfffffd20 -#define ATMEL_BASE_PIT 0xfffffd30 -#define ATMEL_BASE_WDT 0xfffffd40 -/* GPBR(non-XE SoCs): 0xfffffd50 */ -/* GPBR(XE SoCs): 0xfffffd60 */ -/* Reserved: 0xfffffd70 - 0xffffffff */ - -/* - * Internal Memory common on all these SoCs - */ -#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */ -#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ -/* SRAM or FLASH: 0x00200000 */ -/* SRAM: 0x00300000 */ -/* Reserved: 0x00400000 */ -#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */ - -/* - * External memory - */ -#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ -#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ -#define ATMEL_BASE_CS2 0x30000000 -#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ -#define ATMEL_BASE_CS4 0x50000000 -#define ATMEL_BASE_CS5 0x60000000 -#define ATMEL_BASE_CS6 0x70000000 -#define ATMEL_BASE_CS7 0x80000000 - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define ATMEL_BASE_PIO ATMEL_BASE_PIOA - -/* - * SoC specific defines - */ -#if defined(CONFIG_AT91SAM9XE) -# define ATMEL_CPU_NAME "AT91SAM9XE" -# define ATMEL_ID_TWI1 25 /* TWI 1 */ -# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */ -# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */ -# define ATMEL_BASE_TWI1 0xfffd8000 -# define ATMEL_BASE_EEFC 0xfffffa00 -# define ATMEL_BASE_GPBR 0xfffffd60 -#elif defined(CONFIG_AT91SAM9260) -# define ATMEL_CPU_NAME "AT91SAM9260" -# define ATMEL_ID_USART5 25 /* USART 5 */ -# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ -# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ -# define ATMEL_BASE_USART5 0xfffd8000 -# define ATMEL_BASE_GPBR 0xfffffd50 -#elif defined(CONFIG_AT91SAM9G20) -# define ATMEL_CPU_NAME "AT91SAM9G20" -# define ATMEL_ID_USART5 25 /* USART 5 */ -# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ -# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ -# define ATMEL_BASE_USART5 0xfffd8000 -# define ATMEL_BASE_GPBR 0xfffffd50 -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h deleted file mode 100644 index 4755fa10b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#ifndef __ASSEMBLY__ - -/* - * This struct defines access to the matrix' maximum of - * 16 masters and 16 slaves. - * However, on the AT91SAM9260/9G20/9XE there exist only - * 6 Masters and 5 Slaves! - */ -struct at91_matrix { - u32 mcfg[16]; /* Master Configuration Registers */ - u32 scfg[16]; /* Slave Configuration Registers */ - u32 pras[16][2]; /* Priority Assignment Slave Registers */ - u32 mrcr; /* Master Remap Control Register */ - u32 filler[0x06]; - u32 ebicsa; /* EBI Chip Select Assignment Register */ -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_M0PR_SHIFT 0 -#define AT91_MATRIX_M1PR_SHIFT 4 -#define AT91_MATRIX_M2PR_SHIFT 8 -#define AT91_MATRIX_M3PR_SHIFT 12 -#define AT91_MATRIX_M4PR_SHIFT 16 -#define AT91_MATRIX_M5PR_SHIFT 20 - -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) - -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261.h deleted file mode 100644 index f7ad11349..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] - * - * Copyright (C) SAN People - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * Definitions for the SoCs: - * AT91SAM9261, AT91SAM9G10 - * - * Note that those SoCs are mostly software and pin compatible, - * therefore this file applies to all of them. Differences between - * those SoCs are concentrated at the end of this file. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * defines to be used in other places - */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Peripherals */ -#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ -#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ -#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ -/* Reserved: 5 */ -#define ATMEL_ID_USART0 6 /* USART 0 */ -#define ATMEL_ID_USART1 7 /* USART 1 */ -#define ATMEL_ID_USART2 8 /* USART 2 */ -#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ -#define ATMEL_ID_UDP 10 /* USB Device Port */ -#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ -#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ -#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ -#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ -#define ATMEL_ID_UHP 20 /* USB Host port */ -#define ATMEL_ID_LCDC 21 /* LDC Controller */ -/* Reserved: 22-28 */ -#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -/* - * User Peripherals physical base addresses. - */ -#define ATMEL_BASE_TCB0 0xfffa0000 -#define ATMEL_BASE_TC0 0xfffa0000 -#define ATMEL_BASE_TC1 0xfffa0040 -#define ATMEL_BASE_TC2 0xfffa0080 -#define ATMEL_BASE_UDP0 0xfffa4000 -#define ATMEL_BASE_MCI 0xfffa8000 -#define ATMEL_BASE_TWI0 0xfffac000 -#define ATMEL_BASE_USART0 0xfffb0000 -#define ATMEL_BASE_USART1 0xfffb4000 -#define ATMEL_BASE_USART2 0xfffb8000 -#define ATMEL_BASE_SSC0 0xfffbc000 -#define ATMEL_BASE_SSC1 0xfffc0000 -#define ATMEL_BASE_SSC2 0xfffc4000 -#define ATMEL_BASE_SPI0 0xfffc8000 -#define ATMEL_BASE_SPI1 0xfffcc000 -/* Reserved: 0xfffc4000 - 0xffffe9ff */ - -/* - * System Peripherals physical base addresses. - */ -#define ATMEL_BASE_SYS 0xffffea00 -#define ATMEL_BASE_SDRAMC 0xffffea00 -#define ATMEL_BASE_SMC 0xffffec00 -#define ATMEL_BASE_MATRIX 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_DBGU 0xfffff200 -#define ATMEL_BASE_PIOA 0xfffff400 -#define ATMEL_BASE_PIOB 0xfffff600 -#define ATMEL_BASE_PIOC 0xfffff800 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffd00 -#define ATMEL_BASE_SHDWN 0xfffffd10 -#define ATMEL_BASE_RTT 0xfffffd20 -#define ATMEL_BASE_PIT 0xfffffd30 -#define ATMEL_BASE_WDT 0xfffffd40 -#define ATMEL_BASE_GPBR 0xfffffd50 - -/* - * Internal Memory common on all these SoCs - */ -#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ -#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ - -#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ -#define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */ - -#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ -#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ - -/* - * External memory - */ -#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ -#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ -#define ATMEL_BASE_CS2 0x30000000 -#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ -#define ATMEL_BASE_CS4 0x50000000 -#define ATMEL_BASE_CS5 0x60000000 -#define ATMEL_BASE_CS6 0x70000000 -#define ATMEL_BASE_CS7 0x80000000 - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define ATMEL_BASE_PIO ATMEL_BASE_PIOA - -/* - * SoC specific defines - */ -#if defined(CONFIG_AT91SAM9261) -# define ATMEL_CPU_NAME "AT91SAM9261" -#elif defined(CONFIG_AT91SAM9G10) -# define ATMEL_CPU_NAME "AT91SAM9G10" -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h deleted file mode 100644 index fc5f0831b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9261_MATRIX_H -#define AT91SAM9261_MATRIX_H - -#ifndef __ASSEMBLY__ - -struct at91_matrix { - u32 mcfg; /* Master Configuration Registers */ - u32 scfg[5]; /* Slave Configuration Registers */ - u32 filler[6]; - u32 ebicsa; /* EBI Chip Select Assignment Register */ -}; -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_M0PR_SHIFT 0 -#define AT91_MATRIX_M1PR_SHIFT 4 -#define AT91_MATRIX_M2PR_SHIFT 8 -#define AT91_MATRIX_M3PR_SHIFT 12 -#define AT91_MATRIX_M4PR_SHIFT 16 -#define AT91_MATRIX_M5PR_SHIFT 20 - -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) - -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263.h deleted file mode 100644 index 3206af8c3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] - * - * (C) 2007 Atmel Corporation. - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * Definitions for the SoC: - * AT91SAM9263 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * defines to be used in other places - */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Peripherals */ -#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ -#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ -#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -/* Reserved: 5 */ -/* Reserved: 6 */ -#define ATMEL_ID_USART0 7 /* USART 0 */ -#define ATMEL_ID_USART1 8 /* USART 1 */ -#define ATMEL_ID_USART2 9 /* USART 2 */ -#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define ATMEL_ID_CAN 12 /* CAN */ -#define ATMEL_ID_TWI 13 /* Two-Wire Interface */ -#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define ATMEL_ID_AC97C 18 /* AC97 Controller */ -#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define ATMEL_ID_EMAC 21 /* Ethernet */ -/* Reserved: 22 */ -#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */ -#define ATMEL_ID_UDP 24 /* USB Device Port */ -#define ATMEL_ID_ISI 25 /* Image Sensor Interface */ -#define ATMEL_ID_LCDC 26 /* LCD Controller */ -#define ATMEL_ID_DMA 27 /* DMA Controller */ -/* Reserved: 28 */ -#define ATMEL_ID_UHP 29 /* USB Host port */ -#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -/* - * User Peripherals physical base addresses. - */ -#define ATMEL_BASE_UDP 0xfff78000 -#define ATMEL_BASE_TCB0 0xfff7c000 -#define ATMEL_BASE_TC0 0xfff7c000 -#define ATMEL_BASE_TC1 0xfff7c040 -#define ATMEL_BASE_TC2 0xfff7c080 -#define ATMEL_BASE_MCI0 0xfff80000 -#define ATMEL_BASE_MCI1 0xfff84000 -#define ATMEL_BASE_TWI 0xfff88000 -#define ATMEL_BASE_USART0 0xfff8c000 -#define ATMEL_BASE_USART1 0xfff90000 -#define ATMEL_BASE_USART2 0xfff94000 -#define ATMEL_BASE_SSC0 0xfff98000 -#define ATMEL_BASE_SSC1 0xfff9c000 -#define ATMEL_BASE_AC97C 0xfffa0000 -#define ATMEL_BASE_SPI0 0xfffa4000 -#define ATMEL_BASE_SPI1 0xfffa8000 -#define ATMEL_BASE_CAN 0xfffac000 -#define ATMEL_BASE_PWMC 0xfffb8000 -#define ATMEL_BASE_EMAC 0xfffbc000 -#define ATMEL_BASE_ISI 0xfffc4000 -#define ATMEL_BASE_2DGE 0xfffc8000 - -/* - * System Peripherals physical base addresses. - */ -#define ATMEL_BASE_ECC0 0xffffe000 -#define ATMEL_BASE_SDRAMC0 0xffffe200 -#define ATMEL_BASE_SMC0 0xffffe400 -#define ATMEL_BASE_ECC1 0xffffe600 -#define ATMEL_BASE_SDRAMC1 0xffffe800 -#define ATMEL_BASE_SMC1 0xffffea00 -#define ATMEL_BASE_MATRIX 0xffffec00 -#define ATMEL_BASE_CCFG 0xffffed10 -#define ATMEL_BASE_DBGU 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_PIOA 0xfffff200 -#define ATMEL_BASE_PIOB 0xfffff400 -#define ATMEL_BASE_PIOC 0xfffff600 -#define ATMEL_BASE_PIOD 0xfffff800 -#define ATMEL_BASE_PIOE 0xfffffa00 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffd00 -#define ATMEL_BASE_SHDWC 0xfffffd10 -#define ATMEL_BASE_RTT0 0xfffffd20 -#define ATMEL_BASE_PIT 0xfffffd30 -#define ATMEL_BASE_WDT 0xfffffd40 -#define ATMEL_BASE_RTT1 0xfffffd50 -#define ATMEL_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */ - -#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */ - -#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */ - -#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */ -#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */ -#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ - -/* - * External memory - */ -#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ -#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ -#define ATMEL_BASE_CS2 0x30000000 -#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ -#define ATMEL_BASE_CS4 0x50000000 -#define ATMEL_BASE_CS5 0x60000000 -#define ATMEL_BASE_CS6 0x70000000 -#define ATMEL_BASE_CS7 0x80000000 - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ -#define ATMEL_BASE_PIO ATMEL_BASE_PIOA -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - -/* - * Cpu Name - */ -#define ATMEL_CPU_NAME "AT91SAM9263" - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h deleted file mode 100644 index 54d862287..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] - * - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9263_MATRIX_H -#define AT91SAM9263_MATRIX_H - -#ifndef __ASSEMBLY__ - -/* - * This struct defines access to the matrix' maximum of - * 16 masters and 16 slaves. - * Note: not all masters/slaves are available - */ -struct at91_matrix { - u32 mcfg[16]; /* Master Configuration Registers */ - u32 scfg[16]; /* Slave Configuration Registers */ - u32 pras[16][2]; /* Priority Assignment Slave Registers */ - u32 mrcr; /* Master Remap Control Register */ - u32 filler[0x06]; - u32 ebicsa; /* EBI Chip Select Assignment Register */ -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_M0PR_SHIFT 0 -#define AT91_MATRIX_M1PR_SHIFT 4 -#define AT91_MATRIX_M2PR_SHIFT 8 -#define AT91_MATRIX_M3PR_SHIFT 12 -#define AT91_MATRIX_M4PR_SHIFT 16 -#define AT91_MATRIX_M5PR_SHIFT 20 - -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) - -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_matrix.h deleted file mode 100644 index 1b59cc6e4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_matrix.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H -#define __ASM_ARCH_AT91SAM9_MATRIX_H - -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#include <asm/arch/at91sam9260_matrix.h> -#elif defined(CONFIG_AT91SAM9261) -#include <asm/arch/at91sam9261_matrix.h> -#elif defined(CONFIG_AT91SAM9263) -#include <asm/arch/at91sam9263_matrix.h> -#elif defined(CONFIG_AT91SAM9RL) -#include <asm/arch/at91sam9rl_matrix.h> -#elif defined(CONFIG_AT91CAP9) -#include <asm/arch/at91cap9_matrix.h> -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) -#include <asm/arch/at91sam9g45_matrix.h> -#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) -#include <asm/arch/at91sam9x5_matrix.h> -#else -#error "Unsupported AT91SAM9/CAP9 processor" -#endif - -#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h deleted file mode 100644 index 5c98cc70d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * SDRAM Controllers (SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9_SDRAMC_H -#define AT91SAM9_SDRAMC_H - -#ifdef __ASSEMBLY__ - -#ifndef ATMEL_BASE_SDRAMC -#define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0 -#endif - -#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC -#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) -#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) -#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) - -#endif - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_smc.h deleted file mode 100644 index d29e98e71..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_smc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Static Memory Controllers (SMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9_SMC_H -#define AT91SAM9_SMC_H - -#ifdef __ASSEMBLY__ - -#ifndef ATMEL_BASE_SMC -#define ATMEL_BASE_SMC ATMEL_BASE_SMC0 -#endif - -#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC -#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04) -#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08) -#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C) - -#else - -typedef struct at91_cs { - u32 setup; /* 0x00 SMC Setup Register */ - u32 pulse; /* 0x04 SMC Pulse Register */ - u32 cycle; /* 0x08 SMC Cycle Register */ - u32 mode; /* 0x0C SMC Mode Register */ -} at91_cs_t; - -typedef struct at91_smc { - at91_cs_t cs[8]; -} at91_smc_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) -#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) -#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) -#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) - -#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) -#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) -#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) -#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) - -#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) -#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) - -#define AT91_SMC_MODE_RM_NCS 0x00000000 -#define AT91_SMC_MODE_RM_NRD 0x00000001 -#define AT91_SMC_MODE_WM_NCS 0x00000000 -#define AT91_SMC_MODE_WM_NWE 0x00000002 - -#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 -#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 -#define AT91_SMC_MODE_EXNW_READY 0x00000030 - -#define AT91_SMC_MODE_BAT 0x00000100 -#define AT91_SMC_MODE_DBW_8 0x00000000 -#define AT91_SMC_MODE_DBW_16 0x00001000 -#define AT91_SMC_MODE_DBW_32 0x00002000 -#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) -#define AT91_SMC_MODE_TDF 0x00100000 -#define AT91_SMC_MODE_PMEN 0x01000000 -#define AT91_SMC_MODE_PS_4 0x00000000 -#define AT91_SMC_MODE_PS_8 0x10000000 -#define AT91_SMC_MODE_PS_16 0x20000000 -#define AT91_SMC_MODE_PS_32 0x30000000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45.h deleted file mode 100644 index 9cbfc277b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9M1x family - * - * (C) 2008 Atmel Corporation. - * - * Definitions for the SoC: - * AT91SAM9G45 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9G45_H -#define AT91SAM9G45_H - -/* - * defines to be used in other places - */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ -#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ -#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ -#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ -#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define ATMEL_ID_TRNG 6 /* True Random Number Generator */ -#define ATMEL_ID_USART0 7 /* USART 0 */ -#define ATMEL_ID_USART1 8 /* USART 1 */ -#define ATMEL_ID_USART2 9 /* USART 2 */ -#define ATMEL_ID_USART3 10 /* USART 3 */ -#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */ -#define ATMEL_ID_DMA 21 /* DMA Controller */ -#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ -#define ATMEL_ID_LCDC 23 /* LCD Controller */ -#define ATMEL_ID_AC97C 24 /* AC97 Controller */ -#define ATMEL_ID_EMAC 25 /* Ethernet MAC */ -#define ATMEL_ID_ISI 26 /* Image Sensor Interface */ -#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */ -#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define ATMEL_ID_VDEC 30 /* Video Decoder */ -#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripherals physical base addresses. - */ -#define ATMEL_BASE_UDPHS 0xfff78000 -#define ATMEL_BASE_TC0 0xfff7c000 -#define ATMEL_BASE_TC1 0xfff7c040 -#define ATMEL_BASE_TC2 0xfff7c080 -#define ATMEL_BASE_MCI0 0xfff80000 -#define ATMEL_BASE_TWI0 0xfff84000 -#define ATMEL_BASE_TWI1 0xfff88000 -#define ATMEL_BASE_USART0 0xfff8c000 -#define ATMEL_BASE_USART1 0xfff90000 -#define ATMEL_BASE_USART2 0xfff94000 -#define ATMEL_BASE_USART3 0xfff98000 -#define ATMEL_BASE_SSC0 0xfff9c000 -#define ATMEL_BASE_SSC1 0xfffa0000 -#define ATMEL_BASE_SPI0 0xfffa4000 -#define ATMEL_BASE_SPI1 0xfffa8000 -#define ATMEL_BASE_AC97C 0xfffac000 -#define ATMEL_BASE_TSC 0xfffb0000 -#define ATMEL_BASE_ISI 0xfffb4000 -#define ATMEL_BASE_PWMC 0xfffb8000 -#define ATMEL_BASE_EMAC 0xfffbc000 -#define ATMEL_BASE_AES 0xfffc0000 -#define ATMEL_BASE_TDES 0xfffc4000 -#define ATMEL_BASE_SHA 0xfffc8000 -#define ATMEL_BASE_TRNG 0xfffcc000 -#define ATMEL_BASE_MCI1 0xfffd0000 -#define ATMEL_BASE_TC3 0xfffd4000 -#define ATMEL_BASE_TC4 0xfffd4040 -#define ATMEL_BASE_TC5 0xfffd4080 -/* Reserved: 0xfffd8000 - 0xffffe1ff */ - -/* - * System Peripherals physical base addresses. - */ -#define ATMEL_BASE_SYS 0xffffe200 -#define ATMEL_BASE_ECC 0xffffe200 -#define ATMEL_BASE_DDRSDRC1 0xffffe400 -#define ATMEL_BASE_DDRSDRC0 0xffffe600 -#define ATMEL_BASE_SMC 0xffffe800 -#define ATMEL_BASE_MATRIX 0xffffea00 -#define ATMEL_BASE_DMA 0xffffec00 -#define ATMEL_BASE_DBGU 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_PIOA 0xfffff200 -#define ATMEL_BASE_PIOB 0xfffff400 -#define ATMEL_BASE_PIOC 0xfffff600 -#define ATMEL_BASE_PIOD 0xfffff800 -#define ATMEL_BASE_PIOE 0xfffffa00 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffd00 -#define ATMEL_BASE_SHDWN 0xfffffd10 -#define ATMEL_BASE_RTT 0xfffffd20 -#define ATMEL_BASE_PIT 0xfffffd30 -#define ATMEL_BASE_WDT 0xfffffd40 -#define ATMEL_BASE_GPBR 0xfffffd60 -#define ATMEL_BASE_RTC 0xfffffdb0 -/* Reserved: 0xfffffdc0 - 0xffffffff */ - -/* - * Internal Memory. - */ -#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ -#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ -#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ -#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */ -#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */ -#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ - -/* - * External memory - */ -#define ATMEL_BASE_CS0 0x10000000 -#define ATMEL_BASE_CS1 0x20000000 -#define ATMEL_BASE_CS2 0x30000000 -#define ATMEL_BASE_CS3 0x40000000 -#define ATMEL_BASE_CS4 0x50000000 -#define ATMEL_BASE_CS5 0x60000000 -#define ATMEL_BASE_CS6 0x70000000 -#define ATMEL_BASE_CS7 0x80000000 - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ -#define ATMEL_BASE_PIO ATMEL_BASE_PIOA -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define ATMEL_ID_UHP ATMEL_ID_UHPHS -/* - * Cpu Name - */ -#define ATMEL_CPU_NAME "AT91SAM9G45" - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h deleted file mode 100644 index 80e49e343..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9M1x family - * - * Copyright (C) 2008 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9G45 preliminary datasheet. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91SAM9G45_MATRIX_H -#define AT91SAM9G45_MATRIX_H - -#ifndef __ASSEMBLY__ - -struct at91_matrix { - u32 mcfg[16]; - u32 scfg[16]; - u32 pras[16][2]; - u32 mrcr; /* 0x100 Master Remap Control */ - u32 filler[3]; - u32 tcmr; - u32 filler2; - u32 ddrmpr; - u32 filler3[3]; - u32 ebicsa; - u32 filler4[47]; - u32 wpmr; - u32 wpsr; -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) - -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 - -#define AT91_MATRIX_M0PR_SHIFT 0 -#define AT91_MATRIX_M1PR_SHIFT 4 -#define AT91_MATRIX_M2PR_SHIFT 8 -#define AT91_MATRIX_M3PR_SHIFT 12 -#define AT91_MATRIX_M4PR_SHIFT 16 -#define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_M6PR_SHIFT 24 -#define AT91_MATRIX_M7PR_SHIFT 28 - -#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ -#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ -#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ -#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ - -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) - -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl.h deleted file mode 100644 index 00b6aa469..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] - * - * Copyright (C) 2007 Atmel Corporation - * - * Common definitions. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_H -#define AT91SAM9RL_H - -/* - * defines to be used in other places - */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Peripherals */ -#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ -#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ -#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ -#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */ -#define ATMEL_ID_USART0 6 /* USART 0 */ -#define ATMEL_ID_USART1 7 /* USART 1 */ -#define ATMEL_ID_USART2 8 /* USART 2 */ -#define ATMEL_ID_USART3 9 /* USART 3 */ -#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ -#define ATMEL_ID_TWI0 11 /* TWI 0 */ -#define ATMEL_ID_TWI1 12 /* TWI 1 */ -#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ -#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define ATMEL_ID_TC0 16 /* Timer Counter 0 */ -#define ATMEL_ID_TC1 17 /* Timer Counter 1 */ -#define ATMEL_ID_TC2 18 /* Timer Counter 2 */ -#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define ATMEL_ID_TSC 20 /* Touch Screen Controller */ -#define ATMEL_ID_DMA 21 /* DMA Controller */ -#define ATMEL_ID_UDPHS 22 /* USB Device HS */ -#define ATMEL_ID_LCDC 23 /* LCD Controller */ -#define ATMEL_ID_AC97C 24 /* AC97 Controller */ -#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ - -/* - * User Peripheral physical base addresses. - */ -#define ATMEL_BASE_TCB0 0xfffa0000 -#define ATMEL_BASE_TC0 0xfffa0000 -#define ATMEL_BASE_TC1 0xfffa0040 -#define ATMEL_BASE_TC2 0xfffa0080 -#define ATMEL_BASE_MCI 0xfffa4000 -#define ATMEL_BASE_TWI0 0xfffa8000 -#define ATMEL_BASE_TWI1 0xfffac000 -#define ATMEL_BASE_USART0 0xfffb0000 -#define ATMEL_BASE_USART1 0xfffb4000 -#define ATMEL_BASE_USART2 0xfffb8000 -#define ATMEL_BASE_USART3 0xfffbc000 -#define ATMEL_BASE_SSC0 0xfffc0000 -#define ATMEL_BASE_SSC1 0xfffc4000 -#define ATMEL_BASE_PWMC 0xfffc8000 -#define ATMEL_BASE_SPI0 0xfffcc000 -#define ATMEL_BASE_TSC 0xfffd0000 -#define ATMEL_BASE_UDPHS 0xfffd4000 -#define ATMEL_BASE_AC97C 0xfffd8000 -#define ATMEL_BASE_SYS 0xffffc000 - -/* - * System Peripherals - */ -#define ATMEL_BASE_DMA 0xffffe600 -#define ATMEL_BASE_ECC 0xffffe800 -#define ATMEL_BASE_SDRAMC 0xffffea00 -#define ATMEL_BASE_SMC 0xffffec00 -#define ATMEL_BASE_MATRIX 0xffffee00 -#define ATMEL_BASE_CCFG 0xffffef10 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_DBGU 0xfffff200 -#define ATMEL_BASE_PIOA 0xfffff400 -#define ATMEL_BASE_PIOB 0xfffff600 -#define ATMEL_BASE_PIOC 0xfffff800 -#define ATMEL_BASE_PIOD 0xfffffa00 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffd00 -#define ATMEL_BASE_SHDWC 0xfffffd10 -#define ATMEL_BASE_RTT 0xfffffd20 -#define ATMEL_BASE_PIT 0xfffffd30 -#define ATMEL_BASE_WDT 0xfffffd40 -#define ATMEL_BASE_SCKCR 0xfffffd50 -#define ATMEL_BASE_GPBR 0xfffffd60 -#define ATMEL_BASE_RTC 0xfffffe00 - -/* - * Internal Memory. - */ -#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ -#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ - -#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ -#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */ - -/* - * External memory - */ -#define ATMEL_BASE_CS0 0x10000000 -#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ -#define ATMEL_BASE_CS2 0x30000000 -#define ATMEL_BASE_CS3 0x40000000 /* NAND */ -#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ -#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */ -#define ATMEL_BASE_PIO ATMEL_BASE_PIOA - -/* - * Cpu Name - */ -#define ATMEL_CPU_NAME "AT91SAM9RL" - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h deleted file mode 100644 index 295f768b5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_MATRIX_H -#define AT91SAM9RL_MATRIX_H - -#ifndef __ASSEMBLY__ - -struct at91_matrix { - u32 mcfg[16]; /* Master Configuration Registers */ - u32 scfg[16]; /* Slave Configuration Registers */ - u32 pras[16][2]; /* Priority Assignment Slave Registers */ - u32 mrcr; /* Master Remap Control Register */ - u32 filler[7]; - u32 ebicsa; /* EBI Chip Select Assignment Register */ -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_M0PR_SHIFT 0 -#define AT91_MATRIX_M1PR_SHIFT 4 -#define AT91_MATRIX_M2PR_SHIFT 8 -#define AT91_MATRIX_M3PR_SHIFT 12 -#define AT91_MATRIX_M4PR_SHIFT 16 -#define AT91_MATRIX_M5PR_SHIFT 20 - -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) - -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5.h deleted file mode 100644 index a47103851..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9x5 family - * - * Copyright (C) 2012-2013 Atmel Corporation. - * - * Definitions for the SoC: - * AT91SAM9x5 & AT91SAM9N12 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AT91SAM9X5_H__ -#define __AT91SAM9X5_H__ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ -#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */ -#define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */ -#define ATMEL_ID_USART0 5 /* USART 0 */ -#define ATMEL_ID_USART1 6 /* USART 1 */ -#define ATMEL_ID_USART2 7 /* USART 2 */ -#define ATMEL_ID_USART3 8 /* USART 3 */ -#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */ -#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */ -#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_UART0 15 /* UART 0 */ -#define ATMEL_ID_UART1 16 /* UART 1 */ -#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define ATMEL_ID_ADC 19 /* ADC Controller */ -#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */ -#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */ -#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ -#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ -#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */ -#define ATMEL_ID_LCDC 25 /* LCD Controller */ -#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */ -#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */ -#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ -#define ATMEL_ID_TRNG 30 /* True Random Number Generator */ -#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define ATMEL_BASE_SPI0 0xf0000000 -#define ATMEL_BASE_SPI1 0xf0004000 -#define ATMEL_BASE_HSMCI0 0xf0008000 -#define ATMEL_BASE_HSMCI1 0xf000c000 -#define ATMEL_BASE_SSC 0xf0010000 -#define ATMEL_BASE_CAN0 0xf8000000 -#define ATMEL_BASE_CAN1 0xf8004000 -#define ATMEL_BASE_TC0 0xf8008000 -#define ATMEL_BASE_TC1 0xf8008040 -#define ATMEL_BASE_TC2 0xf8008080 -#define ATMEL_BASE_TC3 0xf800c000 -#define ATMEL_BASE_TC4 0xf800c040 -#define ATMEL_BASE_TC5 0xf800c080 -#define ATMEL_BASE_TWI0 0xf8010000 -#define ATMEL_BASE_TWI1 0xf8014000 -#define ATMEL_BASE_TWI2 0xf8018000 -#define ATMEL_BASE_USART0 0xf801c000 -#define ATMEL_BASE_USART1 0xf8020000 -#define ATMEL_BASE_USART2 0xf8024000 -#define ATMEL_BASE_USART3 0xf8028000 -#define ATMEL_BASE_EMAC0 0xf802c000 -#define ATMEL_BASE_EMAC1 0xf8030000 -#define ATMEL_BASE_PWM 0xf8034000 -#define ATMEL_BASE_LCDC 0xf8038000 -#define ATMEL_BASE_UDPHS 0xf803c000 -#define ATMEL_BASE_UART0 0xf8040000 -#define ATMEL_BASE_UART1 0xf8044000 -#define ATMEL_BASE_ISI 0xf8048000 -#define ATMEL_BASE_ADC 0xf804c000 -#define ATMEL_BASE_SYS 0xffffc000 - -/* - * System Peripherals - */ -#define ATMEL_BASE_FUSE 0xffffdc00 -#define ATMEL_BASE_MATRIX 0xffffde00 -#define ATMEL_BASE_PMECC 0xffffe000 -#define ATMEL_BASE_PMERRLOC 0xffffe600 -#define ATMEL_BASE_DDRSDRC 0xffffe800 -#define ATMEL_BASE_SMC 0xffffea00 -#define ATMEL_BASE_DMAC0 0xffffec00 -#define ATMEL_BASE_DMAC1 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_DBGU 0xfffff200 -#define ATMEL_BASE_PIOA 0xfffff400 -#define ATMEL_BASE_PIOB 0xfffff600 -#define ATMEL_BASE_PIOC 0xfffff800 -#define ATMEL_BASE_PIOD 0xfffffa00 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffe00 -#define ATMEL_BASE_SHDWC 0xfffffe10 -#define ATMEL_BASE_PIT 0xfffffe30 -#define ATMEL_BASE_WDT 0xfffffe40 -#define ATMEL_BASE_GPBR 0xfffffe60 -#define ATMEL_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ -#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ - -#ifdef CONFIG_AT91SAM9N12 -#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */ -#else /* AT91SAM9X5 */ -#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */ -#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ -#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ -#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ -#endif - -/* 9x5 series chip id definitions */ -#define ARCH_ID_AT91SAM9X5 0x819a05a0 -#define ARCH_ID_VERSION_MASK 0x1f -#define ARCH_EXID_AT91SAM9G15 0x00000000 -#define ARCH_EXID_AT91SAM9G35 0x00000001 -#define ARCH_EXID_AT91SAM9X35 0x00000002 -#define ARCH_EXID_AT91SAM9G25 0x00000003 -#define ARCH_EXID_AT91SAM9X25 0x00000004 - -#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5) -#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ - (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15)) -#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ - (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25)) -#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ - (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35)) -#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ - (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25)) -#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ - (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35)) - -/* - * Cpu Name - */ -#ifdef CONFIG_AT91SAM9N12 -#define ATMEL_CPU_NAME "AT91SAM9N12" -#else /* AT91SAM9X5 */ -#define ATMEL_CPU_NAME get_cpu_name() -#endif - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 4 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * PMECC table in ROM - */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 - -/* - * at91sam9x5 specific prototypes - */ -#ifndef __ASSEMBLY__ -unsigned int get_chip_id(void); -unsigned int get_extension_chip_id(void); -unsigned int has_emac1(void); -unsigned int has_emac0(void); -unsigned int has_lcdc(void); -char *get_cpu_name(void); -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h deleted file mode 100644 index bd0b25adc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9X5 family - * - * Copyright (C) 2012-2013 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AT91SAM9X5_MATRIX_H__ -#define __AT91SAM9X5_MATRIX_H__ - -#ifndef __ASSEMBLY__ - -/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */ -struct at91_matrix { - u32 mcfg[16]; - u32 scfg[16]; - u32 pras[16][2]; - u32 mrcr; /* 0x100 Master Remap Control */ - u32 filler[5]; -#ifdef CONFIG_AT91SAM9X5 - u32 filler1[2]; -#endif - /* EBI Chip Select Assignment Register - * 0x118: AT91SAM9N12 - * 0x120: AT91SAM9X5 - */ - u32 ebicsa; - u32 filler4[47]; -#ifdef CONFIG_AT91SAM9N12 - u32 filler5[2]; -#endif - u32 wpmr; - u32 wpsr; -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) - -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 - -#define AT91_MATRIX_M0PR_SHIFT 0 -#define AT91_MATRIX_M1PR_SHIFT 4 -#define AT91_MATRIX_M2PR_SHIFT 8 -#define AT91_MATRIX_M3PR_SHIFT 12 -#define AT91_MATRIX_M4PR_SHIFT 16 -#define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_M6PR_SHIFT 24 -#define AT91_MATRIX_M7PR_SHIFT 28 - -#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ -#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ -#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ -#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ - -#define AT91_MATRIX_RCB0 (1 << 0) -#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) - -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_DBPD_ON (0 << 9) -#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9) -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91_MATRIX_NFD0_ON_D16 (1 << 24) -#define AT91_MATRIX_MP_OFF (0 << 25) -#define AT91_MATRIX_MP_ON (1 << 25) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h deleted file mode 100644 index 5741f6e94..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ATMEL_MPDDRC_H__ -#define __ATMEL_MPDDRC_H__ - -/* - * Only define the needed register in mpddr - * If other register needed, will add them later - */ -struct atmel_mpddr { - u32 mr; - u32 rtr; - u32 cr; - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 reserved[2]; - u32 md; -}; - -int ddr2_init(const unsigned int ram_address, - const struct atmel_mpddr *mpddr); - -/* Bit field in mode register */ -#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 -#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 -#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 -#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 -#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 -#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 -#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 -#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 - -/* Bit field in configuration register */ -#define ATMEL_MPDDRC_CR_NC_MASK 0x3 -#define ATMEL_MPDDRC_CR_NC_COL_9 0x0 -#define ATMEL_MPDDRC_CR_NC_COL_10 0x1 -#define ATMEL_MPDDRC_CR_NC_COL_11 0x2 -#define ATMEL_MPDDRC_CR_NC_COL_12 0x3 -#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) -#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) -#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) -#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) -#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) -#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) -#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) -#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) -#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) -#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) -#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) -#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) -#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) -#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) -#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) -#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) -#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) -#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) -#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) -#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) - -/* Bit field in timing parameter 0 register */ -#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 -#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf -#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 -#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf -#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 -#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf -#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 -#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf -#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 -#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf -#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 -#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf -#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 -#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 -#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 -#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 -#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 -#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf - -/* Bit field in timing parameter 1 register */ -#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 -#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f -#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 -#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff -#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 -#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff -#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 -#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf - -/* Bit field in timing parameter 2 register */ -#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 -#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf -#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 -#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf -#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 -#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf -#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 -#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 -#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 -#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf - -/* Bit field in Memory Device Register */ -#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 -#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 -#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) -#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) -#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_usba_udc.h deleted file mode 100644 index 6f540d23a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_usba_udc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2005-2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ATMEL_USBA_UDC_H__ -#define __ATMEL_USBA_UDC_H__ - -#include <linux/usb/atmel_usba_udc.h> - -#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ - [idx] = { \ - .name = nam, \ - .index = idx, \ - .fifo_size = maxpkt, \ - .nr_banks = maxbk, \ - .can_dma = dma, \ - .can_isoc = isoc, \ - } - -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ - defined(CONFIG_AT91SAM9X5) -static struct usba_ep_data usba_udc_ep[] = { - EP("ep0", 0, 64, 1, 0, 0), - EP("ep1", 1, 1024, 2, 1, 1), - EP("ep2", 2, 1024, 2, 1, 1), - EP("ep3", 3, 1024, 3, 1, 0), - EP("ep4", 4, 1024, 3, 1, 0), - EP("ep5", 5, 1024, 3, 1, 1), - EP("ep6", 6, 1024, 3, 1, 1), -}; -#elif defined(CONFIG_SAMA5D3) -static struct usba_ep_data usba_udc_ep[] = { - EP("ep0", 0, 64, 1, 0, 0), - EP("ep1", 1, 1024, 3, 1, 0), - EP("ep2", 2, 1024, 3, 1, 0), - EP("ep3", 3, 1024, 2, 1, 0), - EP("ep4", 4, 1024, 2, 1, 0), - EP("ep5", 5, 1024, 2, 1, 0), - EP("ep6", 6, 1024, 2, 1, 0), - EP("ep7", 7, 1024, 2, 1, 0), - EP("ep8", 8, 1024, 2, 0, 0), - EP("ep9", 9, 1024, 2, 0, 0), - EP("ep10", 10, 1024, 2, 0, 0), - EP("ep11", 11, 1024, 2, 0, 0), - EP("ep12", 12, 1024, 2, 0, 0), - EP("ep13", 13, 1024, 2, 0, 0), - EP("ep14", 14, 1024, 2, 0, 0), - EP("ep15", 15, 1024, 2, 0, 0), -}; -#else -# error "NO usba_udc_ep defined" -#endif - -#undef EP - -struct usba_platform_data pdata = { - .num_ep = ARRAY_SIZE(usba_udc_ep), - .ep = usba_udc_ep, -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/clk.h deleted file mode 100644 index ce9e28f11..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/clk.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2007 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARM_ARCH_CLK_H__ -#define __ASM_ARM_ARCH_CLK_H__ - -#include <asm/arch/hardware.h> -#include <asm/global_data.h> - -static inline unsigned long get_cpu_clk_rate(void) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->arch.cpu_clk_rate_hz; -} - -static inline unsigned long get_main_clk_rate(void) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->arch.main_clk_rate_hz; -} - -static inline unsigned long get_mck_clk_rate(void) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->arch.mck_rate_hz; -} - -static inline unsigned long get_plla_clk_rate(void) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->arch.plla_rate_hz; -} - -static inline unsigned long get_pllb_clk_rate(void) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->arch.pllb_rate_hz; -} - -static inline u32 get_pllb_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->arch.at91_pllb_usb_init; -} - -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_spi_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_twi_clk_rate(unsigned int dev_id) -{ - return get_mck_clk_rate(); -} - -static inline unsigned long get_mci_clk_rate(void) -{ - return get_mck_clk_rate(); -} - -int at91_clock_init(unsigned long main_clock); -void at91_periph_clk_enable(int id); -#endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/gpio.h deleted file mode 100644 index 71213883d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/gpio.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] - * - * Copyright (C) 2005 HP Labs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_AT91_GPIO_H -#define __ASM_ARCH_AT91_GPIO_H - -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/hardware.h> - -#ifdef CONFIG_ATMEL_LEGACY - -#define PIN_BASE 0 - -#define MAX_GPIO_BANKS 5 - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ - -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) - -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) - -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) - -#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) - -#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) - -static unsigned long at91_pios[] = { - ATMEL_BASE_PIOA, - ATMEL_BASE_PIOB, - ATMEL_BASE_PIOC, -#ifdef ATMEL_BASE_PIOD - ATMEL_BASE_PIOD, -#ifdef ATMEL_BASE_PIOE - ATMEL_BASE_PIOE -#endif -#endif -}; - -static inline void *pin_to_controller(unsigned pin) -{ - pin -= PIN_BASE; - pin /= 32; - return (void *)(at91_pios[pin]); -} - -static inline unsigned pin_to_mask(unsigned pin) -{ - pin -= PIN_BASE; - return 1 << (pin % 32); -} - -/* The following macros are need for backward compatibility */ -#define at91_set_GPIO_periph(x, y) \ - at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_A_periph(x, y) \ - at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_B_periph(x, y) \ - at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_output(x, y) \ - at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_input(x, y) \ - at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_value(x, y) \ - at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y) -#define at91_get_gpio_value(x) \ - at91_get_pio_value((x - PIN_BASE) / 32,(x % 32)) -#else -#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) -#define at91_get_gpio_value(x) at91_get_pio_value(x) -#endif - -#define GPIO_PIOA_BASE (0) -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) -#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) -#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) -#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) -#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) - -static inline unsigned at91_gpio_to_port(unsigned gpio) -{ - return gpio / 32; -} - -static inline unsigned at91_gpio_to_pin(unsigned gpio) -{ - return gpio % 32; -} - -#endif /* __ASM_ARCH_AT91_GPIO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/hardware.h deleted file mode 100644 index a63f97406..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/hardware.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARM_ARCH_HARDWARE_H__ -#define __ASM_ARM_ARCH_HARDWARE_H__ - -#if defined(CONFIG_AT91RM9200) -# include <asm/arch/at91rm9200.h> -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \ - defined(CONFIG_AT91SAM9XE) -# include <asm/arch/at91sam9260.h> -#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) -# include <asm/arch/at91sam9261.h> -#elif defined(CONFIG_AT91SAM9263) -# include <asm/arch/at91sam9263.h> -#elif defined(CONFIG_AT91SAM9RL) -# include <asm/arch/at91sam9rl.h> -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) -# include <asm/arch/at91sam9g45.h> -#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) -# include <asm/arch/at91sam9x5.h> -#elif defined(CONFIG_AT91CAP9) -# include <asm/arch/at91cap9.h> -#elif defined(CONFIG_AT91X40) -# include <asm/arch/at91x40.h> -#elif defined(CONFIG_SAMA5D3) -# include <asm/arch/sama5d3.h> -#else -# error "Unsupported AT91 processor" -#endif - -#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3.h deleted file mode 100644 index 6d936f47f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D3 family - * - * (C) 2012 - 2013 Atmel Corporation. - * Bo Shen <voice.shen@atmel.com> - * - * Definitions for the SoC: - * SAMA5D3 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef SAMA5D3_H -#define SAMA5D3_H - -/* - * defines to be used in other places - */ -#define CONFIG_ARMV7 /* ARM A5 Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ - -/* - * Peripheral identifiers/interrupts. - */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ -#define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */ -#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */ -#define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */ -#define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */ -#define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */ -#define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */ -#define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */ -#define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */ -#define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */ -#define ATMEL_ID_SMD 11 /* SMD Soft Modem */ -#define ATMEL_ID_USART0 12 /* USART 0 */ -#define ATMEL_ID_USART1 13 /* USART 1 */ -#define ATMEL_ID_USART2 14 /* USART 2 */ -#define ATMEL_ID_USART3 15 /* USART 3 */ -#define ATMEL_ID_UART0 16 -#define ATMEL_ID_UART1 17 -#define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */ -#define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */ -#define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */ -#define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */ -#define ATMEL_ID_MCI1 22 /* */ -#define ATMEL_ID_MCI2 23 /* */ -#define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_TC0 26 /* */ -#define ATMEL_ID_TC1 27 /* */ -#define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */ -#define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */ -#define ATMEL_ID_DMA0 30 /* DMA Controller */ -#define ATMEL_ID_DMA1 31 /* DMA Controller */ -#define ATMEL_ID_UHPHS 32 /* USB Host High Speed */ -#define ATMEL_ID_UDPHS 33 /* USB Device High Speed */ -#define ATMEL_ID_GMAC 34 -#define ATMEL_ID_EMAC 35 /* Ethernet MAC */ -#define ATMEL_ID_LCDC 36 /* LCD Controller */ -#define ATMEL_ID_ISI 37 /* Image Sensor Interface */ -#define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */ -#define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */ -#define ATMEL_ID_CAN0 40 -#define ATMEL_ID_CAN1 41 -#define ATMEL_ID_SHA 42 -#define ATMEL_ID_AES 43 -#define ATMEL_ID_TDES 44 -#define ATMEL_ID_TRNG 45 -#define ATMEL_ID_ARM 46 -#define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */ -#define ATMEL_ID_FUSE 48 -#define ATMEL_ID_MPDDRC 49 - -/* sama5d3 series chip id definitions */ -#define ARCH_ID_SAMA5D3 0x8a5c07c0 -#define ARCH_EXID_SAMA5D31 0x00444300 -#define ARCH_EXID_SAMA5D33 0x00414300 -#define ARCH_EXID_SAMA5D34 0x00414301 -#define ARCH_EXID_SAMA5D35 0x00584300 -#define ARCH_EXID_SAMA5D36 0x00004301 - -#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3) -#define cpu_is_sama5d31() (cpu_is_sama5d3() && \ - (get_extension_chip_id() == ARCH_EXID_SAMA5D31)) -#define cpu_is_sama5d33() (cpu_is_sama5d3() && \ - (get_extension_chip_id() == ARCH_EXID_SAMA5D33)) -#define cpu_is_sama5d34() (cpu_is_sama5d3() && \ - (get_extension_chip_id() == ARCH_EXID_SAMA5D34)) -#define cpu_is_sama5d35() (cpu_is_sama5d3() && \ - (get_extension_chip_id() == ARCH_EXID_SAMA5D35)) -#define cpu_is_sama5d36() (cpu_is_sama5d3() && \ - (get_extension_chip_id() == ARCH_EXID_SAMA5D36)) - -/* - * User Peripherals physical base addresses. - */ -#define ATMEL_BASE_MCI0 0xf0000000 -#define ATMEL_BASE_SPI0 0xf0004000 -#define ATMEL_BASE_SSC0 0xf000C000 -#define ATMEL_BASE_TC2 0xf0010000 -#define ATMEL_BASE_TWI0 0xf0014000 -#define ATMEL_BASE_TWI1 0xf0018000 -#define ATMEL_BASE_USART0 0xf001c000 -#define ATMEL_BASE_USART1 0xf0020000 -#define ATMEL_BASE_UART0 0xf0024000 -#define ATMEL_BASE_GMAC 0xf0028000 -#define ATMEL_BASE_PWMC 0xf002c000 -#define ATMEL_BASE_LCDC 0xf0030000 -#define ATMEL_BASE_ISI 0xf0034000 -#define ATMEL_BASE_SFR 0xf0038000 -/* Reserved: 0xf003c000 - 0xf8000000 */ -#define ATMEL_BASE_MCI1 0xf8000000 -#define ATMEL_BASE_MCI2 0xf8004000 -#define ATMEL_BASE_SPI1 0xf8008000 -#define ATMEL_BASE_SSC1 0xf800c000 -#define ATMEL_BASE_CAN1 0xf8010000 -#define ATMEL_BASE_TC3 0xf8014000 -#define ATMEL_BASE_TSADC 0xf8018000 -#define ATMEL_BASE_TWI2 0xf801c000 -#define ATMEL_BASE_USART2 0xf8020000 -#define ATMEL_BASE_USART3 0xf8024000 -#define ATMEL_BASE_UART1 0xf8028000 -#define ATMEL_BASE_EMAC 0xf802c000 -#define ATMEL_BASE_UDPHS 0xf8030000 -#define ATMEL_BASE_SHA 0xf8034000 -#define ATMEL_BASE_AES 0xf8038000 -#define ATMEL_BASE_TDES 0xf803c000 -#define ATMEL_BASE_TRNG 0xf8040000 -/* Reserved: 0xf804400 - 0xffffc00 */ - -/* - * System Peripherals physical base addresses. - */ -#define ATMEL_BASE_SYS 0xffffc000 -#define ATMEL_BASE_SMC 0xffffc000 -#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070) -#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500) -#define ATMEL_BASE_FUSE 0xffffe400 -#define ATMEL_BASE_DMAC0 0xffffe600 -#define ATMEL_BASE_DMAC1 0xffffe800 -#define ATMEL_BASE_MPDDRC 0xffffea00 -#define ATMEL_BASE_MATRIX 0xffffec00 -#define ATMEL_BASE_DBGU 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_PIOA 0xfffff200 -#define ATMEL_BASE_PIOB 0xfffff400 -#define ATMEL_BASE_PIOC 0xfffff600 -#define ATMEL_BASE_PIOD 0xfffff800 -#define ATMEL_BASE_PIOE 0xfffffa00 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffe00 -#define ATMEL_BASE_SHDWN 0xfffffe10 -#define ATMEL_BASE_PIT 0xfffffe30 -#define ATMEL_BASE_WDT 0xfffffe40 -#define ATMEL_BASE_SCKCR 0xfffffe50 -#define ATMEL_BASE_GPBR 0xfffffe60 -#define ATMEL_BASE_RTC 0xfffffeb0 -/* Reserved: 0xfffffee0 - 0xffffffff */ - -/* - * Internal Memory. - */ -#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ -#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */ -#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */ -#define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */ -#define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */ -#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ -#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ -#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ -#define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */ -#define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */ - -/* - * External memory - */ -#define ATMEL_BASE_CS0 0x10000000 -#define ATMEL_BASE_DDRCS 0x20000000 -#define ATMEL_BASE_CS1 0x40000000 -#define ATMEL_BASE_CS2 0x50000000 -#define ATMEL_BASE_CS3 0x60000000 - -/* - * Other misc defines - */ -#define ATMEL_PIO_PORTS 5 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV 0x3fff - -/* - * PMECC table in ROM - */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 - -/* - * SAMA5D3 specific prototypes - */ -#ifndef __ASSEMBLY__ -unsigned int get_chip_id(void); -unsigned int get_extension_chip_id(void); -unsigned int has_emac(void); -unsigned int has_gmac(void); -unsigned int has_lcdc(void); -char *get_cpu_name(void); -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3_smc.h deleted file mode 100644 index 6caa9b6ed..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3_smc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2012 Atmel Corporation. - * - * Static Memory Controllers (SMC) - System peripherals registers. - * Based on SAMA5D3 datasheet. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef SAMA5D3_SMC_H -#define SAMA5D3_SMC_H - -#ifdef __ASSEMBLY__ -#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600) -#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604) -#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608) -#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C) -#else -struct at91_cs { - u32 setup; /* 0x600 SMC Setup Register */ - u32 pulse; /* 0x604 SMC Pulse Register */ - u32 cycle; /* 0x608 SMC Cycle Register */ - u32 timings; /* 0x60C SMC Cycle Register */ - u32 mode; /* 0x610 SMC Mode Register */ -}; - -struct at91_smc { - u32 reserved[384]; - struct at91_cs cs[4]; -}; -#endif /* __ASSEMBLY__ */ - -#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) -#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) -#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) -#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) - -#define AT91_SMC_PULSE_NWE(x) (x & 0x3f) -#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) -#define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) -#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) - -#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) -#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) - -#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) -#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) -#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) -#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) -#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) -#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) -#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) -#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) - -#define AT91_SMC_MODE_RM_NCS 0x00000000 -#define AT91_SMC_MODE_RM_NRD 0x00000001 -#define AT91_SMC_MODE_WM_NCS 0x00000000 -#define AT91_SMC_MODE_WM_NWE 0x00000002 - -#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 -#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 -#define AT91_SMC_MODE_EXNW_READY 0x00000030 - -#define AT91_SMC_MODE_BAT 0x00000100 -#define AT91_SMC_MODE_DBW_8 0x00000000 -#define AT91_SMC_MODE_DBW_16 0x00001000 -#define AT91_SMC_MODE_DBW_32 0x00002000 -#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) -#define AT91_SMC_MODE_TDF 0x00100000 -#define AT91_SMC_MODE_PMEN 0x01000000 -#define AT91_SMC_MODE_PS_4 0x00000000 -#define AT91_SMC_MODE_PS_8 0x10000000 -#define AT91_SMC_MODE_PS_16 0x20000000 -#define AT91_SMC_MODE_PS_32 0x30000000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/spl.h deleted file mode 100644 index d8a87daa4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/spl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen <voice.shen@atmel.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -enum { - BOOT_DEVICE_NONE, -#ifdef CONFIG_SYS_USE_MMC - BOOT_DEVICE_MMC1, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_MMC2_2, -#elif CONFIG_SYS_USE_NANDFLASH - BOOT_DEVICE_NAND, -#elif CONFIG_SYS_USE_SERIALFLASH - BOOT_DEVICE_SPI, -#endif -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h deleted file mode 100644 index 1b40a96ad..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright 2013 Broadcom Corporation. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_BCM281XX_GPIO_H -#define __ARCH_BCM281XX_GPIO_H - -/* - * Empty file - cmd_gpio.c requires this. The implementation - * is in drivers/gpio/kona_gpio.c instead of inlined here. - */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h deleted file mode 100644 index 880b4e090..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2013 Broadcom Corporation. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_BCM281XX_SYSMAP_H - -#define BSC1_BASE_ADDR 0x3e016000 -#define BSC2_BASE_ADDR 0x3e017000 -#define BSC3_BASE_ADDR 0x3e018000 -#define GPIO2_BASE_ADDR 0x35003000 -#define KONA_MST_CLK_BASE_ADDR 0x3f001000 -#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 -#define PMU_BSC_BASE_ADDR 0x3500d000 -#define PWRMGR_BASE_ADDR 0x35010000 -#define SDIO1_BASE_ADDR 0x3f180000 -#define SDIO2_BASE_ADDR 0x3f190000 -#define SDIO3_BASE_ADDR 0x3f1a0000 -#define SDIO4_BASE_ADDR 0x3f1b0000 -#define SECWD_BASE_ADDR 0x3500c000 -#define SECWD2_BASE_ADDR 0x35002f40 -#define TIMER_BASE_ADDR 0x3e00d000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/gpio.h deleted file mode 100644 index 9a49b6e05..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/gpio.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2012 Vikram Narayananan - * <vikram186@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _BCM2835_GPIO_H_ -#define _BCM2835_GPIO_H_ - -#define BCM2835_GPIO_BASE 0x20200000 -#define BCM2835_GPIO_COUNT 54 - -#define BCM2835_GPIO_FSEL_MASK 0x7 -#define BCM2835_GPIO_INPUT 0x0 -#define BCM2835_GPIO_OUTPUT 0x1 -#define BCM2835_GPIO_ALT0 0x4 -#define BCM2835_GPIO_ALT1 0x5 -#define BCM2835_GPIO_ALT2 0x6 -#define BCM2835_GPIO_ALT3 0x7 -#define BCM2835_GPIO_ALT4 0x3 -#define BCM2835_GPIO_ALT5 0x2 - -#define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1) -#define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f) - -#define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) -#define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) - -struct bcm2835_gpio_regs { - u32 gpfsel[6]; - u32 reserved1; - u32 gpset[2]; - u32 reserved2; - u32 gpclr[2]; - u32 reserved3; - u32 gplev[2]; - u32 reserved4; - u32 gpeds[2]; - u32 reserved5; - u32 gpren[2]; - u32 reserved6; - u32 gpfen[2]; - u32 reserved7; - u32 gphen[2]; - u32 reserved8; - u32 gplen[2]; - u32 reserved9; - u32 gparen[2]; - u32 reserved10; - u32 gppud; - u32 gppudclk[2]; -}; - -#endif /* _BCM2835_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h deleted file mode 100644 index dded857c3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _BCM2835_MBOX_H -#define _BCM2835_MBOX_H - -#include <linux/compiler.h> - -/* - * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") - * and the ARM CPU. The ARM CPU is often thought of as the main CPU. - * However, the VideoCore actually controls the initial SoC boot, and hides - * much of the hardware behind a protocol. This protocol is transported - * using the SoC's mailbox hardware module. - * - * The mailbox hardware supports passing 32-bit values back and forth. - * Presumably by software convention of the firmware, the bottom 4 bits of the - * value are used to indicate a logical channel, and the upper 28 bits are the - * actual payload. Various channels exist using these simple raw messages. See - * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an - * example, the messages on the power management channel are a bitmask of - * devices whose power should be enabled. - * - * The property mailbox channel passes messages that contain the (16-byte - * aligned) ARM physical address of a memory buffer. This buffer is passed to - * the VC for processing, is modified in-place by the VC, and the address then - * passed back to the ARM CPU as the response mailbox message to indicate - * request completion. The buffers have a generic and extensible format; each - * buffer contains a standard header, a list of "tags", and a terminating zero - * entry. Each tag contains an ID indicating its type, and length fields for - * generic parsing. With some limitations, an arbitrary set of tags may be - * combined together into a single message buffer. This file defines structs - * representing the header and many individual tag layouts and IDs. - */ - -/* Raw mailbox HW */ - -#define BCM2835_MBOX_PHYSADDR 0x2000b880 - -struct bcm2835_mbox_regs { - u32 read; - u32 rsvd0[5]; - u32 status; - u32 config; - u32 write; -}; - -#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000 -#define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000 - -/* Lower 4-bits are channel ID */ -#define BCM2835_CHAN_MASK 0xf -#define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \ - (chan & BCM2835_CHAN_MASK)) -#define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK) -#define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK)) - -/* Property mailbox buffer structures */ - -#define BCM2835_MBOX_PROP_CHAN 8 - -/* All message buffers must start with this header */ -struct bcm2835_mbox_hdr { - u32 buf_size; - u32 code; -}; - -#define BCM2835_MBOX_REQ_CODE 0 -#define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000 - -#define BCM2835_MBOX_INIT_HDR(_m_) { \ - memset((_m_), 0, sizeof(*(_m_))); \ - (_m_)->hdr.buf_size = sizeof(*(_m_)); \ - (_m_)->hdr.code = 0; \ - (_m_)->end_tag = 0; \ - } - -/* - * A message buffer contains a list of tags. Each tag must also start with - * a standardized header. - */ -struct bcm2835_mbox_tag_hdr { - u32 tag; - u32 val_buf_size; - u32 val_len; -}; - -#define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \ - (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ - (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ - (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \ - } - -#define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \ - (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ - (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ - (_t_)->tag_hdr.val_len = 0; \ - } - -/* When responding, the VC sets this bit in val_len to indicate a response */ -#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 - -/* - * Below we define the ID and struct for many possible tags. This header only - * defines individual tag structs, not entire message structs, since in - * general an arbitrary set of tags may be combined into a single message. - * Clients of the mbox API are expected to define their own overall message - * structures by combining the header, a set of tags, and a terminating - * entry. For example, - * - * struct msg { - * struct bcm2835_mbox_hdr hdr; - * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; - * ... perhaps other tags here ... - * u32 end_tag; - * }; - */ - -#define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 - -struct bcm2835_mbox_tag_get_arm_mem { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - } req; - struct { - u32 mem_base; - u32 mem_size; - } resp; - } body; -}; - -#define BCM2835_MBOX_POWER_DEVID_SDHCI 0 -#define BCM2835_MBOX_POWER_DEVID_UART0 1 -#define BCM2835_MBOX_POWER_DEVID_UART1 2 -#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 -#define BCM2835_MBOX_POWER_DEVID_I2C0 4 -#define BCM2835_MBOX_POWER_DEVID_I2C1 5 -#define BCM2835_MBOX_POWER_DEVID_I2C2 6 -#define BCM2835_MBOX_POWER_DEVID_SPI 7 -#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 - -#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) -/* Device doesn't exist */ -#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) - -#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 - -struct bcm2835_mbox_tag_get_power_state { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - u32 device_id; - } req; - struct { - u32 device_id; - u32 state; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 - -#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) -#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) - -struct bcm2835_mbox_tag_set_power_state { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - u32 device_id; - u32 state; - } req; - struct { - u32 device_id; - u32 state; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 - -#define BCM2835_MBOX_CLOCK_ID_EMMC 1 -#define BCM2835_MBOX_CLOCK_ID_UART 2 -#define BCM2835_MBOX_CLOCK_ID_ARM 3 -#define BCM2835_MBOX_CLOCK_ID_CORE 4 -#define BCM2835_MBOX_CLOCK_ID_V3D 5 -#define BCM2835_MBOX_CLOCK_ID_H264 6 -#define BCM2835_MBOX_CLOCK_ID_ISP 7 -#define BCM2835_MBOX_CLOCK_ID_SDRAM 8 -#define BCM2835_MBOX_CLOCK_ID_PIXEL 9 -#define BCM2835_MBOX_CLOCK_ID_PWM 10 - -struct bcm2835_mbox_tag_get_clock_rate { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - u32 clock_id; - } req; - struct { - u32 clock_id; - u32 rate_hz; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 - -struct bcm2835_mbox_tag_allocate_buffer { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - u32 alignment; - } req; - struct { - u32 fb_address; - u32 fb_size; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 - -struct bcm2835_mbox_tag_release_buffer { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - } req; - struct { - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002 - -struct bcm2835_mbox_tag_blank_screen { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - /* bit 0 means on, other bots reserved */ - u32 state; - } req; - struct { - u32 state; - } resp; - } body; -}; - -/* Physical means output signal */ -#define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 -#define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003 -#define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 - -struct bcm2835_mbox_tag_physical_w_h { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 width; - u32 height; - } req; - struct { - u32 width; - u32 height; - } resp; - } body; -}; - -/* Virtual means display buffer */ -#define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 -#define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004 -#define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 - -struct bcm2835_mbox_tag_virtual_w_h { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 width; - u32 height; - } req; - struct { - u32 width; - u32 height; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 -#define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005 -#define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 - -struct bcm2835_mbox_tag_depth { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 bpp; - } req; - struct { - u32 bpp; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 -#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005 -#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 - -#define BCM2835_MBOX_PIXEL_ORDER_BGR 0 -#define BCM2835_MBOX_PIXEL_ORDER_RGB 1 - -struct bcm2835_mbox_tag_pixel_order { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 order; - } req; - struct { - u32 order; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 -#define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007 -#define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 - -#define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 -#define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 -#define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 - -struct bcm2835_mbox_tag_alpha_mode { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 alpha; - } req; - struct { - u32 alpha; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 - -struct bcm2835_mbox_tag_pitch { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - } req; - struct { - u32 pitch; - } resp; - } body; -}; - -/* Offset of display window within buffer */ -#define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 -#define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009 -#define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 - -struct bcm2835_mbox_tag_virtual_offset { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 x; - u32 y; - } req; - struct { - u32 x; - u32 y; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a -#define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a -#define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a - -struct bcm2835_mbox_tag_overscan { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - /* req not used for get */ - struct { - u32 top; - u32 bottom; - u32 left; - u32 right; - } req; - struct { - u32 top; - u32 bottom; - u32 left; - u32 right; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b - -struct bcm2835_mbox_tag_get_palette { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - } req; - struct { - u32 data[1024]; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b - -struct bcm2835_mbox_tag_test_palette { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - u32 offset; - u32 num_entries; - u32 data[256]; - } req; - struct { - u32 is_invalid; - } resp; - } body; -}; - -#define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b - -struct bcm2835_mbox_tag_set_palette { - struct bcm2835_mbox_tag_hdr tag_hdr; - union { - struct { - u32 offset; - u32 num_entries; - u32 data[256]; - } req; - struct { - u32 is_invalid; - } resp; - } body; -}; - -/* - * Pass a raw u32 message to the VC, and receive a raw u32 back. - * - * Returns 0 for success, any other value for error. - */ -int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv); - -/* - * Pass a complete property-style buffer to the VC, and wait until it has - * been processed. - * - * This function expects a pointer to the mbox_hdr structure in an attempt - * to ensure some degree of type safety. However, some number of tags and - * a termination value are expected to immediately follow the header in - * memory, as required by the property protocol. - * - * Returns 0 for success, any other value for error. - */ -int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/sdhci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/sdhci.h deleted file mode 100644 index a4f867b2e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BCM2835_SDHCI_H_ -#define _BCM2835_SDHCI_H_ - -#define BCM2835_SDHCI_BASE 0x20300000 - -int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/timer.h deleted file mode 100644 index c2001b6f9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/timer.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BCM2835_TIMER_H -#define _BCM2835_TIMER_H - -#define BCM2835_TIMER_PHYSADDR 0x20003000 - -struct bcm2835_timer_regs { - u32 cs; - u32 clo; - u32 chi; - u32 c0; - u32 c1; - u32 c2; - u32 c3; -}; - -#define BCM2835_TIMER_CS_M3 (1 << 3) -#define BCM2835_TIMER_CS_M2 (1 << 2) -#define BCM2835_TIMER_CS_M1 (1 << 1) -#define BCM2835_TIMER_CS_M0 (1 << 0) - -extern ulong get_timer_us(ulong base); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/wdog.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/wdog.h deleted file mode 100644 index 303a65f32..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/wdog.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2012 Stephen Warren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BCM2835_TIMER_H -#define _BCM2835_TIMER_H - -#define BCM2835_WDOG_PHYSADDR 0x20100000 - -struct bcm2835_wdog_regs { - u32 unknown0[7]; - u32 rstc; - u32 unknown1; - u32 wdog; -}; - -#define BCM2835_WDOG_PASSWORD 0x5a000000 - -#define BCM2835_WDOG_RSTC_WRCFG_MASK 0x00000030 -#define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020 - -#define BCM2835_WDOG_WDOG_TIMEOUT_MASK 0x0000ffff - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h deleted file mode 100644 index 5063e3964..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _DV_AINTC_DEFS_H_ -#define _DV_AINTC_DEFS_H_ - -struct dv_aintc_regs { - unsigned int fiq0; /* 0x00 */ - unsigned int fiq1; /* 0x04 */ - unsigned int irq0; /* 0x08 */ - unsigned int irq1; /* 0x0c */ - unsigned int fiqentry; /* 0x10 */ - unsigned int irqentry; /* 0x14 */ - unsigned int eint0; /* 0x18 */ - unsigned int eint1; /* 0x1c */ - unsigned int intctl; /* 0x20 */ - unsigned int eabase; /* 0x24 */ - unsigned char rsvd0[8]; /* 0x28 */ - unsigned int intpri0; /* 0x30 */ - unsigned int intpri1; /* 0x34 */ - unsigned int intpri2; /* 0x38 */ - unsigned int intpri3; /* 0x3c */ - unsigned int intpri4; /* 0x40 */ - unsigned int intpri5; /* 0x44 */ - unsigned int intpri6; /* 0x48 */ - unsigned int intpri7; /* 0x4c */ -}; - -#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) - -#define DV_AINTC_INTCTL_IDMODE (1 << 2) - -#endif /* _DV_AINTC_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da850_lowlevel.h deleted file mode 100644 index 45a325c12..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da850_lowlevel.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SoC-specific lowlevel code for DA850 - * - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __DA850_LOWLEVEL_H -#define __DA850_LOWLEVEL_H - -#include <asm/arch/pinmux_defs.h> - -/* pinmux_resource[] vector is defined in the board specific file */ -extern const struct pinmux_resource pinmuxes[]; -extern const int pinmuxes_size; - -extern const struct lpsc_resource lpsc[]; -extern const int lpsc_size; - -/* NOR Boot Configuration Word Field Descriptions */ -#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8) -#define DA850_NORBOOT_METHOD_DIRECT (1 << 4) -#define DA850_NORBOOT_16BIT (1 << 0) - -#define dv_maskbits(addr, val) \ - writel((readl(addr) & val), addr) - -void da850_lpc_transition(unsigned char pscnum, unsigned char module, - unsigned char domain, unsigned char state); -void da850_psc_init(void); -void da850_pinmux_ctl(unsigned long offset, unsigned long mask, - unsigned long value); - -#endif /* #ifndef __DA850_LOWLEVEL_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da8xx-usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da8xx-usb.h deleted file mode 100644 index f091e4989..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da8xx-usb.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions. - * - * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> - * - * Based on drivers/usb/musb/davinci.h - * - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __DA8XX_MUSB_H__ -#define __DA8XX_MUSB_H__ - -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> - -/* Base address of da8xx usb0 wrapper */ -#define DA8XX_USB_OTG_BASE 0x01E00000 - -/* Base address of da8xx musb core */ -#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) - -/* Timeout for DA8xx usb module */ -#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF - -/* - * DA8xx platform USB wrapper register overlay. - */ -struct da8xx_usb_regs { - dv_reg revision; - dv_reg control; - dv_reg status; - dv_reg emulation; - dv_reg mode; - dv_reg autoreq; - dv_reg srpfixtime; - dv_reg teardown; - dv_reg intsrc; - dv_reg intsrc_set; - dv_reg intsrc_clr; - dv_reg intmsk; - dv_reg intmsk_set; - dv_reg intmsk_clr; - dv_reg intsrcmsk; - dv_reg eoi; - dv_reg intvector; - dv_reg grndis_size[4]; -}; - -#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) - -/* DA8XX interrupt bits definitions */ -#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ -#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ -#define DA8XX_USB_TXINT_SHIFT 0 -#define DA8XX_USB_RXINT_SHIFT 8 - -#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ -#define DA8XX_USB_TXINT_MASK \ - (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) -#define DA8XX_USB_RXINT_MASK \ - (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) - -/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ -#define CFGCHIP2_PHYCLKGD (1 << 17) -#define CFGCHIP2_VBUSSENSE (1 << 16) -#define CFGCHIP2_RESET (1 << 15) -#define CFGCHIP2_OTGMODE (3 << 13) -#define CFGCHIP2_NO_OVERRIDE (0 << 13) -#define CFGCHIP2_FORCE_HOST (1 << 13) -#define CFGCHIP2_FORCE_DEVICE (2 << 13) -#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) -#define CFGCHIP2_USB1PHYCLKMUX (1 << 12) -#define CFGCHIP2_USB2PHYCLKMUX (1 << 11) -#define CFGCHIP2_PHYPWRDN (1 << 10) -#define CFGCHIP2_OTGPWRDN (1 << 9) -#define CFGCHIP2_DATPOL (1 << 8) -#define CFGCHIP2_USB1SUSPENDM (1 << 7) -#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ -#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ -#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ -#define CFGCHIP2_REFFREQ (0xf << 0) -#define CFGCHIP2_REFFREQ_12MHZ (1 << 0) -#define CFGCHIP2_REFFREQ_24MHZ (2 << 0) -#define CFGCHIP2_REFFREQ_48MHZ (3 << 0) - -#define DA8XX_USB_VBUS_GPIO (1 << 15) - -int usb_phy_on(void); -void usb_phy_off(void); - -#endif /* __DA8XX_MUSB_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/davinci_misc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/davinci_misc.h deleted file mode 100644 index 03be3882f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MISC_H -#define __MISC_H - -/* pin muxer definitions */ -#define PIN_MUX_NUM_FIELDS 8 /* Per register */ -#define PIN_MUX_FIELD_SIZE 4 /* n in bits */ -#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1) - -/* pin definition */ -struct pinmux_config { - dv_reg *mux; /* Address of mux register */ - unsigned char value; /* Value to set in field */ - unsigned char field; /* field number */ -}; - -/* pin table definition */ -struct pinmux_resource { - const struct pinmux_config *pins; - const int n_pins; -}; - -#define PINMUX_ITEM(item) { \ - .pins = item, \ - .n_pins = ARRAY_SIZE(item) \ - } - -struct lpsc_resource { - const int lpsc_no; -}; - -int dvevm_read_mac_address(uint8_t *buf); -void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); -int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); -int davinci_configure_pin_mux_items(const struct pinmux_resource *item, - int n_items); -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX) -void davinci_emac_mii_mode_sel(int mode_sel); -#endif -#if defined(CONFIG_SOC_DA8XX) -void irq_init(void); -int da8xx_configure_lpsc_items(const struct lpsc_resource *item, - const int n_items); -#endif - -#endif /* __MISC_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/ddr2_defs.h deleted file mode 100644 index 24afd9d52..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/ddr2_defs.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _DV_DDR2_DEFS_H_ -#define _DV_DDR2_DEFS_H_ - -/* - * DDR2 Memory Ctrl Register structure - * See sprueh7d.pdf for more details. - */ -struct dv_ddr2_regs_ctrl { - unsigned char rsvd0[4]; /* 0x00 */ - unsigned int sdrstat; /* 0x04 */ - unsigned int sdbcr; /* 0x08 */ - unsigned int sdrcr; /* 0x0C */ - unsigned int sdtimr; /* 0x10 */ - unsigned int sdtimr2; /* 0x14 */ - unsigned char rsvd1[4]; /* 0x18 */ - unsigned int sdbcr2; /* 0x1C */ - unsigned int pbbpr; /* 0x20 */ - unsigned char rsvd2[156]; /* 0x24 */ - unsigned int irr; /* 0xC0 */ - unsigned int imr; /* 0xC4 */ - unsigned int imsr; /* 0xC8 */ - unsigned int imcr; /* 0xCC */ - unsigned char rsvd3[20]; /* 0xD0 */ - unsigned int ddrphycr; /* 0xE4 */ - unsigned int ddrphycr2; /* 0xE8 */ - unsigned char rsvd4[4]; /* 0xEC */ -}; - -#define DV_DDR_PHY_PWRDNEN 0x40 -#define DV_DDR_PHY_EXT_STRBEN 0x80 -#define DV_DDR_PHY_RD_LATENCY_SHIFT 0 - -#define DV_DDR_SDTMR1_RFC_SHIFT 25 -#define DV_DDR_SDTMR1_RP_SHIFT 22 -#define DV_DDR_SDTMR1_RCD_SHIFT 19 -#define DV_DDR_SDTMR1_WR_SHIFT 16 -#define DV_DDR_SDTMR1_RAS_SHIFT 11 -#define DV_DDR_SDTMR1_RC_SHIFT 6 -#define DV_DDR_SDTMR1_RRD_SHIFT 3 -#define DV_DDR_SDTMR1_WTR_SHIFT 0 - -#define DV_DDR_SDTMR2_RASMAX_SHIFT 27 -#define DV_DDR_SDTMR2_XP_SHIFT 25 -#define DV_DDR_SDTMR2_ODT_SHIFT 23 -#define DV_DDR_SDTMR2_XSNR_SHIFT 16 -#define DV_DDR_SDTMR2_XSRD_SHIFT 8 -#define DV_DDR_SDTMR2_RTP_SHIFT 5 -#define DV_DDR_SDTMR2_CKE_SHIFT 0 - -#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27 -#define DV_DDR_SDCR_IBANK_POS_SHIFT 26 -#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25 -#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24 -#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23 -#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22 -#define DV_DDR_SDCR_DDR2EN_SHIFT 20 -#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18 -#define DV_DDR_SDCR_DDREN_SHIFT 17 -#define DV_DDR_SDCR_SDRAMEN_SHIFT 16 -#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15 -#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14 -#define DV_DDR_SDCR_CL_SHIFT 9 -#define DV_DDR_SDCR_IBANK_SHIFT 4 -#define DV_DDR_SDCR_PAGESIZE_SHIFT 0 - -#define DV_DDR_SDRCR_LPMODEN (1 << 31) -#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) - -#define DV_DDR_SRCR_LPMODEN_SHIFT 31 -#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 - -#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT) -#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) - -#define dv_ddr2_regs_ctrl \ - ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE) - -#endif /* _DV_DDR2_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h deleted file mode 100644 index 6c0275efa..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * SoC-specific lowlevel code for tms320dm365 and similar chips - * - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __DM365_LOWLEVEL_H -#define __DM365_LOWLEVEL_H - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> - -void dm365_waitloop(unsigned long loopcnt); -int dm365_pll1_init(unsigned long pllmult, unsigned long prediv); -int dm365_pll2_init(unsigned long pllm, unsigned long prediv); -int dm365_ddr_setup(void); -void dm365_psc_init(void); -void dm365_pinmux_ctl(unsigned long offset, unsigned long mask, - unsigned long value); -void dm36x_lowlevel_init(ulong bootflag); - -#endif /* #ifndef __DM365_LOWLEVEL_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emac_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emac_defs.h deleted file mode 100644 index c3f046efa..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emac_defs.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Modifications: - * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. - */ - -#ifndef _DM644X_EMAC_H_ -#define _DM644X_EMAC_H_ - -#include <asm/arch/hardware.h> - -#ifdef CONFIG_SOC_DM365 -#define EMAC_BASE_ADDR (0x01d07000) -#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) -#define EMAC_WRAPPER_RAM_ADDR (0x01d08000) -#define EMAC_MDIO_BASE_ADDR (0x01d0b000) -#define DAVINCI_EMAC_VERSION2 -#elif defined(CONFIG_SOC_DA8XX) -#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE -#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE -#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE -#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE -#define DAVINCI_EMAC_VERSION2 -#else -#define EMAC_BASE_ADDR (0x01c80000) -#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) -#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) -#define EMAC_MDIO_BASE_ADDR (0x01c84000) -#endif - -#ifdef CONFIG_SOC_DM646X -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif - -#ifdef CONFIG_SOC_DM646X -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 76500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -#elif defined(CONFIG_SOC_DM365) -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 121500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ -#elif defined(CONFIG_SOC_DA8XX) -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#else -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#endif - -#define PHY_KSZ8873 (0x00221450) -int ksz8873_is_phy_connected(int phy_addr); -int ksz8873_get_link_speed(int phy_addr); -int ksz8873_init_phy(int phy_addr); -int ksz8873_auto_negotiate(int phy_addr); - -#define PHY_LXT972 (0x001378e2) -int lxt972_is_phy_connected(int phy_addr); -int lxt972_get_link_speed(int phy_addr); -int lxt972_init_phy(int phy_addr); -int lxt972_auto_negotiate(int phy_addr); - -#define PHY_DP83848 (0x20005c90) -int dp83848_is_phy_connected(int phy_addr); -int dp83848_get_link_speed(int phy_addr); -int dp83848_init_phy(int phy_addr); -int dp83848_auto_negotiate(int phy_addr); - -#define PHY_ET1011C (0x282f013) -int et1011c_get_link_speed(int phy_addr); - -#endif /* _DM644X_EMAC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emif_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emif_defs.h deleted file mode 100644 index 7e19cfeed..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include <asm/arch/hardware.h> - -struct davinci_emif_regs { - u_int32_t ercsr; - u_int32_t awccr; - u_int32_t sdbcr; - u_int32_t sdrcr; - u_int32_t ab1cr; - u_int32_t ab2cr; - u_int32_t ab3cr; - u_int32_t ab4cr; - u_int32_t sdtimr; - u_int32_t ddrsr; - u_int32_t ddrphycr; - u_int32_t ddrphysr; - u_int32_t totar; - u_int32_t totactr; - u_int32_t ddrphyid_rev; - u_int32_t sdsretr; - u_int32_t eirr; - u_int32_t eimr; - u_int32_t eimsr; - u_int32_t eimcr; - u_int32_t ioctrlr; - u_int32_t iostatr; - u_int8_t rsvd0[8]; - u_int32_t nandfcr; - u_int32_t nandfsr; - u_int8_t rsvd1[8]; - u_int32_t nandfecc[4]; - u_int8_t rsvd2[60]; - u_int32_t nand4biteccload; - u_int32_t nand4bitecc[4]; - u_int32_t nanderradd1; - u_int32_t nanderradd2; - u_int32_t nanderrval1; - u_int32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -#define DAVINCI_NANDFCR_CS2NAND (1 << 0) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/gpio.h deleted file mode 100644 index 7da0060cd..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/gpio.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _GPIO_DEFS_H_ -#define _GPIO_DEFS_H_ - -#ifndef CONFIG_SOC_DA8XX -#define DAVINCI_GPIO_BINTEN 0x01C67008 -#define DAVINCI_GPIO_BANK01 0x01C67010 -#define DAVINCI_GPIO_BANK23 0x01C67038 -#define DAVINCI_GPIO_BANK45 0x01C67060 -#define DAVINCI_GPIO_BANK67 0x01C67088 - -#else /* CONFIG_SOC_DA8XX */ -#define DAVINCI_GPIO_BINTEN 0x01E26008 -#define DAVINCI_GPIO_BANK01 0x01E26010 -#define DAVINCI_GPIO_BANK23 0x01E26038 -#define DAVINCI_GPIO_BANK45 0x01E26060 -#define DAVINCI_GPIO_BANK67 0x01E26088 -#define DAVINCI_GPIO_BANK8 0x01E260B0 -#endif /* CONFIG_SOC_DA8XX */ - -struct davinci_gpio { - unsigned int dir; - unsigned int out_data; - unsigned int set_data; - unsigned int clr_data; - unsigned int in_data; - unsigned int set_rising; - unsigned int clr_rising; - unsigned int set_falling; - unsigned int clr_falling; - unsigned int intstat; -}; - -struct davinci_gpio_bank { - int num_gpio; - unsigned int irq_num; - unsigned int irq_mask; - unsigned long *in_use; - unsigned long base; -}; - -#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) -#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) -#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) -#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) -#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8) - -#define gpio_status() gpio_info() -#define GPIO_NAME_SIZE 20 -#if defined(CONFIG_SOC_DM644X) -/* GPIO0 to GPIO53, omit the V3.3 volts one */ -#define MAX_NUM_GPIOS 70 -#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) -#define MAX_NUM_GPIOS 128 -#else -#define MAX_NUM_GPIOS 144 -#endif -#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5)) -#define GPIO_BIT(gp) ((gp) & 0x1F) - -void gpio_info(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/hardware.h deleted file mode 100644 index 98fe56e68..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/hardware.h +++ /dev/null @@ -1,617 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on: - * - * ------------------------------------------------------------------------- - * - * linux/include/asm-arm/arch-davinci/hardware.h - * - * Copyright (C) 2006 Texas Instruments. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <config.h> -#include <linux/sizes.h> - -#define REG(addr) (*(volatile unsigned int *)(addr)) -#define REG_P(addr) ((volatile unsigned int *)(addr)) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int * dv_reg_p; - -/* - * Base register addresses - * - * NOTE: some of these DM6446-specific addresses DO NOT WORK - * on other DaVinci chips. Double check them before you try - * using the addresses ... or PSC module identifiers, etc. - */ -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_DMA_3PCC_BASE (0x01c00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) -#define DAVINCI_UART0_BASE (0x01c20000) -#define DAVINCI_UART1_BASE (0x01c20400) -#define DAVINCI_TIMER3_BASE (0x01c20800) -#define DAVINCI_I2C_BASE (0x01c21000) -#define DAVINCI_TIMER0_BASE (0x01c21400) -#define DAVINCI_TIMER1_BASE (0x01c21800) -#define DAVINCI_WDOG_BASE (0x01c21c00) -#define DAVINCI_PWM0_BASE (0x01c22000) -#define DAVINCI_PWM1_BASE (0x01c22400) -#define DAVINCI_PWM2_BASE (0x01c22800) -#define DAVINCI_TIMER4_BASE (0x01c23800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) -#define DAVINCI_ARM_INTC_BASE (0x01c48000) -#define DAVINCI_USB_OTG_BASE (0x01c64000) -#define DAVINCI_CFC_ATA_BASE (0x01c66000) -#define DAVINCI_SPI_BASE (0x01c66800) -#define DAVINCI_GPIO_BASE (0x01c67000) -#define DAVINCI_VPSS_REGS_BASE (0x01c70000) -#if !defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#endif -#define DAVINCI_DDR_BASE (0x80000000) - -#ifdef CONFIG_SOC_DM644X -#define DAVINCI_UART2_BASE 0x01c20800 -#define DAVINCI_UHPI_BASE 0x01c67800 -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000 -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000 -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000 -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000 -#define DAVINCI_IMCOP_BASE 0x01cc0000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000 -#define DAVINCI_VLYNQ_BASE 0x01e01000 -#define DAVINCI_ASP_BASE 0x01e02000 -#define DAVINCI_MMC_SD_BASE 0x01e10000 -#define DAVINCI_MS_BASE 0x01e20000 -#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000 - -#elif defined(CONFIG_SOC_DM355) -#define DAVINCI_MMC_SD1_BASE 0x01e00000 -#define DAVINCI_ASP0_BASE 0x01e02000 -#define DAVINCI_ASP1_BASE 0x01e04000 -#define DAVINCI_UART2_BASE 0x01e06000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 -#define DAVINCI_MMC_SD0_BASE 0x01e11000 - -#elif defined(CONFIG_SOC_DM365) -#define DAVINCI_MMC_SD1_BASE 0x01d00000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 -#define DAVINCI_MMC_SD0_BASE 0x01d11000 -#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000 -#define DAVINCI_SPI0_BASE 0x01c66000 -#define DAVINCI_SPI1_BASE 0x01c66800 - -#elif defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 - -#endif - -#else /* CONFIG_SOC_DA8XX */ - -#define DAVINCI_UART0_BASE 0x01c42000 -#define DAVINCI_UART1_BASE 0x01d0c000 -#define DAVINCI_UART2_BASE 0x01d0d000 -#define DAVINCI_I2C0_BASE 0x01c22000 -#define DAVINCI_I2C1_BASE 0x01e28000 -#define DAVINCI_TIMER0_BASE 0x01c20000 -#define DAVINCI_TIMER1_BASE 0x01c21000 -#define DAVINCI_WDOG_BASE 0x01c21000 -#define DAVINCI_RTC_BASE 0x01c23000 -#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 -#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 -#define DAVINCI_PSC0_BASE 0x01c10000 -#define DAVINCI_PSC1_BASE 0x01e27000 -#define DAVINCI_SPI0_BASE 0x01c41000 -#define DAVINCI_USB_OTG_BASE 0x01e00000 -#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \ - 0x01e12000 : 0x01f0e000) -#define DAVINCI_GPIO_BASE 0x01e26000 -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 -#define DAVINCI_SYSCFG1_BASE 0x01e2c000 -#define DAVINCI_MMC_SD0_BASE 0x01c40000 -#define DAVINCI_MMC_SD1_BASE 0x01e1b000 -#define DAVINCI_TIMER2_BASE 0x01f0c000 -#define DAVINCI_TIMER3_BASE 0x01f0d000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000 -#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000 -#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 -#define DAVINCI_INTC_BASE 0xfffee000 -#define DAVINCI_BOOTCFG_BASE 0x01c14000 -#define DAVINCI_LCD_CNTL_BASE 0x01e13000 -#define DAVINCI_L3CBARAM_BASE 0x80000000 -#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) -#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24) -#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) -#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) - -#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) -#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) -#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) -#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) -#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) -#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) -#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) -#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) -#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88) -#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c) -#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90) -#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94) -#endif /* CONFIG_SOC_DA8XX */ - -/* Power and Sleep Controller (PSC) Domains */ -#define DAVINCI_GPSC_ARMDOMAIN 0 -#define DAVINCI_GPSC_DSPDOMAIN 1 - -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_LPSC_VPSSMSTR 0 -#define DAVINCI_LPSC_VPSSSLV 1 -#define DAVINCI_LPSC_TPCC 2 -#define DAVINCI_LPSC_TPTC0 3 -#define DAVINCI_LPSC_TPTC1 4 -#define DAVINCI_LPSC_EMAC 5 -#define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_MDIO 7 -#define DAVINCI_LPSC_IEEE1394 8 -#define DAVINCI_LPSC_USB 9 -#define DAVINCI_LPSC_ATA 10 -#define DAVINCI_LPSC_VLYNQ 11 -#define DAVINCI_LPSC_UHPI 12 -#define DAVINCI_LPSC_DDR_EMIF 13 -#define DAVINCI_LPSC_AEMIF 14 -#define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_MEMSTICK 16 -#define DAVINCI_LPSC_McBSP 17 -#define DAVINCI_LPSC_I2C 18 -#define DAVINCI_LPSC_UART0 19 -#define DAVINCI_LPSC_UART1 20 -#define DAVINCI_LPSC_UART2 21 -#define DAVINCI_LPSC_SPI 22 -#define DAVINCI_LPSC_PWM0 23 -#define DAVINCI_LPSC_PWM1 24 -#define DAVINCI_LPSC_PWM2 25 -#define DAVINCI_LPSC_GPIO 26 -#define DAVINCI_LPSC_TIMER0 27 -#define DAVINCI_LPSC_TIMER1 28 -#define DAVINCI_LPSC_TIMER2 29 -#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_LPSC_ARM 31 -#define DAVINCI_LPSC_SCR2 32 -#define DAVINCI_LPSC_SCR3 33 -#define DAVINCI_LPSC_SCR4 34 -#define DAVINCI_LPSC_CROSSBAR 35 -#define DAVINCI_LPSC_CFG27 36 -#define DAVINCI_LPSC_CFG3 37 -#define DAVINCI_LPSC_CFG5 38 -#define DAVINCI_LPSC_GEM 39 -#define DAVINCI_LPSC_IMCOP 40 -#define DAVINCI_LPSC_VPSSMASTER 47 -#define DAVINCI_LPSC_MJCP 50 -#define DAVINCI_LPSC_HDVICP 51 - -#define DAVINCI_DM646X_LPSC_EMAC 14 -#define DAVINCI_DM646X_LPSC_UART0 26 -#define DAVINCI_DM646X_LPSC_I2C 31 -#define DAVINCI_DM646X_LPSC_TIMER0 34 - -#else /* CONFIG_SOC_DA8XX */ - -#define DAVINCI_LPSC_TPCC 0 -#define DAVINCI_LPSC_TPTC0 1 -#define DAVINCI_LPSC_TPTC1 2 -#define DAVINCI_LPSC_AEMIF 3 -#define DAVINCI_LPSC_SPI0 4 -#define DAVINCI_LPSC_MMC_SD 5 -#define DAVINCI_LPSC_AINTC 6 -#define DAVINCI_LPSC_ARM_RAM_ROM 7 -#define DAVINCI_LPSC_SECCTL_KEYMGR 8 -#define DAVINCI_LPSC_UART0 9 -#define DAVINCI_LPSC_SCR0 10 -#define DAVINCI_LPSC_SCR1 11 -#define DAVINCI_LPSC_SCR2 12 -#define DAVINCI_LPSC_DMAX 13 -#define DAVINCI_LPSC_ARM 14 -#define DAVINCI_LPSC_GEM 15 - -/* for LPSCs in PSC1, offset from 32 for differentiation */ -#define DAVINCI_LPSC_PSC1_BASE 32 -#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1) -#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2) -#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3) -#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4) -#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5) -#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6) -#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7) -#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10) -#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11) -#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12) -#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) -#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16) -#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17) -#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18) -#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20) -#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31) - -/* DA830-specific peripherals */ -#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8) -#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9) -#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21) -#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24) -#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25) -#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26) - -/* DA850-specific peripherals */ -#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0) -#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8) -#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9) -#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14) -#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15) -#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18) -#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19) -#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21) -#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24) -#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25) -#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26) -#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27) -#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28) -#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29) -#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) - -#endif /* CONFIG_SOC_DA8XX */ - -void lpsc_on(unsigned int id); -void lpsc_syncreset(unsigned int id); -void lpsc_disable(unsigned int id); -void dsp_on(void); - -void davinci_enable_uart0(void); -void davinci_enable_emac(void); -void davinci_enable_i2c(void); -void davinci_errata_workarounds(void); - -#ifndef CONFIG_SOC_DA8XX - -/* Some PSC defines */ -#define PSC_CHP_SHRTSW (0x01c40038) -#define PSC_GBLCTL (0x01c41010) -#define PSC_EPCPR (0x01c41070) -#define PSC_EPCCR (0x01c41078) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) -#define PSC_PDSTAT (0x01c41200) -#define PSC_PDSTAT1 (0x01c41204) -#define PSC_PDCTL (0x01c41300) -#define PSC_PDCTL1 (0x01c41304) - -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) - -#define VDD3P3V_PWDN (0x01c40048) -#define UART0_PWREMU_MGMT (0x01c20030) - -#define PSC_SILVER_BULLET (0x01c41a20) - -#else /* CONFIG_SOC_DA8XX */ - -#define PSC_ENABLE 0x3 -#define PSC_DISABLE 0x2 -#define PSC_SYNCRESET 0x1 -#define PSC_SWRSTDISABLE 0x0 - -#define PSC_PSC0_MODULE_ID_CNT 16 -#define PSC_PSC1_MODULE_ID_CNT 32 - -#define UART0_PWREMU_MGMT (0x01c42030) - -struct davinci_psc_regs { - dv_reg revid; - dv_reg rsvd0[71]; - dv_reg ptcmd; - dv_reg rsvd1; - dv_reg ptstat; - dv_reg rsvd2[437]; - union { - struct { - dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT]; - dv_reg rsvd3[112]; - dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; - } psc0; - struct { - dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT]; - dv_reg rsvd3[96]; - dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; - } psc1; - }; -}; - -#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) -#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) - -#endif /* CONFIG_SOC_DA8XX */ - -#define PSC_MDSTAT_STATE 0x3f -#define PSC_MDCTL_NEXT 0x07 - -#ifndef CONFIG_SOC_DA8XX - -/* Miscellania... */ -#define VBPR (0x20000020) - -/* NOTE: system control modules are *highly* chip-specific, both - * as to register content (e.g. for muxing) and which registers exist. - */ -#define PINMUX0 0x01c40000 -#define PINMUX1 0x01c40004 -#define PINMUX2 0x01c40008 -#define PINMUX3 0x01c4000c -#define PINMUX4 0x01c40010 - -struct davinci_uart_ctrl_regs { - dv_reg revid1; - dv_reg res; - dv_reg pwremu_mgmt; - dv_reg mdr; -}; - -#define DAVINCI_UART_CTRL_BASE 0x28 - -/* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) - -#else /* CONFIG_SOC_DA8XX */ - -struct davinci_pllc_regs { - dv_reg revid; - dv_reg rsvd1[56]; - dv_reg rstype; - dv_reg rsvd2[6]; - dv_reg pllctl; - dv_reg ocsel; - dv_reg rsvd3[2]; - dv_reg pllm; - dv_reg prediv; - dv_reg plldiv1; - dv_reg plldiv2; - dv_reg plldiv3; - dv_reg oscdiv; - dv_reg postdiv; - dv_reg rsvd4[3]; - dv_reg pllcmd; - dv_reg pllstat; - dv_reg alnctl; - dv_reg dchange; - dv_reg cken; - dv_reg ckstat; - dv_reg systat; - dv_reg rsvd5[3]; - dv_reg plldiv4; - dv_reg plldiv5; - dv_reg plldiv6; - dv_reg plldiv7; - dv_reg rsvd6[32]; - dv_reg emucnt0; - dv_reg emucnt1; -}; - -#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) -#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE) -#define DAVINCI_PLLC_DIV_MASK 0x1f - -/* - * A clock ID is a 32-bit number where bit 16 represents the PLL controller - * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor, - * counting from 1. Clock IDs may be passed to clk_get(). - */ - -/* flags to select PLL controller */ -#define DAVINCI_PLLC0_FLAG (0) -#define DAVINCI_PLLC1_FLAG (1 << 16) - -enum davinci_clk_ids { - /* - * Clock IDs for PLL outputs. Each may be switched on/off - * independently, and each may map to one or more peripherals. - */ - DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, - DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, - DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, - DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, - DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, - - /* map peripherals to clock IDs */ - DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, - DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, - DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, - DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, - DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, - DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2, - - /* special clock ID - output of PLL multiplier */ - DAVINCI_PLLM_CLKID = 0x0FF, - - /* special clock ID - output of PLL post divisor */ - DAVINCI_PLLC_CLKID = 0x100, - - /* special clock ID - PLL bypass */ - DAVINCI_AUXCLK_CLKID = 0x101, -}; - -#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ - : get_async3_src()) - -#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ - : get_async3_src()) - -int clk_get(enum davinci_clk_ids id); - -/* Boot config */ -struct davinci_syscfg_regs { - dv_reg revid; - dv_reg rsvd[13]; - dv_reg kick0; - dv_reg kick1; - dv_reg rsvd1[52]; - dv_reg mstpri[3]; - dv_reg rsvd2; - dv_reg pinmux[20]; - dv_reg suspsrc; - dv_reg chipsig; - dv_reg chipsig_clr; - dv_reg cfgchip0; - dv_reg cfgchip1; - dv_reg cfgchip2; - dv_reg cfgchip3; - dv_reg cfgchip4; -}; - -#define davinci_syscfg_regs \ - ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) - -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - -/* Emulation suspend bits */ -#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) -#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) -#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) -#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) -#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) -#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) -#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) - -struct davinci_syscfg1_regs { - dv_reg vtpio_ctl; - dv_reg ddr_slew; - dv_reg deepsleep; - dv_reg pupd_ena; - dv_reg pupd_sel; - dv_reg rxactive; - dv_reg pwrdwn; -}; - -#define davinci_syscfg1_regs \ - ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) - -#define DDR_SLEW_CMOSEN_BIT 4 -#define DDR_SLEW_DDR_PDENA_BIT 5 - -#define VTP_POWERDWN (1 << 6) -#define VTP_LOCK (1 << 7) -#define VTP_CLKRZ (1 << 13) -#define VTP_READY (1 << 15) -#define VTP_IOPWRDWN (1 << 14) - -#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13 -#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0 - -/* Interrupt controller */ -struct davinci_aintc_regs { - dv_reg revid; - dv_reg cr; - dv_reg dummy0[2]; - dv_reg ger; - dv_reg dummy1[219]; - dv_reg ecr1; - dv_reg ecr2; - dv_reg ecr3; - dv_reg dummy2[1117]; - dv_reg hier; -}; - -#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE) - -struct davinci_uart_ctrl_regs { - dv_reg revid1; - dv_reg revid2; - dv_reg pwremu_mgmt; - dv_reg mdr; -}; - -#define DAVINCI_UART_CTRL_BASE 0x28 -#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE) -#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE) -#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE) - -#define davinci_uart0_ctrl_regs \ - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR) -#define davinci_uart1_ctrl_regs \ - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR) -#define davinci_uart2_ctrl_regs \ - ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR) - -/* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) - -static inline int cpu_is_da830(void) -{ - unsigned int jtag_id = REG(JTAG_ID_REG); - unsigned short part_no = (jtag_id >> 12) & 0xffff; - - return ((part_no == 0xb7df) ? 1 : 0); -} -static inline int cpu_is_da850(void) -{ - unsigned int jtag_id = REG(JTAG_ID_REG); - unsigned short part_no = (jtag_id >> 12) & 0xffff; - - return ((part_no == 0xb7d1) ? 1 : 0); -} - -static inline enum davinci_clk_ids get_async3_src(void) -{ - return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? - DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2; -} - -#endif /* CONFIG_SOC_DA8XX */ - -#if defined(CONFIG_SOC_DM365) -#include <asm/arch/aintc_defs.h> -#include <asm/arch/ddr2_defs.h> -#include <asm/arch/emif_defs.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pll_defs.h> -#include <asm/arch/psc_defs.h> -#include <asm/arch/syscfg_defs.h> -#include <asm/arch/timer_defs.h> - -#define TMPBUF 0x00017ff8 -#define TMPSTATUS 0x00017ff0 -#define DV_TMPBUF_VAL 0x591b3ed7 -#define FLAG_PORRST 0x00000001 -#define FLAG_WDTRST 0x00000002 -#define FLAG_FLGON 0x00000004 -#define FLAG_FLGOFF 0x00000010 - -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/i2c_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/i2c_defs.h deleted file mode 100644 index 06da8947b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/i2c_defs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2004-2014 - * Texas Instruments, <www.ti.com> - * - * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _I2C_DEFS_H_ -#define _I2C_DEFS_H_ - -#ifndef CONFIG_SOC_DA8XX -#define I2C_BASE 0x01c21000 -#else -#define I2C_BASE 0x01c22000 -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/nand_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/nand_defs.h deleted file mode 100644 index dee1c6f81..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/nand_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Parts shamelesly stolen from Linux Kernel source tree. - * - * ------------------------------------------------------------ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include <asm/arch/hardware.h> - -#ifdef CONFIG_SOC_DM646X -#define MASK_CLE 0x80000 -#define MASK_ALE 0x40000 -#else -#define MASK_CLE 0x10 -#define MASK_ALE 0x08 -#endif - -#ifdef CONFIG_SYS_NAND_MASK_CLE -#undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE -#endif -#ifdef CONFIG_SYS_NAND_MASK_ALE -#undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE -#endif - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pinmux_defs.h deleted file mode 100644 index 2d82af554..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Pinmux configurations for the DAxxx SoCs - * - * Copyright (C) 2011 OMICRON electronics GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_PINMUX_DEFS_H -#define __ASM_ARCH_PINMUX_DEFS_H - -#include <asm/arch/davinci_misc.h> -#include <config.h> - -/* SPI0 pin muxer settings */ -extern const struct pinmux_config spi0_pins_base[3]; -extern const struct pinmux_config spi0_pins_scs0[1]; -extern const struct pinmux_config spi0_pins_ena[1]; - -/* SPI1 pin muxer settings */ -extern const struct pinmux_config spi1_pins_base[3]; -extern const struct pinmux_config spi1_pins_scs0[1]; - -/* UART pin muxer settings */ -extern const struct pinmux_config uart0_pins_txrx[2]; -extern const struct pinmux_config uart0_pins_rtscts[2]; -extern const struct pinmux_config uart1_pins_txrx[2]; -extern const struct pinmux_config uart2_pins_txrx[2]; -extern const struct pinmux_config uart2_pins_rtscts[2]; - -/* EMAC pin muxer settings*/ -extern const struct pinmux_config emac_pins_rmii[8]; -extern const struct pinmux_config emac_pins_rmii_clk_source[1]; -extern const struct pinmux_config emac_pins_mii[15]; -extern const struct pinmux_config emac_pins_mdio[2]; - -/* I2C pin muxer settings */ -extern const struct pinmux_config i2c0_pins[2]; -extern const struct pinmux_config i2c1_pins[2]; - -/* EMIFA pin muxer settings */ -extern const struct pinmux_config emifa_pins[40]; -extern const struct pinmux_config emifa_pins_cs0[1]; -extern const struct pinmux_config emifa_pins_cs2[1]; -extern const struct pinmux_config emifa_pins_cs3[1]; -extern const struct pinmux_config emifa_pins_cs4[1]; -extern const struct pinmux_config emifa_pins_nand[12]; -extern const struct pinmux_config emifa_pins_nor[43]; - -/* USB pin mux setting */ -extern const struct pinmux_config usb_pins[1]; - -/* MMC pin muxer settings */ -extern const struct pinmux_config mmc0_pins_8bit[10]; -extern const struct pinmux_config mmc0_pins[6]; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pll_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pll_defs.h deleted file mode 100644 index d083cccad..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pll_defs.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _DV_PLL_DEFS_H_ -#define _DV_PLL_DEFS_H_ - -struct dv_pll_regs { - unsigned int pid; /* 0x00 */ - unsigned char rsvd0[224]; /* 0x04 */ - unsigned int rstype; /* 0xe4 */ - unsigned char rsvd1[24]; /* 0xe8 */ - unsigned int pllctl; /* 0x100 */ - unsigned char rsvd2[4]; /* 0x104 */ - unsigned int secctl; /* 0x108 */ - unsigned int rv; /* 0x10c */ - unsigned int pllm; /* 0x110 */ - unsigned int prediv; /* 0x114 */ - unsigned int plldiv1; /* 0x118 */ - unsigned int plldiv2; /* 0x11c */ - unsigned int plldiv3; /* 0x120 */ - unsigned int oscdiv1; /* 0x124 */ - unsigned int postdiv; /* 0x128 */ - unsigned int bpdiv; /* 0x12c */ - unsigned char rsvd5[8]; /* 0x130 */ - unsigned int pllcmd; /* 0x138 */ - unsigned int pllstat; /* 0x13c */ - unsigned int alnctl; /* 0x140 */ - unsigned int dchange; /* 0x144 */ - unsigned int cken; /* 0x148 */ - unsigned int ckstat; /* 0x14c */ - unsigned int systat; /* 0x150 */ - unsigned char rsvd6[12]; /* 0x154 */ - unsigned int plldiv4; /* 0x160 */ - unsigned int plldiv5; /* 0x164 */ - unsigned int plldiv6; /* 0x168 */ - unsigned int plldiv7; /* 0x16C */ - unsigned int plldiv8; /* 0x170 */ - unsigned int plldiv9; /* 0x174 */ -}; - -#define PLL_MASTER_LOCK (1 << 4) - -#define PLLCTL_CLOCK_MODE_SHIFT 8 -#define PLLCTL_PLLEN (1 << 0) -#define PLLCTL_PLLPWRDN (1 << 1) -#define PLLCTL_PLLRST (1 << 3) -#define PLLCTL_PLLDIS (1 << 4) -#define PLLCTL_PLLENSRC (1 << 5) -#define PLLCTL_RES_9 (1 << 8) -#define PLLCTL_EXTCLKSRC (1 << 9) - -#define PLL_DIVEN (1 << 15) -#define PLL_POSTDEN PLL_DIVEN - -#define PLL_SCSCFG3_DIV45PENA (1 << 2) -#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1) - -#define PLL_RSTYPE_POR (1 << 0) -#define PLL_RSTYPE_XWRST (1 << 1) - -#define PLLSECCTL_TINITZ (1 << 16) -#define PLLSECCTL_TENABLE (1 << 17) -#define PLLSECCTL_TENABLEDIV (1 << 18) -#define PLLSECCTL_STOPMODE (1 << 22) - -#define PLLCMD_GOSET (1 << 0) -#define PLLCMD_GOSTAT (1 << 0) - -#define PLL0_LOCK 0x07000000 -#define PLL1_LOCK 0x07000000 - -#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) -#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE) - -#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2)) -#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7)) -#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4)) - -unsigned int davinci_clk_get(unsigned int div); -#endif /* _DV_PLL_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/psc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/psc_defs.h deleted file mode 100644 index bcb558049..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/psc_defs.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _DV_PSC_DEFS_H_ -#define _DV_PSC_DEFS_H_ - -/* - * Power/Sleep Ctrl Register structure - * See sprufb3.pdf, Chapter 7 - */ -struct dv_psc_regs { - unsigned int pid; /* 0x000 */ - unsigned char rsvd0[16]; /* 0x004 */ - unsigned char rsvd1[4]; /* 0x014 */ - unsigned int inteval; /* 0x018 */ - unsigned char rsvd2[36]; /* 0x01C */ - unsigned int merrpr0; /* 0x040 */ - unsigned int merrpr1; /* 0x044 */ - unsigned char rsvd3[8]; /* 0x048 */ - unsigned int merrcr0; /* 0x050 */ - unsigned int merrcr1; /* 0x054 */ - unsigned char rsvd4[8]; /* 0x058 */ - unsigned int perrpr; /* 0x060 */ - unsigned char rsvd5[4]; /* 0x064 */ - unsigned int perrcr; /* 0x068 */ - unsigned char rsvd6[4]; /* 0x06C */ - unsigned int epcpr; /* 0x070 */ - unsigned char rsvd7[4]; /* 0x074 */ - unsigned int epccr; /* 0x078 */ - unsigned char rsvd8[144]; /* 0x07C */ - unsigned char rsvd9[20]; /* 0x10C */ - unsigned int ptcmd; /* 0x120 */ - unsigned char rsvd10[4]; /* 0x124 */ - unsigned int ptstat; /* 0x128 */ - unsigned char rsvd11[212]; /* 0x12C */ - unsigned int pdstat0; /* 0x200 */ - unsigned int pdstat1; /* 0x204 */ - unsigned char rsvd12[248]; /* 0x208 */ - unsigned int pdctl0; /* 0x300 */ - unsigned int pdctl1; /* 0x304 */ - unsigned char rsvd13[536]; /* 0x308 */ - unsigned int mckout0; /* 0x520 */ - unsigned int mckout1; /* 0x524 */ - unsigned char rsvd14[728]; /* 0x528 */ - unsigned int mdstat[52]; /* 0x800 */ - unsigned char rsvd15[304]; /* 0x8D0 */ - unsigned int mdctl[52]; /* 0xA00 */ -}; - -/* PSC constants */ -#define EMURSTIE_MASK (0x00000200) - -#define PD0 (0) - -#define PSC_ENABLE (0x3) -#define PSC_DISABLE (0x2) -#define PSC_SYNCRESET (0x1) -#define PSC_SWRSTDISABLE (0x0) - -#define PSC_GOSTAT (1 << 0) -#define PSC_MD_STATE_MSK (0x1f) - -#define PSC_CMD_GO (1 << 0) - -#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) - -#endif /* _DV_PSC_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/sdmmc_defs.h deleted file mode 100644 index 9aa3f4ab2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/sdmmc_defs.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c - * - * Copyright (C) 2010 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SDMMC_DEFS_H_ -#define _SDMMC_DEFS_H_ - -#include <asm/arch/hardware.h> - -/* MMC Control Reg fields */ -#define MMCCTL_DATRST (1 << 0) -#define MMCCTL_CMDRST (1 << 1) -#define MMCCTL_WIDTH_4_BIT (1 << 2) -#define MMCCTL_DATEG_DISABLED (0 << 6) -#define MMCCTL_DATEG_RISING (1 << 6) -#define MMCCTL_DATEG_FALLING (2 << 6) -#define MMCCTL_DATEG_BOTH (3 << 6) -#define MMCCTL_PERMDR_LE (0 << 9) -#define MMCCTL_PERMDR_BE (1 << 9) -#define MMCCTL_PERMDX_LE (0 << 10) -#define MMCCTL_PERMDX_BE (1 << 10) - -/* MMC Clock Control Reg fields */ -#define MMCCLK_CLKEN (1 << 8) -#define MMCCLK_CLKRT_MASK (0xFF << 0) - -/* MMC Status Reg0 fields */ -#define MMCST0_DATDNE (1 << 0) -#define MMCST0_BSYDNE (1 << 1) -#define MMCST0_RSPDNE (1 << 2) -#define MMCST0_TOUTRD (1 << 3) -#define MMCST0_TOUTRS (1 << 4) -#define MMCST0_CRCWR (1 << 5) -#define MMCST0_CRCRD (1 << 6) -#define MMCST0_CRCRS (1 << 7) -#define MMCST0_DXRDY (1 << 9) -#define MMCST0_DRRDY (1 << 10) -#define MMCST0_DATED (1 << 11) -#define MMCST0_TRNDNE (1 << 12) - -#define MMCST0_ERR_MASK (0x00F8) - -/* MMC Status Reg1 fields */ -#define MMCST1_BUSY (1 << 0) -#define MMCST1_CLKSTP (1 << 1) -#define MMCST1_DXEMP (1 << 2) -#define MMCST1_DRFUL (1 << 3) -#define MMCST1_DAT3ST (1 << 4) -#define MMCST1_FIFOEMP (1 << 5) -#define MMCST1_FIFOFUL (1 << 6) - -/* MMC INT Mask Reg fields */ -#define MMCIM_EDATDNE (1 << 0) -#define MMCIM_EBSYDNE (1 << 1) -#define MMCIM_ERSPDNE (1 << 2) -#define MMCIM_ETOUTRD (1 << 3) -#define MMCIM_ETOUTRS (1 << 4) -#define MMCIM_ECRCWR (1 << 5) -#define MMCIM_ECRCRD (1 << 6) -#define MMCIM_ECRCRS (1 << 7) -#define MMCIM_EDXRDY (1 << 9) -#define MMCIM_EDRRDY (1 << 10) -#define MMCIM_EDATED (1 << 11) -#define MMCIM_ETRNDNE (1 << 12) - -#define MMCIM_MASKALL (0xFFFFFFFF) - -/* MMC Resp Tout Reg fields */ -#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */ -#define MMCTOR_TOD_20_16_SHIFT (8) - -/* MMC Data Read Tout Reg fields */ -#define MMCTOD_TOD_0_15_MASK (0xFFFF) - -/* MMC Block len Reg fields */ -#define MMCBLEN_BLEN_MASK (0xFFF) - -/* MMC Num Blocks Reg fields */ -#define MMCNBLK_NBLK_MASK (0xFFFF) -#define MMCNBLK_NBLK_MAX (0xFFFF) - -/* MMC Num Blocks Counter Reg fields */ -#define MMCNBLC_NBLC_MASK (0xFFFF) - -/* MMC Cmd Reg fields */ -#define MMCCMD_CMD_MASK (0x3F) -#define MMCCMD_PPLEN (1 << 7) -#define MMCCMD_BSYEXP (1 << 8) -#define MMCCMD_RSPFMT_NONE (0 << 9) -#define MMCCMD_RSPFMT_R1567 (1 << 9) -#define MMCCMD_RSPFMT_R2 (2 << 9) -#define MMCCMD_RSPFMT_R3 (3 << 9) -#define MMCCMD_DTRW (1 << 11) -#define MMCCMD_STRMTP (1 << 12) -#define MMCCMD_WDATX (1 << 13) -#define MMCCMD_INITCK (1 << 14) -#define MMCCMD_DCLR (1 << 15) -#define MMCCMD_DMATRIG (1 << 16) - -/* FIFO control Reg fields */ -#define MMCFIFOCTL_FIFORST (1 << 0) -#define MMCFIFOCTL_FIFODIR (1 << 1) -#define MMCFIFOCTL_FIFOLEV (1 << 2) -#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ -#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ -#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ -#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ - -/* Davinci MMC Register definitions */ -struct davinci_mmc_regs { - dv_reg mmcctl; - dv_reg mmcclk; - dv_reg mmcst0; - dv_reg mmcst1; - dv_reg mmcim; - dv_reg mmctor; - dv_reg mmctod; - dv_reg mmcblen; - dv_reg mmcnblk; - dv_reg mmcnblc; - dv_reg mmcdrr; - dv_reg mmcdxr; - dv_reg mmccmd; - dv_reg mmcarghl; - dv_reg mmcrsp01; - dv_reg mmcrsp23; - dv_reg mmcrsp45; - dv_reg mmcrsp67; - dv_reg mmcdrsp; - dv_reg mmcetok; - dv_reg mmccidx; - dv_reg mmcckc; - dv_reg mmctorc; - dv_reg mmctodc; - dv_reg mmcblnc; - dv_reg sdioctl; - dv_reg sdiost0; - dv_reg sdioien; - dv_reg sdioist; - dv_reg mmcfifoctl; -}; - -/* Davinci MMC board definitions */ -struct davinci_mmc { - struct davinci_mmc_regs *reg_base; /* Register base address */ - uint input_clk; /* Input clock to MMC controller */ - uint host_caps; /* Host capabilities */ - uint voltages; /* Host supported voltages */ - uint version; /* MMC Controller version */ - struct mmc_config cfg; -}; - -enum { - MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */ - MMC_CTLR_VERSION_2, /* DA830 */ -}; - -int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host); - -#endif /* _SDMMC_DEFS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/spl.h deleted file mode 100644 index 5afe0d4ba..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/spl.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NAND 1 -#define BOOT_DEVICE_SPI 2 -#define BOOT_DEVICE_MMC1 3 -#define BOOT_DEVICE_MMC2 4 /* dummy */ -#define BOOT_DEVICE_MMC2_2 5 /* dummy */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/syscfg_defs.h deleted file mode 100644 index 812088f37..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/syscfg_defs.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _DV_SYSCFG_DEFS_H_ -#define _DV_SYSCFG_DEFS_H_ - -#ifndef CONFIG_SOC_DA8XX -/* System Control Module register structure for DM365 */ -struct dv_sys_module_regs { - unsigned int pinmux[5]; /* 0x00 */ - unsigned int bootcfg; /* 0x14 */ - unsigned int arm_intmux; /* 0x18 */ - unsigned int edma_evtmux; /* 0x1C */ - unsigned int ddr_slew; /* 0x20 */ - unsigned int clkout; /* 0x24 */ - unsigned int device_id; /* 0x28 */ - unsigned int vdac_config; /* 0x2C */ - unsigned int timer64_ctl; /* 0x30 */ - unsigned int usbbphy_ctl; /* 0x34 */ - unsigned int misc; /* 0x38 */ - unsigned int mstpri[2]; /* 0x3C */ - unsigned int vpss_clkctl; /* 0x44 */ - unsigned int peri_clkctl; /* 0x48 */ - unsigned int deepsleep; /* 0x4C */ - unsigned int dft_enable; /* 0x50 */ - unsigned int debounce[8]; /* 0x54 */ - unsigned int vtpiocr; /* 0x74 */ - unsigned int pupdctl0; /* 0x78 */ - unsigned int pupdctl1; /* 0x7C */ - unsigned int hdimcopbt; /* 0x80 */ - unsigned int pll0_config; /* 0x84 */ - unsigned int pll1_config; /* 0x88 */ -}; - -#define VPTIO_RDY (1 << 15) -#define VPTIO_IOPWRDN (1 << 14) -#define VPTIO_CLRZ (1 << 13) -#define VPTIO_LOCK (1 << 7) -#define VPTIO_PWRDN (1 << 6) - -#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) - -#define dv_sys_module_regs \ - ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) - -#endif /* !CONFIG_SOC_DA8XX */ -#endif /* _DV_SYSCFG_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/timer_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/timer_defs.h deleted file mode 100644 index 94d18320d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/timer_defs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2011 DENX Software Engineering GmbH - * Heiko Schocher <hs@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _TIMER_DEFS_H_ -#define _TIMER_DEFS_H_ - -struct davinci_timer { - u_int32_t pid12; - u_int32_t emumgt; - u_int32_t na1; - u_int32_t na2; - u_int32_t tim12; - u_int32_t tim34; - u_int32_t prd12; - u_int32_t prd34; - u_int32_t tcr; - u_int32_t tgcr; - u_int32_t wdtcr; -}; - -#define DV_TIMER_TCR_ENAMODE_MASK 3 - -#define DV_TIMER_TCR_ENAMODE12_SHIFT 6 -#define DV_TIMER_TCR_CLKSRC12_SHIFT 8 -#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10 -#define DV_TIMER_TCR_CAPMODE12_SHIFT 11 -#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12 -#define DV_TIMER_TCR_ENAMODE34_SHIFT 22 -#define DV_TIMER_TCR_CLKSRC34_SHIFT 24 -#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26 -#define DV_TIMER_TCR_CAPMODE34_SHIFT 27 -#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28 - -#define DV_WDT_ENABLE_SYS_RESET 0x00020000 -#define DV_WDT_TRIGGER_SYS_RESET 0x00020002 - -#ifdef CONFIG_HW_WATCHDOG -void davinci_hw_watchdog_enable(void); -void davinci_hw_watchdog_reset(void); -#endif -#endif /* _TIMER_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h deleted file mode 100644 index 9e7f2f348..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Cirrus Logic EP93xx register definitions. - * - * Copyright (C) 2009 - * Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 - * Dominic Rath <Dominic.Rath@gmx.de> - * - * Copyright (C) 2004, 2005 - * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> - * - * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is - * - * Copyright (C) 2004 Ray Lehtiniemi - * Copyright (C) 2003 Cirrus Logic, Inc - * Copyright (C) 1999 ARM Limited. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define EP93XX_AHB_BASE 0x80000000 -#define EP93XX_APB_BASE 0x80800000 - -/* - * 0x80000000 - 0x8000FFFF: DMA - */ -#define DMA_OFFSET 0x000000 -#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) - -#ifndef __ASSEMBLY__ -struct dma_channel { - uint32_t control; - uint32_t interrupt; - uint32_t ppalloc; - uint32_t status; - uint32_t reserved0; - uint32_t remain; - uint32_t reserved1[2]; - uint32_t maxcnt0; - uint32_t base0; - uint32_t current0; - uint32_t reserved2; - uint32_t maxcnt1; - uint32_t base1; - uint32_t current1; - uint32_t reserved3; -}; - -struct dma_regs { - struct dma_channel m2p_channel_0; - struct dma_channel m2p_channel_1; - struct dma_channel m2p_channel_2; - struct dma_channel m2p_channel_3; - struct dma_channel m2m_channel_0; - struct dma_channel m2m_channel_1; - struct dma_channel reserved0[2]; - struct dma_channel m2p_channel_5; - struct dma_channel m2p_channel_4; - struct dma_channel m2p_channel_7; - struct dma_channel m2p_channel_6; - struct dma_channel m2p_channel_9; - struct dma_channel m2p_channel_8; - uint32_t channel_arbitration; - uint32_t reserved[15]; - uint32_t global_interrupt; -}; -#endif - -/* - * 0x80010000 - 0x8001FFFF: Ethernet MAC - */ -#define MAC_OFFSET 0x010000 -#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) - -#ifndef __ASSEMBLY__ -struct mac_queue { - uint32_t badd; - union { /* deal with half-word aligned registers */ - uint32_t blen; - union { - uint16_t filler; - uint16_t curlen; - }; - }; - uint32_t curadd; -}; - -struct mac_regs { - uint32_t rxctl; - uint32_t txctl; - uint32_t testctl; - uint32_t reserved0; - uint32_t miicmd; - uint32_t miidata; - uint32_t miists; - uint32_t reserved1; - uint32_t selfctl; - uint32_t inten; - uint32_t intstsp; - uint32_t intstsc; - uint32_t reserved2[2]; - uint32_t diagad; - uint32_t diagdata; - uint32_t gt; - uint32_t fct; - uint32_t fcf; - uint32_t afp; - union { - struct { - uint32_t indad; - uint32_t indad_upper; - }; - uint32_t hashtbl; - }; - uint32_t reserved3[2]; - uint32_t giintsts; - uint32_t giintmsk; - uint32_t giintrosts; - uint32_t giintfrc; - uint32_t txcollcnt; - uint32_t rxmissnct; - uint32_t rxruntcnt; - uint32_t reserved4; - uint32_t bmctl; - uint32_t bmsts; - uint32_t rxbca; - uint32_t reserved5; - struct mac_queue rxdq; - uint32_t rxdqenq; - struct mac_queue rxstsq; - uint32_t rxstsqenq; - struct mac_queue txdq; - uint32_t txdqenq; - struct mac_queue txstsq; - uint32_t reserved6; - uint32_t rxbufthrshld; - uint32_t txbufthrshld; - uint32_t rxststhrshld; - uint32_t txststhrshld; - uint32_t rxdthrshld; - uint32_t txdthrshld; - uint32_t maxfrmlen; - uint32_t maxhdrlen; -}; -#endif - -#define SELFCTL_RWP (1 << 7) -#define SELFCTL_GPO0 (1 << 5) -#define SELFCTL_PUWE (1 << 4) -#define SELFCTL_PDWE (1 << 3) -#define SELFCTL_MIIL (1 << 2) -#define SELFCTL_RESET (1 << 0) - -#define INTSTS_RWI (1 << 30) -#define INTSTS_RXMI (1 << 29) -#define INTSTS_RXBI (1 << 28) -#define INTSTS_RXSQI (1 << 27) -#define INTSTS_TXLEI (1 << 26) -#define INTSTS_ECIE (1 << 25) -#define INTSTS_TXUHI (1 << 24) -#define INTSTS_MOI (1 << 18) -#define INTSTS_TXCOI (1 << 17) -#define INTSTS_RXROI (1 << 16) -#define INTSTS_MIII (1 << 12) -#define INTSTS_PHYI (1 << 11) -#define INTSTS_TI (1 << 10) -#define INTSTS_AHBE (1 << 8) -#define INTSTS_OTHER (1 << 4) -#define INTSTS_TXSQ (1 << 3) -#define INTSTS_RXSQ (1 << 2) - -#define BMCTL_MT (1 << 13) -#define BMCTL_TT (1 << 12) -#define BMCTL_UNH (1 << 11) -#define BMCTL_TXCHR (1 << 10) -#define BMCTL_TXDIS (1 << 9) -#define BMCTL_TXEN (1 << 8) -#define BMCTL_EH2 (1 << 6) -#define BMCTL_EH1 (1 << 5) -#define BMCTL_EEOB (1 << 4) -#define BMCTL_RXCHR (1 << 2) -#define BMCTL_RXDIS (1 << 1) -#define BMCTL_RXEN (1 << 0) - -#define BMSTS_TXACT (1 << 7) -#define BMSTS_TP (1 << 4) -#define BMSTS_RXACT (1 << 3) -#define BMSTS_QID_MASK 0x07 -#define BMSTS_QID_RXDATA 0x00 -#define BMSTS_QID_TXDATA 0x01 -#define BMSTS_QID_RXSTS 0x02 -#define BMSTS_QID_TXSTS 0x03 -#define BMSTS_QID_RXDESC 0x04 -#define BMSTS_QID_TXDESC 0x05 - -#define AFP_MASK 0x07 -#define AFP_IAPRIMARY 0x00 -#define AFP_IASECONDARY1 0x01 -#define AFP_IASECONDARY2 0x02 -#define AFP_IASECONDARY3 0x03 -#define AFP_TX 0x06 -#define AFP_HASH 0x07 - -#define RXCTL_PAUSEA (1 << 20) -#define RXCTL_RXFCE1 (1 << 19) -#define RXCTL_RXFCE0 (1 << 18) -#define RXCTL_BCRC (1 << 17) -#define RXCTL_SRXON (1 << 16) -#define RXCTL_RCRCA (1 << 13) -#define RXCTL_RA (1 << 12) -#define RXCTL_PA (1 << 11) -#define RXCTL_BA (1 << 10) -#define RXCTL_MA (1 << 9) -#define RXCTL_IAHA (1 << 8) -#define RXCTL_IA3 (1 << 3) -#define RXCTL_IA2 (1 << 2) -#define RXCTL_IA1 (1 << 1) -#define RXCTL_IA0 (1 << 0) - -#define TXCTL_DEFDIS (1 << 7) -#define TXCTL_MBE (1 << 6) -#define TXCTL_ICRC (1 << 5) -#define TXCTL_TPD (1 << 4) -#define TXCTL_OCOLL (1 << 3) -#define TXCTL_SP (1 << 2) -#define TXCTL_PB (1 << 1) -#define TXCTL_STXON (1 << 0) - -#define MIICMD_REGAD_MASK (0x001F) -#define MIICMD_PHYAD_MASK (0x03E0) -#define MIICMD_OPCODE_MASK (0xC000) -#define MIICMD_PHYAD_8950 (0x0000) -#define MIICMD_OPCODE_READ (0x8000) -#define MIICMD_OPCODE_WRITE (0x4000) - -#define MIISTS_BUSY (1 << 0) - -/* - * 0x80020000 - 0x8002FFFF: USB OHCI - */ -#define USB_OFFSET 0x020000 -#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) - -/* - * 0x80030000 - 0x8003FFFF: Raster engine - */ -#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315)) -#define RASTER_OFFSET 0x030000 -#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) -#endif - -/* - * 0x80040000 - 0x8004FFFF: Graphics accelerator - */ -#if defined(CONFIG_EP9315) -#define GFX_OFFSET 0x040000 -#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) -#endif - -/* - * 0x80050000 - 0x8005FFFF: Reserved - */ - -/* - * 0x80060000 - 0x8006FFFF: SDRAM controller - */ -#define SDRAM_OFFSET 0x060000 -#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) - -#ifndef __ASSEMBLY__ -struct sdram_regs { - uint32_t reserved; - uint32_t glconfig; - uint32_t refrshtimr; - uint32_t bootsts; - uint32_t devcfg0; - uint32_t devcfg1; - uint32_t devcfg2; - uint32_t devcfg3; -}; -#endif - -#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2) -#define SDRAM_DEVCFG_BANKCOUNT (1 << 3) -#define SDRAM_DEVCFG_SROMLL (1 << 5) -#define SDRAM_DEVCFG_CASLAT_2 0x00010000 -#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000 - -#define GLCONFIG_INIT (1 << 0) -#define GLCONFIG_MRS (1 << 1) -#define GLCONFIG_SMEMBUSY (1 << 5) -#define GLCONFIG_LCR (1 << 6) -#define GLCONFIG_REARBEN (1 << 7) -#define GLCONFIG_CLKSHUTDOWN (1 << 30) -#define GLCONFIG_CKE (1 << 31) - -/* - * 0x80070000 - 0x8007FFFF: Reserved - */ - -/* - * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA - */ -#define SMC_OFFSET 0x080000 -#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) - -#ifndef __ASSEMBLY__ -struct smc_regs { - uint32_t bcr0; - uint32_t bcr1; - uint32_t bcr2; - uint32_t bcr3; - uint32_t reserved0[2]; - uint32_t bcr6; - uint32_t bcr7; -#if defined(CONFIG_EP9315) - uint32_t pcattribute; - uint32_t pccommon; - uint32_t pcio; - uint32_t reserved1[5]; - uint32_t pcmciactrl; -#endif -}; -#endif - -#define SMC_BCR_IDCY_SHIFT 0 -#define SMC_BCR_WST1_SHIFT 5 -#define SMC_BCR_BLE (1 << 10) -#define SMC_BCR_WST2_SHIFT 11 -#define SMC_BCR_MW_SHIFT 28 - -/* - * 0x80090000 - 0x8009FFFF: Boot ROM - */ - -/* - * 0x800A0000 - 0x800AFFFF: IDE interface - */ - -/* - * 0x800B0000 - 0x800BFFFF: VIC1 - */ - -/* - * 0x800C0000 - 0x800CFFFF: VIC2 - */ - -/* - * 0x800D0000 - 0x800FFFFF: Reserved - */ - -/* - * 0x80800000 - 0x8080FFFF: Reserved - */ - -/* - * 0x80810000 - 0x8081FFFF: Timers - */ -#define TIMER_OFFSET 0x010000 -#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) - -#ifndef __ASSEMBLY__ -struct timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t clear; -}; - -struct timer4 { - uint32_t value_low; - uint32_t value_high; -}; - -struct timer_regs { - struct timer timer1; - uint32_t reserved0[4]; - struct timer timer2; - uint32_t reserved1[12]; - struct timer4 timer4; - uint32_t reserved2[6]; - struct timer timer3; -}; -#endif - -/* - * 0x80820000 - 0x8082FFFF: I2S - */ -#define I2S_OFFSET 0x020000 -#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) - -/* - * 0x80830000 - 0x8083FFFF: Security - */ -#define SECURITY_OFFSET 0x030000 -#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) - -#define EXTENSIONID (SECURITY_BASE + 0x2714) - -/* - * 0x80840000 - 0x8084FFFF: GPIO - */ -#define GPIO_OFFSET 0x040000 -#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) - -#ifndef __ASSEMBLY__ -struct gpio_int { - uint32_t inttype1; - uint32_t inttype2; - uint32_t eoi; - uint32_t inten; - uint32_t intsts; - uint32_t rawintsts; - uint32_t db; -}; - -struct gpio_regs { - uint32_t padr; - uint32_t pbdr; - uint32_t pcdr; - uint32_t pddr; - uint32_t paddr; - uint32_t pbddr; - uint32_t pcddr; - uint32_t pdddr; - uint32_t pedr; - uint32_t peddr; - uint32_t reserved0[2]; - uint32_t pfdr; - uint32_t pfddr; - uint32_t pgdr; - uint32_t pgddr; - uint32_t phdr; - uint32_t phddr; - uint32_t reserved1; - uint32_t finttype1; - uint32_t finttype2; - uint32_t reserved2; - struct gpio_int pfint; - uint32_t reserved3[10]; - struct gpio_int paint; - struct gpio_int pbint; - uint32_t eedrive; -}; -#endif - -/* - * 0x80850000 - 0x8087FFFF: Reserved - */ - -/* - * 0x80880000 - 0x8088FFFF: AAC - */ -#define AAC_OFFSET 0x080000 -#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) - -/* - * 0x80890000 - 0x8089FFFF: Reserved - */ - -/* - * 0x808A0000 - 0x808AFFFF: SPI - */ -#define SPI_OFFSET 0x0A0000 -#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) - -/* - * 0x808B0000 - 0x808BFFFF: IrDA - */ -#define IRDA_OFFSET 0x0B0000 -#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) - -/* - * 0x808C0000 - 0x808CFFFF: UART1 - */ -#define UART1_OFFSET 0x0C0000 -#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) - -/* - * 0x808D0000 - 0x808DFFFF: UART2 - */ -#define UART2_OFFSET 0x0D0000 -#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) - -/* - * 0x808E0000 - 0x808EFFFF: UART3 - */ -#define UART3_OFFSET 0x0E0000 -#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) - -/* - * 0x808F0000 - 0x808FFFFF: Key Matrix - */ -#define KEY_OFFSET 0x0F0000 -#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) - -/* - * 0x80900000 - 0x8090FFFF: Touchscreen - */ -#define TOUCH_OFFSET 0x900000 -#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) - -/* - * 0x80910000 - 0x8091FFFF: Pulse Width Modulation - */ -#define PWM_OFFSET 0x910000 -#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) - -/* - * 0x80920000 - 0x8092FFFF: Real time clock - */ -#define RTC_OFFSET 0x920000 -#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) - -/* - * 0x80930000 - 0x8093FFFF: Syscon - */ -#define SYSCON_OFFSET 0x930000 -#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) - -#ifndef __ASSEMBLY__ -struct syscon_regs { - uint32_t pwrsts; - uint32_t pwrcnt; - uint32_t halt; - uint32_t stby; - uint32_t reserved0[2]; - uint32_t teoi; - uint32_t stfclr; - uint32_t clkset1; - uint32_t clkset2; - uint32_t reserved1[6]; - uint32_t scratch0; - uint32_t scratch1; - uint32_t reserved2[2]; - uint32_t apbwait; - uint32_t bustmstrarb; - uint32_t bootmodeclr; - uint32_t reserved3[9]; - uint32_t devicecfg; - uint32_t vidclkdiv; - uint32_t mirclkdiv; - uint32_t i2sclkdiv; - uint32_t keytchclkdiv; - uint32_t chipid; - uint32_t reserved4; - uint32_t syscfg; - uint32_t reserved5[8]; - uint32_t sysswlock; -}; -#else -#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040) -#endif - -#define SYSCON_PWRCNT_UART_BAUD (1 << 29) - -#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0 -#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5 -#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11 -#define SYSCON_CLKSET_PLL_PS_SHIFT 16 -#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 -#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 -#define SYSCON_CLKSET1_NBYP1 (1 << 23) -#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 - -#define SYSCON_CLKSET2_PLL2_EN (1 << 18) -#define SYSCON_CLKSET2_NBYP2 (1 << 19) -#define SYSCON_CLKSET2_USB_DIV_SHIFT 28 - -#define SYSCON_CHIPID_REV_MASK 0xF0000000 -#define SYSCON_DEVICECFG_SWRST (1 << 31) - -/* - * 0x80930000 - 0x8093FFFF: Watchdog Timer - */ -#define WATCHDOG_OFFSET 0x940000 -#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) - -/* - * 0x80950000 - 0x9000FFFF: Reserved - */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/adc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/adc.h deleted file mode 100644 index a0e26d705..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/adc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * MyungJoo Ham <myungjoo.ham@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_ADC_H_ -#define __ASM_ARM_ARCH_ADC_H_ - -#ifndef __ASSEMBLY__ -struct s5p_adc { - unsigned int adccon; - unsigned int adctsc; - unsigned int adcdly; - unsigned int adcdat0; - unsigned int adcdat1; - unsigned int adcupdn; - unsigned int adcclrint; - unsigned int adcmux; - unsigned int adcclrintpndnup; -}; -#endif - -#endif /* __ASM_ARM_ARCH_ADC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/board.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/board.h deleted file mode 100644 index 1b1cd0dd9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/board.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2013 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EXYNOS_BOARD_H -#define _EXYNOS_BOARD_H - -/* - * Exynos baord specific changes for - * board_init - */ -int exynos_init(void); - -/* - * Exynos board specific changes for - * board_early_init_f - */ -int exynos_early_init_f(void); - -/* - * Exynos board specific changes for - * board_power_init - */ -int exynos_power_init(void); - -#endif /* EXYNOS_BOARD_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clk.h deleted file mode 100644 index cdeef324c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clk.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_CLK_H_ -#define __ASM_ARM_ARCH_CLK_H_ - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 -#define BPLL 5 -#define RPLL 6 - -enum pll_src_bit { - EXYNOS_SRC_MPLL = 6, - EXYNOS_SRC_EPLL, - EXYNOS_SRC_VPLL, -}; - -unsigned long get_pll_clk(int pllreg); -unsigned long get_arm_clk(void); -unsigned long get_i2c_clk(void); -unsigned long get_pwm_clk(void); -unsigned long get_uart_clk(int dev_index); -unsigned long get_mmc_clk(int dev_index); -void set_mmc_clk(int dev_index, unsigned int div); -unsigned long get_lcd_clk(void); -void set_lcd_clk(void); -void set_mipi_clk(void); -int set_i2s_clk_source(unsigned int i2s_id); -int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, - unsigned int i2s_id); -int set_epll_clk(unsigned long rate); -int set_spi_clk(int periph_id, unsigned int rate); - -/** - * get the clk frequency of the required peripheral - * - * @param peripheral Peripheral id - * - * @return frequency of the peripheral clk - */ -unsigned long clock_get_periph_rate(int peripheral); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clock.h deleted file mode 100644 index 8259b92b8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clock.h +++ /dev/null @@ -1,1393 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_CLOCK_H_ -#define __ASM_ARM_ARCH_CLOCK_H_ - -#ifndef __ASSEMBLY__ -struct exynos4_clock { - unsigned char res1[0x4200]; - unsigned int src_leftbus; - unsigned char res2[0x1fc]; - unsigned int mux_stat_leftbus; - unsigned char res4[0xfc]; - unsigned int div_leftbus; - unsigned char res5[0xfc]; - unsigned int div_stat_leftbus; - unsigned char res6[0x1fc]; - unsigned int gate_ip_leftbus; - unsigned char res7[0x1fc]; - unsigned int clkout_leftbus; - unsigned int clkout_leftbus_div_stat; - unsigned char res8[0x37f8]; - unsigned int src_rightbus; - unsigned char res9[0x1fc]; - unsigned int mux_stat_rightbus; - unsigned char res10[0xfc]; - unsigned int div_rightbus; - unsigned char res11[0xfc]; - unsigned int div_stat_rightbus; - unsigned char res12[0x1fc]; - unsigned int gate_ip_rightbus; - unsigned char res13[0x1fc]; - unsigned int clkout_rightbus; - unsigned int clkout_rightbus_div_stat; - unsigned char res14[0x3608]; - unsigned int epll_lock; - unsigned char res15[0xc]; - unsigned int vpll_lock; - unsigned char res16[0xec]; - unsigned int epll_con0; - unsigned int epll_con1; - unsigned char res17[0x8]; - unsigned int vpll_con0; - unsigned int vpll_con1; - unsigned char res18[0xe8]; - unsigned int src_top0; - unsigned int src_top1; - unsigned char res19[0x8]; - unsigned int src_cam; - unsigned int src_tv; - unsigned int src_mfc; - unsigned int src_g3d; - unsigned int src_image; - unsigned int src_lcd0; - unsigned int src_lcd1; - unsigned int src_maudio; - unsigned int src_fsys; - unsigned char res20[0xc]; - unsigned int src_peril0; - unsigned int src_peril1; - unsigned char res21[0xb8]; - unsigned int src_mask_top; - unsigned char res22[0xc]; - unsigned int src_mask_cam; - unsigned int src_mask_tv; - unsigned char res23[0xc]; - unsigned int src_mask_lcd0; - unsigned int src_mask_lcd1; - unsigned int src_mask_maudio; - unsigned int src_mask_fsys; - unsigned char res24[0xc]; - unsigned int src_mask_peril0; - unsigned int src_mask_peril1; - unsigned char res25[0xb8]; - unsigned int mux_stat_top; - unsigned char res26[0x14]; - unsigned int mux_stat_mfc; - unsigned int mux_stat_g3d; - unsigned int mux_stat_image; - unsigned char res27[0xdc]; - unsigned int div_top; - unsigned char res28[0xc]; - unsigned int div_cam; - unsigned int div_tv; - unsigned int div_mfc; - unsigned int div_g3d; - unsigned int div_image; - unsigned int div_lcd0; - unsigned int div_lcd1; - unsigned int div_maudio; - unsigned int div_fsys0; - unsigned int div_fsys1; - unsigned int div_fsys2; - unsigned int div_fsys3; - unsigned int div_peril0; - unsigned int div_peril1; - unsigned int div_peril2; - unsigned int div_peril3; - unsigned int div_peril4; - unsigned int div_peril5; - unsigned char res29[0x18]; - unsigned int div2_ratio; - unsigned char res30[0x8c]; - unsigned int div_stat_top; - unsigned char res31[0xc]; - unsigned int div_stat_cam; - unsigned int div_stat_tv; - unsigned int div_stat_mfc; - unsigned int div_stat_g3d; - unsigned int div_stat_image; - unsigned int div_stat_lcd0; - unsigned int div_stat_lcd1; - unsigned int div_stat_maudio; - unsigned int div_stat_fsys0; - unsigned int div_stat_fsys1; - unsigned int div_stat_fsys2; - unsigned int div_stat_fsys3; - unsigned int div_stat_peril0; - unsigned int div_stat_peril1; - unsigned int div_stat_peril2; - unsigned int div_stat_peril3; - unsigned int div_stat_peril4; - unsigned int div_stat_peril5; - unsigned char res32[0x18]; - unsigned int div2_stat; - unsigned char res33[0x29c]; - unsigned int gate_ip_cam; - unsigned int gate_ip_tv; - unsigned int gate_ip_mfc; - unsigned int gate_ip_g3d; - unsigned int gate_ip_image; - unsigned int gate_ip_lcd0; - unsigned int gate_ip_lcd1; - unsigned char res34[0x4]; - unsigned int gate_ip_fsys; - unsigned char res35[0x8]; - unsigned int gate_ip_gps; - unsigned int gate_ip_peril; - unsigned char res36[0xc]; - unsigned int gate_ip_perir; - unsigned char res37[0xc]; - unsigned int gate_block; - unsigned char res38[0x8c]; - unsigned int clkout_cmu_top; - unsigned int clkout_cmu_top_div_stat; - unsigned char res39[0x37f8]; - unsigned int src_dmc; - unsigned char res40[0xfc]; - unsigned int src_mask_dmc; - unsigned char res41[0xfc]; - unsigned int mux_stat_dmc; - unsigned char res42[0xfc]; - unsigned int div_dmc0; - unsigned int div_dmc1; - unsigned char res43[0xf8]; - unsigned int div_stat_dmc0; - unsigned int div_stat_dmc1; - unsigned char res44[0x2f8]; - unsigned int gate_ip_dmc; - unsigned char res45[0xfc]; - unsigned int clkout_cmu_dmc; - unsigned int clkout_cmu_dmc_div_stat; - unsigned char res46[0x5f8]; - unsigned int dcgidx_map0; - unsigned int dcgidx_map1; - unsigned int dcgidx_map2; - unsigned char res47[0x14]; - unsigned int dcgperf_map0; - unsigned int dcgperf_map1; - unsigned char res48[0x18]; - unsigned int dvcidx_map; - unsigned char res49[0x1c]; - unsigned int freq_cpu; - unsigned int freq_dpm; - unsigned char res50[0x18]; - unsigned int dvsemclk_en; - unsigned int maxperf; - unsigned char res51[0x2f78]; - unsigned int apll_lock; - unsigned char res52[0x4]; - unsigned int mpll_lock; - unsigned char res53[0xf4]; - unsigned int apll_con0; - unsigned int apll_con1; - unsigned int mpll_con0; - unsigned int mpll_con1; - unsigned char res54[0xf0]; - unsigned int src_cpu; - unsigned char res55[0x1fc]; - unsigned int mux_stat_cpu; - unsigned char res56[0xfc]; - unsigned int div_cpu0; - unsigned int div_cpu1; - unsigned char res57[0xf8]; - unsigned int div_stat_cpu0; - unsigned int div_stat_cpu1; - unsigned char res58[0x3f8]; - unsigned int clkout_cmu_cpu; - unsigned int clkout_cmu_cpu_div_stat; - unsigned char res59[0x5f8]; - unsigned int armclk_stopctrl; - unsigned int atclk_stopctrl; - unsigned char res60[0x8]; - unsigned int parityfail_status; - unsigned int parityfail_clear; - unsigned char res61[0xe8]; - unsigned int apll_con0_l8; - unsigned int apll_con0_l7; - unsigned int apll_con0_l6; - unsigned int apll_con0_l5; - unsigned int apll_con0_l4; - unsigned int apll_con0_l3; - unsigned int apll_con0_l2; - unsigned int apll_con0_l1; - unsigned int iem_control; - unsigned char res62[0xdc]; - unsigned int apll_con1_l8; - unsigned int apll_con1_l7; - unsigned int apll_con1_l6; - unsigned int apll_con1_l5; - unsigned int apll_con1_l4; - unsigned int apll_con1_l3; - unsigned int apll_con1_l2; - unsigned int apll_con1_l1; - unsigned char res63[0xe0]; - unsigned int div_iem_l8; - unsigned int div_iem_l7; - unsigned int div_iem_l6; - unsigned int div_iem_l5; - unsigned int div_iem_l4; - unsigned int div_iem_l3; - unsigned int div_iem_l2; - unsigned int div_iem_l1; -}; - -struct exynos4x12_clock { - unsigned char res1[0x4200]; - unsigned int src_leftbus; - unsigned char res2[0x1fc]; - unsigned int mux_stat_leftbus; - unsigned char res3[0xfc]; - unsigned int div_leftbus; - unsigned char res4[0xfc]; - unsigned int div_stat_leftbus; - unsigned char res5[0x1fc]; - unsigned int gate_ip_leftbus; - unsigned char res6[0x12c]; - unsigned int gate_ip_image; - unsigned char res7[0xcc]; - unsigned int clkout_leftbus; - unsigned int clkout_leftbus_div_stat; - unsigned char res8[0x37f8]; - unsigned int src_rightbus; - unsigned char res9[0x1fc]; - unsigned int mux_stat_rightbus; - unsigned char res10[0xfc]; - unsigned int div_rightbus; - unsigned char res11[0xfc]; - unsigned int div_stat_rightbus; - unsigned char res12[0x1fc]; - unsigned int gate_ip_rightbus; - unsigned char res13[0x15c]; - unsigned int gate_ip_perir; - unsigned char res14[0x9c]; - unsigned int clkout_rightbus; - unsigned int clkout_rightbus_div_stat; - unsigned char res15[0x3608]; - unsigned int epll_lock; - unsigned char res16[0xc]; - unsigned int vpll_lock; - unsigned char res17[0xec]; - unsigned int epll_con0; - unsigned int epll_con1; - unsigned int epll_con2; - unsigned char res18[0x4]; - unsigned int vpll_con0; - unsigned int vpll_con1; - unsigned int vpll_con2; - unsigned char res19[0xe4]; - unsigned int src_top0; - unsigned int src_top1; - unsigned char res20[0x8]; - unsigned int src_cam; - unsigned int src_tv; - unsigned int src_mfc; - unsigned int src_g3d; - unsigned char res21[0x4]; - unsigned int src_lcd; - unsigned int src_isp; - unsigned int src_maudio; - unsigned int src_fsys; - unsigned char res22[0xc]; - unsigned int src_peril0; - unsigned int src_peril1; - unsigned int src_cam1; - unsigned char res23[0xb4]; - unsigned int src_mask_top; - unsigned char res24[0xc]; - unsigned int src_mask_cam; - unsigned int src_mask_tv; - unsigned char res25[0xc]; - unsigned int src_mask_lcd; - unsigned int src_mask_isp; - unsigned int src_mask_maudio; - unsigned int src_mask_fsys; - unsigned char res26[0xc]; - unsigned int src_mask_peril0; - unsigned int src_mask_peril1; - unsigned char res27[0xb8]; - unsigned int mux_stat_top0; - unsigned int mux_stat_top1; - unsigned char res28[0x10]; - unsigned int mux_stat_mfc; - unsigned int mux_stat_g3d; - unsigned char res29[0x28]; - unsigned int mux_stat_cam1; - unsigned char res30[0xb4]; - unsigned int div_top; - unsigned char res31[0xc]; - unsigned int div_cam; - unsigned int div_tv; - unsigned int div_mfc; - unsigned int div_g3d; - unsigned char res32[0x4]; - unsigned int div_lcd; - unsigned int div_isp; - unsigned int div_maudio; - unsigned int div_fsys0; - unsigned int div_fsys1; - unsigned int div_fsys2; - unsigned int div_fsys3; - unsigned int div_peril0; - unsigned int div_peril1; - unsigned int div_peril2; - unsigned int div_peril3; - unsigned int div_peril4; - unsigned int div_peril5; - unsigned int div_cam1; - unsigned char res33[0x14]; - unsigned int div2_ratio; - unsigned char res34[0x8c]; - unsigned int div_stat_top; - unsigned char res35[0xc]; - unsigned int div_stat_cam; - unsigned int div_stat_tv; - unsigned int div_stat_mfc; - unsigned int div_stat_g3d; - unsigned char res36[0x4]; - unsigned int div_stat_lcd; - unsigned int div_stat_isp; - unsigned int div_stat_maudio; - unsigned int div_stat_fsys0; - unsigned int div_stat_fsys1; - unsigned int div_stat_fsys2; - unsigned int div_stat_fsys3; - unsigned int div_stat_peril0; - unsigned int div_stat_peril1; - unsigned int div_stat_peril2; - unsigned int div_stat_peril3; - unsigned int div_stat_peril4; - unsigned int div_stat_peril5; - unsigned int div_stat_cam1; - unsigned char res37[0x14]; - unsigned int div2_stat; - unsigned char res38[0x29c]; - unsigned int gate_ip_cam; - unsigned int gate_ip_tv; - unsigned int gate_ip_mfc; - unsigned int gate_ip_g3d; - unsigned char res39[0x4]; - unsigned int gate_ip_lcd; - unsigned int gate_ip_isp; - unsigned char res40[0x4]; - unsigned int gate_ip_fsys; - unsigned char res41[0x8]; - unsigned int gate_ip_gps; - unsigned int gate_ip_peril; - unsigned char res42[0xc]; - unsigned char res43[0x4]; - unsigned char res44[0xc]; - unsigned int gate_block; - unsigned char res45[0x8c]; - unsigned int clkout_cmu_top; - unsigned int clkout_cmu_top_div_stat; - unsigned char res46[0x3600]; - unsigned int mpll_lock; - unsigned char res47[0xfc]; - unsigned int mpll_con0; - unsigned int mpll_con1; - unsigned char res48[0xf0]; - unsigned int src_dmc; - unsigned char res49[0xfc]; - unsigned int src_mask_dmc; - unsigned char res50[0xfc]; - unsigned int mux_stat_dmc; - unsigned char res51[0xfc]; - unsigned int div_dmc0; - unsigned int div_dmc1; - unsigned char res52[0xf8]; - unsigned int div_stat_dmc0; - unsigned int div_stat_dmc1; - unsigned char res53[0xf8]; - unsigned int gate_bus_dmc0; - unsigned int gate_bus_dmc1; - unsigned char res54[0x1f8]; - unsigned int gate_ip_dmc0; - unsigned int gate_ip_dmc1; - unsigned char res55[0xf8]; - unsigned int clkout_cmu_dmc; - unsigned int clkout_cmu_dmc_div_stat; - unsigned char res56[0x5f8]; - unsigned int dcgidx_map0; - unsigned int dcgidx_map1; - unsigned int dcgidx_map2; - unsigned char res57[0x14]; - unsigned int dcgperf_map0; - unsigned int dcgperf_map1; - unsigned char res58[0x18]; - unsigned int dvcidx_map; - unsigned char res59[0x1c]; - unsigned int freq_cpu; - unsigned int freq_dpm; - unsigned char res60[0x18]; - unsigned int dvsemclk_en; - unsigned int maxperf; - unsigned char res61[0x8]; - unsigned int dmc_freq_ctrl; - unsigned int dmc_pause_ctrl; - unsigned int dddrphy_lock_ctrl; - unsigned int c2c_state; - unsigned char res62[0x2f60]; - unsigned int apll_lock; - unsigned char res63[0x8]; - unsigned char res64[0xf4]; - unsigned int apll_con0; - unsigned int apll_con1; - unsigned char res65[0xf8]; - unsigned int src_cpu; - unsigned char res66[0x1fc]; - unsigned int mux_stat_cpu; - unsigned char res67[0xfc]; - unsigned int div_cpu0; - unsigned int div_cpu1; - unsigned char res68[0xf8]; - unsigned int div_stat_cpu0; - unsigned int div_stat_cpu1; - unsigned char res69[0x2f8]; - unsigned int clk_gate_ip_cpu; - unsigned char res70[0xfc]; - unsigned int clkout_cmu_cpu; - unsigned int clkout_cmu_cpu_div_stat; - unsigned char res71[0x5f8]; - unsigned int armclk_stopctrl; - unsigned int atclk_stopctrl; - unsigned char res72[0x10]; - unsigned char res73[0x8]; - unsigned int pwr_ctrl; - unsigned int pwr_ctrl2; - unsigned char res74[0xd8]; - unsigned int apll_con0_l8; - unsigned int apll_con0_l7; - unsigned int apll_con0_l6; - unsigned int apll_con0_l5; - unsigned int apll_con0_l4; - unsigned int apll_con0_l3; - unsigned int apll_con0_l2; - unsigned int apll_con0_l1; - unsigned int iem_control; - unsigned char res75[0xdc]; - unsigned int apll_con1_l8; - unsigned int apll_con1_l7; - unsigned int apll_con1_l6; - unsigned int apll_con1_l5; - unsigned int apll_con1_l4; - unsigned int apll_con1_l3; - unsigned int apll_con1_l2; - unsigned int apll_con1_l1; - unsigned char res76[0xe0]; - unsigned int div_iem_l8; - unsigned int div_iem_l7; - unsigned int div_iem_l6; - unsigned int div_iem_l5; - unsigned int div_iem_l4; - unsigned int div_iem_l3; - unsigned int div_iem_l2; - unsigned int div_iem_l1; - unsigned char res77[0xe0]; - unsigned int l2_status; - unsigned char res78[0xc]; - unsigned int cpu_status; - unsigned char res79[0xc]; - unsigned int ptm_status; - unsigned char res80[0x2edc]; - unsigned int div_isp0; - unsigned int div_isp1; - unsigned char res81[0xf8]; - unsigned int div_stat_isp0; - unsigned int div_stat_isp1; - unsigned char res82[0x3f8]; - unsigned int gate_ip_isp0; - unsigned int gate_ip_isp1; - unsigned char res83[0x1f8]; - unsigned int clkout_cmu_isp; - unsigned int clkout_cmu_ispd_div_stat; - unsigned char res84[0xf8]; - unsigned int cmu_isp_spar0; - unsigned int cmu_isp_spar1; - unsigned int cmu_isp_spar2; - unsigned int cmu_isp_spar3; -}; - -struct exynos5_clock { - unsigned int apll_lock; - unsigned char res1[0xfc]; - unsigned int apll_con0; - unsigned int apll_con1; - unsigned char res2[0xf8]; - unsigned int src_cpu; - unsigned char res3[0x1fc]; - unsigned int mux_stat_cpu; - unsigned char res4[0xfc]; - unsigned int div_cpu0; - unsigned int div_cpu1; - unsigned char res5[0xf8]; - unsigned int div_stat_cpu0; - unsigned int div_stat_cpu1; - unsigned char res6[0x1f8]; - unsigned int gate_sclk_cpu; - unsigned char res7[0x1fc]; - unsigned int clkout_cmu_cpu; - unsigned int clkout_cmu_cpu_div_stat; - unsigned char res8[0x5f8]; - unsigned int armclk_stopctrl; - unsigned char res9[0x0c]; - unsigned int parityfail_status; - unsigned int parityfail_clear; - unsigned char res10[0x8]; - unsigned int pwr_ctrl; - unsigned int pwr_ctr2; - unsigned char res11[0xd8]; - unsigned int apll_con0_l8; - unsigned int apll_con0_l7; - unsigned int apll_con0_l6; - unsigned int apll_con0_l5; - unsigned int apll_con0_l4; - unsigned int apll_con0_l3; - unsigned int apll_con0_l2; - unsigned int apll_con0_l1; - unsigned int iem_control; - unsigned char res12[0xdc]; - unsigned int apll_con1_l8; - unsigned int apll_con1_l7; - unsigned int apll_con1_l6; - unsigned int apll_con1_l5; - unsigned int apll_con1_l4; - unsigned int apll_con1_l3; - unsigned int apll_con1_l2; - unsigned int apll_con1_l1; - unsigned char res13[0xe0]; - unsigned int div_iem_l8; - unsigned int div_iem_l7; - unsigned int div_iem_l6; - unsigned int div_iem_l5; - unsigned int div_iem_l4; - unsigned int div_iem_l3; - unsigned int div_iem_l2; - unsigned int div_iem_l1; - unsigned char res14[0x2ce0]; - unsigned int mpll_lock; - unsigned char res15[0xfc]; - unsigned int mpll_con0; - unsigned int mpll_con1; - unsigned char res16[0xf8]; - unsigned int src_core0; - unsigned int src_core1; - unsigned char res17[0xf8]; - unsigned int src_mask_core; - unsigned char res18[0x100]; - unsigned int mux_stat_core1; - unsigned char res19[0xf8]; - unsigned int div_core0; - unsigned int div_core1; - unsigned int div_sysrgt; - unsigned char res20[0xf4]; - unsigned int div_stat_core0; - unsigned int div_stat_core1; - unsigned int div_stat_sysrgt; - unsigned char res21[0x2f4]; - unsigned int gate_ip_core; - unsigned int gate_ip_sysrgt; - unsigned char res22[0x8]; - unsigned int c2c_monitor; - unsigned char res23[0xec]; - unsigned int clkout_cmu_core; - unsigned int clkout_cmu_core_div_stat; - unsigned char res24[0x5f8]; - unsigned int dcgidx_map0; - unsigned int dcgidx_map1; - unsigned int dcgidx_map2; - unsigned char res25[0x14]; - unsigned int dcgperf_map0; - unsigned int dcgperf_map1; - unsigned char res26[0x18]; - unsigned int dvcidx_map; - unsigned char res27[0x1c]; - unsigned int freq_cpu; - unsigned int freq_dpm; - unsigned char res28[0x18]; - unsigned int dvsemclk_en; - unsigned int maxperf; - unsigned char res29[0xf78]; - unsigned int c2c_config; - unsigned char res30[0x24fc]; - unsigned int div_acp; - unsigned char res31[0xfc]; - unsigned int div_stat_acp; - unsigned char res32[0x1fc]; - unsigned int gate_ip_acp; - unsigned char res33[0xfc]; - unsigned int div_syslft; - unsigned char res34[0xc]; - unsigned int div_stat_syslft; - unsigned char res35[0x1c]; - unsigned int gate_ip_syslft; - unsigned char res36[0xcc]; - unsigned int clkout_cmu_acp; - unsigned int clkout_cmu_acp_div_stat; - unsigned char res37[0x8]; - unsigned int ufmc_config; - unsigned char res38[0x38ec]; - unsigned int div_isp0; - unsigned int div_isp1; - unsigned int div_isp2; - unsigned char res39[0xf4]; - unsigned int div_stat_isp0; - unsigned int div_stat_isp1; - unsigned int div_stat_isp2; - unsigned char res40[0x3f4]; - unsigned int gate_ip_isp0; - unsigned int gate_ip_isp1; - unsigned char res41[0xf8]; - unsigned int gate_sclk_isp; - unsigned char res42[0xc]; - unsigned int mcuisp_pwr_ctrl; - unsigned char res43[0xec]; - unsigned int clkout_cmu_isp; - unsigned int clkout_cmu_isp_div_stat; - unsigned char res44[0x3618]; - unsigned int cpll_lock; - unsigned char res45[0xc]; - unsigned int epll_lock; - unsigned char res46[0xc]; - unsigned int vpll_lock; - unsigned char res47[0xc]; - unsigned int gpll_lock; - unsigned char res48[0xcc]; - unsigned int cpll_con0; - unsigned int cpll_con1; - unsigned char res49[0x8]; - unsigned int epll_con0; - unsigned int epll_con1; - unsigned int epll_con2; - unsigned char res50[0x4]; - unsigned int vpll_con0; - unsigned int vpll_con1; - unsigned int vpll_con2; - unsigned char res51[0x4]; - unsigned int gpll_con0; - unsigned int gpll_con1; - unsigned char res52[0xb8]; - unsigned int src_top0; - unsigned int src_top1; - unsigned int src_top2; - unsigned int src_top3; - unsigned int src_gscl; - unsigned char res53[0x8]; - unsigned int src_disp1_0; - unsigned char res54[0x10]; - unsigned int src_mau; - unsigned int src_fsys; - unsigned int src_gen; - unsigned char res55[0x4]; - unsigned int src_peric0; - unsigned int src_peric1; - unsigned char res56[0x18]; - unsigned int sclk_src_isp; - unsigned char res57[0x9c]; - unsigned int src_mask_top; - unsigned char res58[0xc]; - unsigned int src_mask_gscl; - unsigned char res59[0x8]; - unsigned int src_mask_disp1_0; - unsigned char res60[0x4]; - unsigned int src_mask_mau; - unsigned char res61[0x8]; - unsigned int src_mask_fsys; - unsigned int src_mask_gen; - unsigned char res62[0x8]; - unsigned int src_mask_peric0; - unsigned int src_mask_peric1; - unsigned char res63[0x18]; - unsigned int src_mask_isp; - unsigned char res67[0x9c]; - unsigned int mux_stat_top0; - unsigned int mux_stat_top1; - unsigned int mux_stat_top2; - unsigned int mux_stat_top3; - unsigned char res68[0xf0]; - unsigned int div_top0; - unsigned int div_top1; - unsigned char res69[0x8]; - unsigned int div_gscl; - unsigned char res70[0x8]; - unsigned int div_disp1_0; - unsigned char res71[0xc]; - unsigned int div_gen; - unsigned char res72[0x4]; - unsigned int div_mau; - unsigned int div_fsys0; - unsigned int div_fsys1; - unsigned int div_fsys2; - unsigned char res73[0x4]; - unsigned int div_peric0; - unsigned int div_peric1; - unsigned int div_peric2; - unsigned int div_peric3; - unsigned int div_peric4; - unsigned int div_peric5; - unsigned char res74[0x10]; - unsigned int sclk_div_isp; - unsigned char res75[0xc]; - unsigned int div2_ratio0; - unsigned int div2_ratio1; - unsigned char res76[0x8]; - unsigned int div4_ratio; - unsigned char res77[0x6c]; - unsigned int div_stat_top0; - unsigned int div_stat_top1; - unsigned char res78[0x8]; - unsigned int div_stat_gscl; - unsigned char res79[0x8]; - unsigned int div_stat_disp1_0; - unsigned char res80[0xc]; - unsigned int div_stat_gen; - unsigned char res81[0x4]; - unsigned int div_stat_mau; - unsigned int div_stat_fsys0; - unsigned int div_stat_fsys1; - unsigned int div_stat_fsys2; - unsigned char res82[0x4]; - unsigned int div_stat_peric0; - unsigned int div_stat_peric1; - unsigned int div_stat_peric2; - unsigned int div_stat_peric3; - unsigned int div_stat_peric4; - unsigned int div_stat_peric5; - unsigned char res83[0x10]; - unsigned int sclk_div_stat_isp; - unsigned char res84[0xc]; - unsigned int div2_stat0; - unsigned int div2_stat1; - unsigned char res85[0x8]; - unsigned int div4_stat; - unsigned char res86[0x184]; - unsigned int gate_top_sclk_disp1; - unsigned int gate_top_sclk_gen; - unsigned char res87[0xc]; - unsigned int gate_top_sclk_mau; - unsigned int gate_top_sclk_fsys; - unsigned char res88[0xc]; - unsigned int gate_top_sclk_peric; - unsigned char res89[0x1c]; - unsigned int gate_top_sclk_isp; - unsigned char res90[0xac]; - unsigned int gate_ip_gscl; - unsigned char res91[0x4]; - unsigned int gate_ip_disp1; - unsigned int gate_ip_mfc; - unsigned int gate_ip_g3d; - unsigned int gate_ip_gen; - unsigned char res92[0xc]; - unsigned int gate_ip_fsys; - unsigned char res93[0x8]; - unsigned int gate_ip_peric; - unsigned char res94[0xc]; - unsigned int gate_ip_peris; - unsigned char res95[0x1c]; - unsigned int gate_block; - unsigned char res96[0x1c]; - unsigned int mcuiop_pwr_ctrl; - unsigned char res97[0x5c]; - unsigned int clkout_cmu_top; - unsigned int clkout_cmu_top_div_stat; - unsigned char res98[0x37f8]; - unsigned int src_lex; - unsigned char res99[0x1fc]; - unsigned int mux_stat_lex; - unsigned char res100[0xfc]; - unsigned int div_lex; - unsigned char res101[0xfc]; - unsigned int div_stat_lex; - unsigned char res102[0x1fc]; - unsigned int gate_ip_lex; - unsigned char res103[0x1fc]; - unsigned int clkout_cmu_lex; - unsigned int clkout_cmu_lex_div_stat; - unsigned char res104[0x3af8]; - unsigned int div_r0x; - unsigned char res105[0xfc]; - unsigned int div_stat_r0x; - unsigned char res106[0x1fc]; - unsigned int gate_ip_r0x; - unsigned char res107[0x1fc]; - unsigned int clkout_cmu_r0x; - unsigned int clkout_cmu_r0x_div_stat; - unsigned char res108[0x3af8]; - unsigned int div_r1x; - unsigned char res109[0xfc]; - unsigned int div_stat_r1x; - unsigned char res110[0x1fc]; - unsigned int gate_ip_r1x; - unsigned char res111[0x1fc]; - unsigned int clkout_cmu_r1x; - unsigned int clkout_cmu_r1x_div_stat; - unsigned char res112[0x3608]; - unsigned int bpll_lock; - unsigned char res113[0xfc]; - unsigned int bpll_con0; - unsigned int bpll_con1; - unsigned char res114[0xe8]; - unsigned int src_cdrex; - unsigned char res115[0x1fc]; - unsigned int mux_stat_cdrex; - unsigned char res116[0xfc]; - unsigned int div_cdrex; - unsigned char res117[0xfc]; - unsigned int div_stat_cdrex; - unsigned char res118[0x2fc]; - unsigned int gate_ip_cdrex; - unsigned char res119[0x10]; - unsigned int dmc_freq_ctrl; - unsigned char res120[0x4]; - unsigned int drex2_pause; - unsigned char res121[0xe0]; - unsigned int clkout_cmu_cdrex; - unsigned int clkout_cmu_cdrex_div_stat; - unsigned char res122[0x8]; - unsigned int lpddr3phy_ctrl; - unsigned int lpddr3phy_con0; - unsigned int lpddr3phy_con1; - unsigned int lpddr3phy_con2; - unsigned int lpddr3phy_con3; - unsigned int pll_div2_sel; - unsigned char res123[0xf5d8]; -}; - -struct exynos5420_clock { - unsigned int apll_lock; /* 0x10010000 */ - unsigned char res1[0xfc]; - unsigned int apll_con0; - unsigned int apll_con1; - unsigned char res2[0xf8]; - unsigned int src_cpu; - unsigned char res3[0x1fc]; - unsigned int mux_stat_cpu; - unsigned char res4[0xfc]; - unsigned int div_cpu0; /* 0x10010500 */ - unsigned int div_cpu1; - unsigned char res5[0xf8]; - unsigned int div_stat_cpu0; - unsigned int div_stat_cpu1; - unsigned char res6[0xf8]; - unsigned int gate_bus_cpu; - unsigned char res7[0xfc]; - unsigned int gate_sclk_cpu; - unsigned char res8[0x1fc]; - unsigned int clkout_cmu_cpu; /* 0x10010a00 */ - unsigned int clkout_cmu_cpu_div_stat; - unsigned char res9[0x5f8]; - unsigned int armclk_stopctrl; - unsigned char res10[0x4]; - unsigned int arm_ema_ctrl; - unsigned int arm_ema_status; - unsigned char res11[0x10]; - unsigned int pwr_ctrl; - unsigned int pwr_ctrl2; - unsigned char res12[0xd8]; - unsigned int apll_con0_l8; /* 0x1001100 */ - unsigned int apll_con0_l7; - unsigned int apll_con0_l6; - unsigned int apll_con0_l5; - unsigned int apll_con0_l4; - unsigned int apll_con0_l3; - unsigned int apll_con0_l2; - unsigned int apll_con0_l1; - unsigned int iem_control; - unsigned char res13[0xdc]; - unsigned int apll_con1_l8; /* 0x10011200 */ - unsigned int apll_con1_l7; - unsigned int apll_con1_l6; - unsigned int apll_con1_l5; - unsigned int apll_con1_l4; - unsigned int apll_con1_l3; - unsigned int apll_con1_l2; - unsigned int apll_con1_l1; - unsigned char res14[0xe0]; - unsigned int clkdiv_iem_l8; - unsigned int clkdiv_iem_l7; /* 0x10011304 */ - unsigned int clkdiv_iem_l6; - unsigned int clkdiv_iem_l5; - unsigned int clkdiv_iem_l4; - unsigned int clkdiv_iem_l3; - unsigned int clkdiv_iem_l2; - unsigned int clkdiv_iem_l1; - unsigned char res15[0xe0]; - unsigned int l2_status; - unsigned char res16[0x0c]; - unsigned int cpu_status; /* 0x10011410 */ - unsigned char res17[0x0c]; - unsigned int ptm_status; - unsigned char res18[0xbdc]; - unsigned int cmu_cpu_spare0; - unsigned int cmu_cpu_spare1; - unsigned int cmu_cpu_spare2; - unsigned int cmu_cpu_spare3; - unsigned int cmu_cpu_spare4; - unsigned char res19[0x1fdc]; - unsigned int cmu_cpu_version; - unsigned char res20[0x20c]; - unsigned int src_cperi0; /* 0x10014200 */ - unsigned int src_cperi1; - unsigned char res21[0xf8]; - unsigned int src_mask_cperi; - unsigned char res22[0x100]; - unsigned int mux_stat_cperi1; - unsigned char res23[0xfc]; - unsigned int div_cperi1; - unsigned char res24[0xfc]; - unsigned int div_stat_cperi1; - unsigned char res25[0xf8]; - unsigned int gate_bus_cperi0; /* 0x10014700 */ - unsigned int gate_bus_cperi1; - unsigned char res26[0xf8]; - unsigned int gate_sclk_cperi; - unsigned char res27[0xfc]; - unsigned int gate_ip_cperi; - unsigned char res28[0xfc]; - unsigned int clkout_cmu_cperi; - unsigned int clkout_cmu_cperi_div_stat; - unsigned char res29[0x5f8]; - unsigned int dcgidx_map0; /* 0x10015000 */ - unsigned int dcgidx_map1; - unsigned int dcgidx_map2; - unsigned char res30[0x14]; - unsigned int dcgperf_map0; - unsigned int dcgperf_map1; - unsigned char res31[0x18]; - unsigned int dvcidx_map; - unsigned char res32[0x1c]; - unsigned int freq_cpu; - unsigned int freq_dpm; - unsigned char res33[0x18]; - unsigned int dvsemclk_en; /* 0x10015080 */ - unsigned int maxperf; - unsigned char res34[0x2e78]; - unsigned int cmu_cperi_spare0; - unsigned int cmu_cperi_spare1; - unsigned int cmu_cperi_spare2; - unsigned int cmu_cperi_spare3; - unsigned int cmu_cperi_spare4; - unsigned int cmu_cperi_spare5; - unsigned int cmu_cperi_spare6; - unsigned int cmu_cperi_spare7; - unsigned int cmu_cperi_spare8; - unsigned char res35[0xcc]; - unsigned int cmu_cperi_version; /* 0x10017ff0 */ - unsigned char res36[0x50c]; - unsigned int div_g2d; - unsigned char res37[0xfc]; - unsigned int div_stat_g2d; - unsigned char res38[0xfc]; - unsigned int gate_bus_g2d; - unsigned char res39[0xfc]; - unsigned int gate_ip_g2d; - unsigned char res40[0x1fc]; - unsigned int clkout_cmu_g2d; - unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */ - unsigned char res41[0xf8]; - unsigned int cmu_g2d_spare0; - unsigned int cmu_g2d_spare1; - unsigned int cmu_g2d_spare2; - unsigned int cmu_g2d_spare3; - unsigned int cmu_g2d_spare4; - unsigned char res42[0x34dc]; - unsigned int cmu_g2d_version; - unsigned char res43[0x30c]; - unsigned int div_cmu_isp0; - unsigned int div_cmu_isp1; - unsigned int div_isp2; /* 0x1001c308 */ - unsigned char res44[0xf4]; - unsigned int div_stat_cmu_isp0; - unsigned int div_stat_cmu_isp1; - unsigned int div_stat_isp2; - unsigned char res45[0x2f4]; - unsigned int gate_bus_isp0; - unsigned int gate_bus_isp1; - unsigned int gate_bus_isp2; - unsigned int gate_bus_isp3; - unsigned char res46[0xf0]; - unsigned int gate_ip_isp0; - unsigned int gate_ip_isp1; - unsigned char res47[0xf8]; - unsigned int gate_sclk_isp; - unsigned char res48[0x0c]; - unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */ - unsigned char res49[0x0ec]; - unsigned int clkout_cmu_isp; - unsigned int clkout_cmu_isp_div_stat; - unsigned char res50[0xf8]; - unsigned int cmu_isp_spare0; - unsigned int cmu_isp_spare1; - unsigned int cmu_isp_spare2; - unsigned int cmu_isp_spare3; - unsigned char res51[0x34e0]; - unsigned int cmu_isp_version; - unsigned char res52[0x2c]; - unsigned int cpll_lock; /* 10020020 */ - unsigned char res53[0xc]; - unsigned int dpll_lock; - unsigned char res54[0xc]; - unsigned int epll_lock; - unsigned char res55[0xc]; - unsigned int rpll_lock; - unsigned char res56[0xc]; - unsigned int ipll_lock; - unsigned char res57[0xc]; - unsigned int spll_lock; - unsigned char res58[0xc]; - unsigned int vpll_lock; - unsigned char res59[0xc]; - unsigned int mpll_lock; - unsigned char res60[0x8c]; - unsigned int cpll_con0; /* 10020120 */ - unsigned int cpll_con1; - unsigned int dpll_con0; - unsigned int dpll_con1; - unsigned int epll_con0; - unsigned int epll_con1; - unsigned int epll_con2; - unsigned char res601[0x4]; - unsigned int rpll_con0; - unsigned int rpll_con1; - unsigned int rpll_con2; - unsigned char res602[0x4]; - unsigned int ipll_con0; - unsigned int ipll_con1; - unsigned char res61[0x8]; - unsigned int spll_con0; - unsigned int spll_con1; - unsigned char res62[0x8]; - unsigned int vpll_con0; - unsigned int vpll_con1; - unsigned char res63[0x8]; - unsigned int mpll_con0; - unsigned int mpll_con1; - unsigned char res64[0x78]; - unsigned int src_top0; /* 0x10020200 */ - unsigned int src_top1; - unsigned int src_top2; - unsigned int src_top3; - unsigned int src_top4; - unsigned int src_top5; - unsigned int src_top6; - unsigned int src_top7; - unsigned char res65[0xc]; - unsigned int src_disp10; /* 0x1002022c */ - unsigned char res66[0x10]; - unsigned int src_mau; - unsigned int src_fsys; - unsigned char res67[0x8]; - unsigned int src_peric0; - unsigned int src_peric1; - unsigned char res68[0x18]; - unsigned int src_isp; - unsigned char res69[0x0c]; - unsigned int src_top10; - unsigned int src_top11; - unsigned int src_top12; - unsigned char res70[0x74]; - unsigned int src_mask_top0; - unsigned int src_mask_top1; - unsigned int src_mask_top2; - unsigned char res71[0x10]; - unsigned int src_mask_top7; - unsigned char res72[0xc]; - unsigned int src_mask_disp10; /* 0x1002032c */ - unsigned char res73[0x4]; - unsigned int src_mask_mau; - unsigned char res74[0x8]; - unsigned int src_mask_fsys; - unsigned char res75[0xc]; - unsigned int src_mask_peric0; - unsigned int src_mask_peric1; - unsigned char res76[0x18]; - unsigned int src_mask_isp; - unsigned char res77[0x8c]; - unsigned int mux_stat_top0; /* 0x10020400 */ - unsigned int mux_stat_top1; - unsigned int mux_stat_top2; - unsigned int mux_stat_top3; - unsigned int mux_stat_top4; - unsigned int mux_stat_top5; - unsigned int mux_stat_top6; - unsigned int mux_stat_top7; - unsigned char res78[0x60]; - unsigned int mux_stat_top10; - unsigned int mux_stat_top11; - unsigned int mux_stat_top12; - unsigned char res79[0x74]; - unsigned int div_top0; /* 0x10020500 */ - unsigned int div_top1; - unsigned int div_top2; - unsigned char res80[0x20]; - unsigned int div_disp10; - unsigned char res81[0x14]; - unsigned int div_mau; - unsigned int div_fsys0; - unsigned int div_fsys1; - unsigned int div_fsys2; - unsigned char res82[0x4]; - unsigned int div_peric0; - unsigned int div_peric1; - unsigned int div_peric2; - unsigned int div_peric3; - unsigned int div_peric4; /* 0x10020568 */ - unsigned char res83[0x14]; - unsigned int div_isp0; - unsigned int div_isp1; - unsigned char res84[0x8]; - unsigned int clkdiv2_ratio; - unsigned char res850[0xc]; - unsigned int clkdiv4_ratio; - unsigned char res85[0x5c]; - unsigned int div_stat_top0; - unsigned int div_stat_top1; - unsigned int div_stat_top2; - unsigned char res86[0x20]; - unsigned int div_stat_disp10; - unsigned char res87[0x14]; - unsigned int div_stat_mau; /* 0x10020644 */ - unsigned int div_stat_fsys0; - unsigned int div_stat_fsys1; - unsigned int div_stat_fsys2; - unsigned char res88[0x4]; - unsigned int div_stat_peric0; - unsigned int div_stat_peric1; - unsigned int div_stat_peric2; - unsigned int div_stat_peric3; - unsigned int div_stat_peric4; - unsigned char res89[0x14]; - unsigned int div_stat_isp0; - unsigned int div_stat_isp1; - unsigned char res90[0x8]; - unsigned int clkdiv2_stat0; - unsigned char res91[0xc]; - unsigned int clkdiv4_stat; - unsigned char res92[0x5c]; - unsigned int gate_bus_top; /* 0x10020700 */ - unsigned char res93[0xc]; - unsigned int gate_bus_gscl0; - unsigned char res94[0xc]; - unsigned int gate_bus_gscl1; - unsigned char res95[0x4]; - unsigned int gate_bus_disp1; - unsigned char res96[0x4]; - unsigned int gate_bus_wcore; - unsigned int gate_bus_mfc; - unsigned int gate_bus_g3d; - unsigned int gate_bus_gen; - unsigned int gate_bus_fsys0; - unsigned int gate_bus_fsys1; - unsigned int gate_bus_fsys2; - unsigned int gate_bus_mscl; - unsigned int gate_bus_peric; - unsigned int gate_bus_peric1; - unsigned char res97[0x8]; - unsigned int gate_bus_peris0; - unsigned int gate_bus_peris1; /* 0x10020764 */ - unsigned char res98[0x8]; - unsigned int gate_bus_noc; - unsigned char res99[0xac]; - unsigned int gate_top_sclk_gscl; - unsigned char res1000[0x4]; - unsigned int gate_top_sclk_disp1; - unsigned char res100[0x10]; - unsigned int gate_top_sclk_mau; - unsigned int gate_top_sclk_fsys; - unsigned char res101[0xc]; - unsigned int gate_top_sclk_peric; - unsigned char res102[0xc]; - unsigned int gate_top_sclk_cperi; - unsigned char res103[0xc]; - unsigned int gate_top_sclk_isp; - unsigned char res104[0x9c]; - unsigned int gate_ip_gscl0; - unsigned char res105[0xc]; - unsigned int gate_ip_gscl1; - unsigned char res106[0x4]; - unsigned int gate_ip_disp1; - unsigned int gate_ip_mfc; - unsigned int gate_ip_g3d; - unsigned int gate_ip_gen; /* 0x10020934 */ - unsigned char res107[0xc]; - unsigned int gate_ip_fsys; - unsigned char res108[0x8]; - unsigned int gate_ip_peric; - unsigned char res109[0xc]; - unsigned int gate_ip_peris; - unsigned char res110[0xc]; - unsigned int gate_ip_mscl; - unsigned char res111[0xc]; - unsigned int gate_ip_block; - unsigned char res112[0xc]; - unsigned int bypass; - unsigned char res113[0x6c]; - unsigned int clkout_cmu_top; - unsigned int clkout_cmu_top_div_stat; - unsigned char res114[0xf8]; - unsigned int clkout_top_spare0; - unsigned int clkout_top_spare1; - unsigned int clkout_top_spare2; - unsigned int clkout_top_spare3; - unsigned char res115[0x34e0]; - unsigned int clkout_top_version; - unsigned char res116[0xc01c]; - unsigned int bpll_lock; /* 0x10030010 */ - unsigned char res117[0xfc]; - unsigned int bpll_con0; - unsigned int bpll_con1; - unsigned char res118[0xe8]; - unsigned int src_cdrex; - unsigned char res119[0x1fc]; - unsigned int mux_stat_cdrex; - unsigned char res120[0xfc]; - unsigned int div_cdrex0; - unsigned int div_cdrex1; - unsigned char res121[0xf8]; - unsigned int div_stat_cdrex; - unsigned char res1211[0xfc]; - unsigned int gate_bus_cdrex; - unsigned int gate_bus_cdrex1; - unsigned char res122[0x1f8]; - unsigned int gate_ip_cdrex; - unsigned char res123[0x10]; - unsigned int dmc_freq_ctrl; /* 0x10030914 */ - unsigned char res124[0x4]; - unsigned int pause; - unsigned int ddrphy_lock_ctrl; - unsigned char res125[0xdc]; - unsigned int clkout_cmu_cdrex; - unsigned int clkout_cmu_cdrex_div_stat; - unsigned char res126[0x8]; - unsigned int lpddr3phy_ctrl; - unsigned int lpddr3phy_con0; - unsigned int lpddr3phy_con1; - unsigned int lpddr3phy_con2; - unsigned int lpddr3phy_con3; - unsigned int lpddr3phy_con4; - unsigned int lpddr3phy_con5; /* 0x10030a28 */ - unsigned int pll_div2_sel; - unsigned char res127[0xd0]; - unsigned int cmu_cdrex_spare0; - unsigned int cmu_cdrex_spare1; - unsigned int cmu_cdrex_spare2; - unsigned int cmu_cdrex_spare3; - unsigned int cmu_cdrex_spare4; - unsigned char res128[0x34dc]; - unsigned int cmu_cdrex_version; /* 0x10033ff0 */ - unsigned char res129[0x400c]; - unsigned int kpll_lock; - unsigned char res130[0xfc]; - unsigned int kpll_con0; - unsigned int kpll_con1; - unsigned char res131[0xf8]; - unsigned int src_kfc; - unsigned char res132[0x1fc]; - unsigned int mux_stat_kfc; /* 0x10038400 */ - unsigned char res133[0xfc]; - unsigned int div_kfc0; - unsigned char res134[0xfc]; - unsigned int div_stat_kfc0; - unsigned char res135[0xfc]; - unsigned int gate_bus_cpu_kfc; - unsigned char res136[0xfc]; - unsigned int gate_sclk_cpu_kfc; - unsigned char res137[0x1fc]; - unsigned int clkout_cmu_kfc; - unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */ - unsigned char res138[0x5f8]; - unsigned int armclk_stopctrl_kfc; - unsigned char res139[0x4]; - unsigned int armclk_ema_ctrl_kfc; - unsigned int armclk_ema_status_kfc; - unsigned char res140[0x10]; - unsigned int pwr_ctrl_kfc; - unsigned int pwr_ctrl2_kfc; - unsigned char res141[0xd8]; - unsigned int kpll_con0_l8; - unsigned int kpll_con0_l7; - unsigned int kpll_con0_l6; - unsigned int kpll_con0_l5; - unsigned int kpll_con0_l4; - unsigned int kpll_con0_l3; - unsigned int kpll_con0_l2; - unsigned int kpll_con0_l1; - unsigned int iem_control_kfc; /* 0x10039120 */ - unsigned char res142[0xdc]; - unsigned int kpll_con1_l8; - unsigned int kpll_con1_l7; - unsigned int kpll_con1_l6; - unsigned int kpll_con1_l5; - unsigned int kpll_con1_l4; - unsigned int kpll_con1_l3; - unsigned int kpll_con1_l2; - unsigned int kpll_con1_l1; - unsigned char res143[0xe0]; - unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */ - unsigned int clkdiv_iem_l7_kfc; - unsigned int clkdiv_iem_l6_kfc; - unsigned int clkdiv_iem_l5_kfc; - unsigned int clkdiv_iem_l4_kfc; - unsigned int clkdiv_iem_l3_kfc; - unsigned int clkdiv_iem_l2_kfc; - unsigned int clkdiv_iem_l1_kfc; - unsigned char res144[0xe0]; - unsigned int l2_status_kfc; - unsigned char res145[0xc]; - unsigned int cpu_status_kfc; /* 0x10039410 */ - unsigned char res146[0xc]; - unsigned int ptm_status_kfc; - unsigned char res147[0xbdc]; - unsigned int cmu_kfc_spare0; - unsigned int cmu_kfc_spare1; - unsigned int cmu_kfc_spare2; - unsigned int cmu_kfc_spare3; - unsigned int cmu_kfc_spare4; - unsigned char res148[0x1fdc]; - unsigned int cmu_kfc_version; /* 0x1003bff0 */ -}; - -/* structure for epll configuration used in audio clock configuration */ -struct set_epll_con_val { - unsigned int freq_out; /* frequency out */ - unsigned int en_lock_det; /* enable lock detect */ - unsigned int m_div; /* m divider value */ - unsigned int p_div; /* p divider value */ - unsigned int s_div; /* s divider value */ - unsigned int k_dsm; /* k value of delta signal modulator */ -}; -#endif - -#define MPLL_FOUT_SEL_SHIFT 4 -#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ -#define TIMEOUT_EPLL_LOCK 1000 - -#define AUDIO_0_RATIO_MASK 0x0f -#define AUDIO_1_RATIO_MASK 0x0f - -#define AUDIO0_SEL_MASK 0xf -#define AUDIO1_SEL_MASK 0xf - -#define CLK_SRC_SCLK_EPLL 0x7 -#define CLK_SRC_MOUT_EPLL (1<<12) -#define AUDIO_CLKMUX_ASS (1<<0) - -/* CON0 bit-fields */ -#define EPLL_CON0_MDIV_MASK 0x1ff -#define EPLL_CON0_PDIV_MASK 0x3f -#define EPLL_CON0_SDIV_MASK 0x7 -#define EPLL_CON0_MDIV_SHIFT 16 -#define EPLL_CON0_PDIV_SHIFT 8 -#define EPLL_CON0_SDIV_SHIFT 0 -#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 -#define EPLL_CON0_LOCK_DET_EN_MASK 1 - -#define MPLL_FOUT_SEL_MASK 0x1 -#define BPLL_FOUT_SEL_SHIFT 0 -#define BPLL_FOUT_SEL_MASK 0x1 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/cpu.h deleted file mode 100644 index fdf73b507..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/cpu.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EXYNOS4_CPU_H -#define _EXYNOS4_CPU_H - -#define DEVICE_NOT_AVAILABLE 0 - -#define EXYNOS_CPU_NAME "Exynos" -#define EXYNOS4_ADDR_BASE 0x10000000 - -/* EXYNOS4 Common*/ -#define EXYNOS4_I2C_SPACING 0x10000 - -#define EXYNOS4_GPIO_PART3_BASE 0x03860000 -#define EXYNOS4_PRO_ID 0x10000000 -#define EXYNOS4_SYSREG_BASE 0x10010000 -#define EXYNOS4_POWER_BASE 0x10020000 -#define EXYNOS4_SWRESET 0x10020400 -#define EXYNOS4_CLOCK_BASE 0x10030000 -#define EXYNOS4_SYSTIMER_BASE 0x10050000 -#define EXYNOS4_WATCHDOG_BASE 0x10060000 -#define EXYNOS4_TZPC_BASE 0x10110000 -#define EXYNOS4_DMC_CTRL_BASE 0x10400000 -#define EXYNOS4_MIU_BASE 0x10600000 -#define EXYNOS4_ACE_SFR_BASE 0x10830000 -#define EXYNOS4_GPIO_PART2_BASE 0x11000000 -#define EXYNOS4_GPIO_PART1_BASE 0x11400000 -#define EXYNOS4_FIMD_BASE 0x11C00000 -#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 -#define EXYNOS4_USBOTG_BASE 0x12480000 -#define EXYNOS4_MMC_BASE 0x12510000 -#define EXYNOS4_SROMC_BASE 0x12570000 -#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 -#define EXYNOS4_USBPHY_BASE 0x125B0000 -#define EXYNOS4_UART_BASE 0x13800000 -#define EXYNOS4_I2C_BASE 0x13860000 -#define EXYNOS4_ADC_BASE 0x13910000 -#define EXYNOS4_SPI_BASE 0x13920000 -#define EXYNOS4_PWMTIMER_BASE 0x139D0000 -#define EXYNOS4_MODEM_BASE 0x13A00000 -#define EXYNOS4_USBPHY_CONTROL 0x10020704 -#define EXYNOS4_I2S_BASE 0xE2100000 - -#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE - -/* EXYNOS4X12 */ -#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 -#define EXYNOS4X12_PRO_ID 0x10000000 -#define EXYNOS4X12_SYSREG_BASE 0x10010000 -#define EXYNOS4X12_POWER_BASE 0x10020000 -#define EXYNOS4X12_SWRESET 0x10020400 -#define EXYNOS4X12_USBPHY_CONTROL 0x10020704 -#define EXYNOS4X12_CLOCK_BASE 0x10030000 -#define EXYNOS4X12_SYSTIMER_BASE 0x10050000 -#define EXYNOS4X12_WATCHDOG_BASE 0x10060000 -#define EXYNOS4X12_TZPC_BASE 0x10110000 -#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 -#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 -#define EXYNOS4X12_ACE_SFR_BASE 0x10830000 -#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 -#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 -#define EXYNOS4X12_FIMD_BASE 0x11C00000 -#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 -#define EXYNOS4X12_USBOTG_BASE 0x12480000 -#define EXYNOS4X12_MMC_BASE 0x12510000 -#define EXYNOS4X12_SROMC_BASE 0x12570000 -#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000 -#define EXYNOS4X12_USBPHY_BASE 0x125B0000 -#define EXYNOS4X12_UART_BASE 0x13800000 -#define EXYNOS4X12_I2C_BASE 0x13860000 -#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000 - -#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE - -/* EXYNOS5 */ -#define EXYNOS5_I2C_SPACING 0x10000 - -#define EXYNOS5_AUDIOSS_BASE 0x03810000 -#define EXYNOS5_GPIO_PART4_BASE 0x03860000 -#define EXYNOS5_PRO_ID 0x10000000 -#define EXYNOS5_CLOCK_BASE 0x10010000 -#define EXYNOS5_POWER_BASE 0x10040000 -#define EXYNOS5_SWRESET 0x10040400 -#define EXYNOS5_SYSREG_BASE 0x10050000 -#define EXYNOS5_TZPC_BASE 0x10100000 -#define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 -#define EXYNOS5_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 -#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 -#define EXYNOS5_GPIO_PART1_BASE 0x11400000 -#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 -#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 -#define EXYNOS5_USB3PHY_BASE 0x12100000 -#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 -#define EXYNOS5_USBPHY_BASE 0x12130000 -#define EXYNOS5_USBOTG_BASE 0x12140000 -#define EXYNOS5_MMC_BASE 0x12200000 -#define EXYNOS5_SROMC_BASE 0x12250000 -#define EXYNOS5_UART_BASE 0x12C00000 -#define EXYNOS5_I2C_BASE 0x12C60000 -#define EXYNOS5_SPI_BASE 0x12D20000 -#define EXYNOS5_I2S_BASE 0x12D60000 -#define EXYNOS5_PWMTIMER_BASE 0x12DD0000 -#define EXYNOS5_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5_FIMD_BASE 0x14400000 -#define EXYNOS5_DP_BASE 0x145B0000 - -#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE - -/* EXYNOS5420 */ -#define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 -#define EXYNOS5420_PRO_ID 0x10000000 -#define EXYNOS5420_CLOCK_BASE 0x10010000 -#define EXYNOS5420_POWER_BASE 0x10040000 -#define EXYNOS5420_SWRESET 0x10040400 -#define EXYNOS5420_SYSREG_BASE 0x10050000 -#define EXYNOS5420_TZPC_BASE 0x100E0000 -#define EXYNOS5420_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5420_ACE_SFR_BASE 0x10830000 -#define EXYNOS5420_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000 -#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000 -#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 -#define EXYNOS5420_MMC_BASE 0x12200000 -#define EXYNOS5420_SROMC_BASE 0x12250000 -#define EXYNOS5420_UART_BASE 0x12C00000 -#define EXYNOS5420_I2C_BASE 0x12C60000 -#define EXYNOS5420_I2C_8910_BASE 0x12E00000 -#define EXYNOS5420_SPI_BASE 0x12D20000 -#define EXYNOS5420_I2S_BASE 0x12D60000 -#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 -#define EXYNOS5420_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 -#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 -#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 -#define EXYNOS5420_DP_BASE 0x145B0000 - -#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE - -#ifndef __ASSEMBLY__ -#include <asm/io.h> -/* CPU detection macros */ -extern unsigned int s5p_cpu_id; -extern unsigned int s5p_cpu_rev; - -static inline int s5p_get_cpu_rev(void) -{ - return s5p_cpu_rev; -} - -static inline void s5p_set_cpu_id(void) -{ - unsigned int pro_id = readl(EXYNOS4_PRO_ID); - unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12; - unsigned int cpu_rev = pro_id & 0x000000FF; - - switch (cpu_id) { - case 0x200: - /* Exynos4210 EVT0 */ - s5p_cpu_id = 0x4210; - s5p_cpu_rev = 0; - break; - case 0x210: - /* Exynos4210 EVT1 */ - s5p_cpu_id = 0x4210; - s5p_cpu_rev = cpu_rev; - break; - case 0x412: - /* Exynos4412 */ - s5p_cpu_id = 0x4412; - s5p_cpu_rev = cpu_rev; - break; - case 0x520: - /* Exynos5250 */ - s5p_cpu_id = 0x5250; - break; - case 0x420: - /* Exynos5420 */ - s5p_cpu_id = 0x5420; - break; - } -} - -static inline char *s5p_get_cpu_name(void) -{ - return EXYNOS_CPU_NAME; -} - -#define IS_SAMSUNG_TYPE(type, id) \ -static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \ -{ \ - return (s5p_cpu_id >> 12) == id; \ -} - -IS_SAMSUNG_TYPE(exynos4, 0x4) -IS_SAMSUNG_TYPE(exynos5, 0x5) - -#define IS_EXYNOS_TYPE(type, id) \ -static inline int __attribute__((no_instrument_function)) \ - proid_is_##type(void) \ -{ \ - return s5p_cpu_id == id; \ -} - -IS_EXYNOS_TYPE(exynos4210, 0x4210) -IS_EXYNOS_TYPE(exynos4412, 0x4412) -IS_EXYNOS_TYPE(exynos5250, 0x5250) -IS_EXYNOS_TYPE(exynos5420, 0x5420) - -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int __attribute__((no_instrument_function)) \ - samsung_get_base_##device(void) \ -{ \ - if (cpu_is_exynos4()) { \ - if (proid_is_exynos4412()) \ - return EXYNOS4X12_##base; \ - return EXYNOS4_##base; \ - } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420()) \ - return EXYNOS5420_##base; \ - return EXYNOS5_##base; \ - } \ - return 0; \ -} - -SAMSUNG_BASE(adc, ADC_BASE) -SAMSUNG_BASE(clock, CLOCK_BASE) -SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) -SAMSUNG_BASE(dp, DP_BASE) -SAMSUNG_BASE(sysreg, SYSREG_BASE) -SAMSUNG_BASE(fimd, FIMD_BASE) -SAMSUNG_BASE(i2c, I2C_BASE) -SAMSUNG_BASE(i2s, I2S_BASE) -SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) -SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) -SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) -SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) -SAMSUNG_BASE(pro_id, PRO_ID) -SAMSUNG_BASE(mmc, MMC_BASE) -SAMSUNG_BASE(modem, MODEM_BASE) -SAMSUNG_BASE(sromc, SROMC_BASE) -SAMSUNG_BASE(swreset, SWRESET) -SAMSUNG_BASE(timer, PWMTIMER_BASE) -SAMSUNG_BASE(uart, UART_BASE) -SAMSUNG_BASE(usb_phy, USBPHY_BASE) -SAMSUNG_BASE(usb3_phy, USB3PHY_BASE) -SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) -SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE) -SAMSUNG_BASE(usb_otg, USBOTG_BASE) -SAMSUNG_BASE(watchdog, WATCHDOG_BASE) -SAMSUNG_BASE(power, POWER_BASE) -SAMSUNG_BASE(spi, SPI_BASE) -SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) -SAMSUNG_BASE(tzpc, TZPC_BASE) -SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE) -SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE) -SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE) -SAMSUNG_BASE(audio_ass, AUDIOSS_BASE) -#endif - -#endif /* _EXYNOS4_CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dmc.h deleted file mode 100644 index d78536d2d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dmc.h +++ /dev/null @@ -1,497 +0,0 @@ -#ifndef __DMC_H__ -#define __DMC_H__ - -#ifndef __ASSEMBLY__ -struct exynos4_dmc { - unsigned int concontrol; - unsigned int memcontrol; - unsigned int memconfig0; - unsigned int memconfig1; - unsigned int directcmd; - unsigned int prechconfig; - unsigned int phycontrol0; - unsigned int phycontrol1; - unsigned int phycontrol2; - unsigned int phycontrol3; - unsigned int pwrdnconfig; - unsigned char res1[0x4]; - unsigned int timingref; - unsigned int timingrow; - unsigned int timingdata; - unsigned int timingpower; - unsigned int phystatus; - unsigned int phyzqcontrol; - unsigned int chip0status; - unsigned int chip1status; - unsigned int arefstatus; - unsigned int mrstatus; - unsigned int phytest0; - unsigned int phytest1; - unsigned int qoscontrol0; - unsigned int qosconfig0; - unsigned int qoscontrol1; - unsigned int qosconfig1; - unsigned int qoscontrol2; - unsigned int qosconfig2; - unsigned int qoscontrol3; - unsigned int qosconfig3; - unsigned int qoscontrol4; - unsigned int qosconfig4; - unsigned int qoscontrol5; - unsigned int qosconfig5; - unsigned int qoscontrol6; - unsigned int qosconfig6; - unsigned int qoscontrol7; - unsigned int qosconfig7; - unsigned int qoscontrol8; - unsigned int qosconfig8; - unsigned int qoscontrol9; - unsigned int qosconfig9; - unsigned int qoscontrol10; - unsigned int qosconfig10; - unsigned int qoscontrol11; - unsigned int qosconfig11; - unsigned int qoscontrol12; - unsigned int qosconfig12; - unsigned int qoscontrol13; - unsigned int qosconfig13; - unsigned int qoscontrol14; - unsigned int qosconfig14; - unsigned int qoscontrol15; - unsigned int qosconfig15; - unsigned int qostimeout0; - unsigned int qostimeout1; - unsigned char res2[0x8]; - unsigned int ivcontrol; - unsigned char res3[0x8]; - unsigned int perevconfig; - unsigned char res4[0xDF00]; - unsigned int pmnc_ppc_a; - unsigned char res5[0xC]; - unsigned int cntens_ppc_a; - unsigned char res6[0xC]; - unsigned int cntenc_ppc_a; - unsigned char res7[0xC]; - unsigned int intens_ppc_a; - unsigned char res8[0xC]; - unsigned int intenc_ppc_a; - unsigned char res9[0xC]; - unsigned int flag_ppc_a; - unsigned char res10[0xAC]; - unsigned int ccnt_ppc_a; - unsigned char res11[0xC]; - unsigned int pmcnt0_ppc_a; - unsigned char res12[0xC]; - unsigned int pmcnt1_ppc_a; - unsigned char res13[0xC]; - unsigned int pmcnt2_ppc_a; - unsigned char res14[0xC]; - unsigned int pmcnt3_ppc_a; - unsigned char res15[0xEBC]; - unsigned int pmnc_ppc_m; - unsigned char res16[0xC]; - unsigned int cntens_ppc_m; - unsigned char res17[0xC]; - unsigned int cntenc_ppc_m; - unsigned char res18[0xC]; - unsigned int intens_ppc_m; - unsigned char res19[0xC]; - unsigned int intenc_ppc_m; - unsigned char res20[0xC]; - unsigned int flag_ppc_m; - unsigned char res21[0xAC]; - unsigned int ccnt_ppc_m; - unsigned char res22[0xC]; - unsigned int pmcnt0_ppc_m; - unsigned char res23[0xC]; - unsigned int pmcnt1_ppc_m; - unsigned char res24[0xC]; - unsigned int pmcnt2_ppc_m; - unsigned char res25[0xC]; - unsigned int pmcnt3_ppc_m; -}; - -struct exynos5_dmc { - unsigned int concontrol; - unsigned int memcontrol; - unsigned int memconfig0; - unsigned int memconfig1; - unsigned int directcmd; - unsigned int prechconfig; - unsigned int phycontrol0; - unsigned char res1[0xc]; - unsigned int pwrdnconfig; - unsigned int timingpzq; - unsigned int timingref; - unsigned int timingrow; - unsigned int timingdata; - unsigned int timingpower; - unsigned int phystatus; - unsigned char res2[0x4]; - unsigned int chipstatus_ch0; - unsigned int chipstatus_ch1; - unsigned char res3[0x4]; - unsigned int mrstatus; - unsigned char res4[0x8]; - unsigned int qoscontrol0; - unsigned char resr5[0x4]; - unsigned int qoscontrol1; - unsigned char res6[0x4]; - unsigned int qoscontrol2; - unsigned char res7[0x4]; - unsigned int qoscontrol3; - unsigned char res8[0x4]; - unsigned int qoscontrol4; - unsigned char res9[0x4]; - unsigned int qoscontrol5; - unsigned char res10[0x4]; - unsigned int qoscontrol6; - unsigned char res11[0x4]; - unsigned int qoscontrol7; - unsigned char res12[0x4]; - unsigned int qoscontrol8; - unsigned char res13[0x4]; - unsigned int qoscontrol9; - unsigned char res14[0x4]; - unsigned int qoscontrol10; - unsigned char res15[0x4]; - unsigned int qoscontrol11; - unsigned char res16[0x4]; - unsigned int qoscontrol12; - unsigned char res17[0x4]; - unsigned int qoscontrol13; - unsigned char res18[0x4]; - unsigned int qoscontrol14; - unsigned char res19[0x4]; - unsigned int qoscontrol15; - unsigned char res20[0x14]; - unsigned int ivcontrol; - unsigned int wrtra_config; - unsigned int rdlvl_config; - unsigned char res21[0x8]; - unsigned int brbrsvconfig; - unsigned int brbqosconfig; - unsigned int membaseconfig0; - unsigned int membaseconfig1; - unsigned char res22[0xc]; - unsigned int wrlvl_config; - unsigned char res23[0xc]; - unsigned int perevcontrol; - unsigned int perev0config; - unsigned int perev1config; - unsigned int perev2config; - unsigned int perev3config; - unsigned char res24[0xdebc]; - unsigned int pmnc_ppc_a; - unsigned char res25[0xc]; - unsigned int cntens_ppc_a; - unsigned char res26[0xc]; - unsigned int cntenc_ppc_a; - unsigned char res27[0xc]; - unsigned int intens_ppc_a; - unsigned char res28[0xc]; - unsigned int intenc_ppc_a; - unsigned char res29[0xc]; - unsigned int flag_ppc_a; - unsigned char res30[0xac]; - unsigned int ccnt_ppc_a; - unsigned char res31[0xc]; - unsigned int pmcnt0_ppc_a; - unsigned char res32[0xc]; - unsigned int pmcnt1_ppc_a; - unsigned char res33[0xc]; - unsigned int pmcnt2_ppc_a; - unsigned char res34[0xc]; - unsigned int pmcnt3_ppc_a; -}; - -struct exynos5420_dmc { - unsigned int concontrol; - unsigned int memcontrol; - unsigned int cgcontrol; - unsigned char res500[0x4]; - unsigned int directcmd; - unsigned int prechconfig0; - unsigned int phycontrol0; - unsigned int prechconfig1; - unsigned char res1[0x8]; - unsigned int pwrdnconfig; - unsigned int timingpzq; - unsigned int timingref; - unsigned int timingrow0; - unsigned int timingdata0; - unsigned int timingpower0; - unsigned int phystatus; - unsigned int etctiming; - unsigned int chipstatus; - unsigned char res3[0x8]; - unsigned int mrstatus; - unsigned char res4[0x8]; - unsigned int qoscontrol0; - unsigned char resr5[0x4]; - unsigned int qoscontrol1; - unsigned char res6[0x4]; - unsigned int qoscontrol2; - unsigned char res7[0x4]; - unsigned int qoscontrol3; - unsigned char res8[0x4]; - unsigned int qoscontrol4; - unsigned char res9[0x4]; - unsigned int qoscontrol5; - unsigned char res10[0x4]; - unsigned int qoscontrol6; - unsigned char res11[0x4]; - unsigned int qoscontrol7; - unsigned char res12[0x4]; - unsigned int qoscontrol8; - unsigned char res13[0x4]; - unsigned int qoscontrol9; - unsigned char res14[0x4]; - unsigned int qoscontrol10; - unsigned char res15[0x4]; - unsigned int qoscontrol11; - unsigned char res16[0x4]; - unsigned int qoscontrol12; - unsigned char res17[0x4]; - unsigned int qoscontrol13; - unsigned char res18[0x4]; - unsigned int qoscontrol14; - unsigned char res19[0x4]; - unsigned int qoscontrol15; - unsigned char res20[0x4]; - unsigned int timing_set_sw; - unsigned int timingrow1; - unsigned int timingdata1; - unsigned int timingpower1; - unsigned char res300[0x4]; - unsigned int wrtra_config; - unsigned int rdlvl_config; - unsigned char res21[0x4]; - unsigned int brbrsvcontrol; - unsigned int brbrsvconfig; - unsigned int brbqosconfig; - unsigned char res301[0x14]; - unsigned int wrlvl_config0; - unsigned int wrlvl_config1; - unsigned int wrlvl_status; - unsigned char res23[0x4]; - unsigned int ppcclockon; - unsigned int perevconfig0; - unsigned int perevconfig1; - unsigned int perevconfig2; - unsigned int perevconfig3; - unsigned char res24[0xc]; - unsigned int control_io_rdata; - unsigned char res240[0xc]; - unsigned int cacal_config0; - unsigned int cacal_config1; - unsigned int cacal_status; - unsigned char res302[0xa4]; - unsigned int bp_control0; - unsigned int bp_config0_r; - unsigned int bp_config0_w; - unsigned char res303[0x4]; - unsigned int bp_control1; - unsigned int bp_config1_r; - unsigned int bp_config1_w; - unsigned char res304[0x4]; - unsigned int bp_control2; - unsigned int bp_config2_r; - unsigned int bp_config2_w; - unsigned char res305[0x4]; - unsigned int bp_control3; - unsigned int bp_config3_r; - unsigned int bp_config3_w; - unsigned char res306[0xddb4]; - unsigned int pmnc_ppc; - unsigned char res25[0xc]; - unsigned int cntens_ppc; - unsigned char res26[0xc]; - unsigned int cntenc_ppc; - unsigned char res27[0xc]; - unsigned int intens_ppc; - unsigned char res28[0xc]; - unsigned int intenc_ppc; - unsigned char res29[0xc]; - unsigned int flag_ppc; - unsigned char res30[0xac]; - unsigned int ccnt_ppc; - unsigned char res31[0xc]; - unsigned int pmcnt0_ppc; - unsigned char res32[0xc]; - unsigned int pmcnt1_ppc; - unsigned char res33[0xc]; - unsigned int pmcnt2_ppc; - unsigned char res34[0xc]; - unsigned int pmcnt3_ppc; -}; - -struct exynos5_phy_control { - unsigned int phy_con0; - unsigned int phy_con1; - unsigned int phy_con2; - unsigned int phy_con3; - unsigned int phy_con4; - unsigned char res1[4]; - unsigned int phy_con6; - unsigned char res2[4]; - unsigned int phy_con8; - unsigned int phy_con9; - unsigned int phy_con10; - unsigned char res3[4]; - unsigned int phy_con12; - unsigned int phy_con13; - unsigned int phy_con14; - unsigned int phy_con15; - unsigned int phy_con16; - unsigned char res4[4]; - unsigned int phy_con17; - unsigned int phy_con18; - unsigned int phy_con19; - unsigned int phy_con20; - unsigned int phy_con21; - unsigned int phy_con22; - unsigned int phy_con23; - unsigned int phy_con24; - unsigned int phy_con25; - unsigned int phy_con26; - unsigned int phy_con27; - unsigned int phy_con28; - unsigned int phy_con29; - unsigned int phy_con30; - unsigned int phy_con31; - unsigned int phy_con32; - unsigned int phy_con33; - unsigned int phy_con34; - unsigned int phy_con35; - unsigned int phy_con36; - unsigned int phy_con37; - unsigned int phy_con38; - unsigned int phy_con39; - unsigned int phy_con40; - unsigned int phy_con41; - unsigned int phy_con42; -}; - -struct exynos5420_phy_control { - unsigned int phy_con0; - unsigned int phy_con1; - unsigned int phy_con2; - unsigned int phy_con3; - unsigned int phy_con4; - unsigned int phy_con5; - unsigned int phy_con6; - unsigned char res2[0x4]; - unsigned int phy_con8; - unsigned char res5[0x4]; - unsigned int phy_con10; - unsigned int phy_con11; - unsigned int phy_con12; - unsigned int phy_con13; - unsigned int phy_con14; - unsigned int phy_con15; - unsigned int phy_con16; - unsigned char res4[0x4]; - unsigned int phy_con17; - unsigned int phy_con18; - unsigned int phy_con19; - unsigned int phy_con20; - unsigned int phy_con21; - unsigned int phy_con22; - unsigned int phy_con23; - unsigned int phy_con24; - unsigned int phy_con25; - unsigned int phy_con26; - unsigned int phy_con27; - unsigned int phy_con28; - unsigned int phy_con29; - unsigned int phy_con30; - unsigned int phy_con31; - unsigned int phy_con32; - unsigned int phy_con33; - unsigned int phy_con34; - unsigned char res6[0x8]; - unsigned int phy_con37; - unsigned char res7[0x4]; - unsigned int phy_con39; - unsigned int phy_con40; - unsigned int phy_con41; - unsigned int phy_con42; -}; - -struct exynos5420_tzasc { - unsigned char res1[0xf00]; - unsigned int membaseconfig0; - unsigned int membaseconfig1; - unsigned char res2[0x8]; - unsigned int memconfig0; - unsigned int memconfig1; -}; - -enum ddr_mode { - DDR_MODE_DDR2, - DDR_MODE_DDR3, - DDR_MODE_LPDDR2, - DDR_MODE_LPDDR3, - - DDR_MODE_COUNT, -}; - -enum mem_manuf { - MEM_MANUF_AUTODETECT, - MEM_MANUF_ELPIDA, - MEM_MANUF_SAMSUNG, - - MEM_MANUF_COUNT, -}; - -/* CONCONTROL register fields */ -#define CONCONTROL_DFI_INIT_START_SHIFT 28 -#define CONCONTROL_RD_FETCH_SHIFT 12 -#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) -#define CONCONTROL_AREF_EN_SHIFT 5 - -/* PRECHCONFIG register field */ -#define PRECHCONFIG_TP_CNT_SHIFT 24 - -/* PWRDNCONFIG register field */ -#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 -#define PWRDNCONFIG_DSREF_CYC_SHIFT 16 - -/* PHY_CON0 register fields */ -#define PHY_CON0_T_WRRDCMD_SHIFT 17 -#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) -#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 -#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 - -/* PHY_CON1 register fields */ -#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 - -/* PHY_CON12 register fields */ -#define PHY_CON12_CTRL_START_POINT_SHIFT 24 -#define PHY_CON12_CTRL_INC_SHIFT 16 -#define PHY_CON12_CTRL_FORCE_SHIFT 8 -#define PHY_CON12_CTRL_START_SHIFT 6 -#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) -#define PHY_CON12_CTRL_DLL_ON_SHIFT 5 -#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) -#define PHY_CON12_CTRL_REF_SHIFT 1 - -/* PHY_CON16 register fields */ -#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 -#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) - -#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 -#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) - -#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) - -/* PHY_CON42 register fields */ -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 -#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) - -#define PHY_CON42_CTRL_RDLAT_SHIFT 0 -#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) - -#endif -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp.h deleted file mode 100644 index 0ec58e94c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp.h +++ /dev/null @@ -1,738 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_DP_H_ -#define __ASM_ARM_ARCH_DP_H_ - -#ifndef __ASSEMBLY__ - -struct exynos_dp { - unsigned char res1[0x10]; - unsigned int tx_version; - unsigned int tx_sw_reset; - unsigned int func_en1; - unsigned int func_en2; - unsigned int video_ctl1; - unsigned int video_ctl2; - unsigned int video_ctl3; - unsigned int video_ctl4; - unsigned int color_blue_cb; - unsigned int color_green_y; - unsigned int color_red_cr; - unsigned int video_ctl8; - unsigned char res2[0x4]; - unsigned int video_ctl10; - unsigned int total_ln_cfg_l; - unsigned int total_ln_cfg_h; - unsigned int active_ln_cfg_l; - unsigned int active_ln_cfg_h; - unsigned int vfp_cfg; - unsigned int vsw_cfg; - unsigned int vbp_cfg; - unsigned int total_pix_cfg_l; - unsigned int total_pix_cfg_h; - unsigned int active_pix_cfg_l; - unsigned int active_pix_cfg_h; - unsigned int hfp_cfg_l; - unsigned int hfp_cfg_h; - unsigned int hsw_cfg_l; - unsigned int hsw_cfg_h; - unsigned int hbp_cfg_l; - unsigned int hbp_cfg_h; - unsigned int video_status; - unsigned int total_ln_sta_l; - unsigned int total_ln_sta_h; - unsigned int active_ln_sta_l; - unsigned int active_ln_sta_h; - - unsigned int vfp_sta; - unsigned int vsw_sta; - unsigned int vbp_sta; - - unsigned int total_pix_sta_l; - unsigned int total_pix_sta_h; - unsigned int active_pix_sta_l; - unsigned int active_pix_sta_h; - - unsigned int hfp_sta_l; - unsigned int hfp_sta_h; - unsigned int hsw_sta_l; - unsigned int hsw_sta_h; - unsigned int hbp_sta_l; - unsigned int hbp_sta_h; - - unsigned char res3[0x288]; - - unsigned int lane_map; - unsigned char res4[0x10]; - unsigned int analog_ctl1; - unsigned int analog_ctl2; - unsigned int analog_ctl3; - - unsigned int pll_filter_ctl1; - unsigned int amp_tuning_ctl; - unsigned char res5[0xc]; - - unsigned int aux_hw_retry_ctl; - unsigned char res6[0x2c]; - unsigned int int_state; - unsigned int common_int_sta1; - unsigned int common_int_sta2; - unsigned int common_int_sta3; - unsigned int common_int_sta4; - unsigned char res7[0x8]; - - unsigned int int_sta; - unsigned char res8[0x1c]; - unsigned int int_ctl; - unsigned char res9[0x200]; - unsigned int sys_ctl1; - unsigned int sys_ctl2; - unsigned int sys_ctl3; - unsigned int sys_ctl4; - unsigned int vid_ctl; - unsigned char res10[0x2c]; - unsigned int pkt_send_ctl; - unsigned char res[0x4]; - unsigned int hdcp_ctl; - unsigned char res11[0x34]; - unsigned int link_bw_set; - - unsigned int lane_count_set; - unsigned int training_ptn_set; - unsigned int ln0_link_training_ctl; - unsigned int ln1_link_training_ctl; - unsigned int ln2_link_training_ctl; - unsigned int ln3_link_training_ctl; - unsigned int dn_spread_ctl; - unsigned int hw_link_training_ctl; - unsigned char res12[0x1c]; - - unsigned int debug_ctl; - unsigned int hpd_deglitch_l; - unsigned int hpd_deglitch_h; - - unsigned char res13[0x14]; - unsigned int link_debug_ctl; - - unsigned char res14[0x1c]; - - unsigned int m_vid0; - unsigned int m_vid1; - unsigned int m_vid2; - unsigned int n_vid0; - unsigned int n_vid1; - unsigned int n_vid2; - unsigned int m_vid_mon; - unsigned int pll_ctl; - unsigned int phy_pd; - unsigned int phy_test; - unsigned char res15[0x8]; - - unsigned int video_fifo_thrd; - unsigned char res16[0x8]; - unsigned int audio_margin; - - unsigned int dn_spread_ctl1; - unsigned int dn_spread_ctl2; - unsigned char res17[0x18]; - unsigned int m_cal_ctl; - unsigned int m_vid_gen_filter_th; - unsigned char res18[0x10]; - unsigned int m_aud_gen_filter_th; - unsigned char res50[0x4]; - - unsigned int aux_ch_sta; - unsigned int aux_err_num; - unsigned int aux_ch_defer_ctl; - unsigned int aux_rx_comm; - unsigned int buffer_data_ctl; - - unsigned int aux_ch_ctl1; - unsigned int aux_addr_7_0; - unsigned int aux_addr_15_8; - unsigned int aux_addr_19_16; - unsigned int aux_ch_ctl2; - unsigned char res19[0x18]; - unsigned int buf_data0; - unsigned char res20[0x3c]; - - unsigned int soc_general_ctl; - unsigned char res21[0x8c]; - unsigned int crc_con; - unsigned int crc_result; - unsigned char res22[0x8]; - - unsigned int common_int_mask1; - unsigned int common_int_mask2; - unsigned int common_int_mask3; - unsigned int common_int_mask4; - unsigned int int_sta_mask1; - unsigned int int_sta_mask2; - unsigned int int_sta_mask3; - unsigned int int_sta_mask4; - unsigned int int_sta_mask; - unsigned int crc_result2; - unsigned int scrambler_reset_cnt; - - unsigned int pn_inv; - unsigned int psr_config; - unsigned int psr_command0; - unsigned int psr_command1; - unsigned int psr_crc_mon0; - unsigned int psr_crc_mon1; - - unsigned char res24[0x30]; - unsigned int phy_bist_ctrl; - unsigned char res25[0xc]; - unsigned int phy_ctrl; - unsigned char res26[0x1c]; - unsigned int test_pattern_gen_en; - unsigned int test_pattern_gen_ctrl; -}; - -#endif /* __ASSEMBLY__ */ - -/* For DP VIDEO CTL 1 */ -#define VIDEO_EN_MASK (0x01 << 7) -#define VIDEO_MUTE_MASK (0x01 << 6) - -/* For DP VIDEO CTL 4 */ -#define VIDEO_BIST_MASK (0x1 << 3) - -/* EXYNOS_DP_ANALOG_CTL_1 */ -#define SEL_BG_NEW_BANDGAP (0x0 << 6) -#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6) -#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4) -#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4) -#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4) -#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4) -#define SWING_A_30PER_G_INCREASE (0x1 << 3) -#define SWING_A_30PER_G_NORMAL (0x0 << 3) - -/* EXYNOS_DP_ANALOG_CTL_2 */ -#define CPREG_BLEED (0x1 << 4) -#define SEL_24M (0x1 << 3) -#define TX_DVDD_BIT_1_0000V (0x3 << 0) -#define TX_DVDD_BIT_1_0625V (0x4 << 0) -#define TX_DVDD_BIT_1_1250V (0x5 << 0) - -/* EXYNOS_DP_ANALOG_CTL_3 */ -#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5) -#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) -#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5) -#define SEL_CURRENT_DEFAULT (0x0 << 3) -#define VCO_BIT_000_MICRO (0x0 << 0) -#define VCO_BIT_200_MICRO (0x1 << 0) -#define VCO_BIT_300_MICRO (0x2 << 0) -#define VCO_BIT_400_MICRO (0x3 << 0) -#define VCO_BIT_500_MICRO (0x4 << 0) -#define VCO_BIT_600_MICRO (0x5 << 0) -#define VCO_BIT_700_MICRO (0x6 << 0) -#define VCO_BIT_900_MICRO (0x7 << 0) - -/* EXYNOS_DP_PLL_FILTER_CTL_1 */ -#define PD_RING_OSC (0x1 << 6) -#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4) -#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4) -#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4) -#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4) -#define TX_CUR1_1X (0x0 << 2) -#define TX_CUR1_2X (0x1 << 2) -#define TX_CUR1_3X (0x2 << 2) -#define TX_CUR_1_MA (0x0 << 0) -#define TX_CUR_2_MA (0x1 << 0) -#define TX_CUR_3_MA (0x2 << 0) -#define TX_CUR_4_MA (0x3 << 0) - -/* EXYNOS_DP_PLL_FILTER_CTL_2 */ -#define CH3_AMP_0_MV (0x3 << 12) -#define CH2_AMP_0_MV (0x3 << 8) -#define CH1_AMP_0_MV (0x3 << 4) -#define CH0_AMP_0_MV (0x3 << 0) - -/* EXYNOS_DP_PLL_CTL */ -#define DP_PLL_PD (0x1 << 7) -#define DP_PLL_RESET (0x1 << 6) -#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) -#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) -#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) - -/* EXYNOS_DP_INT_CTL */ -#define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) - -/* DP TX SW RESET */ -#define RESET_DP_TX (0x01 << 0) - -/* DP FUNC_EN_1 */ -#define MASTER_VID_FUNC_EN_N (0x1 << 7) -#define SLAVE_VID_FUNC_EN_N (0x1 << 5) -#define AUD_FIFO_FUNC_EN_N (0x1 << 4) -#define AUD_FUNC_EN_N (0x1 << 3) -#define HDCP_FUNC_EN_N (0x1 << 2) -#define CRC_FUNC_EN_N (0x1 << 1) -#define SW_FUNC_EN_N (0x1 << 0) - -/* DP FUNC_EN_2 */ -#define SSC_FUNC_EN_N (0x1 << 7) -#define AUX_FUNC_EN_N (0x1 << 2) -#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) -#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) - -/* EXYNOS_DP_PHY_PD */ -#define PHY_PD (0x1 << 5) -#define AUX_PD (0x1 << 4) -#define CH3_PD (0x1 << 3) -#define CH2_PD (0x1 << 2) -#define CH1_PD (0x1 << 1) -#define CH0_PD (0x1 << 0) - -/* EXYNOS_DP_COMMON_INT_STA_1 */ -#define VSYNC_DET (0x1 << 7) -#define PLL_LOCK_CHG (0x1 << 6) -#define SPDIF_ERR (0x1 << 5) -#define SPDIF_UNSTBL (0x1 << 4) -#define VID_FORMAT_CHG (0x1 << 3) -#define AUD_CLK_CHG (0x1 << 2) -#define VID_CLK_CHG (0x1 << 1) -#define SW_INT (0x1 << 0) - -/* EXYNOS_DP_DEBUG_CTL */ -#define PLL_LOCK (0x1 << 4) -#define F_PLL_LOCK (0x1 << 3) -#define PLL_LOCK_CTRL (0x1 << 2) - -/* EXYNOS_DP_FUNC_EN_2 */ -#define SSC_FUNC_EN_N (0x1 << 7) -#define AUX_FUNC_EN_N (0x1 << 2) -#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) -#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) - -/* EXYNOS_DP_COMMON_INT_STA_4 */ -#define PSR_ACTIVE (0x1 << 7) -#define PSR_INACTIVE (0x1 << 6) -#define SPDIF_BI_PHASE_ERR (0x1 << 5) -#define HOTPLUG_CHG (0x1 << 2) -#define HPD_LOST (0x1 << 1) -#define PLUG (0x1 << 0) - -/* EXYNOS_DP_INT_STA */ -#define INT_HPD (0x1 << 6) -#define HW_TRAINING_FINISH (0x1 << 5) -#define RPLY_RECEIV (0x1 << 1) -#define AUX_ERR (0x1 << 0) - -/* EXYNOS_DP_SYS_CTL_3 */ -#define HPD_STATUS (0x1 << 6) -#define F_HPD (0x1 << 5) -#define HPD_CTRL (0x1 << 4) -#define HDCP_RDY (0x1 << 3) -#define STRM_VALID (0x1 << 2) -#define F_VALID (0x1 << 1) -#define VALID_CTRL (0x1 << 0) - -/* EXYNOS_DP_AUX_HW_RETRY_CTL */ -#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) -#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) -#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) -#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) -#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) -#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) -#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) - -/* EXYNOS_DP_AUX_CH_DEFER_CTL */ -#define DEFER_CTRL_EN (0x1 << 7) -#define DEFER_COUNT(x) (((x) & 0x7f) << 0) - -#define COMMON_INT_MASK_1 (0) -#define COMMON_INT_MASK_2 (0) -#define COMMON_INT_MASK_3 (0) -#define COMMON_INT_MASK_4 (0) -#define INT_STA_MASK (0) - -/* EXYNOS_DP_BUFFER_DATA_CTL */ -#define BUF_CLR (0x1 << 7) -#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) - -/* EXYNOS_DP_AUX_ADDR_7_0 */ -#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) - -/* EXYNOS_DP_AUX_ADDR_15_8 */ -#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) - -/* EXYNOS_DP_AUX_ADDR_19_16 */ -#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) - -/* EXYNOS_DP_AUX_CH_CTL_1 */ -#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) -#define AUX_TX_COMM_MASK (0xf << 0) -#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) -#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) -#define AUX_TX_COMM_MOT (0x1 << 2) -#define AUX_TX_COMM_WRITE (0x0 << 0) -#define AUX_TX_COMM_READ (0x1 << 0) - -/* EXYNOS_DP_AUX_CH_CTL_2 */ -#define ADDR_ONLY (0x1 << 1) -#define AUX_EN (0x1 << 0) - -/* EXYNOS_DP_AUX_CH_STA */ -#define AUX_BUSY (0x1 << 4) -#define AUX_STATUS_MASK (0xf << 0) - -/* EXYNOS_DP_AUX_RX_COMM */ -#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) -#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) - -/* EXYNOS_DP_PHY_TEST */ -#define MACRO_RST (0x1 << 5) -#define CH1_TEST (0x1 << 1) -#define CH0_TEST (0x1 << 0) - -/* EXYNOS_DP_TRAINING_PTN_SET */ -#define SCRAMBLER_TYPE (0x1 << 9) -#define HW_LINK_TRAINING_PATTERN (0x1 << 8) -#define SCRAMBLING_DISABLE (0x1 << 5) -#define SCRAMBLING_ENABLE (0x0 << 5) -#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) -#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) -#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) -#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) -#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) -#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) -#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) -#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) - -/* EXYNOS_DP_TOTAL_LINE_CFG */ -#define TOTAL_LINE_CFG_L(x) ((x) & 0xff) -#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff) -#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff) -#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff) -#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff) -#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) -#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff) -#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) - -#define H_F_PORCH_CFG_L(x) ((x) & 0xff) -#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) -#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff) -#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) -#define H_B_PORCH_CFG_L(x) ((x) & 0xff) -#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) - -/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ -#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5) -#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3) -#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3) -#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3) -#define PRE_EMPHASIS_SET_0_SHIFT (3) -#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3) -#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3) -#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3) -#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3) -#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2) -#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0) -#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0) -#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3) -#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0) -#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0) -#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0) -#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0) - -/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */ -#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5) -#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3) -#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3) -#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3) -#define PRE_EMPHASIS_SET_1_SHIFT (3) -#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3) -#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3) -#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3) -#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3) -#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2) -#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0) -#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0) -#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3) -#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0) -#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0) -#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0) -#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0) - -/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */ -#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5) -#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3) -#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3) -#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3) -#define PRE_EMPHASIS_SET_2_SHIFT (3) -#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3) -#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3) -#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3) -#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3) -#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2) -#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0) -#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0) -#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3) -#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0) -#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0) -#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0) -#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0) - -/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */ -#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5) -#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3) -#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3) -#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3) -#define PRE_EMPHASIS_SET_3_SHIFT (3) -#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3) -#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3) -#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3) -#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3) -#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2) -#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0) -#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0) -#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3) -#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0) -#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0) -#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0) -#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0) - -/* EXYNOS_DP_VIDEO_CTL_10 */ -#define FORMAT_SEL (0x1 << 4) -#define INTERACE_SCAN_CFG (0x1 << 2) -#define INTERACE_SCAN_CFG_SHIFT (2) -#define VSYNC_POLARITY_CFG (0x1 << 1) -#define V_S_POLARITY_CFG_SHIFT (1) -#define HSYNC_POLARITY_CFG (0x1 << 0) -#define H_S_POLARITY_CFG_SHIFT (0) - -/* EXYNOS_DP_SOC_GENERAL_CTL */ -#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) -#define AUDIO_MODE_MASTER_MODE (0x0 << 8) -#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) -#define VIDEO_MASTER_CLK_SEL (0x1 << 2) -#define VIDEO_MASTER_MODE_EN (0x1 << 1) -#define VIDEO_MODE_MASK (0x1 << 0) -#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) -#define VIDEO_MODE_MASTER_MODE (0x0 << 0) - -/* EXYNOS_DP_VIDEO_CTL_1 */ -#define VIDEO_EN (0x1 << 7) -#define HDCP_VIDEO_MUTE (0x1 << 6) - -/* EXYNOS_DP_VIDEO_CTL_2 */ -#define IN_D_RANGE_MASK (0x1 << 7) -#define IN_D_RANGE_SHIFT (7) -#define IN_D_RANGE_CEA (0x1 << 7) -#define IN_D_RANGE_VESA (0x0 << 7) -#define IN_BPC_MASK (0x7 << 4) -#define IN_BPC_SHIFT (4) -#define IN_BPC_12_BITS (0x3 << 4) -#define IN_BPC_10_BITS (0x2 << 4) -#define IN_BPC_8_BITS (0x1 << 4) -#define IN_BPC_6_BITS (0x0 << 4) -#define IN_COLOR_F_MASK (0x3 << 0) -#define IN_COLOR_F_SHIFT (0) -#define IN_COLOR_F_YCBCR444 (0x2 << 0) -#define IN_COLOR_F_YCBCR422 (0x1 << 0) -#define IN_COLOR_F_RGB (0x0 << 0) - -/* EXYNOS_DP_VIDEO_CTL_3 */ -#define IN_YC_COEFFI_MASK (0x1 << 7) -#define IN_YC_COEFFI_SHIFT (7) -#define IN_YC_COEFFI_ITU709 (0x1 << 7) -#define IN_YC_COEFFI_ITU601 (0x0 << 7) -#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) -#define VID_CHK_UPDATE_TYPE_SHIFT (4) -#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) -#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) - -/* EXYNOS_DP_TEST_PATTERN_GEN_EN */ -#define TEST_PATTERN_GEN_EN (0x1 << 0) -#define TEST_PATTERN_GEN_DIS (0x0 << 0) - -/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */ -#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0) -#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0) -#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0) - -/* EXYNOS_DP_VIDEO_CTL_4 */ -#define BIST_EN (0x1 << 3) -#define BIST_WIDTH_MASK (0x1 << 2) -#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2) -#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2) -#define BIST_TYPE_MASK (0x3 << 0) -#define BIST_TYPE_COLOR_BAR (0x0 << 0) -#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0) -#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0) - -/* EXYNOS_DP_SYS_CTL_1 */ -#define DET_STA (0x1 << 2) -#define FORCE_DET (0x1 << 1) -#define DET_CTRL (0x1 << 0) - -/* EXYNOS_DP_SYS_CTL_2 */ -#define CHA_CRI(x) (((x) & 0xf) << 4) -#define CHA_STA (0x1 << 2) -#define FORCE_CHA (0x1 << 1) -#define CHA_CTRL (0x1 << 0) - -/* EXYNOS_DP_SYS_CTL_3 */ -#define HPD_STATUS (0x1 << 6) -#define F_HPD (0x1 << 5) -#define HPD_CTRL (0x1 << 4) -#define HDCP_RDY (0x1 << 3) -#define STRM_VALID (0x1 << 2) -#define F_VALID (0x1 << 1) -#define VALID_CTRL (0x1 << 0) - -/* EXYNOS_DP_SYS_CTL_4 */ -#define FIX_M_AUD (0x1 << 4) -#define ENHANCED (0x1 << 3) -#define FIX_M_VID (0x1 << 2) -#define M_VID_UPDATE_CTRL (0x3 << 0) - -/* EXYNOS_M_VID_X */ -#define M_VID0_CFG(x) ((x) & 0xff) -#define M_VID1_CFG(x) (((x) >> 8) & 0xff) -#define M_VID2_CFG(x) (((x) >> 16) & 0xff) - -/* EXYNOS_M_VID_X */ -#define N_VID0_CFG(x) ((x) & 0xff) -#define N_VID1_CFG(x) (((x) >> 8) & 0xff) -#define N_VID2_CFG(x) (((x) >> 16) & 0xff) - -/* DPCD_TRAINING_PATTERN_SET */ -#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) -#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) -#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) -#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) -#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) - -/* Definition for DPCD Register */ -#define DPCD_DPCD_REV (0x0000) -#define DPCD_MAX_LINK_RATE (0x0001) -#define DPCD_MAX_LANE_COUNT (0x0002) -#define DPCD_LINK_BW_SET (0x0100) -#define DPCD_LANE_COUNT_SET (0x0101) -#define DPCD_TRAINING_PATTERN_SET (0x0102) -#define DPCD_TRAINING_LANE0_SET (0x0103) -#define DPCD_LANE0_1_STATUS (0x0202) -#define DPCD_LN_ALIGN_UPDATED (0x0204) -#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) -#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) -#define DPCD_TEST_REQUEST (0x0218) -#define DPCD_TEST_RESPONSE (0x0260) -#define DPCD_TEST_EDID_CHECKSUM (0x0261) -#define DPCD_SINK_POWER_STATE (0x0600) - -/* DPCD_TEST_REQUEST */ -#define DPCD_TEST_EDID_READ (0x1 << 2) - -/* DPCD_TEST_RESPONSE */ -#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) - -/* DPCD_SINK_POWER_STATE */ -#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) -#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) - -/* I2C EDID Chip ID, Slave Address */ -#define I2C_EDID_DEVICE_ADDR (0x50) -#define I2C_E_EDID_DEVICE_ADDR (0x30) -#define EDID_BLOCK_LENGTH (0x80) -#define EDID_HEADER_PATTERN (0x00) -#define EDID_EXTENSION_FLAG (0x7e) -#define EDID_CHECKSUM (0x7f) - -/* DPCD_LANE0_1_STATUS */ -#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6) -#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5) -#define DPCD_LANE1_CR_DONE (0x1 << 4) -#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2) -#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1) -#define DPCD_LANE0_CR_DONE (0x1 << 0) - -/* DPCD_ADJUST_REQUEST_LANE0_1 */ -#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6) -#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3) -#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6) -#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6) -#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6) -#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6) -#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4) -#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3) -#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4) -#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4) -#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4) -#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4) -#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2) -#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3) -#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2) -#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2) -#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2) -#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2) -#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0) -#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3) -#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0) -#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0) -#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0) -#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0) - -/* DPCD_ADJUST_REQUEST_LANE2_3 */ -#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6) -#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3) -#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6) -#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6) -#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6) -#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6) -#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4) -#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3) -#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4) -#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4) -#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4) -#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4) -#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2) -#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3) -#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2) -#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2) -#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2) -#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2) -#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0) -#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3) -#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0) -#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0) -#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0) -#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0) - -/* DPCD_LANE_COUNT_SET */ -#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) -#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f) - -/* DPCD_LANE_ALIGN__STATUS_UPDATED */ -#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) -#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) -#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) - -/* DPCD_TRAINING_LANE0_SET */ -#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3) -#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3) -#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3) -#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3) -#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0) -#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0) -#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0) -#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0) - -#define DPCD_REQ_ADJ_SWING (0x00) -#define DPCD_REQ_ADJ_EMPHASIS (0x01) - -#define DP_LANE_STAT_CR_DONE (0x01 << 0) -#define DP_LANE_STAT_CE_DONE (0x01 << 1) -#define DP_LANE_STAT_SYM_LOCK (0x01 << 2) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp_info.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp_info.h deleted file mode 100644 index 3f6750a6b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DP_INFO_H -#define _DP_INFO_H - -#define msleep(a) udelay(a * 1000) - -#define DP_TIMEOUT_LOOP_COUNT 100 -#define MAX_CR_LOOP 5 -#define MAX_EQ_LOOP 4 - -#define EXYNOS_DP_SUCCESS 0 - -enum { - DP_DISABLE, - DP_ENABLE, -}; - -struct edp_disp_info { - char *name; - unsigned int h_total; - unsigned int h_res; - unsigned int h_sync_width; - unsigned int h_back_porch; - unsigned int h_front_porch; - unsigned int v_total; - unsigned int v_res; - unsigned int v_sync_width; - unsigned int v_back_porch; - unsigned int v_front_porch; - - unsigned int v_sync_rate; -}; - -struct edp_link_train_info { - unsigned int lt_status; - - unsigned int ep_loop; - unsigned int cr_loop[4]; - -}; - -struct edp_video_info { - unsigned int master_mode; - unsigned int bist_mode; - unsigned int bist_pattern; - - unsigned int h_sync_polarity; - unsigned int v_sync_polarity; - unsigned int interlaced; - - unsigned int color_space; - unsigned int dynamic_range; - unsigned int ycbcr_coeff; - unsigned int color_depth; -}; - -struct edp_device_info { - struct edp_disp_info disp_info; - struct edp_link_train_info lt_info; - struct edp_video_info video_info; - - /*below info get from panel during training*/ - unsigned char lane_bw; - unsigned char lane_cnt; - unsigned char dpcd_rev; - /*support enhanced frame cap */ - unsigned char dpcd_efc; -}; - -enum analog_power_block { - AUX_BLOCK, - CH0_BLOCK, - CH1_BLOCK, - CH2_BLOCK, - CH3_BLOCK, - ANALOG_TOTAL, - POWER_ALL -}; - -enum pll_status { - PLL_UNLOCKED = 0, - PLL_LOCKED -}; - -enum { - COLOR_RGB, - COLOR_YCBCR422, - COLOR_YCBCR444 -}; - -enum { - VESA, - CEA -}; - -enum { - COLOR_YCBCR601, - COLOR_YCBCR709 -}; - -enum { - COLOR_6, - COLOR_8, - COLOR_10, - COLOR_12 -}; - -enum { - DP_LANE_BW_1_62 = 0x06, - DP_LANE_BW_2_70 = 0x0a, -}; - -enum { - DP_LANE_CNT_1 = 1, - DP_LANE_CNT_2 = 2, - DP_LANE_CNT_4 = 4, -}; - -enum { - DP_DPCD_REV_10 = 0x10, - DP_DPCD_REV_11 = 0x11, -}; - -enum { - DP_LT_NONE, - DP_LT_START, - DP_LT_CR, - DP_LT_ET, - DP_LT_FINISHED, - DP_LT_FAIL, -}; - -enum { - PRE_EMPHASIS_LEVEL_0, - PRE_EMPHASIS_LEVEL_1, - PRE_EMPHASIS_LEVEL_2, - PRE_EMPHASIS_LEVEL_3, -}; - -enum { - PRBS7, - D10_2, - TRAINING_PTN1, - TRAINING_PTN2, - DP_NONE -}; - -enum { - VOLTAGE_LEVEL_0, - VOLTAGE_LEVEL_1, - VOLTAGE_LEVEL_2, - VOLTAGE_LEVEL_3, -}; - -enum pattern_type { - NO_PATTERN, - COLOR_RAMP, - BALCK_WHITE_V_LINES, - COLOR_SQUARE, - INVALID_PATTERN, - COLORBAR_32, - COLORBAR_64, - WHITE_GRAY_BALCKBAR_32, - WHITE_GRAY_BALCKBAR_64, - MOBILE_WHITEBAR_32, - MOBILE_WHITEBAR_64 -}; - -enum { - CALCULATED_M, - REGISTER_M -}; - -enum { - VIDEO_TIMING_FROM_CAPTURE, - VIDEO_TIMING_FROM_REGISTER -}; - - -struct exynos_dp_platform_data { - struct edp_device_info *edp_dev_info; -}; - -#ifdef CONFIG_EXYNOS_DP -unsigned int exynos_init_dp(void); -#else -unsigned int exynos_init_dp(void) -{ - return 0; -} -#endif - -void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd); - -#endif /* _DP_INFO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dsim.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dsim.h deleted file mode 100644 index 86ff4da4d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dsim.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: InKi Dae <inki.dae@samsung.com> - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_DSIM_H_ -#define __ASM_ARM_ARCH_DSIM_H_ - -#ifndef __ASSEMBLY__ - -struct exynos_mipi_dsim { - unsigned int status; - unsigned int swrst; - unsigned int clkctrl; - unsigned int timeout; - unsigned int config; - unsigned int escmode; - unsigned int mdresol; - unsigned int mvporch; - unsigned int mhporch; - unsigned int msync; - unsigned int sdresol; - unsigned int intsrc; - unsigned int intmsk; - unsigned int pkthdr; - unsigned int payload; - unsigned int rxfifo; - unsigned int fifothld; - unsigned int fifoctrl; - unsigned int memacchr; - unsigned int pllctrl; - unsigned int plltmr; - unsigned int phyacchr; - unsigned int phyacchr1; -}; - -#endif /* __ASSEMBLY__ */ - -/* - * Bit Definitions - */ -/* DSIM_STATUS */ -#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) -#define DSIM_PLL_STABLE (1 << 31) - -/* DSIM_SWRST */ -#define DSIM_FUNCRST (1 << 16) -#define DSIM_SWRST (1 << 0) - -/* EXYNOS_DSIM_TIMEOUT */ -#define DSIM_LPDR_TOUT_SHIFT (0) -#define DSIM_BTA_TOUT_SHIFT (16) - -/* EXYNOS_DSIM_CLKCTRL */ -#define DSIM_LANE_ESC_CLKEN_SHIFT (19) -#define DSIM_BYTE_CLKEN_SHIFT (24) -#define DSIM_BYTE_CLK_SRC_SHIFT (25) -#define DSIM_PLL_BYPASS_SHIFT (27) -#define DSIM_ESC_CLKEN_SHIFT (28) -#define DSIM_TX_REQUEST_HSCLK_SHIFT (31) -#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \ - DSIM_LANE_ESC_CLKEN_SHIFT) -#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT) -#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT) -#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT) -#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT) -#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT) - -/* EXYNOS_DSIM_CONFIG */ -#define DSIM_NUM_OF_DATALANE_SHIFT (5) -#define DSIM_SUBPIX_SHIFT (8) -#define DSIM_MAINPIX_SHIFT (12) -#define DSIM_SUBVC_SHIFT (16) -#define DSIM_MAINVC_SHIFT (18) -#define DSIM_HSA_MODE_SHIFT (20) -#define DSIM_HBP_MODE_SHIFT (21) -#define DSIM_HFP_MODE_SHIFT (22) -#define DSIM_HSE_MODE_SHIFT (23) -#define DSIM_AUTO_MODE_SHIFT (24) -#define DSIM_VIDEO_MODE_SHIFT (25) -#define DSIM_BURST_MODE_SHIFT (26) -#define DSIM_EOT_PACKET_SHIFT (28) -#define DSIM_AUTO_FLUSH_SHIFT (29) -#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) - -#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT) - -/* EXYNOS_DSIM_ESCMODE */ -#define DSIM_TX_LPDT_SHIFT (6) -#define DSIM_CMD_LPDT_SHIFT (7) -#define DSIM_TX_LPDT_LP (1 << DSIM_TX_LPDT_SHIFT) -#define DSIM_CMD_LPDT_LP (1 << DSIM_CMD_LPDT_SHIFT) -#define DSIM_STOP_STATE_CNT_SHIFT (21) -#define DSIM_FORCE_STOP_STATE_SHIFT (20) - -/* EXYNOS_DSIM_MDRESOL */ -#define DSIM_MAIN_STAND_BY (1 << 31) -#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) -#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) - -/* EXYNOS_DSIM_MVPORCH */ -#define DSIM_CMD_ALLOW_SHIFT (28) -#define DSIM_STABLE_VFP_SHIFT (16) -#define DSIM_MAIN_VBP_SHIFT (0) -#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT) -#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT) -#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT) - -/* EXYNOS_DSIM_MHPORCH */ -#define DSIM_MAIN_HFP_SHIFT (16) -#define DSIM_MAIN_HBP_SHIFT (0) -#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT) -#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT) - -/* EXYNOS_DSIM_MSYNC */ -#define DSIM_MAIN_VSA_SHIFT (22) -#define DSIM_MAIN_HSA_SHIFT (0) -#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT) -#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT) - -/* EXYNOS_DSIM_SDRESOL */ -#define DSIM_SUB_STANDY_SHIFT (31) -#define DSIM_SUB_VRESOL_SHIFT (16) -#define DSIM_SUB_HRESOL_SHIFT (0) -#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT) -#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT) -#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT) - -/* EXYNOS_DSIM_INTSRC */ -#define INTSRC_FRAME_DONE (1 << 24) -#define INTSRC_PLL_STABLE (1 << 31) -#define INTSRC_SWRST_RELEASE (1 << 30) - -/* EXYNOS_DSIM_INTMSK */ -#define INTMSK_FRAME_DONE (1 << 24) - -/* EXYNOS_DSIM_FIFOCTRL */ -#define SFR_HEADER_EMPTY (1 << 22) - -/* EXYNOS_DSIM_PKTHDR */ -#define DSIM_PKTHDR_DI(x) (((x) & 0x3f) << 0) -#define DSIM_PKTHDR_DAT0(x) ((x) << 8) -#define DSIM_PKTHDR_DAT1(x) ((x) << 16) - -/* EXYNOS_DSIM_PHYACCHR */ -#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) -#define DSIM_AFC_CTL_SHIFT (5) -#define DSIM_AFC_EN (1 << 14) - -/* EXYNOS_DSIM_PHYACCHR1 */ -#define DSIM_DPDN_SWAP_DATA_SHIFT (0) - -/* EXYNOS_DSIM_PLLCTRL */ -#define DSIM_SCALER_SHIFT (1) -#define DSIM_MAIN_SHIFT (4) -#define DSIM_PREDIV_SHIFT (13) -#define DSIM_PRECTRL_SHIFT (20) -#define DSIM_PLL_EN_SHIFT (23) -#define DSIM_FREQ_BAND_SHIFT (24) -#define DSIM_ZEROCTRL_SHIFT (28) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dwmmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dwmmc.h deleted file mode 100644 index a7ca12c47..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dwmmc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2012 SAMSUNG Electronics - * Jaehoon Chung <jh80.chung@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define DWMCI_CLKSEL 0x09C -#define DWMCI_SET_SAMPLE_CLK(x) (x) -#define DWMCI_SET_DRV_CLK(x) ((x) << 16) -#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) - -#define EMMCP_MPSBEGIN0 0x1200 -#define EMMCP_SEND0 0x1204 -#define EMMCP_CTRL0 0x120C - -#define MPSCTRL_SECURE_READ_BIT (0x1<<7) -#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6) -#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5) -#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4) -#define MPSCTRL_USE_FUSE_KEY (0x1<<3) -#define MPSCTRL_ECB_MODE (0x1<<2) -#define MPSCTRL_ENCRYPTION (0x1<<1) -#define MPSCTRL_VALID (0x1<<0) - -/* CLKSEL Register */ -#define DWMCI_DIVRATIO_BIT 24 -#define DWMCI_DIVRATIO_MASK 0x7 - -#ifdef CONFIG_OF_CONTROL -int exynos_dwmmc_init(const void *blob); -#endif -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/ehci.h deleted file mode 100644 index d2d70bd82..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/ehci.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * SAMSUNG EXYNOS USB HOST EHCI Controller - * - * Copyright (C) 2012 Samsung Electronics Co.Ltd - * Vivek Gautam <gautam.vivek@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_EHCI_H__ -#define __ASM_ARM_ARCH_EHCI_H__ - -#define CLK_24MHZ 5 - -#define HOST_CTRL0_PHYSWRSTALL (1 << 31) -#define HOST_CTRL0_COMMONON_N (1 << 9) -#define HOST_CTRL0_SIDDQ (1 << 6) -#define HOST_CTRL0_FORCESLEEP (1 << 5) -#define HOST_CTRL0_FORCESUSPEND (1 << 4) -#define HOST_CTRL0_WORDINTERFACE (1 << 3) -#define HOST_CTRL0_UTMISWRST (1 << 2) -#define HOST_CTRL0_LINKSWRST (1 << 1) -#define HOST_CTRL0_PHYSWRST (1 << 0) - -#define HOST_CTRL0_FSEL_MASK (7 << 16) - -#define EHCICTRL_ENAINCRXALIGN (1 << 29) -#define EHCICTRL_ENAINCR4 (1 << 28) -#define EHCICTRL_ENAINCR8 (1 << 27) -#define EHCICTRL_ENAINCR16 (1 << 26) - -#define HSIC_CTRL_REFCLKSEL (0x2) -#define HSIC_CTRL_REFCLKSEL_MASK (0x3) -#define HSIC_CTRL_REFCLKSEL_SHIFT (23) - -#define HSIC_CTRL_REFCLKDIV_12 (0x24) -#define HSIC_CTRL_REFCLKDIV_MASK (0x7f) -#define HSIC_CTRL_REFCLKDIV_SHIFT (16) - -#define HSIC_CTRL_SIDDQ (0x1 << 6) -#define HSIC_CTRL_FORCESLEEP (0x1 << 5) -#define HSIC_CTRL_FORCESUSPEND (0x1 << 4) -#define HSIC_CTRL_UTMISWRST (0x1 << 2) -#define HSIC_CTRL_PHYSWRST (0x1 << 0) - -/* Register map for PHY control */ -struct exynos_usb_phy { - unsigned int usbphyctrl0; - unsigned int usbphytune0; - unsigned int reserved1[2]; - unsigned int hsicphyctrl1; - unsigned int hsicphytune1; - unsigned int reserved2[2]; - unsigned int hsicphyctrl2; - unsigned int hsicphytune2; - unsigned int reserved3[2]; - unsigned int ehcictrl; - unsigned int ohcictrl; - unsigned int usbotgsys; - unsigned int reserved4; - unsigned int usbotgtune; -}; - -/* Switch on the VBUS power. */ -int board_usb_vbus_init(void); - -#endif /* __ASM_ARM_ARCH_EHCI_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/fb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/fb.h deleted file mode 100644 index f0d69b730..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/fb.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_FB_H_ -#define __ASM_ARM_ARCH_FB_H_ - -#ifndef __ASSEMBLY__ -struct exynos_fb { - unsigned int vidcon0; - unsigned int vidcon1; - unsigned int vidcon2; - unsigned int vidcon3; - unsigned int vidtcon0; - unsigned int vidtcon1; - unsigned int vidtcon2; - unsigned int vidtcon3; - unsigned int wincon0; - unsigned int wincon1; - unsigned int wincon2; - unsigned int wincon3; - unsigned int wincon4; - - unsigned int winshmap; - unsigned int res1; - - unsigned int winchmap2; - unsigned int vidosd0a; - unsigned int vidosd0b; - unsigned int vidosd0c; - unsigned int res2; - - unsigned int vidosd1a; - unsigned int vidosd1b; - unsigned int vidosd1c; - unsigned int vidosd1d; - - unsigned int vidosd2a; - unsigned int vidosd2b; - unsigned int vidosd2c; - unsigned int vidosd2d; - - unsigned int vidosd3a; - unsigned int vidosd3b; - unsigned int vidosd3c; - unsigned int res3; - - unsigned int vidosd4a; - unsigned int vidosd4b; - unsigned int vidosd4c; - unsigned int res4[5]; - - unsigned int vidw00add0b0; - unsigned int vidw00add0b1; - unsigned int vidw01add0b0; - unsigned int vidw01add0b1; - - unsigned int vidw02add0b0; - unsigned int vidw02add0b1; - unsigned int vidw03add0b0; - unsigned int vidw03add0b1; - unsigned int vidw04add0b0; - unsigned int vidw04add0b1; - unsigned int res5[2]; - - unsigned int vidw00add1b0; - unsigned int vidw00add1b1; - unsigned int vidw01add1b0; - unsigned int vidw01add1b1; - - unsigned int vidw02add1b0; - unsigned int vidw02add1b1; - unsigned int vidw03add1b0; - unsigned int vidw03add1b1; - - unsigned int vidw04add1b0; - unsigned int vidw04add1b1; - unsigned int res7[2]; - - unsigned int vidw00add2; - unsigned int vidw01add2; - unsigned int vidw02add2; - unsigned int vidw03add2; - unsigned int vidw04add2; - unsigned int res8[7]; - - unsigned int vidintcon0; - unsigned int vidintcon1; - unsigned int res9[1]; - - unsigned int w1keycon0; - unsigned int w1keycon1; - unsigned int w2keycon0; - unsigned int w2keycon1; - unsigned int w3keycon0; - unsigned int w3keycon1; - unsigned int w4keycon0; - unsigned int w4keycon1; - - unsigned int w1keyalpha; - unsigned int w2keyalpha; - unsigned int w3keyalpha; - unsigned int w4keyalpha; - - unsigned int dithmode; - unsigned int res10[2]; - - unsigned int win0map; - unsigned int win1map; - unsigned int win2map; - unsigned int win3map; - unsigned int win4map; - unsigned int res11[1]; - - unsigned int wpalcon_h; - unsigned int wpalcon_l; - - unsigned int trigcon; - unsigned int res12[2]; - - unsigned int i80ifcona0; - unsigned int i80ifcona1; - unsigned int i80ifconb0; - unsigned int i80ifconb1; - - unsigned int colorgaincon; - unsigned int res13[2]; - - unsigned int ldi_cmdcon0; - unsigned int ldi_cmdcon1; - unsigned int res14[1]; - - /* To be updated */ - - unsigned char res15[156]; - unsigned int dualrgb; - unsigned char res16[16]; - unsigned int dp_mie_clkcon; -}; -#endif - -/* LCD IF register offset */ -#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0 -#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000 - -static inline unsigned int exynos_fimd_get_base_offset(void) -{ - if (cpu_is_exynos5()) - return EXYNOS5_LCD_IF_BASE_OFFSET; - else - return EXYNOS4_LCD_IF_BASE_OFFSET; -} - -/* - * Register offsets -*/ -#define EXYNOS_WINCON(x) (x * 0x04) -#define EXYNOS_VIDOSD(x) (x * 0x10) -#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08) -#define EXYNOS_BUFFER_SIZE(x) (x * 0x04) - -/* - * Bit Definitions -*/ - -/* VIDCON0 */ -#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30) -#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30) -#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29) -#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29) -#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29) -#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26) -#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26) -#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26) -#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26) -#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26) -#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26) -#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26) -#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26) -#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17) -#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17) -#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17) -#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17) -#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17) -#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17) -#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16) -#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16) -#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16) -#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) -#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5) -#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5) -#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5) -#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4) -#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4) -#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4) -#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2) -#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2) -#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2) -#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1) -#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1) -#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0) -#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0) - -/* VIDCON1 */ -#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) -#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7) -#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6) -#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6) -#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5) -#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5) -#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4) -#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4) - -/* VIDCON2 */ -#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23) -#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23) -#define EXYNOS_VIDCON2_EN601_MASK (1 << 23) -#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15) -#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15) -#define EXYNOS_VIDCON2_WB_MASK (1 << 15) -#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14) -#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14) -#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14) -#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12) -#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12) -#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12) -#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8) -#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8) -#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8) -#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7) -#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7) -#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7) - -/* PRTCON */ -#define EXYNOS_PRTCON_UPDATABLE (0 << 11) -#define EXYNOS_PRTCON_PROTECT (1 << 11) - -/* VIDTCON0 */ -#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) -#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) -#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) -#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) - -/* VIDTCON1 */ -#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) -#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16) -#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8) -#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0) - -/* VIDTCON2 */ -#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) -#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) -#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23) -#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22) - -/* Window 0~4 Control - WINCONx */ -#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22) -#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22) -#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22) -#define EXYNOS_WINCON_BUFSEL_0 (0 << 20) -#define EXYNOS_WINCON_BUFSEL_1 (1 << 20) -#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20) -#define EXYNOS_WINCON_BUFSEL_SHIFT (20) -#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19) -#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19) -#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19) -#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18) -#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18) -#define EXYNOS_WINCON_BITSWP_SHIFT (18) -#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17) -#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17) -#define EXYNOS_WINCON_BYTESWP_SHIFT (17) -#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16) -#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16) -#define EXYNOS_WINCON_HAWSWP_SHIFT (16) -#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15) -#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15) -#define EXYNOS_WINCON_WSWP_SHIFT (15) -#define EXYNOS_WINCON_INRGB_RGB (0 << 13) -#define EXYNOS_WINCON_INRGB_YUV (1 << 13) -#define EXYNOS_WINCON_INRGB_MASK (1 << 13) -#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9) -#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9) -#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9) -#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9) -#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7) -#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7) -#define EXYNOS_WINCON_BLD_PLANE (0 << 6) -#define EXYNOS_WINCON_BLD_PIXEL (1 << 6) -#define EXYNOS_WINCON_BLD_MASK (1 << 6) -#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2) -#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2) -#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2) -#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2) -#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2) -#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2) -#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2) -#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2) -#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2) -#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2) -#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2) -#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2) -#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2) -#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2) -#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2) -#define EXYNOS_WINCON_BPPMODE_SHIFT (2) -#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1) -#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1) -#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1) -#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0) -#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0) - -/* WINCON1 special */ -#define EXYNOS_WINCON1_VP_DISABLE (0 << 24) -#define EXYNOS_WINCON1_VP_ENABLE (1 << 24) -#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23) -#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23) -#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23) - -/* WINSHMAP */ -#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10) -#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x)) -#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x)) -#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x)) -#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x)) - -/* VIDOSDxA, VIDOSDxB */ -#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11) -#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) -#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) -#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) -#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23) -#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22) - -/* VIDOSD0C, VIDOSDxD */ -#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) - -/* VIDOSDxC (1~4) */ -#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20) -#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16) -#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12) -#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8) -#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4) -#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0) -#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12) -#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0) - -/* Start Address */ -#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24) -#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0) - -/* End Address */ -#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0) - -/* Buffer Size */ -#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) -#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) -#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27) -#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26) - -/* WIN Color Map */ -#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff) - -/* VIDINTCON0 */ -#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) -#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) -#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) -#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) -#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) -#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) -#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15) -#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) -#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) -#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) -#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15) -#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13) -#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13) -#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) -#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) -#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) -#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) -#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) -#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) -#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) -#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2) -#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1) -#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1) -#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0) -#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0) -#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0) - -/* VIDINTCON1 */ -#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5) -#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2) -#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1) -#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0) - -/* WINMAP */ -#define EXYNOS_WINMAP_ENABLE (1 << 24) - -/* WxKEYCON0 (1~4) */ -#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26) -#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26) -#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25) -#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25) -#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24) -#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24) -#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) - -/* WxKEYCON1 (1~4) */ -#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0) - -/* DUALRGB */ -#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0) -#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0) -#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0) -#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0) -#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2) -#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2) -#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4) -#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16) -#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16) -#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18) - -/* I80IFCONA0 and I80IFCONA1 */ -#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16) -#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12) -#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8) -#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4) -#define EXYNOS_RSPOL_LOW (0 << 2) -#define EXYNOS_RSPOL_HIGH (1 << 2) -#define EXYNOS_I80IFEN_DISABLE (0 << 0) -#define EXYNOS_I80IFEN_ENABLE (1 << 0) - -/* TRIGCON */ -#define EXYNOS_I80SOFT_TRIG_EN (1 << 0) -#define EXYNOS_I80START_TRIG (1 << 1) -#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2) - -/* DP_MIE_CLKCON */ -#define EXYNOS_DP_MIE_DISABLE (0 << 0) -#define EXYNOS_DP_CLK_ENABLE (1 << 1) -#define EXYNOS_MIE_CLK_ENABLE (3 << 0) - -#endif /* _REGS_FB_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/gpio.h deleted file mode 100644 index d6868fa25..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/gpio.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ -struct s5p_gpio_bank { - unsigned int con; - unsigned int dat; - unsigned int pull; - unsigned int drv; - unsigned int pdn_con; - unsigned int pdn_pull; - unsigned char res1[8]; -}; - -struct exynos4_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank e2; - struct s5p_gpio_bank e3; - struct s5p_gpio_bank e4; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; -}; - -struct exynos4_gpio_part2 { - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; - -struct exynos4_gpio_part3 { - struct s5p_gpio_bank z; -}; - -struct exynos4x12_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank res1[0x5]; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank res2[0x2]; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; -}; - -struct exynos4x12_gpio_part2 { - struct s5p_gpio_bank res1[0x2]; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res2[0x3]; - struct s5p_gpio_bank m0; - struct s5p_gpio_bank m1; - struct s5p_gpio_bank m2; - struct s5p_gpio_bank m3; - struct s5p_gpio_bank m4; - struct s5p_gpio_bank res3[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; - -struct exynos4x12_gpio_part3 { - struct s5p_gpio_bank z; -}; - -struct exynos4x12_gpio_part4 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; -}; - -struct exynos5420_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank b4; - struct s5p_gpio_bank h0; -}; - -struct exynos5420_gpio_part2 { - struct s5p_gpio_bank y7; /* 0x1340_0000 */ - struct s5p_gpio_bank res[0x5f]; /* */ - struct s5p_gpio_bank x0; /* 0x1340_0C00 */ - struct s5p_gpio_bank x1; /* 0x1340_0C20 */ - struct s5p_gpio_bank x2; /* 0x1340_0C40 */ - struct s5p_gpio_bank x3; /* 0x1340_0C60 */ -}; - -struct exynos5420_gpio_part3 { - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; -}; - -struct exynos5420_gpio_part4 { - struct s5p_gpio_bank e0; /* 0x1400_0000 */ - struct s5p_gpio_bank e1; /* 0x1400_0020 */ - struct s5p_gpio_bank f0; /* 0x1400_0040 */ - struct s5p_gpio_bank f1; /* 0x1400_0060 */ - struct s5p_gpio_bank g0; /* 0x1400_0080 */ - struct s5p_gpio_bank g1; /* 0x1400_00A0 */ - struct s5p_gpio_bank g2; /* 0x1400_00C0 */ - struct s5p_gpio_bank j4; /* 0x1400_00E0 */ -}; - -struct exynos5420_gpio_part5 { - struct s5p_gpio_bank z0; /* 0x0386_0000 */ -}; - -struct exynos5_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x3]; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank res2[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; - -struct exynos5_gpio_part2 { - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; -}; - -struct exynos5_gpio_part3 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; -}; - -struct exynos5_gpio_part4 { - struct s5p_gpio_bank z; -}; - -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) - -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) - -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) - -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) - -#define EXYNOS4_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4_gpio_part##part *) \ - EXYNOS4_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \ - EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4X12_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS5_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS5420_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5420_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define exynos4_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos4x12_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4X12_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos5420_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5420_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos5_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -static inline unsigned int s5p_gpio_base(int gpio) -{ - unsigned gpio_part = S5P_GPIO_GET_PART(gpio); - - switch (gpio_part) { - case 1: - return samsung_get_base_gpio_part1(); - case 2: - return samsung_get_base_gpio_part2(); - case 3: - return samsung_get_base_gpio_part3(); - case 4: - return samsung_get_base_gpio_part4(); - default: - return 0; - } -} -#endif - -/* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) - -/* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x3 - -/* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/i2s-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/i2s-regs.h deleted file mode 100644 index 4a4a7a00b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/i2s-regs.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * R. Chandrasekar <rcsekar@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __I2S_REGS_H__ -#define __I2S_REGS_H__ - -#define CON_RESET (1 << 31) -#define CON_TXFIFO_FULL (1 << 8) -#define CON_TXCH_PAUSE (1 << 4) -#define CON_ACTIVE (1 << 0) - -#define MOD_OP_CLK (3 << 30) -#define MOD_BLCP_SHIFT 24 -#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) -#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) -#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) -#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) - -#define MOD_BLC_16BIT (0 << 13) -#define MOD_BLC_8BIT (1 << 13) -#define MOD_BLC_24BIT (2 << 13) -#define MOD_BLC_MASK (3 << 13) - -#define MOD_SLAVE (1 << 11) -#define MOD_RCLKSRC (0 << 10) -#define MOD_MASK (3 << 8) -#define MOD_LR_LLOW (0 << 7) -#define MOD_LR_RLOW (1 << 7) -#define MOD_SDF_IIS (0 << 5) -#define MOD_SDF_MSB (1 << 5) -#define MOD_SDF_LSB (2 << 5) -#define MOD_SDF_MASK (3 << 5) -#define MOD_RCLK_256FS (0 << 3) -#define MOD_RCLK_512FS (1 << 3) -#define MOD_RCLK_384FS (2 << 3) -#define MOD_RCLK_768FS (3 << 3) -#define MOD_RCLK_MASK (3 << 3) -#define MOD_BCLK_32FS (0 << 1) -#define MOD_BCLK_48FS (1 << 1) -#define MOD_BCLK_16FS (2 << 1) -#define MOD_BCLK_24FS (3 << 1) -#define MOD_BCLK_MASK (3 << 1) - -#define MOD_CDCLKCON (1 << 12) - -#define FIC_TXFLUSH (1 << 15) -#define FIC_RXFLUSH (1 << 7) - -#define PSREN (1 << 15) -#define PSVAL (3 << 8) - -#endif /* __I2S_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mipi_dsim.h deleted file mode 100644 index 50e5c258a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mipi_dsim.h +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: InKi Dae <inki.dae@samsung.com> - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DSIM_H -#define _DSIM_H - -#include <linux/list.h> -#include <linux/fb.h> -#include <lcd.h> - -#define PANEL_NAME_SIZE (32) - -enum mipi_dsim_interface_type { - DSIM_COMMAND, - DSIM_VIDEO -}; - -enum mipi_dsim_virtual_ch_no { - DSIM_VIRTUAL_CH_0, - DSIM_VIRTUAL_CH_1, - DSIM_VIRTUAL_CH_2, - DSIM_VIRTUAL_CH_3 -}; - -enum mipi_dsim_burst_mode_type { - DSIM_NON_BURST_SYNC_EVENT, - DSIM_BURST_SYNC_EVENT, - DSIM_NON_BURST_SYNC_PULSE, - DSIM_BURST, - DSIM_NON_VIDEO_MODE -}; - -enum mipi_dsim_no_of_data_lane { - DSIM_DATA_LANE_1, - DSIM_DATA_LANE_2, - DSIM_DATA_LANE_3, - DSIM_DATA_LANE_4 -}; - -enum mipi_dsim_byte_clk_src { - DSIM_PLL_OUT_DIV8, - DSIM_EXT_CLK_DIV8, - DSIM_EXT_CLK_BYPASS -}; - -enum mipi_dsim_pixel_format { - DSIM_CMD_3BPP, - DSIM_CMD_8BPP, - DSIM_CMD_12BPP, - DSIM_CMD_16BPP, - DSIM_VID_16BPP_565, - DSIM_VID_18BPP_666PACKED, - DSIM_18BPP_666LOOSELYPACKED, - DSIM_24BPP_888 -}; - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* - * struct mipi_dsim_config - interface for configuring mipi-dsi controller. - * - * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse. - * @eot_disable: enable or disable EoT packet in HS mode. - * @auto_vertical_cnt: specifies auto vertical count mode. - * in Video mode, the vertical line transition uses line counter - * configured by VSA, VBP, and Vertical resolution. - * If this bit is set to '1', the line counter does not use VSA and VBP - * registers.(in command mode, this variable is ignored) - * @hse: set horizontal sync event mode. - * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC - * start packet to MIPI DSI slave at MIPI DSI spec1.1r02. - * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area - * (in mommand mode, this variable is ignored) - * @hfp: specifies HFP disable mode. - * if this variable is set, DSI master ignores HFP area in VIDEO mode. - * (in command mode, this variable is ignored) - * @hbp: specifies HBP disable mode. - * if this variable is set, DSI master ignores HBP area in VIDEO mode. - * (in command mode, this variable is ignored) - * @hsa: specifies HSA disable mode. - * if this variable is set, DSI master ignores HSA area in VIDEO mode. - * (in command mode, this variable is ignored) - * @e_interface: specifies interface to be used.(CPU or RGB interface) - * @e_virtual_ch: specifies virtual channel number that main or - * sub diaplsy uses. - * @e_pixel_format: specifies pixel stream format for main or sub display. - * @e_burst_mode: selects Burst mode in Video mode. - * in Non-burst mode, RGB data area is filled with RGB data and NULL - * packets, according to input bandwidth of RGB interface. - * In Burst mode, RGB data area is filled with RGB data only. - * @e_no_data_lane: specifies data lane count to be used by Master. - * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8) - * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. - * @pll_stable_time: specifies the PLL Timer for stability of the ganerated - * clock(System clock cycle base) - * if the timer value goes to 0x00000000, the clock stable bit of status - * and interrupt register is set. - * @esc_clk: specifies escape clock frequency for getting the escape clock - * prescaler value. - * @stop_holding_cnt: specifies the interval value between transmitting - * read packet(or write "set_tear_on" command) and BTA request. - * after transmitting read packet or write "set_tear_on" command, - * BTA requests to D-PHY automatically. this counter value specifies - * the interval between them. - * @bta_timeout: specifies the timer for BTA. - * this register specifies time out from BTA request to change - * the direction with respect to Tx escape clock. - * @rx_timeout: specifies the timer for LP Rx mode timeout. - * this register specifies time out on how long RxValid deasserts, - * after RxLpdt asserts with respect to Tx escape clock. - * - RxValid specifies Rx data valid indicator. - * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode. - * - RxValid and RxLpdt specifies signal from D-PHY. - */ -struct mipi_dsim_config { - unsigned char auto_flush; - unsigned char eot_disable; - - unsigned char auto_vertical_cnt; - unsigned char hse; - unsigned char hfp; - unsigned char hbp; - unsigned char hsa; - - enum mipi_dsim_interface_type e_interface; - enum mipi_dsim_virtual_ch_no e_virtual_ch; - enum mipi_dsim_pixel_format e_pixel_format; - enum mipi_dsim_burst_mode_type e_burst_mode; - enum mipi_dsim_no_of_data_lane e_no_data_lane; - enum mipi_dsim_byte_clk_src e_byte_clk; - - /* - * =========================================== - * | P | M | S | MHz | - * ------------------------------------------- - * | 3 | 100 | 3 | 100 | - * | 3 | 100 | 2 | 200 | - * | 3 | 63 | 1 | 252 | - * | 4 | 100 | 1 | 300 | - * | 4 | 110 | 1 | 330 | - * | 12 | 350 | 1 | 350 | - * | 3 | 100 | 1 | 400 | - * | 4 | 150 | 1 | 450 | - * | 6 | 118 | 1 | 472 | - * | 3 | 120 | 1 | 480 | - * | 12 | 250 | 0 | 500 | - * | 4 | 100 | 0 | 600 | - * | 3 | 81 | 0 | 648 | - * | 3 | 88 | 0 | 704 | - * | 3 | 90 | 0 | 720 | - * | 3 | 100 | 0 | 800 | - * | 12 | 425 | 0 | 850 | - * | 4 | 150 | 0 | 900 | - * | 12 | 475 | 0 | 950 | - * | 6 | 250 | 0 | 1000 | - * ------------------------------------------- - */ - - /* - * pms could be calculated as the following. - * M * 24 / P * 2 ^ S = MHz - */ - unsigned char p; - unsigned short m; - unsigned char s; - - unsigned int pll_stable_time; - unsigned long esc_clk; - - unsigned short stop_holding_cnt; - unsigned char bta_timeout; - unsigned short rx_timeout; -}; - -/* - * struct mipi_dsim_device - global interface for mipi-dsi driver. - * - * @dsim_config: infomation for configuring mipi-dsi controller. - * @master_ops: callbacks to mipi-dsi operations. - * @dsim_lcd_dev: pointer to activated ddi device. - * (it would be registered by mipi-dsi driver.) - * @dsim_lcd_drv: pointer to activated_ddi driver. - * (it would be registered by mipi-dsi driver.) - * @state: specifies status of MIPI-DSI controller. - * the status could be RESET, INIT, STOP, HSCLKEN and ULPS. - * @data_lane: specifiec enabled data lane number. - * this variable would be set by driver according to e_no_data_lane - * automatically. - * @e_clk_src: select byte clock source. - * @pd: pointer to MIPI-DSI driver platform data. - */ -struct mipi_dsim_device { - struct mipi_dsim_config *dsim_config; - struct mipi_dsim_master_ops *master_ops; - struct mipi_dsim_lcd_device *dsim_lcd_dev; - struct mipi_dsim_lcd_driver *dsim_lcd_drv; - - unsigned int state; - unsigned int data_lane; - enum mipi_dsim_byte_clk_src e_clk_src; - - struct exynos_platform_mipi_dsim *pd; -}; - -/* - * struct exynos_platform_mipi_dsim - interface to platform data - * for mipi-dsi driver. - * - * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver. - * lcd panel driver searched would be actived. - * @dsim_config: pointer of structure for configuring mipi-dsi controller. - * @lcd_panel_info: pointer for lcd panel specific structure. - * this structure specifies width, height, timing and polarity and so on. - * @lcd_power: callback pointer for enabling or disabling lcd power. - * @mipi_power: callback pointer for enabling or disabling mipi power. - * @phy_enable: pointer to a callback controlling D-PHY enable/reset - */ -struct exynos_platform_mipi_dsim { - char lcd_panel_name[PANEL_NAME_SIZE]; - - struct mipi_dsim_config *dsim_config; - void *lcd_panel_info; - - int (*lcd_power)(void); - int (*mipi_power)(void); - void (*phy_enable)(unsigned int dev_index, unsigned int enable); -}; - -/* - * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations. - * - * @cmd_write: transfer command to lcd panel at LP mode. - * @cmd_read: read command from rx register. - * @get_dsim_frame_done: get the status that all screen data have been - * transferred to mipi-dsi. - * @clear_dsim_frame_done: clear frame done status. - * @get_fb_frame_done: get frame done status of display controller. - * @trigger: trigger display controller. - * - this one would be used only in case of CPU mode. - */ -struct mipi_dsim_master_ops { - int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id, - const unsigned char *data0, unsigned int data1); - int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int data1); - int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim); - int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim); - - int (*get_fb_frame_done)(void); - void (*trigger)(struct fb_info *info); -}; - -/* - * device structure for mipi-dsi based lcd panel. - * - * @name: name of the device to use with this device, or an - * alias for that name. - * @id: id of device to be registered. - * @bus_id: bus id for identifing connected bus - * and this bus id should be same as id of mipi_dsim_device. - * @master: pointer to mipi-dsi master device object. - * @platform_data: lcd panel specific platform data. - */ -struct mipi_dsim_lcd_device { - char *name; - int id; - int bus_id; - int reverse_panel; - - struct mipi_dsim_device *master; - void *platform_data; -}; - -/* - * driver structure for mipi-dsi based lcd panel. - * - * this structure should be registered by lcd panel driver. - * mipi-dsi driver seeks lcd panel registered through name field - * and calls these callback functions in appropriate time. - * - * @name: name of the driver to use with this device, or an - * alias for that name. - * @id: id of driver to be registered. - * this id would be used for finding device object registered. - * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi - * dsi interface. - * @mipi_display_on: callback pointer for lcd panel display on. - */ -struct mipi_dsim_lcd_driver { - char *name; - int id; - - int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev); - void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev); -}; - -#ifdef CONFIG_EXYNOS_MIPI_DSIM -int exynos_mipi_dsi_init(void); -#else -static inline int exynos_mipi_dsi_init(void) -{ - return 0; -} -#endif - -/* - * register mipi_dsim_lcd_driver object defined by lcd panel driver - * to mipi-dsi driver. - */ -int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver - *lcd_drv); - -/* - * register mipi_dsim_lcd_device to mipi-dsi master. - */ -int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device - *lcd_dev); - -void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); -void exynos_init_dsim_platform_data(vidinfo_t *vid); - -/* panel driver init based on mipi dsi interface */ -void s6e8ax0_init(void); - -#ifdef CONFIG_OF_CONTROL -extern int mipi_power(void); -#endif -#endif /* _DSIM_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mmc.h deleted file mode 100644 index 0fb6461c0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mmc.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MMC_H_ -#define __ASM_ARCH_MMC_H_ - -#define S5P_MMC_DEV_OFFSET 0x10000 - -#define SDHCI_CONTROL2 0x80 -#define SDHCI_CONTROL3 0x84 -#define SDHCI_CONTROL4 0x8C - -#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define SDHCI_CTRL2_SLCARDOUT (1 << 28) - -#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) -#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) -#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) - -#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) -#define SDHCI_CTRL2_LVLDAT_SHIFT (16) -#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) - -#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define SDHCI_CTRL2_SDCDSEL (1 << 13) -#define SDHCI_CTRL2_SDSIGPC (1 << 12) -#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) - -#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) -#define SDHCI_CTRL2_DFCNT_SHIFT (9) - -#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define SDHCI_CTRL2_RWAITMODE (1 << 7) -#define SDHCI_CTRL2_DISBUFRD (1 << 6) -#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) -#define SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define SDHCI_CTRL2_PWRSYNC (1 << 3) -#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define SDHCI_CTRL3_FCSEL3 (1 << 31) -#define SDHCI_CTRL3_FCSEL2 (1 << 23) -#define SDHCI_CTRL3_FCSEL1 (1 << 15) -#define SDHCI_CTRL3_FCSEL0 (1 << 7) - -#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) -#define SDHCI_CTRL4_DRIVE_SHIFT (16) - -#define SDHCI_MAX_HOSTS 4 - -int s5p_sdhci_init(u32 regbase, int index, int bus_width); - -static inline int s5p_mmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + - (S5P_MMC_DEV_OFFSET * index); - - return s5p_sdhci_init(base, index, bus_width); -} - -#ifdef CONFIG_OF_CONTROL -int exynos_mmc_init(const void *blob); -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/periph.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/periph.h deleted file mode 100644 index 5c1c3d4a9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/periph.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - PERIPH_ID_UART0 = 51, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_I2C0 = 56, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_SPI0 = 68, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_SDMMC0 = 75, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC2, - PERIPH_ID_SDMMC3, - PERIPH_ID_I2C8 = 87, - PERIPH_ID_I2C9, - PERIPH_ID_I2S0 = 98, - PERIPH_ID_I2S1 = 99, - - /* Since following peripherals do - * not have shared peripheral interrupts (SPIs) - * they are numbered arbitiraly after the maximum - * SPIs Exynos has (128) - */ - PERIPH_ID_SROMC = 128, - PERIPH_ID_SPI3, - PERIPH_ID_SPI4, - PERIPH_ID_SDMMC4, - PERIPH_ID_PWM0, - PERIPH_ID_PWM1, - PERIPH_ID_PWM2, - PERIPH_ID_PWM3, - PERIPH_ID_PWM4, - PERIPH_ID_I2C10 = 203, - - PERIPH_ID_NONE = -1, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pinmux.h deleted file mode 100644 index 0b91ef658..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pinmux.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Abhilash Kesavan <a.kesavan@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PINMUX_H -#define __ASM_ARM_ARCH_PINMUX_H - -#include "periph.h" - -/* - * Flags for setting specific configarations of peripherals. - * List will grow with support for more devices getting added. - */ -enum { - PINMUX_FLAG_NONE = 0x00000000, - - /* Flags for eMMC */ - PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ - - /* Flags for SROM controller */ - PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ - PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ -}; - -/** - * Configures the pinmux for a particular peripheral. - * - * Each gpio can be configured in many different ways (4 bits on exynos) - * such as "input", "output", "special function", "external interrupt" - * etc. This function will configure the peripheral pinmux along with - * pull-up/down and drive strength. - * - * @param peripheral peripheral to be configured - * @param flags configure flags - * @return 0 if ok, -1 on error (e.g. unsupported peripheral) - */ -int exynos_pinmux_config(int peripheral, int flags); - -/** - * Decode the peripheral id using the interrpt numbers. - * - * @param blob Device tree blob - * @param node FDT I2C node to find - * @return peripheral id if ok, PERIPH_ID_NONE on error - */ -int pinmux_decode_periph_id(const void *blob, int node); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/power.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/power.h deleted file mode 100644 index c9609a23f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/power.h +++ /dev/null @@ -1,1729 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_POWER_H_ -#define __ASM_ARM_ARCH_POWER_H_ - -#ifndef __ASSEMBLY__ -struct exynos4_power { - unsigned int om_stat; - unsigned char res1[0x8]; - unsigned int rtc_clko_sel; - unsigned int gnss_rtc_out_ctrl; - unsigned char res2[0x1ec]; - unsigned int system_power_down_ctrl; - unsigned int res3; - unsigned int system_power_down_option; - unsigned char res4[0x1f4]; - unsigned int swreset; - unsigned int rst_stat; - unsigned char res5[0x1f8]; - unsigned int wakeup_stat; - unsigned int eint_wakeup_mask; - unsigned int wakeup_mask; - unsigned char res6[0xf4]; - unsigned int hdmi_phy_control; - unsigned int usbdevice_phy_control; - unsigned int usbhost_phy_control; - unsigned int dac_phy_control; - unsigned int mipi_phy0_control; - unsigned int mipi_phy1_control; - unsigned int adc_phy_control; - unsigned int pcie_phy_control; - unsigned int sata_phy_control; - unsigned char res7[0xdc]; - unsigned int inform0; - unsigned int inform1; - unsigned int inform2; - unsigned int inform3; - unsigned int inform4; - unsigned int inform5; - unsigned int inform6; - unsigned int inform7; - unsigned char res8[0x1e0]; - unsigned int pmu_debug; - unsigned char res9[0x5fc]; - unsigned int arm_core0_sys_pwr_reg; - unsigned char res10[0xc]; - unsigned int arm_core1_sys_pwr_reg; - unsigned char res11[0x6c]; - unsigned int arm_common_sys_pwr_reg; - unsigned char res12[0x3c]; - unsigned int arm_cpu_l2_0_sys_pwr_reg; - unsigned int arm_cpu_l2_1_sys_pwr_reg; - unsigned char res13[0x38]; - unsigned int cmu_aclkstop_sys_pwr_reg; - unsigned int cmu_sclkstop_sys_pwr_reg; - unsigned char res14[0x4]; - unsigned int cmu_reset_sys_pwr_reg; - unsigned char res15[0x10]; - unsigned int apll_sysclk_sys_pwr_reg; - unsigned int mpll_sysclk_sys_pwr_reg; - unsigned int vpll_sysclk_sys_pwr_reg; - unsigned int epll_sysclk_sys_pwr_reg; - unsigned char res16[0x8]; - unsigned int cmu_clkstop_gps_alive_sys_pwr_reg; - unsigned int cmu_reset_gps_alive_sys_pwr_reg; - unsigned int cmu_clkstop_cam_sys_pwr_reg; - unsigned int cmu_clkstop_tv_sys_pwr_reg; - unsigned int cmu_clkstop_mfc_sys_pwr_reg; - unsigned int cmu_clkstop_g3d_sys_pwr_reg; - unsigned int cmu_clkstop_lcd0_sys_pwr_reg; - unsigned int cmu_clkstop_lcd1_sys_pwr_reg; - unsigned int cmu_clkstop_maudio_sys_pwr_reg; - unsigned int cmu_clkstop_gps_sys_pwr_reg; - unsigned int cmu_reset_cam_sys_pwr_reg; - unsigned int cmu_reset_tv_sys_pwr_reg; - unsigned int cmu_reset_mfc_sys_pwr_reg; - unsigned int cmu_reset_g3d_sys_pwr_reg; - unsigned int cmu_reset_lcd0_sys_pwr_reg; - unsigned int cmu_reset_lcd1_sys_pwr_reg; - unsigned int cmu_reset_maudio_sys_pwr_reg; - unsigned int cmu_reset_gps_sys_pwr_reg; - unsigned int top_bus_sys_pwr_reg; - unsigned int top_retention_sys_pwr_reg; - unsigned int top_pwr_sys_pwr_reg; - unsigned char res17[0x1c]; - unsigned int logic_reset_sys_pwr_reg; - unsigned char res18[0x14]; - unsigned int onenandxl_mem_sys_pwr_reg; - unsigned int modemif_mem_sys_pwr_reg; - unsigned char res19[0x4]; - unsigned int usbdevice_mem_sys_pwr_reg; - unsigned int sdmmc_mem_sys_pwr_reg; - unsigned int cssys_mem_sys_pwr_reg; - unsigned int secss_mem_sys_pwr_reg; - unsigned char res20[0x4]; - unsigned int pcie_mem_sys_pwr_reg; - unsigned int sata_mem_sys_pwr_reg; - unsigned char res21[0x18]; - unsigned int pad_retention_dram_sys_pwr_reg; - unsigned int pad_retention_maudio_sys_pwr_reg; - unsigned char res22[0x18]; - unsigned int pad_retention_gpio_sys_pwr_reg; - unsigned int pad_retention_uart_sys_pwr_reg; - unsigned int pad_retention_mmca_sys_pwr_reg; - unsigned int pad_retention_mmcb_sys_pwr_reg; - unsigned int pad_retention_ebia_sys_pwr_reg; - unsigned int pad_retention_ebib_sys_pwr_reg; - unsigned char res23[0x8]; - unsigned int pad_isolation_sys_pwr_reg; - unsigned char res24[0x1c]; - unsigned int pad_alv_sel_sys_pwr_reg; - unsigned char res25[0x1c]; - unsigned int xusbxti_sys_pwr_reg; - unsigned int xxti_sys_pwr_reg; - unsigned char res26[0x38]; - unsigned int ext_regulator_sys_pwr_reg; - unsigned char res27[0x3c]; - unsigned int gpio_mode_sys_pwr_reg; - unsigned char res28[0x3c]; - unsigned int gpio_mode_maudio_sys_pwr_reg; - unsigned char res29[0x3c]; - unsigned int cam_sys_pwr_reg; - unsigned int tv_sys_pwr_reg; - unsigned int mfc_sys_pwr_reg; - unsigned int g3d_sys_pwr_reg; - unsigned int lcd0_sys_pwr_reg; - unsigned int lcd1_sys_pwr_reg; - unsigned int maudio_sys_pwr_reg; - unsigned int gps_sys_pwr_reg; - unsigned int gps_alive_sys_pwr_reg; - unsigned char res30[0xc5c]; - unsigned int arm_core0_configuration; - unsigned int arm_core0_status; - unsigned int arm_core0_option; - unsigned char res31[0x74]; - unsigned int arm_core1_configuration; - unsigned int arm_core1_status; - unsigned int arm_core1_option; - unsigned char res32[0x37c]; - unsigned int arm_common_option; - unsigned char res33[0x1f4]; - unsigned int arm_cpu_l2_0_configuration; - unsigned int arm_cpu_l2_0_status; - unsigned char res34[0x18]; - unsigned int arm_cpu_l2_1_configuration; - unsigned int arm_cpu_l2_1_status; - unsigned char res35[0xa00]; - unsigned int pad_retention_maudio_option; - unsigned char res36[0xdc]; - unsigned int pad_retention_gpio_option; - unsigned char res37[0x1c]; - unsigned int pad_retention_uart_option; - unsigned char res38[0x1c]; - unsigned int pad_retention_mmca_option; - unsigned char res39[0x1c]; - unsigned int pad_retention_mmcb_option; - unsigned char res40[0x1c]; - unsigned int pad_retention_ebia_option; - unsigned char res41[0x1c]; - unsigned int pad_retention_ebib_option; - unsigned char res42[0x160]; - unsigned int ps_hold_control; - unsigned char res43[0xf0]; - unsigned int xusbxti_configuration; - unsigned int xusbxti_status; - unsigned char res44[0x14]; - unsigned int xusbxti_duration; - unsigned int xxti_configuration; - unsigned int xxti_status; - unsigned char res45[0x14]; - unsigned int xxti_duration; - unsigned char res46[0x1dc]; - unsigned int ext_regulator_duration; - unsigned char res47[0x5e0]; - unsigned int cam_configuration; - unsigned int cam_status; - unsigned int cam_option; - unsigned char res48[0x14]; - unsigned int tv_configuration; - unsigned int tv_status; - unsigned int tv_option; - unsigned char res49[0x14]; - unsigned int mfc_configuration; - unsigned int mfc_status; - unsigned int mfc_option; - unsigned char res50[0x14]; - unsigned int g3d_configuration; - unsigned int g3d_status; - unsigned int g3d_option; - unsigned char res51[0x14]; - unsigned int lcd0_configuration; - unsigned int lcd0_status; - unsigned int lcd0_option; - unsigned char res52[0x14]; - unsigned int lcd1_configuration; - unsigned int lcd1_status; - unsigned int lcd1_option; - unsigned char res53[0x34]; - unsigned int gps_configuration; - unsigned int gps_status; - unsigned int gps_option; - unsigned char res54[0x14]; - unsigned int gps_alive_configuration; - unsigned int gps_alive_status; - unsigned int gps_alive_option; -}; - -struct exynos5_power { - unsigned int om_stat; - unsigned char res1[0x18]; - unsigned int rtc_clko_sel; - unsigned int gnss_rtc_out_ctrl; - unsigned char res2[0x1dc]; - unsigned int central_seq_configuration; - unsigned int central_seq_status; - unsigned int central_seq_option; - unsigned char res3[0x14]; - unsigned int seq_transition0; - unsigned int seq_transition1; - unsigned int seq_transition2; - unsigned int seq_transition3; - unsigned int seq_transition4; - unsigned int seq_transition5; - unsigned int seq_transition6; - unsigned int seq_transition7; - unsigned int central_seq_dmc_configuration; - unsigned int central_seq_dmc_status; - unsigned int central_seq_dmc_option; - unsigned char res4[0x14]; - unsigned int seq_dmc_transition0; - unsigned int seq_dmc_transition1; - unsigned int seq_dmc_transition2; - unsigned int seq_dmc_transition3; - unsigned int seq_dmc_transition4; - unsigned int seq_dmc_transition5; - unsigned int seq_dmc_transition6; - unsigned int seq_dmc_transition7; - unsigned char res5[0x180]; - unsigned int swreset; - unsigned int rst_stat; - unsigned int automatic_wdt_reset_disable; - unsigned int mask_wdt_reset_request; - unsigned int mask_wreset_request; - unsigned char res6[0xec]; - unsigned int reset_sequencer_configuration; - unsigned int reset_sequencer_status; - unsigned int reset_sequencer_option; - unsigned char res7[0xf4]; - unsigned int wakeup_stat; - unsigned int eint_wakeup_mask; - unsigned int wakeup_mask; - unsigned int wakeup_interrupt; - unsigned char res8[0x10]; - unsigned int wakeup_stat_dmc; - unsigned int eint_wakeup_mask_dmc; - unsigned int wakeup_mask_dmc; - unsigned int wakeup_interrupt_dmc; - unsigned char res9[0xd0]; - unsigned int hdmi_phy_control; - unsigned int usbdrd_phy_control; - unsigned int usbhost_phy_control; - unsigned int efnand_phy_control; - unsigned int mipi_phy0_control; - unsigned int mipi_phy1_control; - unsigned int adc_phy_control; - unsigned int mtcadc_phy_control; - unsigned int dptx_phy_control; - unsigned int sata_phy_control; - unsigned char res10[0xd8]; - unsigned int inform0; - unsigned int inform1; - unsigned int inform2; - unsigned int inform3; - unsigned int sysip_dat0; - unsigned int sysip_dat1; - unsigned int sysip_dat2; - unsigned int sysip_dat3; - unsigned char res11[0xe0]; - unsigned int pmu_spare0; - unsigned int pmu_spare1; - unsigned int pmu_spare2; - unsigned int pmu_spare3; - unsigned char res12[0x70]; - unsigned int irom_data_reg0; - unsigned int irom_data_reg1; - unsigned int irom_data_reg2; - unsigned int irom_data_reg3; - unsigned char res13[0x70]; - unsigned int pmu_debug; - unsigned char res14[0x5fc]; - unsigned int arm_core0_sys_pwr_reg; - unsigned int dis_irq_arm_core0_local_sys_pwr_reg; - unsigned int dis_irq_arm_core0_central_sys_pwr_reg; - unsigned char res15[0x4]; - unsigned int arm_core1_sys_pwr_reg; - unsigned int dis_irq_arm_core1_local_sys_pwr_reg; - unsigned int dis_irq_arm_core1_central_sys_pwr_reg; - unsigned char res16[0x24]; - unsigned int fsys_arm_sys_pwr_reg; - unsigned int dis_irq_fsys_arm_local_sys_pwr_reg; - unsigned int dis_irq_fsys_arm_central_sys_pwr_reg; - unsigned char res17[0x4]; - unsigned int isp_arm_sys_pwr_reg; - unsigned int dis_irq_isp_arm_local_sys_pwr_reg; - unsigned int dis_irq_isp_arm_central_sys_pwr_reg; - unsigned char res18[0x24]; - unsigned int arm_common_sys_pwr_reg; - unsigned char res19[0x3c]; - unsigned int arm_l2_sys_pwr_reg; - unsigned char res20[0x3c]; - unsigned int cmu_aclkstop_sys_pwr_reg; - unsigned int cmu_sclkstop_sys_pwr_reg; - unsigned char res21[0x4]; - unsigned int cmu_reset_sys_pwr_reg; - unsigned char res22[0x10]; - unsigned int cmu_aclkstop_dmc_sys_pwr_reg; - unsigned int cmu_sclkstop_dmc_sys_pwr_reg; - unsigned char res23[0x4]; - unsigned int cmu_reset_dmc_sys_pwr_reg; - unsigned char res24[0x8]; - unsigned int ddrphy_dlllock_sys_pwr_reg; - unsigned char res25[0x4]; - unsigned int apll_sysclk_sys_pwr_reg; - unsigned int mpll_sysclk_sys_pwr_reg; - unsigned int vpll_sysclk_sys_pwr_reg; - unsigned int epll_sysclk_sys_pwr_reg; - unsigned int bpll_sysclk_sys_pwr_reg; - unsigned int cpll_sysclk_sys_pwr_reg; - unsigned int gpll_sysclk_sys_pwr_reg; - unsigned char res26[0x8]; - unsigned int mplluser_sysclk_sys_pwr_reg; - unsigned char res27[0x8]; - unsigned int bplluser_sysclk_sys_pwr_reg; - unsigned char res28[0xc]; - unsigned int top_bus_sys_pwr_reg; - unsigned int top_retention_sys_pwr_reg; - unsigned int top_pwr_sys_pwr_reg; - unsigned char res29[0x4]; - unsigned int top_bus_dmc_sys_pwr_reg; - unsigned int top_retention_dmc_sys_pwr_reg; - unsigned int top_pwr_dmc_sys_pwr_reg; - unsigned char res30[0x4]; - unsigned int logic_reset_sys_pwr_reg; - unsigned int oscclk_gate_sys_pwr_reg; - unsigned char res31[0x8]; - unsigned int logic_reset_dmc_sys_pwr_reg; - unsigned int oscclk_gate_dmc_sys_pwr_reg; - unsigned char res32[0x8]; - unsigned int usbotg_mem_sys_pwr_reg; - unsigned char res33[0x4]; - unsigned int g2d_mem_sys_pwr_reg; - unsigned int usbdrd_mem_sys_pwr_reg; - unsigned int efnand_mem_sys_pwr_reg; - unsigned int cssys_mem_sys_pwr_reg; - unsigned int secss_mem_sys_pwr_reg; - unsigned int rotator_mem_sys_pwr_reg; - unsigned int intram_mem_sys_pwr_reg; - unsigned int introm_mem_sys_pwr_reg; - unsigned int jpeg_mem_sys_pwr_reg; - unsigned int hsi_mem_sys_pwr_reg; - unsigned char res34[0x4]; - unsigned int mcuiop_mem_sys_pwr_reg; - unsigned char res35[0x4]; - unsigned int sata_mem_sys_pwr_reg; - unsigned int pad_retention_dram_sys_pwr_reg; - unsigned int pad_retention_mau_sys_pwr_reg; - unsigned int pad_retention_jtag_sys_pwr_reg; - unsigned char res36[0xc]; - unsigned int pad_retention_mmc2_sys_pwr_reg; - unsigned int pad_retention_mmc3_sys_pwr_reg; - unsigned int pad_retention_gpio_sys_pwr_reg; - unsigned int pad_retention_uart_sys_pwr_reg; - unsigned int pad_retention_mmc0_sys_pwr_reg; - unsigned int pad_retention_mmc1_sys_pwr_reg; - unsigned int pad_retention_ebia_sys_pwr_reg; - unsigned int pad_retention_ebib_sys_pwr_reg; - unsigned int pad_retention_spi_sys_pwr_reg; - unsigned int pad_retention_gpio_dmc_sys_pwr_reg; - unsigned int pad_isolation_sys_pwr_reg; - unsigned char res37[0xc]; - unsigned int pad_isolation_dmc_sys_pwr_reg; - unsigned char res38[0xc]; - unsigned int pad_alv_sel_sys_pwr_reg; - unsigned char res39[0x20]; - unsigned int xxti_sys_pwr_reg; - unsigned char res40[0x38]; - unsigned int ext_regulator_sys_pwr_reg; - unsigned char res41[0x3c]; - unsigned int gpio_mode_sys_pwr_reg; - unsigned char res42[0x1c]; - unsigned int gpio_mode_dmc_sys_pwr_reg; - unsigned char res43[0x1c]; - unsigned int gpio_mode_mau_sys_pwr_reg; - unsigned int top_asb_reset_sys_pwr_reg; - unsigned int top_asb_isolation_sys_pwr_reg; - unsigned char res44[0xb4]; - unsigned int gscl_sys_pwr_reg; - unsigned int isp_sys_pwr_reg; - unsigned int mfc_sys_pwr_reg; - unsigned int g3d_sys_pwr_reg; - unsigned char res45[0x4]; - unsigned int disp1_sys_pwr_reg; - unsigned int mau_sys_pwr_reg; - unsigned char res46[0x64]; - unsigned int cmu_clkstop_gscl_sys_pwr_reg; - unsigned int cmu_clkstop_isp_sys_pwr_reg; - unsigned int cmu_clkstop_mfc_sys_pwr_reg; - unsigned int cmu_clkstop_g3d_sys_pwr_reg; - unsigned char res47[0x4]; - unsigned int cmu_clkstop_disp1_sys_pwr_reg; - unsigned int cmu_clkstop_mau_sys_pwr_reg; - unsigned char res48[0x24]; - unsigned int cmu_sysclk_gscl_sys_pwr_reg; - unsigned int cmu_sysclk_isp_sys_pwr_reg; - unsigned int cmu_sysclk_mfc_sys_pwr_reg; - unsigned int cmu_sysclk_g3d_sys_pwr_reg; - unsigned char res49[0x4]; - unsigned int cmu_sysclk_disp1_sys_pwr_reg; - unsigned int cmu_sysclk_mau_sys_pwr_reg; - unsigned char res50[0xa4]; - unsigned int cmu_reset_gscl_sys_pwr_reg; - unsigned int cmu_reset_isp_sys_pwr_reg; - unsigned int cmu_reset_mfc_sys_pwr_reg; - unsigned int cmu_reset_g3d_sys_pwr_reg; - unsigned char res51[0x4]; - unsigned int cmu_reset_disp1_sys_pwr_reg; - unsigned int cmu_reset_mau_sys_pwr_reg; - unsigned char res52[0xa64]; - unsigned int arm_core0_configuration; - unsigned int arm_core0_status; - unsigned int arm_core0_option; - unsigned char res53[0x14]; - unsigned int dis_irq_arm_core0_local_configuration; - unsigned int dis_irq_arm_core0_local_status; - unsigned int dis_irq_arm_core0_local_option; - unsigned char res54[0x14]; - unsigned int dis_irq_arm_core0_central_configuration; - unsigned int dis_irq_arm_core0_central_status; - unsigned int dis_irq_arm_core0_central_option; - unsigned char res55[0x34]; - unsigned int arm_core1_configuration; - unsigned int arm_core1_status; - unsigned int arm_core1_option; - unsigned char res56[0x14]; - unsigned int dis_irq_arm_core1_local_configuration; - unsigned int dis_irq_arm_core1_local_status; - unsigned int dis_irq_arm_core1_local_option; - unsigned char res57[0x14]; - unsigned int dis_irq_arm_core1_central_configuration; - unsigned int dis_irq_arm_core1_central_status; - unsigned int dis_irq_arm_core1_central_option; - unsigned char res58[0x134]; - unsigned int fsys_arm_configuration; - unsigned int fsys_arm_status; - unsigned int fsys_arm_option; - unsigned char res59[0x14]; - unsigned int dis_irq_fsys_arm_local_configuration; - unsigned int dis_irq_fsys_arm_local_status; - unsigned int dis_irq_fsys_arm_local_option; - unsigned char res60[0x14]; - unsigned int dis_irq_fsys_arm_central_configuration; - unsigned int dis_irq_fsys_arm_central_status; - unsigned int dis_irq_fsys_arm_central_option; - unsigned char res61[0x34]; - unsigned int isp_arm_configuration; - unsigned int isp_arm_status; - unsigned int isp_arm_option; - unsigned char res62[0x14]; - unsigned int dis_irq_isp_arm_local_configuration; - unsigned int dis_irq_isp_arm_local_status; - unsigned int dis_irq_isp_arm_local_option; - unsigned char res63[0x14]; - unsigned int dis_irq_isp_arm_central_configuration; - unsigned int dis_irq_isp_arm_central_status; - unsigned int dis_irq_isp_arm_central_option; - unsigned char res64[0x134]; - unsigned int arm_common_configuration; - unsigned int arm_common_status; - unsigned int arm_common_option; - unsigned char res65[0x1f4]; - unsigned int arm_l2_configuration; - unsigned int arm_l2_status; - unsigned int arm_l2_option; - unsigned char res66[0x1f4]; - unsigned int cmu_aclkstop_configuration; - unsigned int cmu_aclkstop_status; - unsigned int cmu_aclkstop_option; - unsigned char res67[0x14]; - unsigned int cmu_sclkstop_configuration; - unsigned int cmu_sclkstop_status; - unsigned int cmu_sclkstop_option; - unsigned char res68[0x34]; - unsigned int cmu_reset_configuration; - unsigned int cmu_reset_status; - unsigned int cmu_reset_option; - unsigned char res69[0x94]; - unsigned int cmu_aclkstop_dmc_configuration; - unsigned int cmu_aclkstop_dmc_status; - unsigned int cmu_aclkstop_dmc_option; - unsigned char res70[0x14]; - unsigned int cmu_sclkstop_dmc_configuration; - unsigned int cmu_sclkstop_dmc_status; - unsigned int cmu_sclkstop_dmc_option; - unsigned char res71[0x34]; - unsigned int cmu_reset_dmc_configuration; - unsigned int cmu_reset_dmc_status; - unsigned int cmu_reset_dmc_option; - unsigned char res72[0x54]; - unsigned int ddrphy_dlllock_configuration; - unsigned int ddrphy_dlllock_status; - unsigned int ddrphy_dlllock_option; - unsigned char res73[0x34]; - unsigned int apll_sysclk_configuration; - unsigned int apll_sysclk_status; - unsigned int apll_sysclk_option; - unsigned char res74[0x18]; - unsigned int mpll_sysclk_status; - unsigned int mpll_sysclk_option; - unsigned char res75[0x14]; - unsigned int vpll_sysclk_configuration; - unsigned int vpll_sysclk_status; - unsigned int vpll_sysclk_option; - unsigned char res76[0x14]; - unsigned int epll_sysclk_configuration; - unsigned int epll_sysclk_status; - unsigned int epll_sysclk_option; - unsigned char res77[0x14]; - unsigned int bpll_sysclk_configuration; - unsigned int bpll_sysclk_status; - unsigned int bpll_sysclk_option; - unsigned char res78[0x14]; - unsigned int cpll_sysclk_configuration; - unsigned int cpll_sysclk_status; - unsigned int cpll_sysclk_option; - unsigned char res79[0x14]; - unsigned int gpll_sysclk_configuration; - unsigned int gpll_sysclk_status; - unsigned int gpll_sysclk_option; - unsigned char res80[0x54]; - unsigned int mplluser_sysclk_configuration; - unsigned int mplluser_sysclk_status; - unsigned int mplluser_sysclk_option; - unsigned char res81[0x54]; - unsigned int bplluser_sysclk_configuration; - unsigned int bplluser_sysclk_status; - unsigned int bplluser_sysclk_option; - unsigned char res82[0x74]; - unsigned int top_bus_configuration; - unsigned int top_bus_status; - unsigned int top_bus_option; - unsigned char res83[0x14]; - unsigned int top_retention_configuration; - unsigned int top_retention_status; - unsigned int top_retention_option; - unsigned char res84[0x14]; - unsigned int top_pwr_configuration; - unsigned int top_pwr_status; - unsigned int top_pwr_option; - unsigned char res85[0x34]; - unsigned int top_bus_dmc_configuration; - unsigned int top_bus_dmc_status; - unsigned int top_bus_dmc_option; - unsigned char res86[0x14]; - unsigned int top_retention_dmc_configuration; - unsigned int top_retention_dmc_status; - unsigned int top_retention_dmc_option; - unsigned char res87[0x14]; - unsigned int top_pwr_dmc_configuration; - unsigned int top_pwr_dmc_status; - unsigned int top_pwr_dmc_option; - unsigned char res88[0x34]; - unsigned int logic_reset_configuration; - unsigned int logic_reset_status; - unsigned int logic_reset_option; - unsigned char res89[0x14]; - unsigned int oscclk_gate_configuration; - unsigned int oscclk_gate_status; - unsigned int oscclk_gate_option; - unsigned char res90[0x54]; - unsigned int logic_reset_dmc_configuration; - unsigned int logic_reset_dmc_status; - unsigned int logic_reset_dmc_option; - unsigned char res91[0x14]; - unsigned int oscclk_gate_dmc_configuration; - unsigned int oscclk_gate_dmc_status; - unsigned int oscclk_gate_dmc_option; - unsigned char res92[0x54]; - unsigned int usbotg_mem_configuration; - unsigned int usbotg_mem_status; - unsigned int usbotg_mem_option; - unsigned char res93[0x34]; - unsigned int g2d_mem_configuration; - unsigned int g2d_mem_status; - unsigned int g2d_mem_option; - unsigned char res94[0x14]; - unsigned int usbdrd_mem_configuration; - unsigned int usbdrd_mem_status; - unsigned int usbdrd_mem_option; - unsigned char res95[0x14]; - unsigned int efnand_mem_configuration; - unsigned int efnand_mem_status; - unsigned int efnand_mem_option; - unsigned char res96[0x14]; - unsigned int cssys_mem_configuration; - unsigned int cssys_mem_status; - unsigned int cssys_mem_option; - unsigned char res97[0x14]; - unsigned int secss_mem_configuration; - unsigned int secss_mem_status; - unsigned int secss_mem_option; - unsigned char res98[0x14]; - unsigned int rotator_mem_configuration; - unsigned int rotator_mem_status; - unsigned int rotator_mem_option; - unsigned char res99[0x14]; - unsigned int intram_mem_configuration; - unsigned int intram_mem_status; - unsigned int intram_mem_option; - unsigned char res100[0x14]; - unsigned int introm_mem_configuration; - unsigned int introm_mem_status; - unsigned int introm_mem_option; - unsigned char res101[0x14]; - unsigned int jpeg_mem_configuration; - unsigned int jpeg_mem_status; - unsigned int jpeg_mem_option; - unsigned char res102[0x14]; - unsigned int hsi_mem_configuration; - unsigned int hsi_mem_status; - unsigned int hsi_mem_option; - unsigned char res103[0x34]; - unsigned int mcuiop_mem_configuration; - unsigned int mcuiop_mem_status; - unsigned int mcuiop_mem_option; - unsigned char res104[0x14]; - unsigned int sata_mem_configuration; - unsigned int sata_mem_status; - unsigned int sata_mem_option; - unsigned char res105[0x34]; - unsigned int pad_retention_dram_configuration; - unsigned int pad_retention_dram_status; - unsigned int pad_retention_dram_option; - unsigned char res106[0x14]; - unsigned int pad_retention_mau_configuration; - unsigned int pad_retention_mau_status; - unsigned int pad_retention_mau_option; - unsigned char res107[0x14]; - unsigned int pad_retention_jtag_configuration; - unsigned int pad_retention_jtag_status; - unsigned int pad_retention_jtag_option; - unsigned char res108[0x74]; - unsigned int pad_retention_mmc2_configuration; - unsigned int pad_retention_mmc2_status; - unsigned int pad_retention_mmc2_option; - unsigned char res109[0x14]; - unsigned int pad_retention_mmc3_configuration; - unsigned int pad_retention_mmc3_status; - unsigned int pad_retention_mmc3_option; - unsigned char res110[0x14]; - unsigned int pad_retention_gpio_configuration; - unsigned int pad_retention_gpio_status; - unsigned int pad_retention_gpio_option; - unsigned char res111[0x14]; - unsigned int pad_retention_uart_configuration; - unsigned int pad_retention_uart_status; - unsigned int pad_retention_uart_option; - unsigned char res112[0x14]; - unsigned int pad_retention_mmc0_configuration; - unsigned int pad_retention_mmc0_status; - unsigned int pad_retention_mmc0_option; - unsigned char res113[0x14]; - unsigned int pad_retention_mmc1_configuration; - unsigned int pad_retention_mmc1_status; - unsigned int pad_retention_mmc1_option; - unsigned char res114[0x14]; - unsigned int pad_retention_ebia_configuration; - unsigned int pad_retention_ebia_status; - unsigned int pad_retention_ebia_option; - unsigned char res115[0x14]; - unsigned int pad_retention_ebib_configuration; - unsigned int pad_retention_ebib_status; - unsigned int pad_retention_ebib_option; - unsigned char res116[0x14]; - unsigned int pad_retention_spi_configuration; - unsigned int pad_retention_spi_status; - unsigned int pad_retention_spi_option; - unsigned char res117[0x14]; - unsigned int pad_retention_gpio_dmc_configuration; - unsigned int pad_retention_gpio_dmc_status; - unsigned int pad_retention_gpio_dmc_option; - unsigned char res118[0x14]; - unsigned int pad_isolation_configuration; - unsigned int pad_isolation_status; - unsigned int pad_isolation_option; - unsigned char res119[0x74]; - unsigned int pad_isolation_dmc_configuration; - unsigned int pad_isolation_dmc_status; - unsigned int pad_isolation_dmc_option; - unsigned char res120[0x74]; - unsigned int pad_alv_sel_configuration; - unsigned int pad_alv_sel_status; - unsigned int pad_alv_sel_option0; - unsigned int ps_hold_control; - unsigned char res130[0x110]; - unsigned int xxti_configuration; - unsigned int xxti_status; - unsigned int xxti_option; - unsigned char res131[0x10]; - unsigned int xxti_duration3; - unsigned char res132[0x1c0]; - unsigned int ext_regulator_configuration; - unsigned int ext_regulator_status; - unsigned int ext_regulator_option; - unsigned char res133[0x10]; - unsigned int ext_regulator_duration3; - unsigned char res134[0x1e0]; - unsigned int gpio_mode_configuration; - unsigned int gpio_mode_status; - unsigned int gpio_mode_option; - unsigned char res135[0xf4]; - unsigned int gpio_mode_dmc_configuration; - unsigned int gpio_mode_dmc_status; - unsigned int gpio_mode_dmc_option; - unsigned char res136[0xd4]; - unsigned int gpio_mode_mau_configuration; - unsigned int gpio_mode_mau_status; - unsigned int gpio_mode_mau_option; - unsigned char res137[0x14]; - unsigned int top_asb_reset_configuration; - unsigned int top_asb_reset_status; - unsigned int top_asb_reset_option; - unsigned char res138[0x14]; - unsigned int top_asb_isolation_configuration; - unsigned int top_asb_isolation_status; - unsigned int top_asb_isolation_option; - unsigned char res139[0x5d4]; - unsigned int gscl_configuration; - unsigned int gscl_status; - unsigned int gscl_option; - unsigned char res140[0x14]; - unsigned int isp_configuration; - unsigned int isp_status; - unsigned int isp_option; - unsigned char res141[0x14]; - unsigned int mfc_configuration; - unsigned int mfc_status; - unsigned int mfc_option; - unsigned char res142[0x14]; - unsigned int g3d_configuration; - unsigned int g3d_status; - unsigned int g3d_option; - unsigned char res143[0x34]; - unsigned int disp1_configuration; - unsigned int disp1_status; - unsigned int disp1_option; - unsigned char res144[0x14]; - unsigned int mau_configuration; - unsigned int mau_status; - unsigned int mau_option; - unsigned char res145[0x334]; - unsigned int cmu_clkstop_gscl_configuration; - unsigned int cmu_clkstop_gscl_status; - unsigned int cmu_clkstop_gscl_option; - unsigned char res146[0x14]; - unsigned int cmu_clkstop_isp_configuration; - unsigned int cmu_clkstop_isp_status; - unsigned int cmu_clkstop_isp_option; - unsigned char res147[0x14]; - unsigned int cmu_clkstop_mfc_configuration; - unsigned int cmu_clkstop_mfc_status; - unsigned int cmu_clkstop_mfc_option; - unsigned char res148[0x14]; - unsigned int cmu_clkstop_g3d_configuration; - unsigned int cmu_clkstop_g3d_status; - unsigned int cmu_clkstop_g3d_option; - unsigned char res149[0x34]; - unsigned int cmu_clkstop_disp1_configuration; - unsigned int cmu_clkstop_disp1_status; - unsigned int cmu_clkstop_disp1_option; - unsigned char res150[0x14]; - unsigned int cmu_clkstop_mau_configuration; - unsigned int cmu_clkstop_mau_status; - unsigned int cmu_clkstop_mau_option; - unsigned char res151[0x134]; - unsigned int cmu_sysclk_gscl_configuration; - unsigned int cmu_sysclk_gscl_status; - unsigned int cmu_sysclk_gscl_option; - unsigned char res152[0x18]; - unsigned int cmu_sysclk_isp_status; - unsigned int cmu_sysclk_isp_option; - unsigned char res153[0x18]; - unsigned int cmu_sysclk_mfc_status; - unsigned int cmu_sysclk_mfc_option; - unsigned char res154[0x18]; - unsigned int cmu_sysclk_g3d_status; - unsigned int cmu_sysclk_g3d_option; - unsigned char res155[0x38]; - unsigned int cmu_sysclk_disp1_status; - unsigned int cmu_sysclk_disp1_option; - unsigned char res156[0x18]; - unsigned int cmu_sysclk_mau_status; - unsigned int cmu_sysclk_mau_option; - unsigned char res157[0x534]; - unsigned int cmu_reset_gscl_configuration; - unsigned int cmu_reset_gscl_status; - unsigned int cmu_reset_gscl_option; - unsigned char res158[0x14]; - unsigned int cmu_reset_isp_configuration; - unsigned int cmu_reset_isp_status; - unsigned int cmu_reset_isp_option; - unsigned char res159[0x14]; - unsigned int cmu_reset_mfc_configuration; - unsigned int cmu_reset_mfc_status; - unsigned int cmu_reset_mfc_option; - unsigned char res160[0x14]; - unsigned int cmu_reset_g3d_configuration; - unsigned int cmu_reset_g3d_status; - unsigned int cmu_reset_g3d_option; - unsigned char res161[0x34]; - unsigned int cmu_reset_disp1_configuration; - unsigned int cmu_reset_disp1_status; - unsigned int cmu_reset_disp1_option; - unsigned char res162[0x14]; - unsigned int cmu_reset_mau_configuration; - unsigned int cmu_reset_mau_status; - unsigned int cmu_reset_mau_option; - unsigned char res163[0x24]; -}; - -struct exynos5420_power { - unsigned int om_stat; - unsigned int lpi_mask0; - unsigned int lpi_mask1; - unsigned char res1[0x10]; - unsigned int rtc_clko_sel; - unsigned char res2[0x1e0]; - unsigned int central_seq_configuration; - unsigned int central_seq_status; - unsigned int central_seq_option; - unsigned char res3[0x14]; - unsigned int seq_transition0; - unsigned int seq_transition1; - unsigned int seq_transition2; - unsigned int seq_transition3; - unsigned int seq_transition4; - unsigned int seq_transition5; - unsigned int seq_transition6; - unsigned int seq_transition7; - unsigned int central_seq_coreblk_configuration; - unsigned int central_seq_coreblk_status; - unsigned int central_seq_coreblk_option; - unsigned char res4[0x14]; - unsigned int seq_coreblk_transition0; - unsigned int seq_coreblk_transition1; - unsigned int seq_coreblk_transition2; - unsigned int seq_coreblk_transition3; - unsigned int seq_coreblk_transition4; - unsigned int seq_coreblk_transition5; - unsigned int seq_coreblk_transition6; - unsigned int seq_coreblk_transition7; - unsigned char res5[0x180]; - unsigned int swreset; - unsigned int rst_stat; - unsigned int automatic_wdt_reset_disable; - unsigned int mask_wdt_reset_request; - unsigned int mask_wreset_request; - unsigned char res6[0xec]; - unsigned int reset_sequencer_configuration; - unsigned int reset_sequencer_status; - unsigned int reset_sequencer_option; - unsigned char res7[0xf4]; - unsigned int wakeup_stat; - unsigned int eint_wakeup_mask; - unsigned int wakeup_mask; - unsigned int wakeup_interrupt; - unsigned char res8[0x10]; - unsigned int wakeup_stat_coreblk; - unsigned int eint_wakeup_mask_coreblk; - unsigned int wakeup_mask_coreblk; - unsigned int wakeup_interrupt_coreblk; - unsigned char res9[0xd0]; - unsigned int hdmi_phy_control; - unsigned int usbdev_phy_control; - unsigned int usbdev1_phy_control; - unsigned int usbhost_phy_control; - unsigned char res104[0x4]; - unsigned int mipi_phy0_control; - unsigned int mipi_phy1_control; - unsigned int mipi_phy2_control; - unsigned int adc_phy_control; - unsigned int mtcadc_phy_control; - unsigned int dptx_phy_control; - unsigned char res10[0xd4]; - unsigned int inform0; - unsigned int inform1; - unsigned int inform2; - unsigned int inform3; - unsigned int sysip_dat0; - unsigned int sysip_dat1; - unsigned int sysip_dat2; - unsigned int sysip_dat3; - unsigned char res11[0xe0]; - unsigned int pmu_spare0; - unsigned int pmu_spare1; - unsigned int pmu_spare2; - unsigned int pmu_spare3; - unsigned char res12[0x4]; - unsigned int cg_status0; - unsigned int cg_status1; - unsigned int cg_status2; - unsigned int cg_status3; - unsigned int cg_status4; - unsigned char res200[0x58]; - unsigned int irom_data_reg0; - unsigned int irom_data_reg1; - unsigned int irom_data_reg2; - unsigned int irom_data_reg3; - unsigned char res13[0x70]; - unsigned int pmu_debug; - unsigned char res14[0x5fc]; - unsigned int arm_core0_sys_pwr_reg; - unsigned char res500[0xc]; - unsigned int arm_core1_sys_pwr_reg; - unsigned char res501[0xc]; - unsigned int arm_core2_sys_pwr_reg; - unsigned char res502[0xc]; - unsigned int arm_core3_sys_pwr_reg; - unsigned char res503[0xc]; - unsigned int kfc_core0_sys_pwr_reg; - unsigned char res504[0xc]; - unsigned int kfc_core1_sys_pwr_reg; - unsigned char res505[0xc]; - unsigned int kfc_core2_sys_pwr_reg; - unsigned char res506[0xc]; - unsigned int kfc_core3_sys_pwr_reg; - unsigned char res507[0x1c]; - unsigned int isp_arm_sys_pwr_reg; - unsigned char res18[0xc]; - unsigned int arm_common_sys_pwr_reg; - unsigned char res508[0xc]; - unsigned int kfc_common_sys_pwr_reg; - unsigned char res19[0xc]; - unsigned int arm_l2_sys_pwr_reg; - unsigned char res509[0xc]; - unsigned int kfc_l2_sys_pwr_reg; - unsigned char res20[0xc]; - unsigned int cmu_cpu_aclkstop_sys_pwr_reg; - unsigned int cmu_cpu_sclkstop_sys_pwr_reg; - unsigned char res510[0x8]; - unsigned int cmu_kfc_aclkstop_sys_pwr_reg; - unsigned char res511[0xc]; - unsigned int cmu_aclkstop_sys_pwr_reg; - unsigned int cmu_sclkstop_sys_pwr_reg; - unsigned char res21[0x4]; - unsigned int cmu_reset_sys_pwr_reg; - unsigned char res22[0x10]; - unsigned int cmu_aclkstop_coreblk_sys_pwr_reg; - unsigned int cmu_sclkstop_coreblk_sys_pwr_reg; - unsigned char res23[0x4]; - unsigned int cmu_reset_coreblk_sys_pwr_reg; - unsigned int dram_freq_down_sys_pwr_reg; - unsigned int ddrphy_dlloff_sys_pwr_reg; - unsigned int ddrphy_dlllock_sys_pwr_reg; - unsigned char res25[0x4]; - unsigned int apll_sysclk_sys_pwr_reg; - unsigned int mpll_sysclk_sys_pwr_reg; - unsigned int vpll_sysclk_sys_pwr_reg; - unsigned int epll_sysclk_sys_pwr_reg; - unsigned int bpll_sysclk_sys_pwr_reg; - unsigned int cpll_sysclk_sys_pwr_reg; - unsigned int dpll_sysclk_sys_pwr_reg; - unsigned int ipll_sysclk_sys_pwr_reg; - unsigned int kpll_sysclk_sys_pwr_reg; - unsigned int mplluser_sysclk_sys_pwr_reg; - unsigned char res512[0x8]; - unsigned int bplluser_sysclk_sys_pwr_reg; - unsigned int rpll_sysclk_sys_pwr_reg; - unsigned int spll_sysclk_sys_pwr_reg; - unsigned char res26[0x4]; - unsigned int top_bus_sys_pwr_reg; - unsigned int top_retention_sys_pwr_reg; - unsigned int top_pwr_sys_pwr_reg; - unsigned char res29[0x4]; - unsigned int top_bus_coreblk_sys_pwr_reg; - unsigned int top_retention_coreblk_sys_pwr_reg; - unsigned int top_pwr_coreblk_sys_pwr_reg; - unsigned char res30[0x4]; - unsigned int logic_reset_sys_pwr_reg; - unsigned int oscclk_gate_sys_pwr_reg; - unsigned char res31[0x8]; - unsigned int logic_reset_coreblk_sys_pwr_reg; - unsigned int oscclk_gate_coreblk_sys_pwr_reg; - unsigned int intram_mem_sys_pwr_reg; - unsigned int introm_mem_sys_pwr_reg; - unsigned char res32[0x44]; - unsigned int pad_retention_mau_sys_pwr_reg; - unsigned int pad_retention_jtag_sys_pwr_reg; - unsigned char res36[0x4]; - unsigned int pad_retention_dram_sys_pwr_reg; - unsigned int pad_retention_uart_sys_pwr_reg; - unsigned int pad_retention_mmca_sys_pwr_reg; - unsigned int pad_retention_mmcb_sys_pwr_reg; - unsigned int pad_retention_mmcc_sys_pwr_reg; - unsigned int pad_retention_hsi_sys_pwr_reg; - unsigned int pad_retention_ebia_sys_pwr_reg; - unsigned int pad_retention_ebib_sys_pwr_reg; - unsigned int pad_retention_spi_sys_pwr_reg; - unsigned int pad_retention_dram_coreblk_sys_pwr_reg; - unsigned char res28[0x8]; - unsigned int pad_isolation_sys_pwr_reg; - unsigned char res37[0xc]; - unsigned int pad_isolation_coreblk_sys_pwr_reg; - unsigned char res38[0xc]; - unsigned int pad_alv_sel_sys_pwr_reg; - unsigned char res39[0x1c]; - unsigned int xusbxti_sys_pwr_reg; - unsigned int xxti_sys_pwr_reg; - unsigned char res40[0x38]; - unsigned int ext_regulator_sys_pwr_reg; - unsigned char res41[0x3c]; - unsigned int gpio_mode_sys_pwr_reg; - unsigned char res42[0x1c]; - unsigned int gpio_mode_coreblk_sys_pwr_reg; - unsigned char res43[0x1c]; - unsigned int gpio_mode_mau_sys_pwr_reg; - unsigned int top_asb_reset_sys_pwr_reg; - unsigned int top_asb_isolation_sys_pwr_reg; - unsigned char res44[0xb4]; - unsigned int gscl_sys_pwr_reg; - unsigned int isp_sys_pwr_reg; - unsigned int mfc_sys_pwr_reg; - unsigned int g3d_sys_pwr_reg; - unsigned int disp1_sys_pwr_reg; - unsigned int mau_sys_pwr_reg; - unsigned int g2d_sys_pwr_reg; - unsigned int msc_sys_pwr_reg; - unsigned int fsys_sys_pwr_reg; - unsigned int fsys2_sys_pwr_reg; - unsigned int psgen_sys_pwr_reg; - unsigned int peric_sys_pwr_reg; - unsigned int wcore_sys_pwr_reg; - unsigned char res46[0x4c]; - unsigned int cmu_clkstop_gscl_sys_pwr_reg; - unsigned int cmu_clkstop_isp_sys_pwr_reg; - unsigned int cmu_clkstop_mfc_sys_pwr_reg; - unsigned int cmu_clkstop_g3d_sys_pwr_reg; - unsigned int cmu_clkstop_disp1_sys_pwr_reg; - unsigned int cmu_clkstop_mau_sys_pwr_reg; - unsigned int cmu_clkstop_g2d_sys_pwr_reg; - unsigned int cmu_clkstop_msc_sys_pwr_reg; - unsigned int cmu_clkstop_fsys_sys_pwr_reg; - unsigned int cmu_clkstop_fsys2_sys_pwr_reg; - unsigned int cmu_clkstop_psgen_sys_pwr_reg; - unsigned int cmu_clkstop_peric_sys_pwr_reg; - unsigned int cmu_clkstop_wcore_sys_pwr_reg; - unsigned char res48[0x8]; - unsigned int cmu_sysclk_toppwr_sys_pwr_reg; - unsigned int cmu_sysclk_gscl_sys_pwr_reg; - unsigned int cmu_sysclk_isp_sys_pwr_reg; - unsigned int cmu_sysclk_mfc_sys_pwr_reg; - unsigned int cmu_sysclk_g3d_sys_pwr_reg; - unsigned int cmu_sysclk_disp1_sys_pwr_reg; - unsigned int cmu_sysclk_mau_sys_pwr_reg; - unsigned int cmu_sysclk_g2d_sys_pwr_reg; - unsigned int cmu_sysclk_msc_sys_pwr_reg; - unsigned int cmu_sysclk_fsys_sys_pwr_reg; - unsigned int cmu_sysclk_fsys2_sys_pwr_reg; - unsigned int cmu_sysclk_psgen_sys_pwr_reg; - unsigned int cmu_sysclk_peric_sys_pwr_reg; - unsigned int cmu_sysclk_wcore_sys_pwr_reg; - unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg; - unsigned char res50[0x78]; - unsigned int cmu_reset_fsys2_sys_pwr_reg; - unsigned int cmu_reset_psgen_sys_pwr_reg; - unsigned int cmu_reset_peric_sys_pwr_reg; - unsigned int cmu_reset_wcore_sys_pwr_reg; - unsigned int cmu_reset_gscl_sys_pwr_reg; - unsigned int cmu_reset_isp_sys_pwr_reg; - unsigned int cmu_reset_mfc_sys_pwr_reg; - unsigned int cmu_reset_g3d_sys_pwr_reg; - unsigned int cmu_reset_disp1_sys_pwr_reg; - unsigned int cmu_reset_mau_sys_pwr_reg; - unsigned int cmu_reset_g2d_sys_pwr_reg; - unsigned int cmu_reset_msc_sys_pwr_reg; - unsigned int cmu_reset_fsys_sys_pwr_reg; - unsigned char res52[0xa5c]; - unsigned int arm_core0_configuration; - unsigned int arm_core0_status; - unsigned int arm_core0_option; - unsigned char res53[0x14]; - unsigned int dis_irq_arm_core0_local_configuration; - unsigned int dis_irq_arm_core0_local_status; - unsigned int dis_irq_arm_core0_local_option; - unsigned char res54[0x14]; - unsigned int dis_irq_arm_core0_central_configuration; - unsigned int dis_irq_arm_core0_central_status; - unsigned int dis_irq_arm_core0_central_option; - unsigned char res55[0x34]; - unsigned int arm_core1_configuration; - unsigned int arm_core1_status; - unsigned int arm_core1_option; - unsigned char res56[0x14]; - unsigned int dis_irq_arm_core1_local_configuration; - unsigned int dis_irq_arm_core1_local_status; - unsigned int dis_irq_arm_core1_local_option; - unsigned char res57[0x14]; - unsigned int dis_irq_arm_core1_central_configuration; - unsigned int dis_irq_arm_core1_central_status; - unsigned int dis_irq_arm_core1_central_option; - unsigned char res600[0x34]; - unsigned int arm_core2_configuration; - unsigned int arm_core2_status; - unsigned int arm_core2_option; - unsigned char res601[0x14]; - unsigned int dis_irq_arm_core2_local_configuration; - unsigned int dis_irq_arm_core2_local_status; - unsigned int dis_irq_arm_core2_local_option; - unsigned char res602[0x14]; - unsigned int dis_irq_arm_core2_central_configuration; - unsigned int dis_irq_arm_core2_central_status; - unsigned int dis_irq_arm_core2_central_option; - unsigned char res603[0x34]; - unsigned int arm_core3_configuration; - unsigned int arm_core3_status; - unsigned int arm_core3_option; - unsigned char res900[0x14]; - unsigned int dis_irq_arm_core3_local_configuration; - unsigned int dis_irq_arm_core3_local_status; - unsigned int dis_irq_arm_core3_local_option; - unsigned char res901[0x14]; - unsigned int dis_irq_arm_core3_central_configuration; - unsigned int dis_irq_arm_core3_central_status; - unsigned int dis_irq_arm_core3_central_option; - unsigned char res604[0x34]; - unsigned int kfc_core0_configuration; - unsigned int kfc_core0_status; - unsigned int kfc_core0_option; - unsigned char res605[0x14]; - unsigned int dis_irq_kfc_core0_local_configuration; - unsigned int dis_irq_kfc_core0_local_status; - unsigned int dis_irq_kfc_core0_local_option; - unsigned char res606[0x14]; - unsigned int dis_irq_kfc_core0_central_configuration; - unsigned int dis_irq_kfc_core0_central_status; - unsigned int dis_irq_kfc_core0_central_option; - unsigned char res607[0x34]; - unsigned int kfc_core1_configuration; - unsigned int kfc_core1_status; - unsigned int kfc_core1_option; - unsigned char res608[0x14]; - unsigned int dis_irq_kfc_core1_local_configuration; - unsigned int dis_irq_kfc_core1_local_status; - unsigned int dis_irq_kfc_core1_local_option; - unsigned char res609[0x14]; - unsigned int dis_irq_kfc_core1_central_configuration; - unsigned int dis_irq_kfc_core1_central_status; - unsigned int dis_irq_kfc_core1_central_option; - unsigned char res610[0x34]; - unsigned int kfc_core2_configuration; - unsigned int kfc_core2_status; - unsigned int kfc_core2_option; - unsigned char res611[0x14]; - unsigned int dis_irq_kfc_core2_local_configuration; - unsigned int dis_irq_kfc_core2_local_status; - unsigned int dis_irq_kfc_core2_local_option; - unsigned char res612[0x14]; - unsigned int dis_irq_kfc_core2_central_configuration; - unsigned int dis_irq_kfc_core2_central_status; - unsigned int dis_irq_kfc_core2_central_option; - unsigned char res613[0x34]; - unsigned int kfc_core3_configuration; - unsigned int kfc_core3_status; - unsigned int kfc_core3_option; - unsigned char res614[0x14]; - unsigned int dis_irq_kfc_core3_local_configuration; - unsigned int dis_irq_kfc_core3_local_status; - unsigned int dis_irq_kfc_core3_local_option; - unsigned char res615[0x14]; - unsigned int dis_irq_kfc_core3_central_configuration; - unsigned int dis_irq_kfc_core3_central_status; - unsigned int dis_irq_kfc_core3_central_option; - unsigned char res61[0xb4]; - unsigned int isp_arm_configuration; - unsigned int isp_arm_status; - unsigned int isp_arm_option; - unsigned char res62[0x14]; - unsigned int dis_irq_isp_arm_local_configuration; - unsigned int dis_irq_isp_arm_local_status; - unsigned int dis_irq_isp_arm_local_option; - unsigned char res63[0x14]; - unsigned int dis_irq_isp_arm_central_configuration; - unsigned int dis_irq_isp_arm_central_status; - unsigned int dis_irq_isp_arm_central_option; - unsigned char res64[0x34]; - unsigned int arm_common_configuration; - unsigned int arm_common_status; - unsigned int arm_common_option; - unsigned char res616[0x74]; - unsigned int kfc_common_configuration; - unsigned int kfc_common_status; - unsigned int kfc_common_option; - unsigned char res65[0x74]; - unsigned int arm_l2_configuration; - unsigned int arm_l2_status; - unsigned int arm_l2_option; - unsigned char res617[0x74]; - unsigned int kfc_l2_configuration; - unsigned int kfc_l2_status; - unsigned int kfc_l2_option; - unsigned char res66[0x74]; - unsigned int cmu_cpu_aclkstop_configuration; - unsigned int cmu_cpu_aclkstop_status; - unsigned int cmu_cpu_aclkstop_option; - unsigned char res67[0x14]; - unsigned int cmu_cpu_sclkstop_configuration; - unsigned int cmu_cpu_sclkstop_status; - unsigned int cmu_cpu_sclkstop_option; - unsigned char res618[0x4]; - unsigned int cmu_kfc_aclkstop_configuration; - unsigned int cmu_kfc_aclkstop_status; - unsigned int cmu_kfc_aclkstop_option; - unsigned char res619[0xc4]; - unsigned int cmu_aclkstop_configuration; - unsigned int cmu_aclkstop_status; - unsigned int cmu_aclkstop_option; - unsigned char res620[0x14]; - unsigned int cmu_sclkstop_configuration; - unsigned int cmu_sclkstop_status; - unsigned int cmu_sclkstop_option; - unsigned char res68[0x34]; - unsigned int cmu_reset_configuration; - unsigned int cmu_reset_status; - unsigned int cmu_reset_option; - unsigned char res69[0x94]; - unsigned int cmu_aclkstop_coreblk_configuration; - unsigned int cmu_aclkstop_coreblk_status; - unsigned int cmu_aclkstop_coreblk_option; - unsigned char res70[0x14]; - unsigned int cmu_sclkstop_coreblk_configuration; - unsigned int cmu_sclkstop_coreblk_status; - unsigned int cmu_sclkstop_coreblk_option; - unsigned char res71[0x34]; - unsigned int cmu_reset_coreblk_configuration; - unsigned int cmu_reset_coreblk_status; - unsigned int cmu_reset_coreblk_option; - unsigned char res621[0x14]; - unsigned int dram_freq_down_configuration; - unsigned int dram_freq_down_status; - unsigned int dram_freq_down_option; - unsigned char res622[0x14]; - unsigned int ddrphy_dlloff_configuration; - unsigned int ddrphy_dlloff_status; - unsigned int ddrphy_dlloff_option; - unsigned char res72[0x14]; - unsigned int ddrphy_dlllock_configuration; - unsigned int ddrphy_dlllock_status; - unsigned int ddrphy_dlllock_option; - unsigned char res73[0x34]; - unsigned int apll_sysclk_configuration; - unsigned int apll_sysclk_status; - unsigned int apll_sysclk_option; - unsigned char res74[0x18]; - unsigned int mpll_sysclk_status; - unsigned int mpll_sysclk_option; - unsigned char res75[0x14]; - unsigned int vpll_sysclk_configuration; - unsigned int vpll_sysclk_status; - unsigned int vpll_sysclk_option; - unsigned char res76[0x14]; - unsigned int epll_sysclk_configuration; - unsigned int epll_sysclk_status; - unsigned int epll_sysclk_option; - unsigned char res77[0x14]; - unsigned int bpll_sysclk_configuration; - unsigned int bpll_sysclk_status; - unsigned int bpll_sysclk_option; - unsigned char res78[0x14]; - unsigned int cpll_sysclk_configuration; - unsigned int cpll_sysclk_status; - unsigned int cpll_sysclk_option; - unsigned char res79[0x14]; - unsigned int dpll_sysclk_configuration; - unsigned int dpll_sysclk_status; - unsigned int dpll_sysclk_option; - unsigned char res700[0x14]; - unsigned int ipll_sysclk_configuration; - unsigned int ipll_sysclk_status; - unsigned int ipll_sysclk_option; - unsigned char res903[0x14]; - unsigned int kpll_sysclk_configuration; - unsigned int kpll_sysclk_status; - unsigned int kpll_sysclk_option; - unsigned char res80[0x14]; - unsigned int mplluser_sysclk_configuration; - unsigned int mplluser_sysclk_status; - unsigned int mplluser_sysclk_option; - unsigned char res81[0x54]; - unsigned int bplluser_sysclk_configuration; - unsigned int bplluser_sysclk_status; - unsigned int bplluser_sysclk_option; - unsigned char res701[0x14]; - unsigned int rplluser_sysclk_configuration; - unsigned int rplluser_sysclk_status; - unsigned int rplluser_sysclk_option; - unsigned char res702[0x14]; - unsigned int splluser_sysclk_configuration; - unsigned int splluser_sysclk_status; - unsigned int splluser_sysclk_option; - unsigned char res82[0x34]; - unsigned int top_bus_configuration; - unsigned int top_bus_status; - unsigned int top_bus_option; - unsigned char res83[0x14]; - unsigned int top_retention_configuration; - unsigned int top_retention_status; - unsigned int top_retention_option; - unsigned char res84[0x14]; - unsigned int top_pwr_configuration; - unsigned int top_pwr_status; - unsigned int top_pwr_option; - unsigned char res85[0x34]; - unsigned int top_bus_coreblk_configuration; - unsigned int top_bus_coreblk_status; - unsigned int top_bus_coreblk_option; - unsigned char res86[0x14]; - unsigned int top_retention_coreblk_configuration; - unsigned int top_retention_coreblk_status; - unsigned int top_retention_coreblk_option; - unsigned char res87[0x14]; - unsigned int top_pwr_coreblk_configuration; - unsigned int top_pwr_coreblk_status; - unsigned int top_pwr_coreblk_option; - unsigned char res88[0x34]; - unsigned int logic_reset_configuration; - unsigned int logic_reset_status; - unsigned int logic_reset_option; - unsigned char res89[0x14]; - unsigned int oscclk_gate_configuration; - unsigned int oscclk_gate_status; - unsigned int oscclk_gate_option; - unsigned char res90[0x54]; - unsigned int logic_reset_coreblk_configuration; - unsigned int logic_reset_coreblk_status; - unsigned int logic_reset_coreblk_option; - unsigned char res91[0x14]; - unsigned int oscclk_gate_coreblk_configuration; - unsigned int oscclk_gate_coreblk_status; - unsigned int oscclk_gate_coreblk_option; - unsigned char res99[0x174]; - unsigned int intram_mem_configuration; - unsigned int intram_mem_status; - unsigned int intram_mem_option; - unsigned char res100[0x14]; - unsigned int introm_mem_configuration; - unsigned int introm_mem_status; - unsigned int introm_mem_option; - unsigned char res101[0xb4]; - unsigned int pad_retention_dram_configuration; - unsigned int pad_retention_dram_status; - unsigned int pad_retention_dram_option; - unsigned char res106[0x14]; - unsigned int pad_retention_mau_configuration; - unsigned int pad_retention_mau_status; - unsigned int pad_retention_mau_option; - unsigned char res107[0x14]; - unsigned int pad_retention_jtag_configuration; - unsigned int pad_retention_jtag_status; - unsigned int pad_retention_jtag_option; - unsigned char res92[0x74]; - unsigned int pad_retention_dram_configuration_2; - unsigned int pad_retention_dram_status_2; - unsigned int pad_retention_dram_option_2; - unsigned char res111[0x14]; - unsigned int pad_retention_uart_configuration; - unsigned int pad_retention_uart_status; - unsigned int pad_retention_uart_option; - unsigned char res112[0x14]; - unsigned int pad_retention_mmca_configuration; - unsigned int pad_retention_mmca_status; - unsigned int pad_retention_mmca_option; - unsigned char res113[0x14]; - unsigned int pad_retention_mmcb_configuration; - unsigned int pad_retention_mmcb_status; - unsigned int pad_retention_mmcb_option; - unsigned char res93[0x14]; - unsigned int pad_retention_mmcc_configuration; - unsigned int pad_retention_mmcc_status; - unsigned int pad_retention_mmcc_option; - unsigned char res94[0x14]; - unsigned int pad_retention_hsi_configuration; - unsigned int pad_retention_hsi_status; - unsigned int pad_retention_hsi_option; - unsigned char res114[0x14]; - unsigned int pad_retention_ebia_configuration; - unsigned int pad_retention_ebia_status; - unsigned int pad_retention_ebia_option; - unsigned char res115[0x14]; - unsigned int pad_retention_ebib_configuration; - unsigned int pad_retention_ebib_status; - unsigned int pad_retention_ebib_option; - unsigned char res116[0x14]; - unsigned int pad_retention_spi_configuration; - unsigned int pad_retention_spi_status; - unsigned int pad_retention_spi_option; - unsigned char res117[0x14]; - unsigned int pad_retention_dram_coreblk_configuration; - unsigned int pad_retention_dram_coreblk_status; - unsigned int pad_retention_dram_coreblk_option; - unsigned char res118[0x14]; - unsigned int pad_isolation_configuration; - unsigned int pad_isolation_status; - unsigned int pad_isolation_option; - unsigned char res119[0x74]; - unsigned int pad_isolation_coreblk_configuration; - unsigned int pad_isolation_coreblk_status; - unsigned int pad_isolation_coreblk_option; - unsigned char res120[0x74]; - unsigned int pad_alv_sel_configuration; - unsigned int pad_alv_sel_status; - unsigned int pad_alv_sel_option0; - unsigned int ps_hold_control; - unsigned char res130[0xf0]; - unsigned int xusbxti_configuration; - unsigned int xusbxti_status; - unsigned int xusbxti_option; - unsigned char res910[0x10]; - unsigned int xusbxti_duration3; - unsigned int xxti_configuration; - unsigned int xxti_status; - unsigned int xxti_option; - unsigned char res131[0x10]; - unsigned int xxti_duration3; - unsigned char res132[0x1c0]; - unsigned int ext_regulator_configuration; - unsigned int ext_regulator_status; - unsigned int ext_regulator_option; - unsigned char res133[0x10]; - unsigned int ext_regulator_duration3; - unsigned char res134[0x1e0]; - unsigned int gpio_mode_configuration; - unsigned int gpio_mode_status; - unsigned int gpio_mode_option; - unsigned char res135[0xf4]; - unsigned int gpio_mode_coreblk_configuration; - unsigned int gpio_mode_coreblk_status; - unsigned int gpio_mode_coreblk_option; - unsigned char res136[0xd4]; - unsigned int gpio_mode_mau_configuration; - unsigned int gpio_mode_mau_status; - unsigned int gpio_mode_mau_option; - unsigned char res137[0x14]; - unsigned int top_asb_reset_configuration; - unsigned int top_asb_reset_status; - unsigned int top_asb_reset_option; - unsigned char res138[0x14]; - unsigned int top_asb_isolation_configuration; - unsigned int top_asb_isolation_status; - unsigned int top_asb_isolation_option; - unsigned char res139[0x5d4]; - unsigned int gscl_configuration; - unsigned int gscl_status; - unsigned int gscl_option; - unsigned char res140[0x14]; - unsigned int isp_configuration; - unsigned int isp_status; - unsigned int isp_option; - unsigned char res141[0x34]; - unsigned int mfc_configuration; - unsigned int mfc_status; - unsigned int mfc_option; - unsigned char res142[0x14]; - unsigned int g3d_configuration; - unsigned int g3d_status; - unsigned int g3d_option; - unsigned char res143[0x34]; - unsigned int disp1_configuration; - unsigned int disp1_status; - unsigned int disp1_option; - unsigned char res144[0x14]; - unsigned int mau_configuration; - unsigned int mau_status; - unsigned int mau_option; - unsigned char res800[0x14]; - unsigned int g2d_configuration; - unsigned int g2d_status; - unsigned int g2d_option; - unsigned char res801[0x14]; - unsigned int msc_configuration; - unsigned int msc_status; - unsigned int msc_option; - unsigned char res802[0x14]; - unsigned int fsys_configuration; - unsigned int fsys_status; - unsigned int fsys_option; - unsigned char res803[0x14]; - unsigned int fsys2_configuration; - unsigned int fsys2_status; - unsigned int fsys2_option; - unsigned char res804[0x14]; - unsigned int psgen_configuration; - unsigned int psgen_status; - unsigned int psgen_option; - unsigned char res805[0x14]; - unsigned int peric_configuration; - unsigned int peric_status; - unsigned int peric_option; - unsigned char res806[0x14]; - unsigned int wcore_configuration; - unsigned int wcore_status; - unsigned int wcore_option; - unsigned char res145[0x234]; - unsigned int cmu_clkstop_gscl_configuration; - unsigned int cmu_clkstop_gscl_status; - unsigned int cmu_clkstop_gscl_option; - unsigned char res146[0x14]; - unsigned int cmu_clkstop_isp_configuration; - unsigned int cmu_clkstop_isp_status; - unsigned int cmu_clkstop_isp_option; - unsigned char res147[0x34]; - unsigned int cmu_clkstop_mfc_configuration; - unsigned int cmu_clkstop_mfc_status; - unsigned int cmu_clkstop_mfc_option; - unsigned char res148[0x14]; - unsigned int cmu_clkstop_g3d_configuration; - unsigned int cmu_clkstop_g3d_status; - unsigned int cmu_clkstop_g3d_option; - unsigned char res149[0x34]; - unsigned int cmu_clkstop_disp1_configuration; - unsigned int cmu_clkstop_disp1_status; - unsigned int cmu_clkstop_disp1_option; - unsigned char res150[0x14]; - unsigned int cmu_clkstop_mau_configuration; - unsigned int cmu_clkstop_mau_status; - unsigned int cmu_clkstop_mau_option; - unsigned char res807[0x14]; - unsigned int cmu_clkstop_g2d_configuration; - unsigned int cmu_clkstop_g2d_status; - unsigned int cmu_clkstop_g2d_option; - unsigned char res808[0x14]; - unsigned int cmu_clkstop_msc_configuration; - unsigned int cmu_clkstop_msc_status; - unsigned int cmu_clkstop_msc_option; - unsigned char res809[0x14]; - unsigned int cmu_clkstop_fsys_configuration; - unsigned int cmu_clkstop_fsys_status; - unsigned int cmu_clkstop_fsys_option; - unsigned char res810[0x14]; - unsigned int cmu_clkstop_fsys2_configuration; - unsigned int cmu_clkstop_fsys2_status; - unsigned int cmu_clkstop_fsys2_option; - unsigned char res811[0x14]; - unsigned int cmu_clkstop_psgen_configuration; - unsigned int cmu_clkstop_psgen_status; - unsigned int cmu_clkstop_psgen_option; - unsigned char res812[0x14]; - unsigned int cmu_clkstop_peric_configuration; - unsigned int cmu_clkstop_peric_status; - unsigned int cmu_clkstop_peric_option; - unsigned char res813[0x14]; - unsigned int cmu_clkstop_wcore_configuration; - unsigned int cmu_clkstop_wcore_status; - unsigned int cmu_clkstop_wcore_option; - unsigned char res151[0x14]; - unsigned int cmu_sysclk_toppwr_configuration; - unsigned int cmu_sysclk_toppwr_status; - unsigned int cmu_sysclk_toppwr_option; - unsigned char res920[0x18]; - unsigned int cmu_sysclk_gscl_status; - unsigned int cmu_sysclk_gscl_option; - unsigned char res152[0x18]; - unsigned int cmu_sysclk_isp_status; - unsigned int cmu_sysclk_isp_option; - unsigned char res153[0x38]; - unsigned int cmu_sysclk_mfc_status; - unsigned int cmu_sysclk_mfc_option; - unsigned char res154[0x18]; - unsigned int cmu_sysclk_g3d_status; - unsigned int cmu_sysclk_g3d_option; - unsigned char res155[0x38]; - unsigned int cmu_sysclk_disp1_status; - unsigned int cmu_sysclk_disp1_option; - unsigned char res156[0x18]; - unsigned int cmu_sysclk_mau_status; - unsigned int cmu_sysclk_mau_option; - unsigned char res814[0x18]; - unsigned int cmu_sysclk_g2d_status; - unsigned int cmu_sysclk_g2d_option; - unsigned char res815[0x18]; - unsigned int cmu_sysclk_msc_status; - unsigned int cmu_sysclk_msc_option; - unsigned char res922[0x18]; - unsigned int cmu_sysclk_fsys_status; - unsigned int cmu_sysclk_fsys_option; - unsigned char res816[0x18]; - unsigned int cmu_sysclk_fsys2_status; - unsigned int cmu_sysclk_fsys2_option; - unsigned char res817[0x18]; - unsigned int cmu_sysclk_psgen_status; - unsigned int cmu_sysclk_psgen_option; - unsigned char res950[0x18]; - unsigned int cmu_sysclk_peric_status; - unsigned int cmu_sysclk_peric_option; - unsigned char res818[0x18]; - unsigned int cmu_sysclk_wcore_status; - unsigned int cmu_sysclk_wcore_option; - unsigned char res819[0x18]; - unsigned int cmu_sysclk_coreblk_toppwr_status; - unsigned int cmu_sysclk_coreblk_toppwr_option; - unsigned char res157[0x414]; - unsigned int cmu_reset_gscl_configuration; - unsigned int cmu_reset_gscl_status; - unsigned int cmu_reset_gscl_option; - unsigned char res158[0x14]; - unsigned int cmu_reset_isp_configuration; - unsigned int cmu_reset_isp_status; - unsigned int cmu_reset_isp_option; - unsigned char res159[0x34]; - unsigned int cmu_reset_mfc_configuration; - unsigned int cmu_reset_mfc_status; - unsigned int cmu_reset_mfc_option; - unsigned char res160[0x14]; - unsigned int cmu_reset_g3d_configuration; - unsigned int cmu_reset_g3d_status; - unsigned int cmu_reset_g3d_option; - unsigned char res161[0x34]; - unsigned int cmu_reset_disp1_configuration; - unsigned int cmu_reset_disp1_status; - unsigned int cmu_reset_disp1_option; - unsigned char res162[0x14]; - unsigned int cmu_reset_mau_configuration; - unsigned int cmu_reset_mau_status; - unsigned int cmu_reset_mau_option; - unsigned char res163[0x14]; - unsigned int version_info; - unsigned int i2s_bypass; - unsigned int kfc_swreset_mask_from_eagle; - unsigned char res164[0xf4]; - unsigned int cmu_reset_g2d_configuration; - unsigned int cmu_reset_g2d_status; - unsigned int cmu_reset_g2d_option; - unsigned char res165[0x14]; - unsigned int cmu_reset_msc_configuration; - unsigned int cmu_reset_msc_status; - unsigned int cmu_reset_msc_option; - unsigned char res166[0x14]; - unsigned int cmu_reset_fsys_configuration; - unsigned int cmu_reset_fsys_status; - unsigned int cmu_reset_fsys_option; - unsigned char res167[0x14]; - unsigned int cmu_reset_fsys2_configuration; - unsigned int cmu_reset_fsys2_status; - unsigned int cmu_reset_fsys2_option; - unsigned char res168[0x14]; - unsigned int cmu_reset_psgen_configuration; - unsigned int cmu_reset_psgen_status; - unsigned int cmu_reset_psgen_option; - unsigned char res169[0x14]; - unsigned int cmu_reset_peric_configuration; - unsigned int cmu_reset_peric_status; - unsigned int cmu_reset_peric_option; - unsigned char res170[0x14]; - unsigned int cmu_reset_wcore_configuration; - unsigned int cmu_reset_wcore_status; - unsigned int cmu_reset_wcore_option; -}; -#endif /* __ASSEMBLY__ */ - -void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); - -#define EXYNOS_MIPI_PHY_ENABLE (1 << 0) -#define EXYNOS_MIPI_PHY_SRESETN (1 << 1) -#define EXYNOS_MIPI_PHY_MRESETN (1 << 2) - -void set_usbhost_phy_ctrl(unsigned int enable); - -/* Enables hardware tripping to power off the system when TMU fails */ -void set_hw_thermal_trip(void); - -#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) -#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) - -void set_usbdrd_phy_ctrl(unsigned int enable); - -#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0) -#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0) - -void set_dp_phy_ctrl(unsigned int enable); - -#define EXYNOS_DP_PHY_ENABLE (1 << 0) - -#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) -#define POWER_ENABLE_HW_TRIP (1UL << 31) - -/* - * Set ps_hold data driving value high - * This enables the machine to stay powered on - * after the initial power-on condition goes away - * (e.g. power button). - */ -void set_ps_hold_ctrl(void); - -/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ -#define PMU_DEBUG_XXTI 0x1000 -/* Mask bit[12:8] for xxti clock selection */ -#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 - -/* - * Pmu debug is used for xclkout, enable xclkout with - * source as XXTI - */ -void set_xclkout(void); - -/* - * Read inform1 to get the reset status. - * @return: the value can be either S5P_CHECK_SLEEP or - * S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1 - * if none of these then its normal booting. - */ -uint32_t get_reset_status(void); - - -/* Read the resume function and call it */ -void power_exit_wakeup(void); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm.h deleted file mode 100644 index 43474c34b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PWM_H_ -#define __ASM_ARM_ARCH_PWM_H_ - -#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ -#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ - -/* Divider MUX */ -#define MUX_DIV_1 0 /* 1/1 period */ -#define MUX_DIV_2 1 /* 1/2 period */ -#define MUX_DIV_4 2 /* 1/4 period */ -#define MUX_DIV_8 3 /* 1/8 period */ -#define MUX_DIV_16 4 /* 1/16 period */ - -#define MUX_DIV_SHIFT(x) (x * 4) - -#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) - -#define TCON_START(x) (1 << TCON_OFFSET(x)) -#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) -#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) -#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) -#define TCON4_AUTO_RELOAD (1 << 22) - -#ifndef __ASSEMBLY__ -struct s5p_timer { - unsigned int tcfg0; - unsigned int tcfg1; - unsigned int tcon; - unsigned int tcntb0; - unsigned int tcmpb0; - unsigned int tcnto0; - unsigned int tcntb1; - unsigned int tcmpb1; - unsigned int tcnto1; - unsigned int tcntb2; - unsigned int tcmpb2; - unsigned int tcnto2; - unsigned int tcntb3; - unsigned int tcmpb3; - unsigned int tcnto3; - unsigned int tcntb4; - unsigned int tcnto4; - unsigned int tintcstat; -}; -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm_backlight.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm_backlight.h deleted file mode 100644 index 4f54fa737..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm_backlight.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Author: Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PWM_BACKLIGHT_H_ -#define _PWM_BACKLIGHT_H_ - -struct pwm_backlight_data { - int pwm_id; - int period; - int max_brightness; - int brightness; -}; - -extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd); - -#endif /* _PWM_BACKLIGHT_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sound.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sound.h deleted file mode 100644 index bff57c691..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sound.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics - * Rajeshwari Shinde <rajeshwari.s@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __SOUND_ARCH_H__ -#define __SOUND_ARCH_H__ - -/* I2S values */ -#define I2S_PLL_CLK 192000000 -#define I2S_SAMPLING_RATE 48000 -#define I2S_BITS_PER_SAMPLE 16 -#define I2S_CHANNELS 2 -#define I2S_RFS 256 -#define I2S_BFS 32 - -/* I2C values */ -#define AUDIO_I2C_BUS 1 -#define AUDIO_I2C_REG 0x1a - -/* Audio Codec */ -#define AUDIO_CODEC "wm8994" - -#define AUDIO_COMPAT 1 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spi.h deleted file mode 100644 index 0ba931b7e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spi.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2012 SAMSUNG Electronics - * Padmavathi Venna <padma.v@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_ -#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_ - -#ifndef __ASSEMBLY__ - -/* SPI peripheral register map; padded to 64KB */ -struct exynos_spi { - unsigned int ch_cfg; /* 0x00 */ - unsigned char reserved0[4]; - unsigned int mode_cfg; /* 0x08 */ - unsigned int cs_reg; /* 0x0c */ - unsigned char reserved1[4]; - unsigned int spi_sts; /* 0x14 */ - unsigned int tx_data; /* 0x18 */ - unsigned int rx_data; /* 0x1c */ - unsigned int pkt_cnt; /* 0x20 */ - unsigned char reserved2[4]; - unsigned int swap_cfg; /* 0x28 */ - unsigned int fb_clk; /* 0x2c */ - unsigned char padding[0xffd0]; -}; - -#define EXYNOS_SPI_MAX_FREQ 50000000 - -#define SPI_TIMEOUT_MS 10 -#define SF_READ_DATA_CMD 0x3 - -/* SPI_CHCFG */ -#define SPI_CH_HS_EN (1 << 6) -#define SPI_CH_RST (1 << 5) -#define SPI_SLAVE_MODE (1 << 4) -#define SPI_CH_CPOL_L (1 << 3) -#define SPI_CH_CPHA_B (1 << 2) -#define SPI_RX_CH_ON (1 << 1) -#define SPI_TX_CH_ON (1 << 0) - -/* SPI_MODECFG */ -#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29) -#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17) - -/* SPI_CSREG */ -#define SPI_SLAVE_SIG_INACT (1 << 0) - -/* SPI_STS */ -#define SPI_ST_TX_DONE (1 << 25) -#define SPI_FIFO_LVL_MASK 0x1ff -#define SPI_TX_LVL_OFFSET 6 -#define SPI_RX_LVL_OFFSET 15 - -/* Feedback Delay */ -#define SPI_CLK_BYPASS (0 << 0) -#define SPI_FB_DELAY_90 (1 << 0) -#define SPI_FB_DELAY_180 (2 << 0) -#define SPI_FB_DELAY_270 (3 << 0) - -/* Packet Count */ -#define SPI_PACKET_CNT_EN (1 << 16) - -/* Swap config */ -#define SPI_TX_SWAP_EN (1 << 0) -#define SPI_TX_BYTE_SWAP (1 << 2) -#define SPI_TX_HWORD_SWAP (1 << 3) -#define SPI_TX_BYTE_SWAP (1 << 2) -#define SPI_RX_SWAP_EN (1 << 4) -#define SPI_RX_BYTE_SWAP (1 << 6) -#define SPI_RX_HWORD_SWAP (1 << 7) - -#endif /* __ASSEMBLY__ */ -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h deleted file mode 100644 index b1d68c3d2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_EXYNOS_SPL_H__ -#define __ASM_ARCH_EXYNOS_SPL_H__ - -#include <asm/arch-exynos/dmc.h> - -enum boot_mode { - /* - * Assign the OM pin values for respective boot modes. - * Exynos4 does not support spi boot and the mmc boot OM - * pin values are the same across Exynos4 and Exynos5. - */ - BOOT_MODE_MMC = 4, - BOOT_MODE_EMMC = 8, /* EMMC4.4 */ - BOOT_MODE_SERIAL = 20, - /* Boot based on Operating Mode pin settings */ - BOOT_MODE_OM = 32, - BOOT_MODE_USB, /* Boot using USB download */ -}; - -#ifndef __ASSEMBLY__ -/* Parameters of early board initialization in SPL */ -struct spl_machine_param { - /* Add fields as and when required */ - u32 signature; - u32 version; /* Version number */ - u32 size; /* Size of block */ - /** - * Parameters we expect, in order, terminated with \0. Each parameter - * is a single character representing one 32-bit word in this - * structure. - * - * Valid characters in this string are: - * - * Code Name - * v mem_iv_size - * m mem_type - * u uboot_size - * b boot_source - * f frequency_mhz (memory frequency in MHz) - * a ARM clock frequency in MHz - * s serial base address - * i i2c base address for early access (meant for PMIC) - * r board rev GPIO numbers used to read board revision - * (lower halfword=bit 0, upper=bit 1) - * M Memory Manufacturer name - * \0 termination - */ - char params[12]; /* Length must be word-aligned */ - u32 mem_iv_size; /* Memory channel interleaving size */ - enum ddr_mode mem_type; /* Type of on-board memory */ - /* - * U-boot size - The iROM mmc copy function used by the SPL takes a - * block count paramter to describe the u-boot size unlike the spi - * boot copy function which just uses the u-boot size directly. Align - * the u-boot size to block size (512 bytes) when populating the SPL - * table only for mmc boot. - */ - u32 uboot_size; - enum boot_mode boot_source; /* Boot device */ - unsigned frequency_mhz; /* Frequency of memory in MHz */ - unsigned arm_freq_mhz; /* ARM Frequency in MHz */ - u32 serial_base; /* Serial base address */ - u32 i2c_base; /* i2c base address */ - u32 board_rev_gpios; /* Board revision GPIOs */ - enum mem_manuf mem_manuf; /* Memory Manufacturer */ -} __attribute__((__packed__)); -#endif - -/** - * Validate signature and return a pointer to the parameter table. If the - * signature is invalid, call panic() and never return. - * - * @return pointer to the parameter table if signature matched or never return. - */ -struct spl_machine_param *spl_get_machine_params(void); - -#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sromc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sromc.h deleted file mode 100644 index 7f584033b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sromc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Naveen Krishna Ch <ch.naveen@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Note: This file contains the register description for SROMC - */ - -#ifndef __ASM_ARCH_SROMC_H_ -#define __ASM_ARCH_SROMC_H_ - -#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) -#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ - /* 1-> Byte base address*/ -#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) -#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) - -#define SROMC_BC_TACS(x) (x << 28) /* address set-up */ -#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ -#define SROMC_BC_TACC(x) (x << 16) /* access cycle */ -#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ -#define SROMC_BC_TAH(x) (x << 8) /* address holding time */ -#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ -#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ - -#ifndef __ASSEMBLY__ -struct s5p_sromc { - unsigned int bw; - unsigned int bc[4]; -}; -#endif /* __ASSEMBLY__ */ - -/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); - -enum { - FDT_SROM_PMC, - FDT_SROM_TACP, - FDT_SROM_TAH, - FDT_SROM_TCOH, - FDT_SROM_TACC, - FDT_SROM_TCOS, - FDT_SROM_TACS, - - FDT_SROM_TIMING_COUNT, -}; - -struct fdt_sromc { - u8 bank; /* srom bank number */ - u8 width; /* bus width in bytes */ - unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ -}; - -#endif /* __ASM_ARCH_SROMC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sys_proto.h deleted file mode 100644 index 83ae42a74..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sys_proto.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2010 Samsung Electrnoics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_device_type(void); -void invalidate_dcache(u32); -void l2_cache_disable(void); -void l2_cache_enable(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/system.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/system.h deleted file mode 100644 index 7e2057ca6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/system.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * Donghwa Lee <dh09.lee@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_SYSTEM_H_ -#define __ASM_ARM_ARCH_SYSTEM_H_ - -#ifndef __ASSEMBLY__ -struct exynos4_sysreg { - unsigned char res1[0x210]; - unsigned int display_ctrl; - unsigned int display_ctrl2; - unsigned int camera_control; - unsigned int audio_endian; - unsigned int jtag_con; -}; - -struct exynos5_sysreg { - unsigned char res1[0x214]; - unsigned int disp1blk_cfg; - unsigned int disp2blk_cfg; - unsigned int hdcp_e_fuse; - unsigned int gsclblk_cfg0; - unsigned int gsclblk_cfg1; - unsigned int reserved; - unsigned int ispblk_cfg; - unsigned int usb20phy_cfg; - unsigned char res2[0x29c]; - unsigned int mipi_dphy; - unsigned int dptx_dphy; - unsigned int phyclk_sel; -}; -#endif - -#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) - -void set_usbhost_mode(unsigned int mode); -void set_system_display_ctrl(void); - -#endif /* _EXYNOS4_SYSTEM_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tmu.h deleted file mode 100644 index cad35694f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tmu.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Akshay Saraswat <akshay.s@samsung.com> - * - * EXYNOS - Thermal Management Unit - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_TMU_H -#define __ASM_ARCH_TMU_H - -struct exynos5_tmu_reg { - u32 triminfo; - u32 rsvd1[4]; - u32 triminfo_control; - u32 rsvd5[2]; - u32 tmu_control; - u32 rsvd7; - u32 tmu_status; - u32 sampling_internal; - u32 counter_value0; - u32 counter_value1; - u32 rsvd8[2]; - u32 current_temp; - u32 rsvd10[3]; - u32 threshold_temp_rise; - u32 threshold_temp_fall; - u32 rsvd13[2]; - u32 past_temp3_0; - u32 past_temp7_4; - u32 past_temp11_8; - u32 past_temp15_12; - u32 inten; - u32 intstat; - u32 intclear; - u32 rsvd15; - u32 emul_con; -}; -#endif /* __ASM_ARCH_TMU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tzpc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tzpc.h deleted file mode 100644 index 0a4be2391..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tzpc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2012 Samsung Electronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __TZPC_H_ -#define __TZPC_H_ - -#ifndef __ASSEMBLY__ -struct exynos_tzpc { - unsigned int r0size; - char res1[0x7FC]; - unsigned int decprot0stat; - unsigned int decprot0set; - unsigned int decprot0clr; - unsigned int decprot1stat; - unsigned int decprot1set; - unsigned int decprot1clr; - unsigned int decprot2stat; - unsigned int decprot2set; - unsigned int decprot2clr; - unsigned int decprot3stat; - unsigned int decprot3set; - unsigned int decprot3clr; - char res2[0x7B0]; - unsigned int periphid0; - unsigned int periphid1; - unsigned int periphid2; - unsigned int periphid3; - unsigned int pcellid0; - unsigned int pcellid1; - unsigned int pcellid2; - unsigned int pcellid3; -}; - -#define EXYNOS4_NR_TZPC_BANKS 6 -#define EXYNOS5_NR_TZPC_BANKS 10 - -/* TZPC : Register Offsets */ -#define TZPC_BASE_OFFSET 0x10000 - -/* - * TZPC Register Value : - * R0SIZE: 0x0 : Size of secured ram - */ -#define R0SIZE 0x0 - -/* - * TZPC Decode Protection Register Value : - * DECPROTXSET: 0xFF : Set Decode region to non-secure - */ -#define DECPROTXSET 0xFF -void tzpc_init(void); - -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/uart.h deleted file mode 100644 index 33d6ba3b6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/uart.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_UART_H_ -#define __ASM_ARCH_UART_H_ - -#ifndef __ASSEMBLY__ -/* baudrate rest value */ -union br_rest { - unsigned short slot; /* udivslot */ - unsigned char value; /* ufracval */ -}; - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - union br_rest rest; - unsigned char res3[0xffd0]; -}; - -static inline int s5p_uart_divslot(void) -{ - return 0; -} - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/watchdog.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/watchdog.h deleted file mode 100644 index eb6410906..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/watchdog.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_WATCHDOG_H_ -#define __ASM_ARM_ARCH_WATCHDOG_H_ - -#define WTCON_RESET_OFFSET 0 -#define WTCON_INTEN_OFFSET 2 -#define WTCON_CLKSEL_OFFSET 3 -#define WTCON_EN_OFFSET 5 -#define WTCON_PRE_OFFSET 8 - -#define WTCON_CLK_16 0x0 -#define WTCON_CLK_32 0x1 -#define WTCON_CLK_64 0x2 -#define WTCON_CLK_128 0x3 - -#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) -#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) -#define WTCON_EN (0x1 << WTCON_EN_OFFSET) -#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) -#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) - -#ifndef __ASSEMBLY__ -struct s5p_watchdog { - unsigned int wtcon; - unsigned int wtdat; - unsigned int wtcnt; - unsigned int wtclrint; -}; - -/* functions */ -void wdt_stop(void); -void wdt_start(unsigned int timeout); -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/xhci-exynos.h deleted file mode 100644 index 92b90a462..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/xhci-exynos.h +++ /dev/null @@ -1,88 +0,0 @@ -/* Copyright (c) 2012 Samsung Electronics Co. Ltd - * - * Exynos Phy register definitions - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_XHCI_EXYNOS_H_ -#define _ASM_ARCH_XHCI_EXYNOS_H_ - -/* Phy register MACRO definitions */ - -#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) -#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) -#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) - -#define PHYUTMI_OTGDISABLE (1 << 6) -#define PHYUTMI_FORCESUSPEND (1 << 1) -#define PHYUTMI_FORCESLEEP (1 << 0) - -#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) -#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) - -#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) -#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) - -#define PHYCLKRST_SSC_EN (0x1 << 20) -#define PHYCLKRST_REF_SSP_EN (0x1 << 19) -#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) - -#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) - -#define PHYCLKRST_FSEL_MASK (0x3f << 5) -#define PHYCLKRST_FSEL(_x) ((_x) << 5) -#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) -#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) -#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) -#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) - -#define PHYCLKRST_RETENABLEN (0x1 << 4) - -#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) -#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) -#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) - -#define PHYCLKRST_PORTRESET (0x1 << 1) -#define PHYCLKRST_COMMONONN (0x1 << 0) - -#define PHYPARAM0_REF_USE_PAD (0x1 << 31) -#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) -#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) - -#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) -#define PHYPARAM1_PCS_TXDEEMPH (0x1c) - -#define PHYTEST_POWERDOWN_SSP (0x1 << 3) -#define PHYTEST_POWERDOWN_HSP (0x1 << 2) - -#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) - -#define FSEL_CLKSEL_24M (0x5) - -/* XHCI PHY register structure */ -struct exynos_usb3_phy { - unsigned int reserve1; - unsigned int link_system; - unsigned int phy_utmi; - unsigned int phy_pipe; - unsigned int phy_clk_rst; - unsigned int phy_reg0; - unsigned int phy_reg1; - unsigned int phy_param0; - unsigned int phy_param1; - unsigned int phy_term; - unsigned int phy_test; - unsigned int phy_adp; - unsigned int phy_batchg; - unsigned int phy_resume; - unsigned int reserve2[3]; - unsigned int link_port; -}; - -#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h deleted file mode 100644 index a35940e64..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 -#define MXC_CPU_MX6D 0x64 diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/imx-regs.h deleted file mode 100644 index 4de0779d2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/imx-regs.h +++ /dev/null @@ -1,637 +0,0 @@ -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#define ARCH_MXC - -/* ------------------------------------------------------------------------ - * Motorola IMX system registers - * ------------------------------------------------------------------------ - * - */ - -#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) - -# ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# define __REG2(x,y) ((x)+(y)) -#endif - -#define IMX_IO_BASE 0x00200000 - -/* - * Register BASEs, based on OFFSETs - * - */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) - -/* Watchdog Registers*/ - -#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ -#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ - -/* SYSCTRL Registers */ -#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ -#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ -#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ - -/* Chip Select Registers */ -#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ -#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ -#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ -#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ -#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ -#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ -#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ -#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ -#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ -#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ -#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ -#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ -#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ - -/* SDRAM controller registers */ - -#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ -#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ -#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ - -/* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define CSCR_SPLL_RESTART (1<<22) -#define CSCR_MPLL_RESTART (1<<21) -#define CSCR_SYSTEM_SEL (1<<16) -#define CSCR_BCLK_DIV (0xf<<10) -#define CSCR_MPU_PRESC (1<<15) -#define CSCR_SPEN (1<<1) -#define CSCR_MPEN (1<<0) - -#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ - -/* - * GPIO Module and I/O Multiplexer - * x = 0..3 for reg_A, reg_B, reg_C, reg_D - */ -#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) -#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) -#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) -#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) -#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) -#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) -#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) -#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) -#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) -#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) -#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) -#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) -#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) -#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) -#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) -#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) -#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) - -#define GPIO_PORT_MAX 3 - -#define GPIO_PIN_MASK 0x1f -#define GPIO_PORT_MASK (0x3 << 5) - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORTA (0<<5) -#define GPIO_PORTB (1<<5) -#define GPIO_PORTC (2<<5) -#define GPIO_PORTD (3<<5) - -#define GPIO_OUT (1<<7) -#define GPIO_IN (0<<7) -#define GPIO_PUEN (1<<8) - -#define GPIO_PF (0<<9) -#define GPIO_AF (1<<9) - -#define GPIO_OCR_SHIFT 10 -#define GPIO_OCR_MASK (3<<10) -#define GPIO_AIN (0<<10) -#define GPIO_BIN (1<<10) -#define GPIO_CIN (2<<10) -#define GPIO_DR (3<<10) - -#define GPIO_AOUT_SHIFT 12 -#define GPIO_AOUT_MASK (3<<12) -#define GPIO_AOUT (0<<12) -#define GPIO_AOUT_ISR (1<<12) -#define GPIO_AOUT_0 (2<<12) -#define GPIO_AOUT_1 (3<<12) - -#define GPIO_BOUT_SHIFT 14 -#define GPIO_BOUT_MASK (3<<14) -#define GPIO_BOUT (0<<14) -#define GPIO_BOUT_ISR (1<<14) -#define GPIO_BOUT_0 (2<<14) -#define GPIO_BOUT_1 (3<<14) - -#define GPIO_GIUS (1<<16) - -/* assignements for GPIO alternate/primary functions */ - -/* FIXME: This list is not completed. The correct directions are - * missing on some (many) pins - */ -#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) -#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) -#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) -#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) -#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) -#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) -#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) -#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) -#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) -#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) -#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) -#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) -#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) -#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) -#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) -#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) -#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) -#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) -#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) -#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) -#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) -#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) -#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) -#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) -#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) -#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) -#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) -#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) -#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) -#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) -#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) -#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) -#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) -#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) -#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) -#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) -#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) -#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) -#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) -#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) -#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) -#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) -#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) -#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) -#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) -#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) -#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) -#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) -#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) -#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) -#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) -#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) -#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) -#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) -#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) -#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) -#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) -#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) -#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) -#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) -#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) -#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) -#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) -#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) -#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) -#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) -#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) -#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) -#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) -#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) -#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) -#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) -#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) -#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) -#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) -#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) -#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) -#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) -#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) -#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) -#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) -#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) -#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) -#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) -#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) -#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) -#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) -#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) -#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) -#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) -#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) -#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) -#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) -#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) -#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) -#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) -#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) -#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) -#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) -#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) -#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) -#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) -#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) -#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) -#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) -#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) -#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) -#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) -#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) -#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) -#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) -#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) -#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) -#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) -#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) - -/* - * PWM controller - */ -#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ -#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ -#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ -#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ - -#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ -#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ -#define PWMC_SWR (0x01<<16) /* Software Reset */ -#define PWMC_CLKSRC (0x01<<15) /* Clock Source */ -#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ -#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ -#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ -#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ -#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ -#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ -#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ - -#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ -#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ -#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ - -/* - * DMA Controller - */ -#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ -#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ -#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ -#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ -#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ -#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ -#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ -#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ -#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ -#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ -#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ -#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ -#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ -#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ -#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ -#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ -#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ -#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ -#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ -#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ -#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ -#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ - -/* TODO: define DMA_REQ lines */ - -#define DCR_DRST (1<<1) -#define DCR_DEN (1<<0) -#define DBTOCR_EN (1<<15) -#define DBTOCR_CNT(x) ((x) & 0x7fff ) -#define CNTR_CNT(x) ((x) & 0xffffff ) -#define CCR_DMOD_LINEAR ( 0x0 << 12 ) -#define CCR_DMOD_2D ( 0x1 << 12 ) -#define CCR_DMOD_FIFO ( 0x2 << 12 ) -#define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) -#define CCR_SMOD_LINEAR ( 0x0 << 10 ) -#define CCR_SMOD_2D ( 0x1 << 10 ) -#define CCR_SMOD_FIFO ( 0x2 << 10 ) -#define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) -#define CCR_MDIR_DEC (1<<9) -#define CCR_MSEL_B (1<<8) -#define CCR_DSIZ_32 ( 0x0 << 6 ) -#define CCR_DSIZ_8 ( 0x1 << 6 ) -#define CCR_DSIZ_16 ( 0x2 << 6 ) -#define CCR_SSIZ_32 ( 0x0 << 4 ) -#define CCR_SSIZ_8 ( 0x1 << 4 ) -#define CCR_SSIZ_16 ( 0x2 << 4 ) -#define CCR_REN (1<<3) -#define CCR_RPT (1<<2) -#define CCR_FRC (1<<1) -#define CCR_CEN (1<<0) -#define RTOR_EN (1<<15) -#define RTOR_CLK (1<<14) -#define RTOR_PSC (1<<13) - -/* - * LCD Controller - */ - -#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) - -#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) -#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) -#define SIZE_YMAX(y) ( (y) & 0x1ff ) - -#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) -#define VPW_VPW(x) ( (x) & 0x3ff ) - -#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) -#define CPOS_CC1 (1<<31) -#define CPOS_CC0 (1<<30) -#define CPOS_OP (1<<28) -#define CPOS_CXP(x) (((x) & 3ff) << 16) -#define CPOS_CYP(y) ((y) & 0x1ff) - -#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) -#define LCWHB_BK_EN (1<<31) -#define LCWHB_CW(w) (((w) & 0x1f) << 24) -#define LCWHB_CH(h) (((h) & 0x1f) << 16) -#define LCWHB_BD(x) ((x) & 0xff) - -#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) -#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) -#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) -#define LCHCC_CUR_COL_B(b) ((b) & 0x1f) - -#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) -#define PCR_TFT (1<<31) -#define PCR_COLOR (1<<30) -#define PCR_PBSIZ_1 (0<<28) -#define PCR_PBSIZ_2 (1<<28) -#define PCR_PBSIZ_4 (2<<28) -#define PCR_PBSIZ_8 (3<<28) -#define PCR_BPIX_1 (0<<25) -#define PCR_BPIX_2 (1<<25) -#define PCR_BPIX_4 (2<<25) -#define PCR_BPIX_8 (3<<25) -#define PCR_BPIX_12 (4<<25) -#define PCR_BPIX_16 (4<<25) -#define PCR_PIXPOL (1<<24) -#define PCR_FLMPOL (1<<23) -#define PCR_LPPOL (1<<22) -#define PCR_CLKPOL (1<<21) -#define PCR_OEPOL (1<<20) -#define PCR_SCLKIDLE (1<<19) -#define PCR_END_SEL (1<<18) -#define PCR_END_BYTE_SWAP (1<<17) -#define PCR_REV_VS (1<<16) -#define PCR_ACD_SEL (1<<15) -#define PCR_ACD(x) (((x) & 0x7f) << 8) -#define PCR_SCLK_SEL (1<<7) -#define PCR_SHARP (1<<6) -#define PCR_PCD(x) ((x) & 0x3f) - -#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) -#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) -#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) -#define HCR_H_WAIT_2(x) ((x) & 0xff) - -#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) -#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) -#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) -#define VCR_V_WAIT_2(x) ((x) & 0xff) - -#define LCDC_POS __REG(IMX_LCDC_BASE+0x24) -#define POS_POS(x) ((x) & 1f) - -#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) -#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) -#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) -#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) -#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) -#define LSCR1_GRAY1(x) (((x) & 0xf)) - -#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) -#define PWMR_CLS(x) (((x) & 0x1ff) << 16) -#define PWMR_LDMSK (1<<15) -#define PWMR_SCR1 (1<<10) -#define PWMR_SCR0 (1<<9) -#define PWMR_CC_EN (1<<8) -#define PWMR_PW(x) ((x) & 0xff) - -#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) -#define DMACR_BURST (1<<31) -#define DMACR_HM(x) (((x) & 0xf) << 16) -#define DMACR_TM(x) ((x) &0xf) - -#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) -#define RMCR_LCDC_EN (1<<1) -#define RMCR_SELF_REF (1<<0) - -#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) -#define LCDICR_INT_SYN (1<<2) -#define LCDICR_INT_CON (1) - -#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) -#define LCDISR_UDR_ERR (1<<3) -#define LCDISR_ERR_RES (1<<2) -#define LCDISR_EOF (1<<1) -#define LCDISR_BOF (1<<0) -/* - * UART Module - */ -#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */ -#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */ -#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */ -#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */ -#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */ -#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */ -#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */ -#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */ -#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */ -#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */ -#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */ -#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */ -#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */ -#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */ -#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */ -#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */ -#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */ -#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */ -#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */ -#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */ -#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */ -#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */ -#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */ - -/* UART Control Register Bit Fields.*/ -#define URXD_CHARRDY (1<<15) -#define URXD_ERR (1<<14) -#define URXD_OVRRUN (1<<13) -#define URXD_FRMERR (1<<12) -#define URXD_BRK (1<<11) -#define URXD_PRERR (1<<10) -#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ -#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ -#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ -#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ -#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ -#define UCR1_IREN (1<<7) /* Infrared interface enable */ -#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ -#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ -#define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ -#define UCR1_DOZE (1<<1) /* Doze */ -#define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ -#define UCR2_CTS (1<<12) /* Clear to send */ -#define UCR2_ESCEN (1<<11) /* Escape enable */ -#define UCR2_PREN (1<<8) /* Parity enable */ -#define UCR2_PROE (1<<7) /* Parity odd/even */ -#define UCR2_STPB (1<<6) /* Stop */ -#define UCR2_WS (1<<5) /* Word size */ -#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ -#define UCR2_TXEN (1<<2) /* Transmitter enabled */ -#define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ -#define UCR3_PARERREN (1<<12) /* Parity enable */ -#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ -#define UCR3_DSR (1<<10) /* Data set ready */ -#define UCR3_DCD (1<<9) /* Data carrier detect */ -#define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ -#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ -#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ -#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ -#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ -#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ -#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ -#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ -#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ -#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ -#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ -#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ -#define USR2_ORE (1<<1) /* Overrun error */ -#define USR2_RDR (1<<0) /* Recv data ready */ -#define UTS_FRCPERR (1<<13) /* Force parity error */ -#define UTS_LOOP (1<<12) /* Loop tx and rx */ -#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ -#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ -#define UTS_SOFTRST (1<<0) /* Software reset */ - -/* General purpose timers registers */ -#define TCTL1 __REG(IMX_TIM1_BASE) -#define TPRER1 __REG(IMX_TIM1_BASE + 0x4) -#define TCMP1 __REG(IMX_TIM1_BASE + 0x8) -#define TCR1 __REG(IMX_TIM1_BASE + 0xc) -#define TCN1 __REG(IMX_TIM1_BASE + 0x10) -#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14) -#define TCTL2 __REG(IMX_TIM2_BASE) -#define TPRER2 __REG(IMX_TIM2_BASE + 0x4) -#define TCMP2 __REG(IMX_TIM2_BASE + 0x8) -#define TCR2 __REG(IMX_TIM2_BASE + 0xc) -#define TCN2 __REG(IMX_TIM2_BASE + 0x10) -#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14) - -/* General purpose timers bitfields */ -#define TCTL_SWR (1<<15) /* Software reset */ -#define TCTL_FRR (1<<8) /* Freerun / restart */ -#define TCTL_CAP (3<<6) /* Capture Edge */ -#define TCTL_OM (1<<5) /* output mode */ -#define TCTL_IRQEN (1<<4) /* interrupt enable */ -#define TCTL_CLKSOURCE (7<<1) /* Clock source */ -#define TCTL_TEN (1) /* Timer enable */ -#define TPRER_PRES (0xff) /* Prescale */ -#define TSTAT_CAPT (1<<1) /* Capture event */ -#define TSTAT_COMP (1) /* Compare event */ - -#endif /* _IMX_REGS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock-k2hk.h deleted file mode 100644 index 6a69a8d2b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * K2HK: Clock management APIs - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_K2HK_H -#define __ASM_ARCH_CLOCK_K2HK_H - -#include <asm/arch/hardware.h> - -#ifndef __ASSEMBLY__ - -enum ext_clk_e { - sys_clk, - alt_core_clk, - pa_clk, - tetris_clk, - ddr3a_clk, - ddr3b_clk, - mcm_clk, - pcie_clk, - sgmii_srio_clk, - xgmii_clk, - usb_clk, - rp1_clk, - ext_clk_count /* number of external clocks */ -}; - -extern unsigned int external_clk[ext_clk_count]; - -enum clk_e { - core_pll_clk, - pass_pll_clk, - tetris_pll_clk, - ddr3a_pll_clk, - ddr3b_pll_clk, - sys_clk0_clk, - sys_clk0_1_clk, - sys_clk0_2_clk, - sys_clk0_3_clk, - sys_clk0_4_clk, - sys_clk0_6_clk, - sys_clk0_8_clk, - sys_clk0_12_clk, - sys_clk0_24_clk, - sys_clk1_clk, - sys_clk1_3_clk, - sys_clk1_4_clk, - sys_clk1_6_clk, - sys_clk1_12_clk, - sys_clk2_clk, - sys_clk3_clk -}; - -#define K2HK_CLK1_6 sys_clk0_6_clk - -/* PLL identifiers */ -enum pll_type_e { - CORE_PLL, - PASS_PLL, - TETRIS_PLL, - DDR3A_PLL, - DDR3B_PLL, -}; -#define MAIN_PLL CORE_PLL - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int pll_m; /* PLL Multiplier */ - int pll_d; /* PLL divider */ - int pll_od; /* PLL output divider */ -}; - -#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} -#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} -#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} -#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} -#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} -#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} -#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} -#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} -#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} -#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} -#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} -#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} -#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} -#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} -#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} -#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} -#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} -#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} -#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} -#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} -#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} - -void init_plls(int num_pll, struct pll_init_data *config); -void init_pll(const struct pll_init_data *data); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock.h deleted file mode 100644 index 324501b75..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * keystone2: common clock header file - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#ifdef CONFIG_SOC_K2HK -#include <asm/arch/clock-k2hk.h> -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock_defs.h deleted file mode 100644 index b251aff38..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock_defs.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * keystone2: common pll clock definitions - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CLOCK_DEFS_H_ -#define _CLOCK_DEFS_H_ - -#include <asm/arch/hardware.h> - -#define BIT(x) (1 << (x)) - -/* PLL Control Registers */ -struct pllctl_regs { - u32 ctl; /* 00 */ - u32 ocsel; /* 04 */ - u32 secctl; /* 08 */ - u32 resv0; - u32 mult; /* 10 */ - u32 prediv; /* 14 */ - u32 div1; /* 18 */ - u32 div2; /* 1c */ - u32 div3; /* 20 */ - u32 oscdiv1; /* 24 */ - u32 resv1; /* 28 */ - u32 bpdiv; /* 2c */ - u32 wakeup; /* 30 */ - u32 resv2; - u32 cmd; /* 38 */ - u32 stat; /* 3c */ - u32 alnctl; /* 40 */ - u32 dchange; /* 44 */ - u32 cken; /* 48 */ - u32 ckstat; /* 4c */ - u32 systat; /* 50 */ - u32 ckctl; /* 54 */ - u32 resv3[2]; - u32 div4; /* 60 */ - u32 div5; /* 64 */ - u32 div6; /* 68 */ - u32 div7; /* 6c */ - u32 div8; /* 70 */ - u32 div9; /* 74 */ - u32 div10; /* 78 */ - u32 div11; /* 7c */ - u32 div12; /* 80 */ -}; - -static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(CLOCK_BASE + 0x100) -}; - -#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) -#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) -#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) - -#define pllctl_reg_rmw(pll, reg, mask, val) \ - pllctl_reg_write(pll, reg, \ - (pllctl_reg_read(pll, reg) & ~(mask)) | val) - -#define pllctl_reg_setbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, 0, mask) - -#define pllctl_reg_clrbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, mask, 0) - -#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) - -/* PLLCTL Bits */ -#define PLLCTL_BYPASS BIT(23) -#define PLL_PLLRST BIT(14) -#define PLLCTL_PAPLL BIT(13) -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_ENSAT BIT(6) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) -#define PLLSTAT_GO BIT(0) - -#define MAIN_ENSAT_OFFSET 6 - -#define PLLDIV_ENABLE BIT(15) - -#define PLL_DIV_MASK 0x3f -#define PLL_MULT_MASK 0x1fff -#define PLL_MULT_SHIFT 6 -#define PLLM_MULT_HI_MASK 0x7f -#define PLLM_MULT_HI_SHIFT 12 -#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) -#define PLLM_MULT_LO_MASK 0x3f -#define PLL_CLKOD_MASK 0xf -#define PLL_CLKOD_SHIFT 19 -#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) -#define PLL_BWADJ_LO_MASK 0xff -#define PLL_BWADJ_LO_SHIFT 24 -#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) -#define PLL_BWADJ_HI_MASK 0xf - -#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17) - -#endif /* _CLOCK_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emac_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emac_defs.h deleted file mode 100644 index 0aa2f89d7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emac_defs.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * emac definitions for keystone2 devices - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EMAC_DEFS_H_ -#define _EMAC_DEFS_H_ - -#include <asm/arch/hardware.h> -#include <asm/io.h> - -#define DEVICE_REG32_R(a) readl(a) -#define DEVICE_REG32_W(a, v) writel(v, a) - -#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900) -#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300) -#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100) - -#define KEYSTONE2_EMAC_GIG_ENABLE - -#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) - -#ifdef CONFIG_SOC_K2HK -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */ -#endif - -/* MII Status Register */ -#define MII_STATUS_REG 1 -#define MII_STATUS_LINK_MASK (0x4) - -/* Marvell 88E1111 PHY ID */ -#define PHY_MARVELL_88E1111 (0x01410cc0) - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 - -struct mac_sl_cfg { - u_int32_t max_rx_len; /* Maximum receive packet length. */ - u_int32_t ctl; /* Control bitfield */ -}; - -/* - * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t - */ -#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24) -#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23) -#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22) -#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18) -#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17) -#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16) -#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15) -#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11) -#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10) -#define GMACSL_ENABLE_GIG_MODE (1 << 7) -#define GMACSL_TX_ENABLE_PACE (1 << 6) -#define GMACSL_ENABLE (1 << 5) -#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4) -#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3) -#define GMACSL_ENABLE_LOOPBACK (1 << 1) -#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0) - -/* - * DEFINTITION: function return values - */ -#define GMACSL_RET_OK 0 -#define GMACSL_RET_INVALID_PORT -1 -#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 -#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 -#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 - -/* Register offsets */ -#define CPGMACSL_REG_ID 0x00 -#define CPGMACSL_REG_CTL 0x04 -#define CPGMACSL_REG_STATUS 0x08 -#define CPGMACSL_REG_RESET 0x0c -#define CPGMACSL_REG_MAXLEN 0x10 -#define CPGMACSL_REG_BOFF 0x14 -#define CPGMACSL_REG_RX_PAUSE 0x18 -#define CPGMACSL_REG_TX_PAURSE 0x1c -#define CPGMACSL_REG_EM_CTL 0x20 -#define CPGMACSL_REG_PRI 0x24 - -/* Soft reset register values */ -#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0) -#define CPGMAC_REG_RESET_VAL_RESET (1 << 0) - -/* Maxlen register values */ -#define CPGMAC_REG_MAXLEN_LEN 0x3fff - -/* Control bitfields */ -#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5) -#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4) -#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3) -#define CPSW_CTL_P0_ENABLE (1 << 2) -#define CPSW_CTL_VLAN_AWARE (1 << 1) -#define CPSW_CTL_FIFO_LOOPBACK (1 << 0) - -#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */ -#define DEVICE_CPSW_BASE (0x02090800) -#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */ -#define SWITCH_MAX_PKT_SIZE 9000 - -/* Register offsets */ -#define CPSW_REG_CTL 0x004 -#define CPSW_REG_STAT_PORT_EN 0x00c -#define CPSW_REG_MAXLEN 0x040 -#define CPSW_REG_ALE_CONTROL 0x608 -#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4) - -/* Register values */ -#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf -#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) -#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) -#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 - -#define SGMII_REG_STATUS_LOCK BIT(4) -#define SGMII_REG_STATUS_LINK BIT(0) -#define SGMII_REG_STATUS_AUTONEG BIT(2) -#define SGMII_REG_CONTROL_AUTONEG BIT(0) -#define SGMII_REG_CONTROL_MASTER BIT(5) -#define SGMII_REG_MR_ADV_ENABLE BIT(0) -#define SGMII_REG_MR_ADV_LINK BIT(15) -#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) -#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) - -#define SGMII_LINK_MAC_MAC_AUTONEG 0 -#define SGMII_LINK_MAC_PHY 1 -#define SGMII_LINK_MAC_MAC_FORCED 2 -#define SGMII_LINK_MAC_FIBER 3 -#define SGMII_LINK_MAC_PHY_FORCED 4 - -#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100 -#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \ - KS2_PASS_BASE + 0x00090200, \ - KS2_PASS_BASE + 0x00090400, \ - KS2_PASS_BASE + 0x00090500} - -#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) - -/* - * SGMII registers - */ -#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000) -#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004) -#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010) -#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014) -#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018) -#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020) -#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030) -#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034) -#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038) - -#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040) -#define DEVICE_N_GMACSL_PORTS 4 -#define DEVICE_EMACSL_RESET_POLL_COUNT 100 - -#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604) - -#ifdef CONFIG_SOC_K2HK -#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606 -#endif - -#define hw_config_streaming_switch() \ - DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \ - DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI); - -/* EMAC MDIO Registers Structure */ -struct mdio_regs { - dv_reg version; - dv_reg control; - dv_reg alive; - dv_reg link; - dv_reg linkintraw; - dv_reg linkintmasked; - u_int8_t rsvd0[8]; - dv_reg userintraw; - dv_reg userintmasked; - dv_reg userintmaskset; - dv_reg userintmaskclear; - u_int8_t rsvd1[80]; - dv_reg useraccess0; - dv_reg userphysel0; - dv_reg useraccess1; - dv_reg userphysel1; -}; - -/* Ethernet MAC Registers Structure */ -struct emac_regs { - dv_reg idver; - dv_reg maccontrol; - dv_reg macstatus; - dv_reg soft_reset; - dv_reg rx_maxlen; - u32 rsvd0; - dv_reg rx_pause; - dv_reg tx_pause; - dv_reg emcontrol; - dv_reg pri_map; - u32 rsvd1[6]; -}; - -#define SGMII_ACCESS(port, reg) \ - *((volatile unsigned int *)(sgmiis[port] + reg)) - -struct eth_priv_t { - char int_name[32]; - int rx_flow; - int phy_addr; - int slave_port; - int sgmii_link_type; -}; - -extern struct eth_priv_t eth_priv_cfg[]; - -int keystone2_emac_initialize(struct eth_priv_t *eth_priv); -void sgmii_serdes_setup_156p25mhz(void); -void sgmii_serdes_shutdown(void); - -#endif /* _EMAC_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emif_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emif_defs.h deleted file mode 100644 index a3378aa30..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emif_defs.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * emif definitions to re-use davinci emif driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include <asm/arch/hardware.h> - -struct davinci_emif_regs { - uint32_t ercsr; - uint32_t awccr; - uint32_t sdbcr; - uint32_t sdrcr; - uint32_t abncr[4]; - uint32_t sdtimr; - uint32_t ddrsr; - uint32_t ddrphycr; - uint32_t ddrphysr; - uint32_t totar; - uint32_t totactr; - uint32_t ddrphyid_rev; - uint32_t sdsretr; - uint32_t eirr; - uint32_t eimr; - uint32_t eimsr; - uint32_t eimcr; - uint32_t ioctrlr; - uint32_t iostatr; - uint32_t rsvd0; - uint32_t one_nand_cr; - uint32_t nandfcr; - uint32_t nandfsr; - uint32_t rsvd1[2]; - uint32_t nandfecc[4]; - uint32_t rsvd2[15]; - uint32_t nand4biteccload; - uint32_t nand4bitecc[4]; - uint32_t nanderradd1; - uint32_t nanderradd2; - uint32_t nanderrval1; - uint32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) ((n) << 26) -#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20) -#define DAVINCI_ABCR_WHOLD(n) ((n) << 17) -#define DAVINCI_ABCR_RSETUP(n) ((n) << 13) -#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7) -#define DAVINCI_ABCR_RHOLD(n) ((n) << 4) -#define DAVINCI_ABCR_TA(n) ((n) << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware-k2hk.h deleted file mode 100644 index 50ff13a3b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * K2HK: SoC definitions - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_K2HK_H -#define __ASM_ARCH_HARDWARE_K2HK_H - -#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE -#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000 -#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000 -#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000 - -#define K2HK_PLL_CNTRL_BASE 0x02310000 -#define CLOCK_BASE K2HK_PLL_CNTRL_BASE -#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 - -#define K2HK_PSC_BASE 0x02350000 -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) - -#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) - -#define ARM_PLL_EN BIT(13) - -#define K2HK_SPI0_BASE 0x21000400 -#define K2HK_SPI1_BASE 0x21000600 -#define K2HK_SPI2_BASE 0x21000800 -#define K2HK_SPI_BASE K2HK_SPI0_BASE - -/* Chip configuration unlock codes and registers */ -#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KEYSTONE_KICK0_MAGIC 0x83e70b13 -#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0 - -/* PA SS Registers */ -#define KS2_PASS_BASE 0x02000000 - -/* PLL control registers */ -#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) -#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) -#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) -#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) - -/* Power and Sleep Controller (PSC) Domains */ -#define K2HK_LPSC_MOD 0 -#define K2HK_LPSC_DUMMY1 1 -#define K2HK_LPSC_USB 2 -#define K2HK_LPSC_EMIF25_SPI 3 -#define K2HK_LPSC_TSIP 4 -#define K2HK_LPSC_DEBUGSS_TRC 5 -#define K2HK_LPSC_TETB_TRC 6 -#define K2HK_LPSC_PKTPROC 7 -#define KS2_LPSC_PA K2HK_LPSC_PKTPROC -#define K2HK_LPSC_SGMII 8 -#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII -#define K2HK_LPSC_CRYPTO 9 -#define K2HK_LPSC_PCIE 10 -#define K2HK_LPSC_SRIO 11 -#define K2HK_LPSC_VUSR0 12 -#define K2HK_LPSC_CHIP_SRSS 13 -#define K2HK_LPSC_MSMC 14 -#define K2HK_LPSC_GEM_0 15 -#define K2HK_LPSC_GEM_1 16 -#define K2HK_LPSC_GEM_2 17 -#define K2HK_LPSC_GEM_3 18 -#define K2HK_LPSC_GEM_4 19 -#define K2HK_LPSC_GEM_5 20 -#define K2HK_LPSC_GEM_6 21 -#define K2HK_LPSC_GEM_7 22 -#define K2HK_LPSC_EMIF4F_DDR3A 23 -#define K2HK_LPSC_EMIF4F_DDR3B 24 -#define K2HK_LPSC_TAC 25 -#define K2HK_LPSC_RAC 26 -#define K2HK_LPSC_RAC_1 27 -#define K2HK_LPSC_FFTC_A 28 -#define K2HK_LPSC_FFTC_B 29 -#define K2HK_LPSC_FFTC_C 30 -#define K2HK_LPSC_FFTC_D 31 -#define K2HK_LPSC_FFTC_E 32 -#define K2HK_LPSC_FFTC_F 33 -#define K2HK_LPSC_AI2 34 -#define K2HK_LPSC_TCP3D_0 35 -#define K2HK_LPSC_TCP3D_1 36 -#define K2HK_LPSC_TCP3D_2 37 -#define K2HK_LPSC_TCP3D_3 38 -#define K2HK_LPSC_VCP2X4_A 39 -#define K2HK_LPSC_CP2X4_B 40 -#define K2HK_LPSC_VCP2X4_C 41 -#define K2HK_LPSC_VCP2X4_D 42 -#define K2HK_LPSC_VCP2X4_E 43 -#define K2HK_LPSC_VCP2X4_F 44 -#define K2HK_LPSC_VCP2X4_G 45 -#define K2HK_LPSC_VCP2X4_H 46 -#define K2HK_LPSC_BCP 47 -#define K2HK_LPSC_DXB 48 -#define K2HK_LPSC_VUSR1 49 -#define K2HK_LPSC_XGE 50 -#define K2HK_LPSC_ARM_SREFLEX 51 -#define K2HK_LPSC_TETRIS 52 - -#define K2HK_UART0_BASE 0x02530c00 - -/* DDR3A definitions */ -#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000 -#define K2HK_DDR3A_DDRPHYC 0x02329000 -/* DDR3B definitions */ -#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000 -#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000 -#define K2HK_DDR3B_DDRPHYC 0x02328000 - -/* Queue manager */ -#define DEVICE_QM_MANAGER_BASE 0x02a02000 -#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000 -#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000 -#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000 -#define DEVICE_QM_NUM_LINKRAMS 2 -#define DEVICE_QM_NUM_MEMREGIONS 20 - -#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000 -#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400 -#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800 -#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000 - -#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24 -#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32 -#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9 - -/* MSMC control */ -#define K2HK_MSMC_CTRL_BASE 0x0bc00000 - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware.h deleted file mode 100644 index a305a0cc0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Keystone2: Common SoC definitions, structures etc. - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <config.h> - -#ifndef __ASSEMBLY__ - -#include <linux/sizes.h> -#include <asm/io.h> - -#define REG(addr) (*(volatile unsigned int *)(addr)) -#define REG_P(addr) ((volatile unsigned int *)(addr)) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - -struct ddr3_phy_config { - unsigned int pllcr; - unsigned int pgcr1_mask; - unsigned int pgcr1_val; - unsigned int ptr0; - unsigned int ptr1; - unsigned int ptr2; - unsigned int ptr3; - unsigned int ptr4; - unsigned int dcr_mask; - unsigned int dcr_val; - unsigned int dtpr0; - unsigned int dtpr1; - unsigned int dtpr2; - unsigned int mr0; - unsigned int mr1; - unsigned int mr2; - unsigned int dtcr; - unsigned int pgcr2; - unsigned int zq0cr1; - unsigned int zq1cr1; - unsigned int zq2cr1; - unsigned int pir_v1; - unsigned int pir_v2; -}; - -struct ddr3_emif_config { - unsigned int sdcfg; - unsigned int sdtim1; - unsigned int sdtim2; - unsigned int sdtim3; - unsigned int sdtim4; - unsigned int zqcfg; - unsigned int sdrfc; -}; - -#endif - -#define BIT(x) (1 << (x)) - -#define KS2_DDRPHY_PIR_OFFSET 0x04 -#define KS2_DDRPHY_PGCR0_OFFSET 0x08 -#define KS2_DDRPHY_PGCR1_OFFSET 0x0C -#define KS2_DDRPHY_PGSR0_OFFSET 0x10 -#define KS2_DDRPHY_PGSR1_OFFSET 0x14 -#define KS2_DDRPHY_PLLCR_OFFSET 0x18 -#define KS2_DDRPHY_PTR0_OFFSET 0x1C -#define KS2_DDRPHY_PTR1_OFFSET 0x20 -#define KS2_DDRPHY_PTR2_OFFSET 0x24 -#define KS2_DDRPHY_PTR3_OFFSET 0x28 -#define KS2_DDRPHY_PTR4_OFFSET 0x2C -#define KS2_DDRPHY_DCR_OFFSET 0x44 - -#define KS2_DDRPHY_DTPR0_OFFSET 0x48 -#define KS2_DDRPHY_DTPR1_OFFSET 0x4C -#define KS2_DDRPHY_DTPR2_OFFSET 0x50 - -#define KS2_DDRPHY_MR0_OFFSET 0x54 -#define KS2_DDRPHY_MR1_OFFSET 0x58 -#define KS2_DDRPHY_MR2_OFFSET 0x5C -#define KS2_DDRPHY_DTCR_OFFSET 0x68 -#define KS2_DDRPHY_PGCR2_OFFSET 0x8C - -#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 -#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194 -#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 -#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 - -#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 - -#define IODDRM_MASK 0x00000180 -#define ZCKSEL_MASK 0x01800000 -#define CL_MASK 0x00000072 -#define WR_MASK 0x00000E00 -#define BL_MASK 0x00000003 -#define RRMODE_MASK 0x00040000 -#define UDIMM_MASK 0x20000000 -#define BYTEMASK_MASK 0x0003FC00 -#define MPRDQ_MASK 0x00000080 -#define PDQ_MASK 0x00000070 -#define NOSRA_MASK 0x08000000 -#define ECC_MASK 0x00000001 - -#define KS2_DDR3_MIDR_OFFSET 0x00 -#define KS2_DDR3_STATUS_OFFSET 0x04 -#define KS2_DDR3_SDCFG_OFFSET 0x08 -#define KS2_DDR3_SDRFC_OFFSET 0x10 -#define KS2_DDR3_SDTIM1_OFFSET 0x18 -#define KS2_DDR3_SDTIM2_OFFSET 0x1C -#define KS2_DDR3_SDTIM3_OFFSET 0x20 -#define KS2_DDR3_SDTIM4_OFFSET 0x28 -#define KS2_DDR3_PMCTL_OFFSET 0x38 -#define KS2_DDR3_ZQCFG_OFFSET 0xC8 - -#ifdef CONFIG_SOC_K2HK -#include <asm/arch/hardware-k2hk.h> -#endif - -#ifndef __ASSEMBLY__ -static inline int cpu_is_k2hk(void) -{ - unsigned int jtag_id = __raw_readl(JTAG_ID_REG); - unsigned int part_no = (jtag_id >> 12) & 0xffff; - - return (part_no == 0xb981) ? 1 : 0; -} - -static inline int cpu_revision(void) -{ - unsigned int jtag_id = __raw_readl(JTAG_ID_REG); - unsigned int rev = (jtag_id >> 28) & 0xf; - - return rev; -} - -void share_all_segments(int priv_id); -int cpu_to_bus(u32 *ptr, u32 length); -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); -void init_ddr3(void); -void sdelay(unsigned long); - -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/i2c_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/i2c_defs.h deleted file mode 100644 index d4256526c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/i2c_defs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * keystone: i2c driver definitions - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _I2C_DEFS_H_ -#define _I2C_DEFS_H_ - -#define I2C0_BASE 0x02530000 -#define I2C1_BASE 0x02530400 -#define I2C2_BASE 0x02530800 -#define I2C_BASE I2C0_BASE - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/keystone_nav.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/keystone_nav.h deleted file mode 100644 index ab81eaf1f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/keystone_nav.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Multicore Navigator definitions - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _KEYSTONE_NAV_H_ -#define _KEYSTONE_NAV_H_ - -#include <asm/arch/hardware.h> -#include <asm/io.h> - -enum soc_type_t { - k2hk -}; - -#define QM_OK 0 -#define QM_ERR -1 -#define QM_DESC_TYPE_HOST 0 -#define QM_DESC_PSINFO_IN_DESCR 0 -#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \ - (QM_DESC_PSINFO_IN_DESCR << 22) - -/* Packet Info */ -#define QM_DESC_PINFO_EPIB 1 -#define QM_DESC_PINFO_RETURN_OWN 1 -#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \ - (QM_DESC_PINFO_RETURN_OWN << 15) - -struct qm_cfg_reg { - u32 revision; - u32 __pad1; - u32 divert; - u32 link_ram_base0; - u32 link_ram_size0; - u32 link_ram_base1; - u32 link_ram_size1; - u32 link_ram_base2; - u32 starvation[0]; -}; - -struct descr_mem_setup_reg { - u32 base_addr; - u32 start_idx; - u32 desc_reg_size; - u32 _res0; -}; - -struct qm_reg_queue { - u32 entry_count; - u32 byte_count; - u32 packet_size; - u32 ptr_size_thresh; -}; - -struct qm_config { - /* QM module addresses */ - u32 stat_cfg; /* status and config */ - struct qm_reg_queue *queue; /* management region */ - u32 mngr_vbusm; /* management region (VBUSM) */ - u32 i_lram; /* internal linking RAM */ - struct qm_reg_queue *proxy; - u32 status_ram; - struct qm_cfg_reg *mngr_cfg; - /* Queue manager config region */ - u32 intd_cfg; /* QMSS INTD config region */ - struct descr_mem_setup_reg *desc_mem; - /* descritor memory setup region*/ - u32 region_num; - u32 pdsp_cmd; /* PDSP1 command interface */ - u32 pdsp_ctl; /* PDSP1 control registers */ - u32 pdsp_iram; - /* QM configuration parameters */ - - u32 qpool_num; /* */ -}; - -struct qm_host_desc { - u32 desc_info; - u32 tag_info; - u32 packet_info; - u32 buff_len; - u32 buff_ptr; - u32 next_bdptr; - u32 orig_buff_len; - u32 orig_buff_ptr; - u32 timestamp; - u32 swinfo[3]; - u32 ps_data[20]; -}; - -#define HDESC_NUM 256 - -int qm_init(void); -void qm_close(void); -void qm_push(struct qm_host_desc *hd, u32 qnum); -struct qm_host_desc *qm_pop(u32 qnum); - -void qm_buff_push(struct qm_host_desc *hd, u32 qnum, - void *buff_ptr, u32 buff_len); - -struct qm_host_desc *qm_pop_from_free_pool(void); -void queue_close(u32 qnum); - -/* - * DMA API - */ -#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \ - psloc, sopoff, qmgr, qnum) \ - (((einfo & 1) << 30) | \ - ((psinfo & 1) << 29) | \ - ((rxerr & 1) << 28) | \ - ((desc & 3) << 26) | \ - ((psloc & 1) << 25) | \ - ((sopoff & 0x1ff) << 16) | \ - ((qmgr & 3) << 12) | \ - ((qnum & 0xfff) << 0)) - -#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \ - (((fd0qm & 3) << 28) | \ - ((fd0qnum & 0xfff) << 16) | \ - ((fd1qm & 3) << 12) | \ - ((fd1qnum & 0xfff) << 0)) - -#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31) -#define CPDMA_CHAN_A_TDOWN (1 << 30) -#define TDOWN_TIMEOUT_COUNT 100 - -struct global_ctl_regs { - u32 revision; - u32 perf_control; - u32 emulation_control; - u32 priority_control; - u32 qm_base_addr[4]; -}; - -struct tx_chan_regs { - u32 cfg_a; - u32 cfg_b; - u32 res[6]; -}; - -struct rx_chan_regs { - u32 cfg_a; - u32 res[7]; -}; - -struct rx_flow_regs { - u32 control; - u32 tags; - u32 tag_sel; - u32 fdq_sel[2]; - u32 thresh[3]; -}; - -struct pktdma_cfg { - struct global_ctl_regs *global; - struct tx_chan_regs *tx_ch; - u32 tx_ch_num; - struct rx_chan_regs *rx_ch; - u32 rx_ch_num; - u32 *tx_sched; - struct rx_flow_regs *rx_flows; - u32 rx_flow_num; - - u32 rx_free_q; - u32 rx_rcv_q; - u32 tx_snd_q; - - u32 rx_flow; /* flow that is used for RX */ -}; - -/* - * packet dma user allocates memory for rx buffers - * and describe it in the following structure - */ -struct rx_buff_desc { - u8 *buff_ptr; - u32 num_buffs; - u32 buff_len; - u32 rx_flow; -}; - -int netcp_close(void); -int netcp_init(struct rx_buff_desc *rx_buffers); -int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2); -void *netcp_recv(u32 **pkt, int *num_bytes); -void netcp_release_rxhd(void *hd); - -#endif /* _KEYSTONE_NAV_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/nand_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/nand_defs.h deleted file mode 100644 index 58417dbc0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * nand driver definitions to re-use davinci nand driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include <asm/arch/hardware.h> -#include <linux/mtd/nand.h> - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/psc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/psc_defs.h deleted file mode 100644 index 70d22cf21..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/psc_defs.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _PSC_DEFS_H_ -#define _PSC_DEFS_H_ - -#include <asm/arch/hardware.h> - -/* - * FILE PURPOSE: Local Power Sleep Controller definitions - * - * FILE NAME: psc_defs.h - * - * DESCRIPTION: Provides local definitions for the power saver controller - * - */ - -/* Register offsets */ -#define PSC_REG_PTCMD 0x120 -#define PSC_REG_PSTAT 0x128 -#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) -#define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) -#define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) -#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) -#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) - -#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ - (u32)1)) << ((u32)y))) - -#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y) -#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ - ((((u32)f) << (y)) & BOOTBITMASK(x, y)) - -/* PDCTL */ -#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) -#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) - -/* PDSTAT */ -#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0) - -/* MDCFG */ -#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16) -#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14) - -/* MDCTL */ -#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) -#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) -#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) -#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ - 12, 12) - -/* MDSTAT */ -#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) -#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) -#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) - -/* PDCTL states */ -#define PSC_REG_VAL_PDCTL_NEXT_ON 1 -#define PSC_REG_VAL_PDCTL_NEXT_OFF 0 - -#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0 - -/* MDCTL states */ -#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0 -#define PSC_REG_VAL_MDCTL_NEXT_OFF 2 -#define PSC_REG_VAL_MDCTL_NEXT_ON 3 - -/* MDSTAT states */ -#define PSC_REG_VAL_MDSTAT_STATE_ON 3 -#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24 -#define PSC_REG_VAL_MDSTAT_STATE_OFF 2 -#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20 -#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21 -#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22 - -/* - * Timeout limit on checking PTSTAT. This is the number of times the - * wait function will be called before giving up. - */ -#define PSC_PTSTAT_TIMEOUT_LIMIT 100 - -u32 psc_get_domain_num(u32 mod_num); -int psc_enable_module(u32 mod_num); -int psc_disable_module(u32 mod_num); -int psc_disable_domain(u32 domain_num); - -#endif /* _PSC_DEFS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/spl.h deleted file mode 100644 index 7012ea7ff..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012-2014 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ - -#define BOOT_DEVICE_SPI 2 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/config.h deleted file mode 100644 index 7a688e46b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/config.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file should be included in board config header file. - * - * It supports common definitions for Kirkwood platform - */ - -#ifndef _KW_CONFIG_H -#define _KW_CONFIG_H - -#if defined (CONFIG_KW88F6281) -#include <asm/arch/kw88f6281.h> -#elif defined (CONFIG_KW88F6192) -#include <asm/arch/kw88f6192.h> -#else -#error "SOC Name not defined" -#endif /* CONFIG_KW88F6281 */ - -#include <asm/arch/kirkwood.h> -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* default Dcache Line length for kirkwood */ -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ - -/* - * By default kwbimage.cfg from board specific folder is used - * If for some board, different configuration file need to be used, - * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file - */ -#ifndef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#endif /* CONFIG_SYS_KWD_CONFIG */ - -/* Kirkwood has 2k of Security SRAM, use it for SP */ -#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE -#define MV_UART_CONSOLE_BASE KW_UART0_BASE -#define MV_SATA_BASE KW_SATA_BASE -#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET -#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET - -/* - * NAND configuration - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif - -/* - * SPI Flash configuration - */ -#ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 -#ifndef CONFIG_ENV_SPI_BUS -# define CONFIG_ENV_SPI_BUS 0 -#endif -#ifndef CONFIG_ENV_SPI_CS -# define CONFIG_ENV_SPI_CS 0 -#endif -#ifndef CONFIG_ENV_SPI_MAX_HZ -# define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif -#endif - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ -#endif /* CONFIG_CMD_NET */ - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MARVELL -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* - * IDE Support on SATA ports - */ -#ifdef CONFIG_CMD_IDE -#define __io -#define CONFIG_CMD_EXT2 -#define CONFIG_MVSATA_IDE -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT1 -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE -#endif /* CONFIG_CMD_IDE */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI -#endif -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -#endif /* _KW_CONFIG_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/cpu.h deleted file mode 100644 index 97daa403c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/cpu.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _KWCPU_H -#define _KWCPU_H - -#include <asm/system.h> - -#ifndef __ASSEMBLY__ - -#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) - -#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c) - -#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) -#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) -#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) -#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) -#define SYSRST_CNT_1SEC_VAL (25*1000000) -#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) - -enum memory_bank { - BANK0, - BANK1, - BANK2, - BANK3 -}; - -enum kwcpu_winen { - KWCPU_WIN_DISABLE, - KWCPU_WIN_ENABLE -}; - -enum kwcpu_target { - KWCPU_TARGET_RESERVED, - KWCPU_TARGET_MEMORY, - KWCPU_TARGET_1RESERVED, - KWCPU_TARGET_SASRAM, - KWCPU_TARGET_PCIE -}; - -enum kwcpu_attrib { - KWCPU_ATTR_SASRAM = 0x01, - KWCPU_ATTR_DRAM_CS0 = 0x0e, - KWCPU_ATTR_DRAM_CS1 = 0x0d, - KWCPU_ATTR_DRAM_CS2 = 0x0b, - KWCPU_ATTR_DRAM_CS3 = 0x07, - KWCPU_ATTR_NANDFLASH = 0x2f, - KWCPU_ATTR_SPIFLASH = 0x1e, - KWCPU_ATTR_BOOTROM = 0x1d, - KWCPU_ATTR_PCIE_IO = 0xe0, - KWCPU_ATTR_PCIE_MEM = 0xe8 -}; - -/* - * Default Device Address MAP BAR values - */ -#define KW_DEFADR_PCI_MEM 0x90000000 -#define KW_DEFADR_PCI_IO 0xC0000000 -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 -#define KW_DEFADR_SASRAM 0xC8010000 -#define KW_DEFADR_NANDF 0xD8000000 -#define KW_DEFADR_SPIF 0xE8000000 -#define KW_DEFADR_BOOTROM 0xF8000000 - -/* - * read feroceon/sheeva core extra feature register - * using co-proc instruction - */ -static inline unsigned int readfr_extra_feature_reg(void) -{ - unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" - (val)::"cc"); - return val; -} - -/* - * write feroceon/sheeva core extra feature register - * using co-proc instruction - */ -static inline void writefr_extra_feature_reg(unsigned int val) -{ - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" - (val):"cc"); - isb(); -} - -/* - * MBus-L to Mbus Bridge Registers - * Ref: Datasheet sec:A.3 - */ -struct kwwin_registers { - u32 ctrl; - u32 base; - u32 remap_lo; - u32 remap_hi; -}; - -/* - * CPU control and status Registers - * Ref: Datasheet sec:A.3.2 - */ -struct kwcpu_registers { - u32 config; /*0x20100 */ - u32 ctrl_stat; /*0x20104 */ - u32 rstoutn_mask; /* 0x20108 */ - u32 sys_soft_rst; /* 0x2010C */ - u32 ahb_mbus_cause_irq; /* 0x20110 */ - u32 ahb_mbus_mask_irq; /* 0x20114 */ - u32 pad1[2]; - u32 ftdll_config; /* 0x20120 */ - u32 pad2; - u32 l2_cfg; /* 0x20128 */ -}; - -/* - * GPIO Registers - * Ref: Datasheet sec:A.19 - */ -struct kwgpio_registers { - u32 dout; - u32 oe; - u32 blink_en; - u32 din_pol; - u32 din; - u32 irq_cause; - u32 irq_mask; - u32 irq_level; -}; - -/* - * functions - */ -unsigned char get_random_hex(void); -unsigned int kw_sdram_bar(enum memory_bank bank); -unsigned int kw_sdram_bs(enum memory_bank bank); -void kw_sdram_size_adjust(enum memory_bank bank); -int kw_config_adr_windows(void); -void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, - unsigned int gpp0_oe, unsigned int gpp1_oe); -int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, - unsigned int mpp16_23, unsigned int mpp24_31, - unsigned int mpp32_39, unsigned int mpp40_47, - unsigned int mpp48_55); -unsigned int kw_winctrl_calcsize(unsigned int sizeval); -#endif /* __ASSEMBLY__ */ -#endif /* _KWCPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/gpio.h deleted file mode 100644 index 5f4d78608..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/gpio.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/asm-arm/mach-kirkwood/include/mach/gpio.h - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. - * Removed kernel level irq handling. Took some macros from kernel to - * allow build. - * - * Dieter Kiermaier dk-arm-linux@gmx.de - */ - -#ifndef __KIRKWOOD_GPIO_H -#define __KIRKWOOD_GPIO_H - -/* got from kernel include/linux/bitops.h */ -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) - -#define GPIO_MAX 50 -#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) - -/* - * Kirkwood-specific GPIO API - */ - -void kw_gpio_set_valid(unsigned pin, int mode); -int kw_gpio_is_valid(unsigned pin, int mode); -int kw_gpio_direction_input(unsigned pin); -int kw_gpio_direction_output(unsigned pin, int value); -int kw_gpio_get_value(unsigned pin); -void kw_gpio_set_value(unsigned pin, int value); -void kw_gpio_set_blink(unsigned pin, int blink); -void kw_gpio_set_unused(unsigned pin); - -#define GPIO_INPUT_OK (1 << 0) -#define GPIO_OUTPUT_OK (1 << 1) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kirkwood.h deleted file mode 100644 index bc207f536..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Header file for the Marvell's Feroceon CPU core. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_KIRKWOOD_H -#define _ASM_ARCH_KIRKWOOD_H - -#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) - -/* SOC specific definations */ -#define INTREG_BASE 0xd0000000 -#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) -#define KW_OFFSET_REG (INTREG_BASE + 0x20080) - -/* undocumented registers */ -#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) -#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) - -#define KW_TWSI_BASE (KW_REGISTER(0x11000)) -#define KW_UART0_BASE (KW_REGISTER(0x12000)) -#define KW_UART1_BASE (KW_REGISTER(0x12100)) -#define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) -#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) -#define KW_RTC_BASE (KW_REGISTER(0x10300)) -#define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define KW_SPI_BASE (KW_REGISTER(0x10600)) -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) -#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) -#define KW_TIMER_BASE (KW_REGISTER(0x20300)) -#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) -#define KW_USB20_BASE (KW_REGISTER(0x50000)) -#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) -#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) -#define KW_SATA_BASE (KW_REGISTER(0x80000)) - -/* Kirkwood Sata controller has two ports */ -#define KW_SATA_PORT0_OFFSET 0x2000 -#define KW_SATA_PORT1_OFFSET 0x4000 - -/* Kirkwood GbE controller has two ports */ -#define MAX_MVGBE_DEVS 2 -#define MVGBE0_BASE KW_EGIGA0_BASE -#define MVGBE1_BASE KW_EGIGA1_BASE - -/* Kirkwood USB Host controller */ -#define MVUSB0_BASE KW_USB20_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 - -/* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE -#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE - -#if defined (CONFIG_KW88F6281) -#include <asm/arch/kw88f6281.h> -#elif defined (CONFIG_KW88F6192) -#include <asm/arch/kw88f6192.h> -#else -#error "SOC Name not defined" -#endif /* CONFIG_KW88F6281 */ -#endif /* CONFIG_FEROCEON_88FR131 */ -#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6192.h deleted file mode 100644 index de220d57d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6192.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_KW88F6192_H -#define _CONFIG_KW88F6192_H - -/* SOC specific definations */ -#define KW88F6192_REGS_PHYS_BASE 0xf1000000 -#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE - -/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -#endif /* _CONFIG_KW88F6192_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6281.h deleted file mode 100644 index ca88a300e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6281.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_KW88F6281_H -#define _ASM_ARCH_KW88F6281_H - -/* SOC specific definitions */ -#define KW88F6281_REGS_PHYS_BASE 0xf1000000 -#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE - -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ -#endif - -#endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/mpp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/mpp.h deleted file mode 100644 index 7c8f6eba9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/mpp.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins - * - * Copyright 2009: Marvell Technology Group Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KIRKWOOD_MPP_H -#define __KIRKWOOD_MPP_H - -#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ - /* MPP number */ ((_num) & 0xff) | \ - /* MPP select value */ (((_sel) & 0xf) << 8) | \ - /* may be input signal */ ((!!(_in)) << 12) | \ - /* may be output signal */ ((!!(_out)) << 13) | \ - /* available on F6180 */ ((!!(_F6180)) << 14) | \ - /* available on F6190 */ ((!!(_F6190)) << 15) | \ - /* available on F6192 */ ((!!(_F6192)) << 16) | \ - /* available on F6281 */ ((!!(_F6281)) << 17)) - -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - - /* num sel i o 6180 6190 6192 6281 */ - -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) - -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) - -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) - -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) - -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) - -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) - -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) -#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) - -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) - -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) - -#define MPP_MAX 49 - -void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/spi.h deleted file mode 100644 index b1cf614ca..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/spi.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Derived from drivers/spi/mpc8xxx_spi.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KW_SPI_H__ -#define __KW_SPI_H__ - -/* SPI Registers on kirkwood SOC */ -struct kwspi_registers { - u32 ctrl; /* 0x10600 */ - u32 cfg; /* 0x10604 */ - u32 dout; /* 0x10608 */ - u32 din; /* 0x1060c */ - u32 irq_cause; /* 0x10610 */ - u32 irq_mask; /* 0x10614 */ -}; - -/* They are used to define CONFIG_SYS_KW_SPI_MPP - * each of the below #defines selects which mpp is - * configured for each SPI signal in spi_claim_bus - * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) - * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) - * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) - */ -#define MOSI_MPP6 (1 << 0) -#define SCK_MPP10 (1 << 1) -#define MISO_MPP11 (1 << 2) - -#define KWSPI_CLKPRESCL_MASK 0x1f -#define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ -#define KWSPI_XFERLEN_1BYTE 0 -#define KWSPI_XFERLEN_2BYTE (1 << 5) -#define KWSPI_XFERLEN_MASK (1 << 5) -#define KWSPI_ADRLEN_1BYTE 0 -#define KWSPI_ADRLEN_2BYTE 1 << 8 -#define KWSPI_ADRLEN_3BYTE 2 << 8 -#define KWSPI_ADRLEN_4BYTE 3 << 8 -#define KWSPI_ADRLEN_MASK 3 << 8 -#define KWSPI_TIMEOUT 10000 - -#endif /* __KW_SPI_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-ks8695/platform.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-ks8695/platform.h deleted file mode 100644 index 02f604926..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-ks8695/platform.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __address_h -#define __address_h 1 - -#define KS8695_SDRAM_START 0x00000000 -#define KS8695_SDRAM_SIZE 0x01000000 -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE -#define KS8695_MEM_START KS8695_SDRAM_START - -#define KS8695_PCMCIA_IO_BASE 0x03800000 -#define KS8695_PCMCIA_IO_SIZE 0x00040000 - -#define KS8695_IO_BASE 0x03FF0000 -#define KS8695_IO_SIZE 0x00010000 - -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 - -#define KS8695_FLASH_START 0x02800000 -#define KS8695_FLASH_SIZE 0x00400000 - -/*i/o control registers offset difinitions*/ -#define KS8695_IO_CTRL0 0x4000 -#define KS8695_IO_CTRL1 0x4004 -#define KS8695_IO_CTRL2 0x4008 -#define KS8695_IO_CTRL3 0x400C - -/*memory control registers offset difinitions*/ -#define KS8695_MEM_CTRL0 0x4010 -#define KS8695_MEM_CTRL1 0x4014 -#define KS8695_MEM_CTRL2 0x4018 -#define KS8695_MEM_CTRL3 0x401C -#define KS8695_MEM_GENERAL 0x4020 -#define KS8695_SDRAM_CTRL0 0x4030 -#define KS8695_SDRAM_CTRL1 0x4034 -#define KS8695_SDRAM_GENERAL 0x4038 -#define KS8695_SDRAM_BUFFER 0x403C -#define KS8695_SDRAM_REFRESH 0x4040 - -/*WAN control registers offset difinitions*/ -#define KS8695_WAN_DMA_TX 0x6000 -#define KS8695_WAN_DMA_RX 0x6004 -#define KS8695_WAN_DMA_TX_START 0x6008 -#define KS8695_WAN_DMA_RX_START 0x600C -#define KS8695_WAN_TX_LIST 0x6010 -#define KS8695_WAN_RX_LIST 0x6014 -#define KS8695_WAN_MAC_LOW 0x6018 -#define KS8695_WAN_MAC_HIGH 0x601C -#define KS8695_WAN_MAC_ELOW 0x6080 -#define KS8695_WAN_MAC_EHIGH 0x6084 - -/*LAN control registers offset difinitions*/ -#define KS8695_LAN_DMA_TX 0x8000 -#define KS8695_LAN_DMA_RX 0x8004 -#define KS8695_LAN_DMA_TX_START 0x8008 -#define KS8695_LAN_DMA_RX_START 0x800C -#define KS8695_LAN_TX_LIST 0x8010 -#define KS8695_LAN_RX_LIST 0x8014 -#define KS8695_LAN_MAC_LOW 0x8018 -#define KS8695_LAN_MAC_HIGH 0x801C -#define KS8695_LAN_MAC_ELOW 0X8080 -#define KS8695_LAN_MAC_EHIGH 0X8084 - -/*HPNA control registers offset difinitions*/ -#define KS8695_HPNA_DMA_TX 0xA000 -#define KS8695_HPNA_DMA_RX 0xA004 -#define KS8695_HPNA_DMA_TX_START 0xA008 -#define KS8695_HPNA_DMA_RX_START 0xA00C -#define KS8695_HPNA_TX_LIST 0xA010 -#define KS8695_HPNA_RX_LIST 0xA014 -#define KS8695_HPNA_MAC_LOW 0xA018 -#define KS8695_HPNA_MAC_HIGH 0xA01C -#define KS8695_HPNA_MAC_ELOW 0xA080 -#define KS8695_HPNA_MAC_EHIGH 0xA084 - -/*UART control registers offset difinitions*/ -#define KS8695_UART_RX_BUFFER 0xE000 -#define KS8695_UART_TX_HOLDING 0xE004 - -#define KS8695_UART_FIFO_CTRL 0xE008 -#define KS8695_UART_FIFO_TRIG01 0x00 -#define KS8695_UART_FIFO_TRIG04 0x80 -#define KS8695_UART_FIFO_TXRST 0x03 -#define KS8695_UART_FIFO_RXRST 0x02 -#define KS8695_UART_FIFO_FEN 0x01 - -#define KS8695_UART_LINE_CTRL 0xE00C -#define KS8695_UART_LINEC_BRK 0x40 -#define KS8695_UART_LINEC_EPS 0x10 -#define KS8695_UART_LINEC_PEN 0x08 -#define KS8695_UART_LINEC_STP2 0x04 -#define KS8695_UART_LINEC_WLEN8 0x03 -#define KS8695_UART_LINEC_WLEN7 0x02 -#define KS8695_UART_LINEC_WLEN6 0x01 -#define KS8695_UART_LINEC_WLEN5 0x00 - -#define KS8695_UART_MODEM_CTRL 0xE010 -#define KS8695_UART_MODEMC_RTS 0x02 -#define KS8695_UART_MODEMC_DTR 0x01 - -#define KS8695_UART_LINE_STATUS 0xE014 -#define KS8695_UART_LINES_TXFE 0x20 -#define KS8695_UART_LINES_BE 0x10 -#define KS8695_UART_LINES_FE 0x08 -#define KS8695_UART_LINES_PE 0x04 -#define KS8695_UART_LINES_OE 0x02 -#define KS8695_UART_LINES_RXFE 0x01 -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) - -#define KS8695_UART_MODEM_STATUS 0xE018 -#define KS8695_UART_MODEM_DCD 0x80 -#define KS8695_UART_MODEM_DSR 0x20 -#define KS8695_UART_MODEM_CTS 0x10 -#define KS8695_UART_MODEM_DDCD 0x08 -#define KS8695_UART_MODEM_DDSR 0x02 -#define KS8695_UART_MODEM_DCTS 0x01 -#define UART8695_MODEM_ANY 0xFF - -#define KS8695_UART_DIVISOR 0xE01C -#define KS8695_UART_STATUS 0xE020 - -/*Interrupt controlller registers offset difinitions*/ -#define KS8695_INT_CONTL 0xE200 -#define KS8695_INT_ENABLE 0xE204 -#define KS8695_INT_ENABLE_MODEM 0x0800 -#define KS8695_INT_ENABLE_ERR 0x0400 -#define KS8695_INT_ENABLE_RX 0x0200 -#define KS8695_INT_ENABLE_TX 0x0100 - -#define KS8695_INT_STATUS 0xE208 -#define KS8695_INT_WAN_PRIORITY 0xE20C -#define KS8695_INT_HPNA_PRIORITY 0xE210 -#define KS8695_INT_LAN_PRIORITY 0xE214 -#define KS8695_INT_TIMER_PRIORITY 0xE218 -#define KS8695_INT_UART_PRIORITY 0xE21C -#define KS8695_INT_EXT_PRIORITY 0xE220 -#define KS8695_INT_CHAN_PRIORITY 0xE224 -#define KS8695_INT_BUSERROR_PRO 0xE228 -#define KS8695_INT_MASK_STATUS 0xE22C -#define KS8695_FIQ_PEND_PRIORITY 0xE230 -#define KS8695_IRQ_PEND_PRIORITY 0xE234 - -/*timer registers offset difinitions*/ -#define KS8695_TIMER_CTRL 0xE400 -#define KS8695_TIMER1 0xE404 -#define KS8695_TIMER0 0xE408 -#define KS8695_TIMER1_PCOUNT 0xE40C -#define KS8695_TIMER0_PCOUNT 0xE410 - -/*GPIO registers offset difinitions*/ -#define KS8695_GPIO_MODE 0xE600 -#define KS8695_GPIO_CTRL 0xE604 -#define KS8695_GPIO_DATA 0xE608 - -/*SWITCH registers offset difinitions*/ -#define KS8695_SWITCH_CTRL0 0xE800 -#define KS8695_SWITCH_CTRL1 0xE804 -#define KS8695_SWITCH_PORT1 0xE808 -#define KS8695_SWITCH_PORT2 0xE80C -#define KS8695_SWITCH_PORT3 0xE810 -#define KS8695_SWITCH_PORT4 0xE814 -#define KS8695_SWITCH_PORT5 0xE818 -#define KS8695_SWITCH_AUTO0 0xE81C -#define KS8695_SWITCH_AUTO1 0xE820 -#define KS8695_SWITCH_LUE_CTRL 0xE824 -#define KS8695_SWITCH_LUE_HIGH 0xE828 -#define KS8695_SWITCH_LUE_LOW 0xE82C -#define KS8695_SWITCH_ADVANCED 0xE830 - -#define KS8695_SWITCH_LPPM12 0xE874 -#define KS8695_SWITCH_LPPM34 0xE878 - -/*host communication registers difinitions*/ -#define KS8695_DSCP_HIGH 0xE834 -#define KS8695_DSCP_LOW 0xE838 -#define KS8695_SWITCH_MAC_HIGH 0xE83C -#define KS8695_SWITCH_MAC_LOW 0xE840 - -/*miscellaneours registers difinitions*/ -#define KS8695_MANAGE_COUNTER 0xE844 -#define KS8695_MANAGE_DATA 0xE848 -#define KS8695_LAN12_POWERMAGR 0xE84C -#define KS8695_LAN34_POWERMAGR 0xE850 - -#define KS8695_DEVICE_ID 0xEA00 -#define KS8695_REVISION_ID 0xEA04 - -#define KS8695_MISC_CONTROL 0xEA08 -#define KS8695_WAN_CONTROL 0xEA0C -#define KS8695_WAN_POWERMAGR 0xEA10 -#define KS8695_WAN_PHY_CONTROL 0xEA14 -#define KS8695_WAN_PHY_STATUS 0xEA18 - -/* bus clock definitions*/ -#define KS8695_BUS_CLOCK_125MHZ 0x0 -#define KS8695_BUS_CLOCK_100MHZ 0x1 -#define KS8695_BUS_CLOCK_62MHZ 0x2 -#define KS8695_BUS_CLOCK_50MHZ 0x3 -#define KS8695_BUS_CLOCK_41MHZ 0x4 -#define KS8695_BUS_CLOCK_33MHZ 0x5 -#define KS8695_BUS_CLOCK_31MHZ 0x6 -#define KS8695_BUS_CLOCK_25MHZ 0x7 - -/* ------------------------------------------------------------------------------- - * definations for IRQ - * -------------------------------------------------------------------------------*/ - -#define KS8695_INT_EXT_INT0 2 -#define KS8695_INT_EXT_INT1 3 -#define KS8695_INT_EXT_INT2 4 -#define KS8695_INT_EXT_INT3 5 -#define KS8695_INT_TIMERINT0 6 -#define KS8695_INT_TIMERINT1 7 -#define KS8695_INT_UART_TX 8 -#define KS8695_INT_UART_RX 9 -#define KS8695_INT_UART_LINE_ERR 10 -#define KS8695_INT_UART_MODEMS 11 -#define KS8695_INT_LAN_STOP_RX 12 -#define KS8695_INT_LAN_STOP_TX 13 -#define KS8695_INT_LAN_BUF_RX_STATUS 14 -#define KS8695_INT_LAN_BUF_TX_STATUS 15 -#define KS8695_INT_LAN_RX_STATUS 16 -#define KS8695_INT_LAN_TX_STATUS 17 -#define KS8695_INT_HPAN_STOP_RX 18 -#define KS8695_INT_HPNA_STOP_TX 19 -#define KS8695_INT_HPNA_BUF_RX_STATUS 20 -#define KS8695_INT_HPNA_BUF_TX_STATUS 21 -#define KS8695_INT_HPNA_RX_STATUS 22 -#define KS8695_INT_HPNA_TX_STATUS 23 -#define KS8695_INT_BUS_ERROR 24 -#define KS8695_INT_WAN_STOP_RX 25 -#define KS8695_INT_WAN_STOP_TX 26 -#define KS8695_INT_WAN_BUF_RX_STATUS 27 -#define KS8695_INT_WAN_BUF_TX_STATUS 28 -#define KS8695_INT_WAN_RX_STATUS 29 -#define KS8695_INT_WAN_TX_STATUS 30 - -#define KS8695_INT_UART KS8695_INT_UART_TX - -/* ------------------------------------------------------------------------------- - * Interrupt bit positions - * - * ------------------------------------------------------------------------------- - */ - -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) - -#define KS8695_SC_VALID_INT 0xFFFFFFFF -#define MAXIRQNUM 31 - -/* - * Timer definitions - * - * Use timer 1 & 2 - * (both run at 25MHz). - * - */ -#define TICKS_PER_uSEC 25 -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - -#endif - -/* END */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h deleted file mode 100644 index 92f6c15f2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_CLK_H -#define _LPC32XX_CLK_H - -#include <asm/types.h> - -#define OSC_CLK_FREQUENCY 13000000 -#define RTC_CLK_FREQUENCY 32768 - -/* Clocking and Power Control Registers */ -struct clk_pm_regs { - u32 reserved0[5]; - u32 boot_map; /* Boot Map Control Register */ - u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */ - u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */ - /* Internal Start Signal Sources Registers */ - u32 start_er_int; /* Start Enable Register */ - u32 start_rsr_int; /* Start Raw Status Register */ - u32 start_sr_int; /* Start Status Register */ - u32 start_apr_int; /* Start Activation Polarity Register */ - /* Device Pin Start Signal Sources Registers */ - u32 start_er_pin; /* Start Enable Register */ - u32 start_rsr_pin; /* Start Raw Status Register */ - u32 start_sr_pin; /* Start Status Register */ - u32 start_apr_pin; /* Start Activation Polarity Register */ - /* Clock Control Registers */ - u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ - u32 pwr_ctrl; /* Power Control Register */ - u32 pll397_ctrl; /* PLL397 Control Register */ - u32 osc_ctrl; /* Main Oscillator Control Register */ - u32 sysclk_ctrl; /* SYSCLK Control Register */ - u32 lcdclk_ctrl; /* LCD Clock Control Register */ - u32 hclkpll_ctrl; /* HCLK PLL Control Register */ - u32 reserved1; - u32 adclk_ctrl1; /* ADC Clock Control1 Register */ - u32 usb_ctrl; /* USB Control Register */ - u32 sdramclk_ctrl; /* SDRAM Clock Control Register */ - u32 ddr_lap_nom; /* DDR Calibration Nominal Value */ - u32 ddr_lap_count; /* DDR Calibration Measured Value */ - u32 ddr_cal_delay; /* DDR Calibration Delay Value */ - u32 ssp_ctrl; /* SSP Control Register */ - u32 i2s_ctrl; /* I2S Clock Control Register */ - u32 ms_ctrl; /* Memory Card Control Register */ - u32 reserved2[3]; - u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */ - u32 reserved3[4]; - u32 test_clk; /* Test Clock Selection Register */ - u32 sw_int; /* Software Interrupt Register */ - u32 i2cclk_ctrl; /* I2C Clock Control Register */ - u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */ - u32 adclk_ctrl; /* ADC Clock Control Register */ - u32 pwmclk_ctrl; /* PWM Clock Control Register */ - u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */ - u32 timclk_ctrl1; /* Motor and Timer Clock Control */ - u32 spi_ctrl; /* SPI Control Register */ - u32 flashclk_ctrl; /* NAND Flash Clock Control Register */ - u32 reserved4; - u32 u3clk; /* UART 3 Clock Control Register */ - u32 u4clk; /* UART 4 Clock Control Register */ - u32 u5clk; /* UART 5 Clock Control Register */ - u32 u6clk; /* UART 6 Clock Control Register */ - u32 irdaclk; /* IrDA Clock Control Register */ - u32 uartclk_ctrl; /* UART Clock Control Register */ - u32 dmaclk_ctrl; /* DMA Clock Control Register */ - u32 autoclk_ctrl; /* Autoclock Control Register */ -}; - -/* HCLK Divider Control Register bits */ -#define CLK_HCLK_DDRAM_HALF (0x2 << 7) -#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) -#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) -#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) -#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) -#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) -#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) -#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) -#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) - -/* Power Control Register bits */ -#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) -#define CLK_PWR_EMC_SREFREQ (1 << 9) -#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) -#define CLK_PWR_SDRAM_SREFREQ (1 << 7) -#define CLK_PWR_HIGHCORE_LEVEL (1 << 5) -#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) -#define CLK_PWR_SYSCLKEN_CTRL (1 << 3) -#define CLK_PWR_NORMAL_RUN (1 << 2) -#define CLK_PWR_HIGHCORE_CTRL (1 << 1) -#define CLK_PWR_STOP_MODE (1 << 0) - -/* SYSCLK Control Register bits */ -#define CLK_SYSCLK_PLL397 (1 << 1) -#define CLK_SYSCLK_MUX (1 << 0) - -/* HCLK PLL Control Register bits */ -#define CLK_HCLK_PLL_OPERATING (1 << 16) -#define CLK_HCLK_PLL_BYPASS (1 << 15) -#define CLK_HCLK_PLL_DIRECT (1 << 14) -#define CLK_HCLK_PLL_FEEDBACK (1 << 13) -#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) -#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) -#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) -#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) -#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) -#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) -#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) -#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) -#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) -#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) -#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) -#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) -#define CLK_HCLK_PLL_LOCKED (1 << 0) - -/* Ethernet MAC Clock Control Register bits */ -#define CLK_MAC_RMII (0x3 << 3) -#define CLK_MAC_MII (0x1 << 3) -#define CLK_MAC_MASTER (1 << 2) -#define CLK_MAC_SLAVE (1 << 1) -#define CLK_MAC_REG (1 << 0) - -/* Timer Clock Control1 Register bits */ -#define CLK_TIMCLK_MOTOR (1 << 6) -#define CLK_TIMCLK_TIMER3 (1 << 5) -#define CLK_TIMCLK_TIMER2 (1 << 4) -#define CLK_TIMCLK_TIMER1 (1 << 3) -#define CLK_TIMCLK_TIMER0 (1 << 2) -#define CLK_TIMCLK_TIMER5 (1 << 1) -#define CLK_TIMCLK_TIMER4 (1 << 0) - -/* Timer Clock Control Register bits */ -#define CLK_TIMCLK_HSTIMER (1 << 1) -#define CLK_TIMCLK_WATCHDOG (1 << 0) - -/* UART Clock Control Register bits */ -#define CLK_UART(n) (1 << ((n) - 3)) - -/* UARTn Clock Select Registers bits */ -#define CLK_UART_HCLK (1 << 16) -#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) -#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) - -/* DMA Clock Control Register bits */ -#define CLK_DMA_ENABLE (1 << 0) - -unsigned int get_sys_clk_rate(void); -unsigned int get_hclk_pll_rate(void); -unsigned int get_hclk_clk_div(void); -unsigned int get_hclk_clk_rate(void); -unsigned int get_periph_clk_div(void); -unsigned int get_periph_clk_rate(void); - -#endif /* _LPC32XX_CLK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h deleted file mode 100644 index c985401d3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Common definitions for LPC32XX board configurations - * - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_CONFIG_H -#define _LPC32XX_CONFIG_H - -/* Basic CPU architecture */ -#define CONFIG_ARM926EJS -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -/* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) -#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ - (CONFIG_SYS_LPC32XX_UART == 7) -#define CONFIG_LPC32XX_HSUART -#else -#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" -#endif - -#if defined(CONFIG_SYS_NS16550_SERIAL) -#define CONFIG_SYS_NS16550 - -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_NS16550_COM1 UART3_BASE -#define CONFIG_SYS_NS16550_COM2 UART4_BASE -#define CONFIG_SYS_NS16550_COM3 UART5_BASE -#define CONFIG_SYS_NS16550_COM4 UART6_BASE -#endif - -#if defined(CONFIG_LPC32XX_HSUART) -#if CONFIG_SYS_LPC32XX_UART == 1 -#define HS_UART_BASE HS_UART1_BASE -#elif CONFIG_SYS_LPC32XX_UART == 2 -#define HS_UART_BASE HS_UART2_BASE -#else /* CONFIG_SYS_LPC32XX_UART == 7 */ -#define HS_UART_BASE HS_UART7_BASE -#endif -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } - -/* NOR Flash */ -#if defined(CONFIG_SYS_FLASH_CFI) -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_PROTECTION -#endif - -#endif /* _LPC32XX_CONFIG_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h deleted file mode 100644 index 199b4a026..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_CPU_H -#define _LPC32XX_CPU_H - -/* LPC32XX Memory map */ - -/* AHB physical base addresses */ -#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ -#define SSP0_BASE 0x20084000 /* SSP0 registers base */ -#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ -#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ -#define DMA_BASE 0x31000000 /* DMA controller registers base */ -#define USB_BASE 0x31020000 /* USB registers base */ -#define LCD_BASE 0x31040000 /* LCD registers base */ -#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ -#define EMC_BASE 0x31080000 /* EMC configuration registers base */ - -/* FAB peripherals base addresses */ -#define CLK_PM_BASE 0x40004000 /* System control registers base */ -#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ -#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ -#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ -#define RTC_BASE 0x40024000 /* RTC registers base */ -#define GPIO_BASE 0x40028000 /* GPIO registers base */ -#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ -#define TIMER0_BASE 0x40044000 /* Timer0 registers base */ -#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ -#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ - -/* APB peripherals base addresses */ -#define UART3_BASE 0x40080000 /* UART 3 registers base */ -#define UART4_BASE 0x40088000 /* UART 4 registers base */ -#define UART5_BASE 0x40090000 /* UART 5 registers base */ -#define UART6_BASE 0x40098000 /* UART 6 registers base */ - -/* External SDRAM Memory Bank base addresses */ -#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ -#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ - -/* External Static Memory Bank base addresses */ -#define EMC_CS0_BASE 0xE0000000 -#define EMC_CS1_BASE 0xE1000000 -#define EMC_CS2_BASE 0xE2000000 -#define EMC_CS3_BASE 0xE3000000 - -#endif /* _LPC32XX_CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h deleted file mode 100644 index 82d9bcce5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_EMC_H -#define _LPC32XX_EMC_H - -#include <asm/types.h> - -/* EMC Registers */ -struct emc_regs { - u32 ctrl; /* Controls operation of the EMC */ - u32 status; /* Provides EMC status information */ - u32 config; /* Configures operation of the EMC */ - u32 reserved0[5]; - u32 control; /* Controls dyn memory operation */ - u32 refresh; /* Configures dyn memory refresh operation */ - u32 read_config; /* Configures the dyn memory read strategy */ - u32 reserved1; - u32 t_rp; /* Precharge command period */ - u32 t_ras; /* Active to precharge command period */ - u32 t_srex; /* Self-refresh exit time */ - u32 reserved2[2]; - u32 t_wr; /* Write recovery time */ - u32 t_rc; /* Active to active command period */ - u32 t_rfc; /* Auto-refresh period */ - u32 t_xsr; /* Exit self-refresh to active command time */ - u32 t_rrd; /* Active bank A to active bank B latency */ - u32 t_mrd; /* Load mode register to active command time */ - u32 t_cdlr; /* Last data in to read command time */ - u32 reserved3[8]; - u32 extended_wait; /* time for static memory rd/wr transfers */ - u32 reserved4[31]; - u32 config0; /* Configuration information for the SDRAM */ - u32 rascas0; /* RAS and CAS latencies for the SDRAM */ - u32 reserved5[6]; - u32 config1; /* Configuration information for the SDRAM */ - u32 rascas1; /* RAS and CAS latencies for the SDRAM */ - u32 reserved6[54]; - struct emc_stat_t { - u32 config; /* Static memory configuration */ - u32 waitwen; /* Delay from chip select to write enable */ - u32 waitoen; /* Delay to output enable */ - u32 waitrd; /* Delay to a read access */ - u32 waitpage; /* Delay for async page mode read */ - u32 waitwr; /* Delay to a write access */ - u32 waitturn; /* Number of bus turnaround cycles */ - u32 reserved; - } stat[4]; - u32 reserved7[96]; - struct emc_ahb_t { - u32 control; /* Control register for AHB */ - u32 status; /* Status register for AHB */ - u32 timeout; /* Timeout register for AHB */ - u32 reserved[5]; - } ahb[5]; -}; - -/* Static Memory Configuration Register bits */ -#define EMC_STAT_CONFIG_WP (1 << 20) -#define EMC_STAT_CONFIG_EW (1 << 8) -#define EMC_STAT_CONFIG_PB (1 << 7) -#define EMC_STAT_CONFIG_PC (1 << 6) -#define EMC_STAT_CONFIG_PM (1 << 3) -#define EMC_STAT_CONFIG_32BIT (2 << 0) -#define EMC_STAT_CONFIG_16BIT (1 << 0) -#define EMC_STAT_CONFIG_8BIT (0 << 0) - -/* Static Memory Delay Registers */ -#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) -#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F) -#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) -#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) -#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) -#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) - -#endif /* _LPC32XX_EMC_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h deleted file mode 100644 index 28812be3c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_SYS_PROTO_H -#define _LPC32XX_SYS_PROTO_H - -void lpc32xx_uart_init(unsigned int uart_id); - -#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h deleted file mode 100644 index bd90144c0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_TIMER_H -#define _LPC32XX_TIMER_H - -#include <asm/types.h> - -/* Timer/Counter Registers */ -struct timer_regs { - u32 ir; /* Interrupt Register */ - u32 tcr; /* Timer Control Register */ - u32 tc; /* Timer Counter */ - u32 pr; /* Prescale Register */ - u32 pc; /* Prescale Counter */ - u32 mcr; /* Match Control Register */ - u32 mr[4]; /* Match Registers */ - u32 ccr; /* Capture Control Register */ - u32 cr[4]; /* Capture Registers */ - u32 emr; /* External Match Register */ - u32 reserved[12]; - u32 ctcr; /* Count Control Register */ -}; - -/* Timer/Counter Interrupt Register bits */ -#define TIMER_IR_CR(n) (1 << ((n) + 4)) -#define TIMER_IR_MR(n) (1 << (n)) - -/* Timer/Counter Timer Control Register bits */ -#define TIMER_TCR_COUNTER_RESET (1 << 1) -#define TIMER_TCR_COUNTER_ENABLE (1 << 0) -#define TIMER_TCR_COUNTER_DISABLE (0 << 0) - -/* Timer/Counter Match Control Register bits */ -#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) -#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) -#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) - -/* Timer/Counter Capture Control Register bits */ -#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) -#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) -#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) - -/* Timer/Counter External Match Register bits */ -#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) -#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) -#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) -#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) -#define TIMER_EMR_EM(n) (1 << (n)) - -/* Timer/Counter Count Control Register bits */ -#define TIMER_CTCR_INPUT(n) ((n) << 2) -#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) -#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) -#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) -#define TIMER_CTCR_MODE_TIMER (0x0 << 0) - -#endif /* _LPC32XX_TIMER_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h deleted file mode 100644 index 01dacd61b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_UART_H -#define _LPC32XX_UART_H - -#include <asm/types.h> - -/* 14-clock UART Registers */ -struct hsuart_regs { - union { - u32 rx; /* Receiver FIFO */ - u32 tx; /* Transmitter FIFO */ - }; - u32 level; /* FIFO Level Register */ - u32 iir; /* Interrupt ID Register */ - u32 ctrl; /* Control Register */ - u32 rate; /* Rate Control Register */ -}; - -/* 14-clock UART Receiver FIFO Register bits */ -#define HSUART_RX_BREAK (1 << 10) -#define HSUART_RX_ERROR (1 << 9) -#define HSUART_RX_EMPTY (1 << 8) -#define HSUART_RX_DATA (0xff << 0) - -/* 14-clock UART Level Register bits */ -#define HSUART_LEVEL_TX (0xff << 8) -#define HSUART_LEVEL_RX (0xff << 0) - -/* 14-clock UART Interrupt Identification Register bits */ -#define HSUART_IIR_TX_INT_SET (1 << 6) -#define HSUART_IIR_RX_OE (1 << 5) -#define HSUART_IIR_BRK (1 << 4) -#define HSUART_IIR_FE (1 << 3) -#define HSUART_IIR_RX_TIMEOUT (1 << 2) -#define HSUART_IIR_RX_TRIG (1 << 1) -#define HSUART_IIR_TX (1 << 0) - -/* 14-clock UART Control Register bits */ -#define HSUART_CTRL_HRTS_INV (1 << 21) -#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19) -#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19) -#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19) -#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19) -#define HSUART_CTRL_HRTS_EN (1 << 18) -#define HSUART_CTRL_TMO_16 (0x3 << 16) -#define HSUART_CTRL_TMO_8 (0x2 << 16) -#define HSUART_CTRL_TMO_4 (0x1 << 16) -#define HSUART_CTRL_TMO_DISABLED (0x0 << 16) -#define HSUART_CTRL_HCTS_INV (1 << 15) -#define HSUART_CTRL_HCTS_EN (1 << 14) -#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) -#define HSUART_CTRL_HSU_BREAK (1 << 8) -#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7) -#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6) -#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5) -#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2) -#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2) -#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0) -#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0) -#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0) -#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0) - -/* UART Control Registers */ -struct uart_ctrl_regs { - u32 ctrl; /* Control Register */ - u32 clkmode; /* Clock Mode Register */ - u32 loop; /* Loopback Control Register */ -}; - -/* UART Control Register bits */ -#define UART_CTRL_UART3_MD_CTRL (1 << 11) -#define UART_CTRL_HDPX_INV (1 << 10) -#define UART_CTRL_HDPX_EN (1 << 9) -#define UART_CTRL_UART6_IRDA (1 << 5) -#define UART_CTRL_IR_TX6_INV (1 << 4) -#define UART_CTRL_IR_RX6_INV (1 << 3) -#define UART_CTRL_IR_RX_LENGTH (1 << 2) -#define UART_CTRL_IR_TX_LENGTH (1 << 1) -#define UART_CTRL_UART5_USB_MODE (1 << 0) - -/* UART Clock Mode Register bits */ -#define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) -#define UART_CLKMODE_STAT (1 << 14) -#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) -#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) -#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) -#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) - -/* UART Loopback Control Register bits */ -#define UART_LOOPBACK(n) (1 << ((n) - 1)) - -#endif /* _LPC32XX_UART_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h deleted file mode 100644 index d7903c243..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LPC32XX_WDT_H -#define _LPC32XX_WDT_H - -#include <asm/types.h> - -/* Watchdog Timer Registers */ -struct wdt_regs { - u32 isr; /* Interrupt Status Register */ - u32 ctrl; /* Control Register */ - u32 counter; /* Counter Value Register */ - u32 mctrl; /* Match Control Register */ - u32 match0; /* Match 0 Register */ - u32 emr; /* External Match Control Register */ - u32 pulse; /* Reset Pulse Length Register */ - u32 res; /* Reset Source Register */ -}; - -/* Watchdog Timer Control Register bits */ -#define WDTIM_CTRL_PAUSE_EN (1 << 2) -#define WDTIM_CTRL_RESET_COUNT (1 << 1) -#define WDTIM_CTRL_COUNT_ENAB (1 << 0) - -/* Watchdog Timer Match Control Register bits */ -#define WDTIM_MCTRL_RESFRC2 (1 << 6) -#define WDTIM_MCTRL_RESFRC1 (1 << 5) -#define WDTIM_MCTRL_M_RES2 (1 << 4) -#define WDTIM_MCTRL_M_RES1 (1 << 3) -#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) -#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) -#define WDTIM_MCTRL_MR0_INT (1 << 0) - -#endif /* _LPC32XX_WDT_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/hardware.h deleted file mode 100644 index 42a52bc36..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2007 - * - * Author : Carsten Schneider, mycable GmbH - * <cs@mycable.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/sizes.h> -#include <asm/arch/mb86r0x.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h deleted file mode 100644 index 7fec9715b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * (C) Copyright 2007 - * - * mb86r0x definitions - * - * Author : Carsten Schneider, mycable GmbH - * <cs@mycable.de> - * - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef MB86R0X_H -#define MB86R0X_H - -#ifndef __ASSEMBLY__ - -/* GPIO registers */ -struct mb86r0x_gpio { - uint32_t gpdr0; - uint32_t gpdr1; - uint32_t gpdr2; - uint32_t res; - uint32_t gpddr0; - uint32_t gpddr1; - uint32_t gpddr2; -}; - -/* PWM registers */ -struct mb86r0x_pwm { - uint32_t bcr; - uint32_t tpr; - uint32_t pr; - uint32_t dr; - uint32_t cr; - uint32_t sr; - uint32_t ccr; - uint32_t ir; -}; - -/* The mb86r0x chip control (CCNT) register set. */ -struct mb86r0x_ccnt { - uint32_t ccid; - uint32_t csrst; - uint32_t pad0[2]; - uint32_t cist; - uint32_t cistm; - uint32_t cgpio_ist; - uint32_t cgpio_istm; - uint32_t cgpio_ip; - uint32_t cgpio_im; - uint32_t caxi_bw; - uint32_t caxi_ps; - uint32_t cmux_md; - uint32_t cex_pin_st; - uint32_t cmlb; - uint32_t pad1[1]; - uint32_t cusb; - uint32_t pad2[41]; - uint32_t cbsc; - uint32_t cdcrc; - uint32_t cmsr0; - uint32_t cmsr1; - uint32_t pad3[2]; -}; - -/* The mb86r0x clock reset generator */ -struct mb86r0x_crg { - uint32_t crpr; - uint32_t pad0; - uint32_t crwr; - uint32_t crsr; - uint32_t crda; - uint32_t crdb; - uint32_t crha; - uint32_t crpa; - uint32_t crpb; - uint32_t crhb; - uint32_t cram; -}; - -/* The mb86r0x timer */ -struct mb86r0x_timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t intclr; - uint32_t ris; - uint32_t mis; - uint32_t bgload; -}; - -/* mb86r0x gdc display controller */ -struct mb86r0x_gdc_dsp { - /* Display settings */ - uint32_t dcm0; - uint16_t pad00; - uint16_t htp; - uint16_t hdp; - uint16_t hdb; - uint16_t hsp; - uint8_t hsw; - uint8_t vsw; - uint16_t pad01; - uint16_t vtr; - uint16_t vsp; - uint16_t vdp; - uint16_t wx; - uint16_t wy; - uint16_t ww; - uint16_t wh; - - /* Layer 0 */ - uint32_t l0m; - uint32_t l0oa; - uint32_t l0da; - uint16_t l0dx; - uint16_t l0dy; - - /* Layer 1 */ - uint32_t l1m; - uint32_t cbda0; - uint32_t cbda1; - uint32_t pad02; - - /* Layer 2 */ - uint32_t l2m; - uint32_t l2oa0; - uint32_t l2da0; - uint32_t l2oa1; - uint32_t l2da1; - uint16_t l2dx; - uint16_t l2dy; - - /* Layer 3 */ - uint32_t l3m; - uint32_t l3oa0; - uint32_t l3da0; - uint32_t l3oa1; - uint32_t l3da1; - uint16_t l3dx; - uint16_t l3dy; - - /* Layer 4 */ - uint32_t l4m; - uint32_t l4oa0; - uint32_t l4da0; - uint32_t l4oa1; - uint32_t l4da1; - uint16_t l4dx; - uint16_t l4dy; - - /* Layer 5 */ - uint32_t l5m; - uint32_t l5oa0; - uint32_t l5da0; - uint32_t l5oa1; - uint32_t l5da1; - uint16_t l5dx; - uint16_t l5dy; - - /* Cursor */ - uint16_t cutc; - uint8_t cpm; - uint8_t csize; - uint32_t cuoa0; - uint16_t cux0; - uint16_t cuy0; - uint32_t cuoa1; - uint16_t cux1; - uint16_t cuy1; - - /* Layer blending */ - uint32_t l0bld; - uint32_t pad03; - uint32_t l0tc; - uint16_t l3tc; - uint16_t l2tc; - uint32_t pad04[15]; - - /* Display settings */ - uint32_t dcm1; - uint32_t dcm2; - uint32_t dcm3; - uint32_t pad05; - - /* Layer 0 extended */ - uint32_t l0em; - uint16_t l0wx; - uint16_t l0wy; - uint16_t l0ww; - uint16_t l0wh; - uint32_t pad06; - - /* Layer 1 extended */ - uint32_t l1em; - uint16_t l1wx; - uint16_t l1wy; - uint16_t l1ww; - uint16_t l1wh; - uint32_t pad07; - - /* Layer 2 extended */ - uint32_t l2em; - uint16_t l2wx; - uint16_t l2wy; - uint16_t l2ww; - uint16_t l2wh; - uint32_t pad08; - - /* Layer 3 extended */ - uint32_t l3em; - uint16_t l3wx; - uint16_t l3wy; - uint16_t l3ww; - uint16_t l3wh; - uint32_t pad09; - - /* Layer 4 extended */ - uint32_t l4em; - uint16_t l4wx; - uint16_t l4wy; - uint16_t l4ww; - uint16_t l4wh; - uint32_t pad10; - - /* Layer 5 extended */ - uint32_t l5em; - uint16_t l5wx; - uint16_t l5wy; - uint16_t l5ww; - uint16_t l5wh; - uint32_t pad11; - - /* Multi screen control */ - uint32_t msc; - uint32_t pad12[3]; - uint32_t dls; - uint32_t dbgc; - - /* Layer blending */ - uint32_t l1bld; - uint32_t l2bld; - uint32_t l3bld; - uint32_t l4bld; - uint32_t l5bld; - uint32_t pad13; - - /* Extended transparency control */ - uint32_t l0etc; - uint32_t l1etc; - uint32_t l2etc; - uint32_t l3etc; - uint32_t l4etc; - uint32_t l5etc; - uint32_t pad14[10]; - - /* YUV coefficients */ - uint32_t l1ycr0; - uint32_t l1ycr1; - uint32_t l1ycg0; - uint32_t l1ycg1; - uint32_t l1ycb0; - uint32_t l1ycb1; - uint32_t pad15[130]; - - /* Layer palletes */ - uint32_t l0pal[256]; - uint32_t l1pal[256]; - uint32_t pad16[256]; - uint32_t l2pal[256]; - uint32_t l3pal[256]; - uint32_t pad17[256]; - - /* PWM settings */ - uint32_t vpwmm; - uint16_t vpwms; - uint16_t vpwme; - uint32_t vpwmc; - uint32_t pad18[253]; -}; - -/* mb86r0x gdc capture controller */ -struct mb86r0x_gdc_cap { - uint32_t vcm; - uint32_t csc; - uint32_t vcs; - uint32_t pad01; - - uint32_t cbm; - uint32_t cboa; - uint32_t cbla; - uint16_t cihstr; - uint16_t civstr; - uint16_t cihend; - uint16_t civend; - uint32_t pad02; - - uint32_t chp; - uint32_t cvp; - uint32_t pad03[4]; - - uint32_t clpf; - uint32_t pad04; - uint32_t cmss; - uint32_t cmds; - uint32_t pad05[12]; - - uint32_t rgbhc; - uint32_t rgbhen; - uint32_t rgbven; - uint32_t pad06; - uint32_t rgbs; - uint32_t pad07[11]; - - uint32_t rgbcmy; - uint32_t rgbcmcb; - uint32_t rgbcmcr; - uint32_t rgbcmb; - uint32_t pad08[12 + 1984]; -}; - -/* mb86r0x gdc draw */ -struct mb86r0x_gdc_draw { - uint32_t ys; - uint32_t xs; - uint32_t dxdy; - uint32_t xus; - uint32_t dxudy; - uint32_t xls; - uint32_t dxldy; - uint32_t usn; - uint32_t lsn; - uint32_t pad01[7]; - uint32_t rs; - uint32_t drdx; - uint32_t drdy; - uint32_t gs; - uint32_t dgdx; - uint32_t dgdy; - uint32_t bs; - uint32_t dbdx; - uint32_t dbdy; - uint32_t pad02[7]; - uint32_t zs; - uint32_t dzdx; - uint32_t dzdy; - uint32_t pad03[13]; - uint32_t ss; - uint32_t dsdx; - uint32_t dsdy; - uint32_t ts; - uint32_t dtdx; - uint32_t dtdy; - uint32_t qs; - uint32_t dqdx; - uint32_t dqdy; - uint32_t pad04[23]; - uint32_t lpn; - uint32_t lxs; - uint32_t lxde; - uint32_t lys; - uint32_t lyde; - uint32_t lzs; - uint32_t lzde; - uint32_t pad05[13]; - uint32_t pxdc; - uint32_t pydc; - uint32_t pzdc; - uint32_t pad06[25]; - uint32_t rxs; - uint32_t rys; - uint32_t rsizex; - uint32_t rsizey; - uint32_t pad07[12]; - uint32_t saddr; - uint32_t sstride; - uint32_t srx; - uint32_t sry; - uint32_t daddr; - uint32_t dstride; - uint32_t drx; - uint32_t dry; - uint32_t brsizex; - uint32_t brsizey; - uint32_t tcolor; - uint32_t pad08[93]; - uint32_t blpo; - uint32_t pad09[7]; - uint32_t ctr; - uint32_t ifsr; - uint32_t ifcnt; - uint32_t sst; - uint32_t ds; - uint32_t pst; - uint32_t est; - uint32_t pad10; - uint32_t mdr0; - uint32_t mdr1; - uint32_t mdr2; - uint32_t mdr3; - uint32_t mdr4; - uint32_t pad14[2]; - uint32_t mdr7; - uint32_t fbr; - uint32_t xres; - uint32_t zbr; - uint32_t tbr; - uint32_t pfbr; - uint32_t cxmin; - uint32_t cxmax; - uint32_t cymin; - uint32_t cymax; - uint32_t txs; - uint32_t tis; - uint32_t toa; - uint32_t sho; - uint32_t abr; - uint32_t pad15[2]; - uint32_t fc; - uint32_t bc; - uint32_t alf; - uint32_t blp; - uint32_t pad16; - uint32_t tbc; - uint32_t pad11[42]; - uint32_t lx0dc; - uint32_t ly0dc; - uint32_t lx1dc; - uint32_t ly1dc; - uint32_t pad12[12]; - uint32_t x0dc; - uint32_t y0dc; - uint32_t x1dc; - uint32_t y1dc; - uint32_t x2dc; - uint32_t y2dc; - uint32_t pad13[666]; -}; - -/* mb86r0x gdc geometry engine */ -struct mb86r0x_gdc_geom { - uint32_t gctr; - uint32_t pad00[15]; - uint32_t gmdr0; - uint32_t gmdr1; - uint32_t gmdr2; - uint32_t pad01[237]; - uint32_t dfifog; - uint32_t pad02[767]; -}; - -/* mb86r0x gdc */ -struct mb86r0x_gdc { - uint32_t pad00[2]; - uint32_t lts; - uint32_t pad01; - uint32_t lsta; - uint32_t pad02[3]; - uint32_t ist; - uint32_t imask; - uint32_t pad03[6]; - uint32_t lsa; - uint32_t lco; - uint32_t lreq; - - uint32_t pad04[16*1024 - 19]; - struct mb86r0x_gdc_dsp dsp0; - struct mb86r0x_gdc_dsp dsp1; - uint32_t pad05[4*1024 - 2]; - uint32_t vccc; - uint32_t vcsr; - struct mb86r0x_gdc_cap cap0; - struct mb86r0x_gdc_cap cap1; - uint32_t pad06[4*1024]; - uint32_t texture_base[16*1024]; - struct mb86r0x_gdc_draw draw; - uint32_t pad07[7*1024]; - struct mb86r0x_gdc_geom geom; - uint32_t pad08[7*1024]; -}; - -/* mb86r0x ddr2c */ -struct mb86r0x_ddr2c { - uint16_t dric; - uint16_t dric1; - uint16_t dric2; - uint16_t drca; - uint16_t drcm; - uint16_t drcst1; - uint16_t drcst2; - uint16_t drcr; - uint16_t pad00[8]; - uint16_t drcf; - uint16_t pad01[7]; - uint16_t drasr; - uint16_t pad02[15]; - uint16_t drims; - uint16_t pad03[7]; - uint16_t dros; - uint16_t pad04; - uint16_t dribsodt1; - uint16_t dribsocd; - uint16_t dribsocd2; - uint16_t pad05[3]; - uint16_t droaba; - uint16_t pad06[9]; - uint16_t drobs; - uint16_t pad07[5]; - uint16_t drimr1; - uint16_t drimr2; - uint16_t drimr3; - uint16_t drimr4; - uint16_t droisr1; - uint16_t droisr2; -}; - -/* mb86r0x memc */ -struct mb86r0x_memc { - uint32_t mcfmode[8]; - uint32_t mcftim[8]; - uint32_t mcfarea[8]; -}; - -#endif /* __ASSEMBLY__ */ - -/* - * Physical Address Defines - */ -#define MB86R0x_DDR2_BASE 0xf3000000 -#define MB86R0x_GDC_BASE 0xf1fc0000 -#define MB86R0x_CCNT_BASE 0xfff42000 -#define MB86R0x_CAN0_BASE 0xfff54000 -#define MB86R0x_CAN1_BASE 0xfff55000 -#define MB86R0x_I2C0_BASE 0xfff56000 -#define MB86R0x_I2C1_BASE 0xfff57000 -#define MB86R0x_EHCI_BASE 0xfff80000 -#define MB86R0x_OHCI_BASE 0xfff81000 -#define MB86R0x_IRC1_BASE 0xfffb0000 -#define MB86R0x_MEMC_BASE 0xfffc0000 -#define MB86R0x_TIMER_BASE 0xfffe0000 -#define MB86R0x_UART0_BASE 0xfffe1000 -#define MB86R0x_UART1_BASE 0xfffe2000 -#define MB86R0x_IRCE_BASE 0xfffe4000 -#define MB86R0x_CRG_BASE 0xfffe7000 -#define MB86R0x_IRC0_BASE 0xfffe8000 -#define MB86R0x_GPIO_BASE 0xfffe9000 -#define MB86R0x_PWM0_BASE 0xfff41000 -#define MB86R0x_PWM1_BASE 0xfff41100 - -#define MB86R0x_CRSR_SWRSTREQ (1 << 1) - -/* - * Timer register bits - */ -#define MB86R0x_TIMER_ENABLE (1 << 7) -#define MB86R0x_TIMER_MODE_MSK (1 << 6) -#define MB86R0x_TIMER_MODE_FR (0 << 6) -#define MB86R0x_TIMER_MODE_PD (1 << 6) - -#define MB86R0x_TIMER_INT_EN (1 << 5) -#define MB86R0x_TIMER_PRS_MSK (3 << 2) -#define MB86R0x_TIMER_PRS_4S (1 << 2) -#define MB86R0x_TIMER_PRS_8S (1 << 3) -#define MB86R0x_TIMER_SIZE_32 (1 << 1) -#define MB86R0x_TIMER_ONE_SHT (1 << 0) - -/* - * Clock reset generator bits - */ -#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) -#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) -/* - * DDR2 controller bits - */ -#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) -#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) -#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) -#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN | \ - MB86R0x_DDR2_DRCI_DRCMD) -#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN) -#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN -#endif /* MB86R0X_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h deleted file mode 100644 index 9fdaa9dc0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> - * - * Modified for mx25 by John Rigby <jrigby@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_MX25_HCLK_FREQ -#define MXC_HCLK CONFIG_MX25_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX25_CLK32 -#define MXC_CLK32 CONFIG_MX25_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - /* PER clocks (do not change order) */ - MXC_CSI_CLK, - MXC_EPIT_CLK, - MXC_ESAI_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_GPT_CLK, - MXC_I2C_CLK, - MXC_LCDC_CLK, - MXC_NFC_CLK, - MXC_OWIRE_CLK, - MXC_PWM_CLK, - MXC_SIM1_CLK, - MXC_SIM2_CLK, - MXC_SSI1_CLK, - MXC_SSI2_CLK, - MXC_UART_CLK, - /* Other clocks */ - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_CLK_NUM -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); - -#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h deleted file mode 100644 index 81d95ea48..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_MX25_GPIO_H -#define __ASM_ARCH_MX25_GPIO_H - -#include <asm/imx-common/gpio.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h deleted file mode 100644 index a17f82834..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright (C) 2009, DENX Software Engineering - * Author: John Rigby <jcrigby@gmail.com - * - * Based on arch-mx31/imx-regs.h - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems <yanok@emcraft.com> - * and arch-mx27/imx-regs.h - * Copyright (C) 2007 Pengutronix, - * Sascha Hauer <s.hauer@pengutronix.de> - * Copyright (C) 2009 Ilya Yanok, - * Emcraft Systems <yanok@emcraft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 mpctl; /* Core PLL Control */ - u32 upctl; /* USB PLL Control */ - u32 cctl; /* Clock Control */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 pcdr[4]; /* PER Clock Dividers */ - u32 rcsr; /* CCM Status */ - u32 crdr; /* CCM Reset and Debug */ - u32 dcvr0; /* DPTC Comparator Value 0 */ - u32 dcvr1; /* DPTC Comparator Value 1 */ - u32 dcvr2; /* DPTC Comparator Value 2 */ - u32 dcvr3; /* DPTC Comparator Value 3 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ - u32 ltbr1; /* Load Tracking Buffer 1 */ - u32 pcmr0; /* Power Management Control 0 */ - u32 pcmr1; /* Power Management Control 1 */ - u32 pcmr2; /* Power Management Control 2 */ - u32 mcr; /* Miscellaneous Control */ - u32 lpimr0; /* Low Power Interrupt Mask 0 */ - u32 lpimr1; /* Low Power Interrupt Mask 1 */ -}; - -/* Enhanced SDRAM Controller (ESDRAMC) registers */ -struct esdramc_regs { - u32 ctl0; /* control 0 */ - u32 cfg0; /* configuration 0 */ - u32 ctl1; /* control 1 */ - u32 cfg1; /* configuration 1 */ - u32 misc; /* miscellaneous */ - u32 pad[3]; - u32 cdly1; /* Delay Line 1 configuration debug */ - u32 cdly2; /* delay line 2 configuration debug */ - u32 cdly3; /* delay line 3 configuration debug */ - u32 cdly4; /* delay line 4 configuration debug */ - u32 cdly5; /* delay line 5 configuration debug */ - u32 cdlyl; /* delay line cycle length debug */ -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* Watchdog Timer (WDOG) registers */ -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Misc Control */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_25[0xa]; - u32 mac_addr[6]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr5; - u32 fuse23_29[7]; - u32 usr6[2]; -}; - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; -}; - -#endif - -#define ARCH_MXC - -/* AIPS 1 */ -#define IMX_AIPS1_BASE (0x43F00000) -#define IMX_MAX_BASE (0x43F04000) -#define IMX_CLKCTL_BASE (0x43F08000) -#define IMX_ETB_SLOT4_BASE (0x43F0C000) -#define IMX_ETB_SLOT5_BASE (0x43F10000) -#define IMX_ECT_CTIO_BASE (0x43F18000) -#define IMX_I2C_BASE (0x43F80000) -#define IMX_I2C3_BASE (0x43F84000) -#define IMX_CAN1_BASE (0x43F88000) -#define IMX_CAN2_BASE (0x43F8C000) -#define UART1_BASE (0x43F90000) -#define UART2_BASE (0x43F94000) -#define IMX_I2C2_BASE (0x43F98000) -#define IMX_OWIRE_BASE (0x43F9C000) -#define IMX_CSPI1_BASE (0x43FA4000) -#define IMX_KPP_BASE (0x43FA8000) -#define IMX_IOPADMUX_BASE (0x43FAC000) -#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE -#define IMX_IOPADCTL_BASE (0x43FAC22C) -#define IMX_IOPADGRPCTL_BASE (0x43FAC418) -#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) -#define IMX_AUDMUX_BASE (0x43FB0000) -#define IMX_ECT_IP1_BASE (0x43FB8000) -#define IMX_ECT_IP2_BASE (0x43FBC000) - -/* SPBA */ -#define IMX_SPBA_BASE (0x50000000) -#define IMX_CSPI3_BASE (0x50004000) -#define UART4_BASE (0x50008000) -#define UART3_BASE (0x5000C000) -#define IMX_CSPI2_BASE (0x50010000) -#define IMX_SSI2_BASE (0x50014000) -#define IMX_ESAI_BASE (0x50018000) -#define IMX_ATA_DMA_BASE (0x50020000) -#define IMX_SIM1_BASE (0x50024000) -#define IMX_SIM2_BASE (0x50028000) -#define UART5_BASE (0x5002C000) -#define IMX_TSC_BASE (0x50030000) -#define IMX_SSI1_BASE (0x50034000) -#define IMX_FEC_BASE (0x50038000) -#define IMX_SPBA_CTRL_BASE (0x5003C000) - -/* AIPS 2 */ -#define IMX_AIPS2_BASE (0x53F00000) -#define IMX_CCM_BASE (0x53F80000) -#define IMX_GPT4_BASE (0x53F84000) -#define IMX_GPT3_BASE (0x53F88000) -#define IMX_GPT2_BASE (0x53F8C000) -#define IMX_GPT1_BASE (0x53F90000) -#define IMX_EPIT1_BASE (0x53F94000) -#define IMX_EPIT2_BASE (0x53F98000) -#define IMX_GPIO4_BASE (0x53F9C000) -#define IMX_PWM2_BASE (0x53FA0000) -#define IMX_GPIO3_BASE (0x53FA4000) -#define IMX_PWM3_BASE (0x53FA8000) -#define IMX_SCC_BASE (0x53FAC000) -#define IMX_SCM_BASE (0x53FAE000) -#define IMX_SMN_BASE (0x53FAF000) -#define IMX_RNGD_BASE (0x53FB0000) -#define IMX_MMC_SDHC1_BASE (0x53FB4000) -#define IMX_MMC_SDHC2_BASE (0x53FB8000) -#define IMX_LCDC_BASE (0x53FBC000) -#define IMX_SLCDC_BASE (0x53FC0000) -#define IMX_PWM4_BASE (0x53FC8000) -#define IMX_GPIO1_BASE (0x53FCC000) -#define IMX_GPIO2_BASE (0x53FD0000) -#define IMX_SDMA_BASE (0x53FD4000) -#define IMX_WDT_BASE (0x53FDC000) -#define IMX_PWM1_BASE (0x53FE0000) -#define IMX_RTIC_BASE (0x53FEC000) -#define IMX_IIM_BASE (0x53FF0000) -#define IIM_BASE_ADDR IMX_IIM_BASE -#define IMX_USB_BASE (0x53FF4000) -#define IMX_USB_PORT_OFFSET 0x200 -#define IMX_CSI_BASE (0x53FF8000) -#define IMX_DRYICE_BASE (0x53FFC000) - -#define IMX_ARM926_ROMPATCH (0x60000000) -#define IMX_ARM926_ASIC (0x68000000) - -/* 128K Internal Static RAM */ -#define IMX_RAM_BASE (0x78000000) -#define IMX_RAM_SIZE (128 * 1024) - -/* SDRAM BANKS */ -#define IMX_SDRAM_BANK0_BASE (0x80000000) -#define IMX_SDRAM_BANK1_BASE (0x90000000) - -#define IMX_WEIM_CS0 (0xA0000000) -#define IMX_WEIM_CS1 (0xA8000000) -#define IMX_WEIM_CS2 (0xB0000000) -#define IMX_WEIM_CS3 (0xB2000000) -#define IMX_WEIM_CS4 (0xB4000000) -#define IMX_ESDRAMC_BASE (0xB8001000) -#define IMX_WEIM_CTRL_BASE (0xB8002000) -#define IMX_M3IF_CTRL_BASE (0xB8003000) -#define IMX_EMI_CTRL_BASE (0xB8004000) - -/* NAND Flash Controller */ -#define IMX_NFC_BASE (0xBB000000) -#define NFC_BASE_ADDR IMX_NFC_BASE - -/* CCM bitfields */ -#define CCM_PLL_MFI_SHIFT 10 -#define CCM_PLL_MFI_MASK 0xf -#define CCM_PLL_MFN_SHIFT 0 -#define CCM_PLL_MFN_MASK 0x3ff -#define CCM_PLL_MFD_SHIFT 16 -#define CCM_PLL_MFD_MASK 0x3ff -#define CCM_PLL_PD_SHIFT 26 -#define CCM_PLL_PD_MASK 0xf -#define CCM_CCTL_ARM_DIV_SHIFT 30 -#define CCM_CCTL_ARM_DIV_MASK 3 -#define CCM_CCTL_AHB_DIV_SHIFT 28 -#define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) -#define CCM_CGR1_GPT1 (1 << 19) -#define CCM_PERCLK_REG(clk) (clk / 4) -#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) -#define CCM_PERCLK_MASK 0x3f -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) -#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) - -/* ESDRAM Controller register bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -/* GPT bits */ -#define GPT_CTRL_SWR (1 << 15) /* Software reset */ -#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ -#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ -#define GPT_CTRL_TEN 1 /* Timer enable */ - -/* WDOG enable */ -#define WCR_WDE 0x04 -#define WSR_UNLOCK1 0x5555 -#define WSR_UNLOCK2 0xAAAA - -/* Names used in GPIO driver */ -#define GPIO1_BASE_ADDR IMX_GPIO1_BASE -#define GPIO2_BASE_ADDR IMX_GPIO2_BASE -#define GPIO3_BASE_ADDR IMX_GPIO3_BASE -#define GPIO4_BASE_ADDR IMX_GPIO4_BASE - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_1_2 0x12 - -#endif /* _IMX_REGS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h deleted file mode 100644 index 220cf4ef2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h +++ /dev/null @@ -1,529 +0,0 @@ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on mainline Linux i.MX iomux-mx25.h file: - * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de> - * - * Based on Linux arch/arm/mach-mx25/mx25_pins.h: - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IOMUX_MX25_H__ -#define __IOMUX_MX25_H__ - -#include <asm/imx-common/iomux-v3.h> - -/* Pad control groupings */ -#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP -#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -/* - * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL), - - MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL), - MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL), - - MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL), - - MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL), - - MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL), - - MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL), - MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL), - MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL), - MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL), - MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL), - MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE), - MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE), - - MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP), - - MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL), - MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL), - MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL), - - MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL), - - MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL), - - MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL), - - MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL), - - MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL), - - MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL), - - MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE), - MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN), - MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL), - MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL), - MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL), - MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE), - - MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP), - - MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP), - - MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL), - MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL), - - MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL), - - MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL), - - MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL), - - MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL), - MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX25_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h deleted file mode 100644 index 6c41ea038..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2011 - * Matthias Weisser <weisserm@arcor.de> - * - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby <jrigby@gmail.com> - * - * Common asm macros for imx25 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_MACRO_H__ -#define __ASM_ARM_ARCH_MACRO_H__ -#ifdef __ASSEMBLY__ - -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - */ -.macro init_aips mpr=0x77777777 - ldr r0, =IMX_AIPS1_BASE - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =IMX_AIPS2_BASE - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =IMX_MAX_BASE - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 - * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000 - * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000001 - */ -.macro init_m3if ctl=0x00000001 - /* M3IF Control Register (M3IFCTL) */ - write32 IMX_M3IF_CTRL_BASE, \ctl -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h deleted file mode 100644 index c174bd04c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * - * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -enum mxc_clock { - MXC_ARM_CLK, - MXC_I2C_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_FEC_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK) -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h deleted file mode 100644 index 1e38b9319..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2012 - * Philippe Reynes <tremyfr@yahoo.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_MX27_GPIO_H -#define __ASM_ARCH_MX27_GPIO_H - -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dir; /* DDIR */ - u32 ocr1; - u32 ocr2; - u32 iconfa1; - u32 iconfa2; - u32 iconfb1; - u32 iconfb2; - u32 gpio_dr; /* DR */ - u32 gius; - u32 gpio_psr; /* SSR */ - u32 icr1; - u32 icr2; - u32 imr; - u32 isr; - u32 gpr; - u32 swr; - u32 puen; - u32 res[0x2f]; -}; - -/* This structure is used by the function imx_gpio_mode */ -struct gpio_port_regs { - struct gpio_regs port[6]; -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h deleted file mode 100644 index 92c847e44..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h +++ /dev/null @@ -1,503 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -#include <asm/arch/regs-rtc.h> - -#ifndef __ASSEMBLY__ - -extern void imx_gpio_mode (int gpio_mode); - -#ifdef CONFIG_MXC_UART -extern void mx27_uart1_init_pins(void); -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -extern void mx27_fec_init_pins(void); -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MXC_MMC -extern void mx27_sd1_init_pins(void); -extern void mx27_sd2_init_pins(void); -#endif /* CONFIG_MXC_MMC */ - -/* AIPI */ -struct aipi_regs { - u32 psr0; - u32 psr1; -}; - -/* System Control */ -struct system_control_regs { - u32 res[5]; - u32 fmcr; - u32 gpcr; - u32 wbcr; - u32 dscr1; - u32 dscr2; - u32 dscr3; - u32 dscr4; - u32 dscr5; - u32 dscr6; - u32 dscr7; - u32 dscr8; - u32 dscr9; - u32 dscr10; - u32 dscr11; - u32 dscr12; - u32 dscr13; - u32 pscr; - u32 pmcr; - u32 res1; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; -}; - -/* Chip Select Registers */ -struct weim_regs { - u32 cs0u; /* Chip Select 0 Upper Register */ - u32 cs0l; /* Chip Select 0 Lower Register */ - u32 cs0a; /* Chip Select 0 Addition Register */ - u32 pad0; - u32 cs1u; /* Chip Select 1 Upper Register */ - u32 cs1l; /* Chip Select 1 Lower Register */ - u32 cs1a; /* Chip Select 1 Addition Register */ - u32 pad1; - u32 cs2u; /* Chip Select 2 Upper Register */ - u32 cs2l; /* Chip Select 2 Lower Register */ - u32 cs2a; /* Chip Select 2 Addition Register */ - u32 pad2; - u32 cs3u; /* Chip Select 3 Upper Register */ - u32 cs3l; /* Chip Select 3 Lower Register */ - u32 cs3a; /* Chip Select 3 Addition Register */ - u32 pad3; - u32 cs4u; /* Chip Select 4 Upper Register */ - u32 cs4l; /* Chip Select 4 Lower Register */ - u32 cs4a; /* Chip Select 4 Addition Register */ - u32 pad4; - u32 cs5u; /* Chip Select 5 Upper Register */ - u32 cs5l; /* Chip Select 5 Lower Register */ - u32 cs5a; /* Chip Select 5 Addition Register */ - u32 pad5; - u32 eim; /* WEIM Configuration Register */ -}; - -/* SDRAM Controller registers */ -struct esdramc_regs { -/* Enhanced SDRAM Control Register 0 */ - u32 esdctl0; -/* Enhanced SDRAM Configuration Register 0 */ - u32 esdcfg0; -/* Enhanced SDRAM Control Register 1 */ - u32 esdctl1; -/* Enhanced SDRAM Configuration Register 1 */ - u32 esdcfg1; -/* Enhanced SDRAM Miscellanious Register */ - u32 esdmisc; -}; - -/* Watchdog Registers*/ -struct wdog_regs { - u32 wcr; - u32 wsr; - u32 wstr; -}; - -/* PLL registers */ -struct pll_regs { - u32 cscr; /* Clock Source Control Register */ - u32 mpctl0; /* MCU PLL Control Register 0 */ - u32 mpctl1; /* MCU PLL Control Register 1 */ - u32 spctl0; /* System PLL Control Register 0 */ - u32 spctl1; /* System PLL Control Register 1 */ - u32 osc26mctl; /* Oscillator 26M Register */ - u32 pcdr0; /* Peripheral Clock Divider Register 0 */ - u32 pcdr1; /* Peripheral Clock Divider Register 1 */ - u32 pccr0; /* Peripheral Clock Control Register 0 */ - u32 pccr1; /* Peripheral Clock Control Register 1 */ - u32 ccsr; /* Clock Control Status Register */ -}; - -/* - * Definitions for the clocksource registers - */ -struct gpt_regs { - u32 gpt_tctl; - u32 gpt_tprer; - u32 gpt_tcmp; - u32 gpt_tcr; - u32 gpt_tcn; - u32 gpt_tstat; -}; - -/* - * GPIO Module and I/O Multiplexer - */ -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTD 3 -#define PORTE 4 -#define PORTF 5 - -/* IIM Control Registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[2]; -}; - -struct fuse_bank0_regs { - u32 fuse0_3[5]; - u32 mac_addr[6]; - u32 fuse10_31[0x16]; -}; - -#endif - -#define ARCH_MXC - -#define IMX_IO_BASE 0x10000000 - -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) -#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) -#define UART1_BASE (0x0a000 + IMX_IO_BASE) -#define UART2_BASE (0x0b000 + IMX_IO_BASE) -#define UART3_BASE (0x0c000 + IMX_IO_BASE) -#define UART4_BASE (0x0d000 + IMX_IO_BASE) -#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) -#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) -#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) -#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) -#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) -#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) -#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) -#define IIM_BASE_ADDR IMX_IIM_BASE -#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) - -#define IMX_NFC_BASE (0xD8000000) -#define IMX_ESD_BASE (0xD8001000) -#define IMX_WEIM_BASE (0xD8002000) - -#define NFC_BASE_ADDR IMX_NFC_BASE - - -/* FMCR System Control bit definition*/ -#define UART4_RXD_CTL (1 << 25) -#define UART4_RTS_CTL (1 << 24) -#define KP_COL6_CTL (1 << 18) -#define KP_ROW7_CTL (1 << 17) -#define KP_ROW6_CTL (1 << 16) -#define PC_WAIT_B_CTL (1 << 14) -#define PC_READY_CTL (1 << 13) -#define PC_VS1_CTL (1 << 12) -#define PC_VS2_CTL (1 << 11) -#define PC_BVD1_CTL (1 << 10) -#define PC_BVD2_CTL (1 << 9) -#define IOS16_CTL (1 << 8) -#define NF_FMS (1 << 5) -#define NF_16BIT_SEL (1 << 4) -#define SLCDC_SEL (1 << 2) -#define SDCS1_SEL (1 << 1) -#define SDCS0_SEL (1 << 0) - - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_AHB_DIV -#define CSCR_ARM_DIV -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) -#define CSCR_SD_CNT -#define CSCR_USB_DIV -#define CSCR_UPDATE_DIS (1 << 31) - -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) - -/* SDRAM Controller registers bitfields */ -#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (1 << 16) -#define ESDCTL_DSIZ_32 (2 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHARGE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) - -#define ESDMISC_RST (1 << 1) -#define ESDMISC_MDDREN (1 << 2) -#define ESDMISC_MDDR_DL_RST (1 << 3) -#define ESDMISC_MDDR_MDIS (1 << 4) -#define ESDMISC_LHD (1 << 5) -#define ESDMISC_MA10_SHARE (1 << 6) -#define ESDMISC_SDRAM_RDY (1 << 31) - -#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) -#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) - -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) -#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) - -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) - -/* Clocksource Bitfields */ -#define TCTL_SWR (1 << 15) /* Software reset */ -#define TCTL_FRR (1 << 8) /* Freerun / restart */ -#define TCTL_CAP (3 << 6) /* Capture Edge */ -#define TCTL_OM (1 << 5) /* output mode */ -#define TCTL_IRQEN (1 << 4) /* interrupt enable */ -#define TCTL_CLKSOURCE 1 /* Clock source bit position */ -#define TCTL_TEN 1 /* Timer enable */ -#define TPRER_PRES 0xff /* Prescale */ -#define TSTAT_CAPT (1 << 1) /* Capture event */ -#define TSTAT_COMP 1 /* Compare event */ - -#define GPIO1_BASE_ADDR 0x10015000 -#define GPIO2_BASE_ADDR 0x10015100 -#define GPIO3_BASE_ADDR 0x10015200 -#define GPIO4_BASE_ADDR 0x10015300 -#define GPIO5_BASE_ADDR 0x10015400 -#define GPIO6_BASE_ADDR 0x10015500 - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) -#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) -#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) -#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) -#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) -#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define IIM_STAT_BUSY (1 << 7) -#define IIM_STAT_PRGD (1 << 1) -#define IIM_STAT_SNSD (1 << 0) -#define IIM_ERR_PRGE (1 << 7) -#define IIM_ERR_WPE (1 << 6) -#define IIM_ERR_OPE (1 << 5) -#define IIM_ERR_RPE (1 << 4) -#define IIM_ERR_WLRE (1 << 3) -#define IIM_ERR_SNSE (1 << 2) -#define IIM_ERR_PARITYE (1 << 1) - -#endif /* _IMX_REGS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h deleted file mode 100644 index 116328c8f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ASM_ARCH_MXCMMC_H -#define ASM_ARCH_MXCMMC_H - -int mxc_mmc_init(bd_t *bis); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h deleted file mode 100644 index 6b382546e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Freescale i.MX27 RTC Register Definitions - * - * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX27_REGS_RTC_H__ -#define __MX27_REGS_RTC_H__ - -#ifndef __ASSEMBLY__ -struct rtc_regs { - u32 hourmin; - u32 seconds; - u32 alrm_hm; - u32 alrm_sec; - u32 rtcctl; - u32 rtcisr; - u32 rtcienr; - u32 stpwch; - u32 dayr; - u32 dayalarm; -}; -#endif /* __ASSEMBLY__*/ - -#endif /* __MX28_REGS_RTC_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h deleted file mode 100644 index b955deb29..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_MX31_HCLK_FREQ -#define MXC_HCLK CONFIG_MX31_HCLK_FREQ -#else -#define MXC_HCLK 26000000 -#endif - -#ifdef CONFIG_MX31_CLK32 -#define MXC_CLK32 CONFIG_MX31_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_CSPI_CLK, - MXC_UART_CLK, - MXC_IPU_CLK, - MXC_ESDHC_CLK, - MXC_I2C_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -extern u32 imx_get_uartclk(void); -extern void mx31_gpio_mux(unsigned long mode); -extern void mx31_set_pad(enum iomux_pins pin, u32 config); -extern void mx31_set_gpr(enum iomux_gp_func gp, char en); - -void mx31_uart1_hw_init(void); -void mx31_uart2_hw_init(void); -void mx31_spi2_hw_init(void); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h deleted file mode 100644 index 14e9b85c8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_MX31_GPIO_H -#define __ASM_ARCH_MX31_GPIO_H - -#include <asm/imx-common/gpio.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h deleted file mode 100644 index f23350e5c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h +++ /dev/null @@ -1,917 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX31_IMX_REGS_H -#define __ASM_ARCH_MX31_IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock control module registers */ -struct clock_control_regs { - u32 ccmr; - u32 pdr0; - u32 pdr1; - u32 rcsr; - u32 mpctl; - u32 upctl; - u32 spctl; - u32 cosr; - u32 cgr0; - u32 cgr1; - u32 cgr2; - u32 wimr0; - u32 ldc; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; - u32 ltr0; - u32 ltr1; - u32 ltr2; - u32 ltr3; - u32 ltbr0; - u32 ltbr1; - u32 pmcr0; - u32 pmcr1; - u32 pdr2; -}; - -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 intr; - u32 dma; - u32 stat; - u32 period; - u32 test; -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_5[6]; - u32 usr; - u32 fuse7_15[9]; -}; - -struct fuse_bank2_regs { - u32 fuse0; - u32 uid[8]; - u32 fuse9_15[7]; -}; - -struct iomuxc_regs { - u32 unused1; - u32 unused2; - u32 gpr; -}; - -struct mx3_cpu_type { - u8 srev; - u32 v; -}; - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), - MX31_PIN_PWMO = IOMUX_PIN(9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN(8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* Bit definitions for RCSR register in CCM */ -#define CCM_RCSR_NF16B (1 << 31) -#define CCM_RCSR_NFMS (1 << 30) - -/* WEIM CS control registers */ -struct mx31_weim_cscr { - u32 upper; - u32 lower; - u32 additional; - u32 reserved; -}; - -struct mx31_weim { - struct mx31_weim_cscr cscr[6]; -}; - -/* ESD control registers */ -struct esdc_regs { - u32 ctl0; - u32 cfg0; - u32 ctl1; - u32 cfg1; - u32 misc; - u32 dly[5]; - u32 dlyl; -}; - -#endif - -#define ARCH_MXC - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -#define CCM_BASE 0x53f80000 -#define CCM_CCMR (CCM_BASE + 0x00) -#define CCM_PDR0 (CCM_BASE + 0x04) -#define CCM_PDR1 (CCM_BASE + 0x08) -#define CCM_RCSR (CCM_BASE + 0x0c) -#define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x14) -#define CCM_SPCTL (CCM_BASE + 0x18) -#define CCM_COSR (CCM_BASE + 0x1C) -#define CCM_CGR0 (CCM_BASE + 0x20) -#define CCM_CGR1 (CCM_BASE + 0x24) -#define CCM_CGR2 (CCM_BASE + 0x28) - -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) - -#define MX31_IIM_BASE_ADDR 0x5001C000 -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR - -#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) -#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) - -#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) -#define PDR1_USB_PODF(x) (((x) & 0x7) << 27) -#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) -#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) -#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) -#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) -#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) -#define PDR1_SSI1_PODF(x) ((x) & 0x3f) - -#define PLL_BRMO(x) (((x) & 0x1) << 31) -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) -#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) -#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) -#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) -#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) -#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) -#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) -#define GET_PDR0_MCU_PODF(x) ((x) & 0x7) - -#define GET_PLL_PD(x) (((x) >> 26) & 0xf) -#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) -#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) -#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) - - -#define WEIM_ESDCTL0 0xB8001000 -#define WEIM_ESDCFG0 0xB8001004 -#define WEIM_ESDCTL1 0xB8001008 -#define WEIM_ESDCFG1 0xB800100C -#define WEIM_ESDMISC 0xB8001010 - -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define UART3_BASE 0x5000C000 -#define UART4_BASE 0x43FB0000 -#define UART5_BASE 0x43FB4000 - -#define I2C1_BASE_ADDR 0x43f80000 -#define I2C1_CLK_OFFSET 26 -#define I2C2_BASE_ADDR 0x43F98000 -#define I2C2_CLK_OFFSET 28 -#define I2C3_BASE_ADDR 0x43f84000 -#define I2C3_CLK_OFFSET 30 - -#define ESDCTL_SDE (1 << 31) -#define ESDCTL_CMD_RW (0 << 28) -#define ESDCTL_CMD_PRECHARGE (1 << 28) -#define ESDCTL_CMD_AUTOREFRESH (2 << 28) -#define ESDCTL_CMD_LOADMODEREG (3 << 28) -#define ESDCTL_CMD_MANUALREFRESH (4 << 28) -#define ESDCTL_ROW_13 (2 << 24) -#define ESDCTL_ROW(x) ((x) << 24) -#define ESDCTL_COL_9 (1 << 20) -#define ESDCTL_COL(x) ((x) << 20) -#define ESDCTL_DSIZ(x) ((x) << 16) -#define ESDCTL_SREFR(x) ((x) << 13) -#define ESDCTL_PWDT(x) ((x) << 10) -#define ESDCTL_FP(x) ((x) << 8) -#define ESDCTL_BL(x) ((x) << 7) -#define ESDCTL_PRCT(x) ((x) << 0) - -#define ESDCTL_BASE_ADDR 0xB8001000 - -/* 13 fields of the upper CS control register */ -#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ - (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ - (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -#define WEIM_BASE 0xb8002000 - -#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) - -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -#define ARM_PPMRR 0x40000015 - -#define WDOG1_BASE_ADDR 0x53FDC000 - -/* - * GPIO - */ -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define GPIO_DR 0x00000000 /* data register */ -#define GPIO_GDIR 0x00000004 /* direction register */ -#define GPIO_PSR 0x00000008 /* pad status register */ - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) - -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_CSPI3_MISO 0x0c -#define MUX_CTL_CSPI3_SCLK 0x0d -#define MUX_CTL_CSPI3_SPI_RDY 0x0e -#define MUX_CTL_CSPI3_MOSI 0x13 - -#define MUX_CTL_SD1_DATA1 0x18 -#define MUX_CTL_SD1_DATA2 0x19 -#define MUX_CTL_SD1_DATA3 0x1a -#define MUX_CTL_SD1_CMD 0x1d -#define MUX_CTL_SD1_CLK 0x1e -#define MUX_CTL_SD1_DATA0 0x1f - -#define MUX_CTL_USBH2_DATA1 0x40 -#define MUX_CTL_USBH2_DIR 0x44 -#define MUX_CTL_USBH2_STP 0x45 -#define MUX_CTL_USBH2_NXT 0x46 -#define MUX_CTL_USBH2_DATA0 0x47 -#define MUX_CTL_USBH2_CLK 0x4B - -#define MUX_CTL_TXD2 0x70 -#define MUX_CTL_RTS2 0x71 -#define MUX_CTL_CTS2 0x72 -#define MUX_CTL_RXD2 0x77 - -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -#define MUX_CTL_CSPI2_SS0 0x85 -#define MUX_CTL_CSPI2_SS1 0x86 -#define MUX_CTL_CSPI2_SS2 0x87 -#define MUX_CTL_CSPI1_SS2 0x88 -#define MUX_CTL_CSPI1_SCLK 0x89 -#define MUX_CTL_CSPI1_SPI_RDY 0x8a -#define MUX_CTL_CSPI2_MOSI 0x8b -#define MUX_CTL_CSPI1_MOSI 0x8c -#define MUX_CTL_CSPI1_MISO 0x8d -#define MUX_CTL_CSPI1_SS0 0x8e -#define MUX_CTL_CSPI1_SS1 0x8f -#define MUX_CTL_STXD6 0x90 -#define MUX_CTL_SRXD6 0x91 -#define MUX_CTL_SCK6 0x92 -#define MUX_CTL_SFS6 0x93 - -#define MUX_CTL_STXD3 0x9C -#define MUX_CTL_SRXD3 0x9D -#define MUX_CTL_SCK3 0x9E -#define MUX_CTL_SFS3 0x9F - -#define MUX_CTL_NFC_WP 0xD0 -#define MUX_CTL_NFC_CE 0xD1 -#define MUX_CTL_NFC_RB 0xD2 -#define MUX_CTL_NFC_WE 0xD4 -#define MUX_CTL_NFC_RE 0xD5 -#define MUX_CTL_NFC_ALE 0xD6 -#define MUX_CTL_NFC_CLE 0xD7 - - -#define MUX_CTL_CAPTURE 0x150 -#define MUX_CTL_COMPARE 0x151 - -/* - * Helper macros for the MUX_[contact name]__[pin function] macros - */ -#define IOMUX_MODE_POS 9 -#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) - -/* - * These macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) -#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) -#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) -#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) - -#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) -#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) -#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) -#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) - -#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) -#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) -#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) -#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) -#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) -#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) -#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) -#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) -#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) - -/* PAD control registers for SDR/DDR */ -#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) -#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) -#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) -#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) -#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) -#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) -#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) -#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) -#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) -#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) -#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) -#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) -#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) -#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) -#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) -#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) -#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) -#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) -#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) -#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) -#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) -#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) -#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) -#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) -#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) -#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) -#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) -#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) -#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE 0x70000000 -#define CSD0_BASE 0x80000000 -#define CSD1_BASE 0x90000000 -#define CS0_BASE 0xA0000000 -#define CS1_BASE 0xA8000000 -#define CS2_BASE 0xB0000000 -#define CS3_BASE 0xB2000000 -#define CS4_BASE 0xB4000000 -#define CS4_PSRAM_BASE 0xB5000000 -#define CS5_BASE 0xB6000000 -#define PCMCIA_MEM_BASE 0xC0000000 - -/* - * NAND controller - */ -#define NFC_BASE_ADDR 0xB8000000 - -/* SD card controller */ -#define SDHC1_BASE_ADDR 0x50004000 -#define SDHC2_BASE_ADDR 0x50008000 - -/* - * Internal RAM (16KB) - */ -#define IRAM_BASE_ADDR 0x1FFFC000 -#define IRAM_SIZE (16 * 1024) - -#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) -#define IMX_USB_PORT_OFFSET 0x200 - -/* - * CSPI register definitions - */ -#define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 8) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0x1f - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, \ - 0x53f84000, - -#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h deleted file mode 100644 index b0dfcba58..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -struct mxc_weimcs { - u32 upper; - u32 lower; - u32 additional; -}; - -void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); -int mxc_mmc_init(bd_t *bis); -u32 get_cpu_rev(void); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h deleted file mode 100644 index bc85aa73b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_MX35_HCLK_FREQ -#define MXC_HCLK CONFIG_MX35_HCLK_FREQ -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_MX35_CLK32 -#define MXC_CLK32 CONFIG_MX35_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_ESDHC1_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_USB_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; - -enum mxc_main_clock { - CPU_CLK, - AHB_CLK, - IPG_CLK, - IPG_PER_CLK, - NFC_CLK, - USB_CLK, - HSP_CLK, -}; - -enum mxc_peri_clock { - UART1_BAUD, - UART2_BAUD, - UART3_BAUD, - SSI1_BAUD, - SSI2_BAUD, - CSI_BAUD, - MSHC_CLK, - ESDHC1_CLK, - ESDHC2_CLK, - ESDHC3_CLK, - SPDIF_CLK, - SPI1_CLK, - SPI2_CLK, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h deleted file mode 100644 index a58ebd523..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright 2004-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ -#define __CPU_ARM1136_MX35_CRM_REGS_H__ - -/* Register bit definitions */ -#define MXC_CCM_CCMR_WFI (1 << 30) -#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) -#define MXC_CCM_CCMR_VSTBY (1 << 28) -#define MXC_CCM_CCMR_WBEN (1 << 27) -#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 -#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) -#define MXC_CCM_CCMR_ROMW_OFFSET 18 -#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 16 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) -#define MXC_CCM_CCMR_LPM_OFFSET 14 -#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) -#define MXC_CCM_CCMR_UPE (1 << 9) -#define MXC_CCM_CCMR_MPE (1 << 3) - -#define MXC_CCM_PDR0_PER_SEL (1 << 26) -#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) -#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 -#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) -#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 -#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) -#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) -#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) -#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 -#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) -#define MXC_CCM_PDR0_AUTO_CON 0x1 - -#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 -#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) -#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 -#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) - -#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 -#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) -#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 -#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 -#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR2_CSI_M_U (1 << 7) -#define MXC_CCM_PDR2_SSI_M_U (1 << 6) -#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 -#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) - -#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 -#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) -#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 -#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) -#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 14) -#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) -#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) - -#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 -#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) -#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) -#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) -#define MXC_CCM_PDR4_USB_M_U (1 << 9) - -/* Bit definitions for RCSR */ -#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) -#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) -#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) -#define MXC_CCM_RCSR_PAGE_512 (0 << 27) -#define MXC_CCM_RCSR_PAGE_2K (1 << 27) -#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) -#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) -#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) -#define MXC_CCM_RCSR_NF16B (1 << 14) -#define MXC_CCM_RCSR_NFC_4K (1 << 9) -#define MXC_CCM_RCSR_NFC_FMS (1 << 8) - -/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ -#define MXC_CCM_PCTL_BRM 0x80000000 -#define MXC_CCM_PCTL_PD_OFFSET 26 -#define MXC_CCM_PCTL_PD_MASK (0xF << 26) -#define MXC_CCM_PCTL_MFD_OFFSET 16 -#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) -#define MXC_CCM_PCTL_MFI_OFFSET 10 -#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) -#define MXC_CCM_PCTL_MFN_OFFSET 0 -#define MXC_CCM_PCTL_MFN_MASK 0x3FF - -/* Bit definitions for Audio clock mux register*/ -#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 -#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) -#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 -#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) -#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 -#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) -#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 -#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) - -/* Bit definitions for Clock gating Register*/ -#define MXC_CCM_CGR_CG_MASK 0x3 -#define MXC_CCM_CGR_CG_OFF 0x0 -#define MXC_CCM_CGR_CG_RUN_ON 0x1 -#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 -#define MXC_CCM_CGR_CG_ON 0x3 - -#define MXC_CCM_CGR0_ASRC_OFFSET 0 -#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) -#define MXC_CCM_CGR0_ATA_OFFSET 2 -#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) -#define MXC_CCM_CGR0_CAN1_OFFSET 6 -#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) -#define MXC_CCM_CGR0_CAN2_OFFSET 8 -#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) -#define MXC_CCM_CGR0_CSPI1_OFFSET 10 -#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) -#define MXC_CCM_CGR0_CSPI2_OFFSET 12 -#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) -#define MXC_CCM_CGR0_ECT_OFFSET 14 -#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) -#define MXC_CCM_CGR0_EDIO_OFFSET 16 -#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) -#define MXC_CCM_CGR0_EMI_OFFSET 18 -#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) -#define MXC_CCM_CGR0_EPIT1_OFFSET 20 -#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) -#define MXC_CCM_CGR0_EPIT2_OFFSET 22 -#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) -#define MXC_CCM_CGR0_ESAI_OFFSET 24 -#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) -#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 -#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) -#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 -#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) -#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 -#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) - -#define MXC_CCM_CGR1_FEC_OFFSET 0 -#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) -#define MXC_CCM_CGR1_GPIO1_OFFSET 2 -#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) -#define MXC_CCM_CGR1_GPIO2_OFFSET 4 -#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) -#define MXC_CCM_CGR1_GPIO3_OFFSET 6 -#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) -#define MXC_CCM_CGR1_GPT_OFFSET 8 -#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) -#define MXC_CCM_CGR1_I2C1_OFFSET 10 -#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) -#define MXC_CCM_CGR1_I2C2_OFFSET 12 -#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) -#define MXC_CCM_CGR1_I2C3_OFFSET 14 -#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) -#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 -#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) -#define MXC_CCM_CGR1_IPU_OFFSET 18 -#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) -#define MXC_CCM_CGR1_KPP_OFFSET 20 -#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) -#define MXC_CCM_CGR1_MLB_OFFSET 22 -#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) -#define MXC_CCM_CGR1_MSHC_OFFSET 24 -#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) -#define MXC_CCM_CGR1_OWIRE_OFFSET 26 -#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) -#define MXC_CCM_CGR1_PWM_OFFSET 28 -#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) -#define MXC_CCM_CGR1_RNGC_OFFSET 30 -#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) - -#define MXC_CCM_CGR2_RTC_OFFSET 0 -#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) -#define MXC_CCM_CGR2_RTIC_OFFSET 2 -#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) -#define MXC_CCM_CGR2_SCC_OFFSET 4 -#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) -#define MXC_CCM_CGR2_SDMA_OFFSET 6 -#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) -#define MXC_CCM_CGR2_SPBA_OFFSET 8 -#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) -#define MXC_CCM_CGR2_SPDIF_OFFSET 10 -#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) -#define MXC_CCM_CGR2_SSI1_OFFSET 12 -#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) -#define MXC_CCM_CGR2_SSI2_OFFSET 14 -#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) -#define MXC_CCM_CGR2_UART1_OFFSET 16 -#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) -#define MXC_CCM_CGR2_UART2_OFFSET 18 -#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) -#define MXC_CCM_CGR2_UART3_OFFSET 20 -#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) -#define MXC_CCM_CGR2_USBOTG_OFFSET 22 -#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) -#define MXC_CCM_CGR2_WDOG_OFFSET 24 -#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) -#define MXC_CCM_CGR2_MAX_OFFSET 26 -#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) -#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) -#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 -#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) - -#define MXC_CCM_CGR3_CSI_OFFSET 0 -#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) -#define MXC_CCM_CGR3_IIM_OFFSET 2 -#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) -#define MXC_CCM_CGR3_GPU2D_OFFSET 4 -#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) - -#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F -#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 -#define MXC_CCM_COSR_CLKOEN (1 << 5) -#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) -#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 -#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) -#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 -#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) -#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 -#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) -#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 -#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) -#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 -#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) -#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) -#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h deleted file mode 100644 index f3572a402..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_MX35_GPIO_H -#define __ASM_ARCH_MX35_GPIO_H - -#include <asm/imx-common/gpio.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h deleted file mode 100644 index b5300291a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h +++ /dev/null @@ -1,375 +0,0 @@ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX35_H -#define __ASM_ARCH_MX35_H - -#define ARCH_MXC - -/* - * IRAM - */ -#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define IRAM_SIZE 0x00020000 /* 128 KB */ - -#define LOW_LEVEL_SRAM_STACK 0x1001E000 - -/* - * AIPS 1 - */ -#define AIPS1_BASE_ADDR 0x43F00000 -#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR -#define MAX_BASE_ADDR 0x43F04000 -#define EVTMON_BASE_ADDR 0x43F08000 -#define CLKCTL_BASE_ADDR 0x43F0C000 -#define I2C1_BASE_ADDR 0x43F80000 -#define I2C3_BASE_ADDR 0x43F84000 -#define ATA_BASE_ADDR 0x43F8C000 -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define I2C2_BASE_ADDR 0x43F98000 -#define CSPI1_BASE_ADDR 0x43FA4000 -#define IOMUXC_BASE_ADDR 0x43FAC000 - -/* - * SPBA - */ -#define SPBA_BASE_ADDR 0x50000000 -#define UART3_BASE 0x5000C000 -#define CSPI2_BASE_ADDR 0x50010000 -#define ATA_DMA_BASE_ADDR 0x50020000 -#define FEC_BASE_ADDR 0x50038000 -#define SPBA_CTRL_BASE_ADDR 0x5003C000 - -/* - * AIPS 2 - */ -#define AIPS2_BASE_ADDR 0x53F00000 -#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR -#define CCM_BASE_ADDR 0x53F80000 -#define GPT1_BASE_ADDR 0x53F90000 -#define EPIT1_BASE_ADDR 0x53F94000 -#define EPIT2_BASE_ADDR 0x53F98000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define MMC_SDHC1_BASE_ADDR 0x53FB4000 -#define MMC_SDHC2_BASE_ADDR 0x53FB8000 -#define MMC_SDHC3_BASE_ADDR 0x53FBC000 -#define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define SDMA_BASE_ADDR 0x53FD4000 -#define RTC_BASE_ADDR 0x53FD8000 -#define WDOG1_BASE_ADDR 0x53FDC000 -#define PWM_BASE_ADDR 0x53FE0000 -#define RTIC_BASE_ADDR 0x53FEC000 -#define IIM_BASE_ADDR 0x53FF0000 -#define IMX_USB_BASE 0x53FF4000 -#define IMX_USB_PORT_OFFSET 0x400 - -#define IMX_CCM_BASE CCM_BASE_ADDR - -/* - * ROMPATCH and AVIC - */ -#define ROMPATCH_BASE_ADDR 0x60000000 -#define AVIC_BASE_ADDR 0x68000000 - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define EXT_MEM_CTRL_BASE 0xB8000000 -#define ESDCTL_BASE_ADDR 0xB8001000 -#define WEIM_BASE_ADDR 0xB8002000 -#define WEIM_CTRL_CS0 WEIM_BASE_ADDR -#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) -#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) -#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) -#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) -#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) -#define M3IF_BASE_ADDR 0xB8003000 -#define EMI_BASE_ADDR 0xB8004000 - -#define NFC_BASE_ADDR 0xBB000000 - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE_ADDR 0x70000000 -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 -#define CS0_BASE_ADDR 0xA0000000 -#define CS1_BASE_ADDR 0xA8000000 -#define CS2_BASE_ADDR 0xB0000000 -#define CS3_BASE_ADDR 0xB2000000 -#define CS4_BASE_ADDR 0xB4000000 -#define CS5_BASE_ADDR 0xB6000000 - -/* - * IRQ Controller Register Definitions. - */ -#define AVIC_NIMASK 0x04 -#define AVIC_INTTYPEH 0x18 -#define AVIC_INTTYPEL 0x1C - -/* L210 */ -#define L2CC_BASE_ADDR 0x30000000 -#define L2_CACHE_LINE_SIZE 32 -#define L2_CACHE_CTL_REG 0x100 -#define L2_CACHE_AUX_CTL_REG 0x104 -#define L2_CACHE_SYNC_REG 0x730 -#define L2_CACHE_INV_LINE_REG 0x770 -#define L2_CACHE_INV_WAY_REG 0x77C -#define L2_CACHE_CLEAN_LINE_REG 0x7B0 -#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 -#define L2_CACHE_DBG_CTL_REG 0xF40 - -#define CLKMODE_AUTO 0 -#define CLKMODE_CONSUMER 1 - -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define _PLL_BRM(x) ((x) << 31) -#define _PLL_PD(x) (((x) - 1) << 26) -#define _PLL_MFD(x) (((x) - 1) << 16) -#define _PLL_MFI(x) ((x) << 10) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - -#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) -#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) -#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) - -#define IIM_SREV 0x24 -#define ROMPATCH_REV 0x40 - -#define IPU_CONF IPU_CTRL_BASE_ADDR - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -/* - * CSPI register definitions - */ -#define MXC_CSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, - -#define GPIO_PORT_NUM 3 -#define GPIO_NUM_PIN 32 - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_2_0 0x20 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock Control Module (CCM) registers */ -struct ccm_regs { - u32 ccmr; /* Control */ - u32 pdr0; /* Post divider 0 */ - u32 pdr1; /* Post divider 1 */ - u32 pdr2; /* Post divider 2 */ - u32 pdr3; /* Post divider 3 */ - u32 pdr4; /* Post divider 4 */ - u32 rcsr; /* CCM Status */ - u32 mpctl; /* Core PLL Control */ - u32 ppctl; /* Peripheral PLL Control */ - u32 acmr; /* Audio clock mux */ - u32 cosr; /* Clock out source */ - u32 cgr0; /* Clock Gating Control 0 */ - u32 cgr1; /* Clock Gating Control 1 */ - u32 cgr2; /* Clock Gating Control 2 */ - u32 cgr3; /* Clock Gating Control 3 */ - u32 reserved; - u32 dcvr0; /* DPTC Comparator 0 */ - u32 dcvr1; /* DPTC Comparator 0 */ - u32 dcvr2; /* DPTC Comparator 0 */ - u32 dcvr3; /* DPTC Comparator 0 */ - u32 ltr0; /* Load Tracking 0 */ - u32 ltr1; /* Load Tracking 1 */ - u32 ltr2; /* Load Tracking 2 */ - u32 ltr3; /* Load Tracking 3 */ - u32 ltbr0; /* Load Tracking Buffer 0 */ -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res1[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_31[0x10]; -}; - -struct fuse_bank1_regs { - u32 fuse0_21[0x16]; - u32 usr; - u32 fuse23_31[9]; -}; - -/* General Purpose Timer (GPT) registers */ -struct gpt_regs { - u32 ctrl; /* control */ - u32 pre; /* prescaler */ - u32 stat; /* status */ - u32 intr; /* interrupt */ - u32 cmp[3]; /* output compare 1-3 */ - u32 capt[2]; /* input capture 1-2 */ - u32 counter; /* counter */ -}; - -/* CSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 intr; - u32 dma; - u32 stat; - u32 period; - u32 test; -}; - -struct esdc_regs { - u32 esdctl0; - u32 esdcfg0; - u32 esdctl1; - u32 esdcfg1; - u32 esdmisc; - u32 reserved[4]; - u32 esdcdly[5]; - u32 esdcdlyl; -}; - -#define ESDC_MISC_RST (1 << 1) -#define ESDC_MISC_MDDR_EN (1 << 2) -#define ESDC_MISC_MDDR_DL_RST (1 << 3) -#define ESDC_MISC_DDR_EN (1 << 8) -#define ESDC_MISC_DDR2_EN (1 << 9) - -/* Multi-Layer AHB Crossbar Switch (MAX) registers */ -struct max_regs { - u32 mpr0; - u32 pad00[3]; - u32 sgpcr0; - u32 pad01[59]; - u32 mpr1; - u32 pad02[3]; - u32 sgpcr1; - u32 pad03[59]; - u32 mpr2; - u32 pad04[3]; - u32 sgpcr2; - u32 pad05[59]; - u32 mpr3; - u32 pad06[3]; - u32 sgpcr3; - u32 pad07[59]; - u32 mpr4; - u32 pad08[3]; - u32 sgpcr4; - u32 pad09[251]; - u32 mgpcr0; - u32 pad10[63]; - u32 mgpcr1; - u32 pad11[63]; - u32 mgpcr2; - u32 pad12[63]; - u32 mgpcr3; - u32 pad13[63]; - u32 mgpcr4; - u32 pad14[63]; - u32 mgpcr5; -}; - -/* AHB <-> IP-Bus Interface (AIPS) */ -struct aips_regs { - u32 mpr_0_7; - u32 mpr_8_15; - u32 pad0[6]; - u32 pacr_0_7; - u32 pacr_8_15; - u32 pacr_16_23; - u32 pacr_24_31; - u32 pad1[4]; - u32 opacr_0_7; - u32 opacr_8_15; - u32 opacr_16_23; - u32 opacr_24_31; - u32 opacr_32_39; -}; - -/* - * NFMS bit in RCSR register for pagesize of nandflash - */ -#define NFMS_BIT 8 -#define NFMS_NF_DWIDTH 14 -#define NFMS_NF_PG_SZ 8 - -#define CCM_RCSR_NF_16BIT_SEL (1 << 14) - -#endif -#endif /* __ASM_ARCH_MX35_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h deleted file mode 100644 index 5898b46f4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h +++ /dev/null @@ -1,1260 +0,0 @@ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on mainline Linux i.MX iomux-mx35.h file: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IOMUX_MX35_H__ -#define __IOMUX_MX35_H__ - -#include <asm/imx-common/iomux-v3.h> - -/* - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL), - MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL), - - MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL), - MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL), - MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL), - MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL), - - MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL), - - MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL), - MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL), - - MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL), - MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL), - MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL), - - MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL), - - MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL), - MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL), - MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL), - MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL), - MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL), - MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL), - MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL), - MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL), - - MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL), - MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL), - MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL), - MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL), - MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL), - MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL), - MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL), - MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL), - MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL), - MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL), - MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL), - MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL), - MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL), - MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL), - MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL), - MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL), - MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL), - - MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL), - MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL), - MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL), - - MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL), - MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL), - - MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL), - MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL), - MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL), - - MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL), - MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL), - - MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL), - MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL), - - MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL), - MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL), - MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL), - MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL), - - MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL), - MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL), - MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL), - MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL), - MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL), - - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL), - MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL), - MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL), - MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL), - MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL), - MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL), - MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL), - MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL), - - MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL), - MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL), - MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL), - - MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL), - MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL), - - MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL), - MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL), - - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL), - MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL), - - MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL), - MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL), - MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL), - MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL), - MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL), - MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL), - MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL), - MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL), - MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL), - MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL), - MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL), - MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL), - MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL), - MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL), - MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL), - MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL), - MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL), - MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL), - MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL), - MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL), - MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL), - MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL), - MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL), - MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL), - MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL), - MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL), - MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL), - MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL), - MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL), - MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL), - MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL), - MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL), - MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL), - MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL), - MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL), - MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL), - MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL), - MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL), - MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL), - MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL), - - MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL), - MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL), - - MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL), - MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL), - - MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL), - MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL), - MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL), - - MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL), - MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL), - MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL), - MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL), - MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL), - - MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL), - MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL), - MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL), - - MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX35_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S deleted file mode 100644 index b55d2ef04..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> -#include <asm/macro.h> - -/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - * - * Default argument values: - * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to - * user-mode. - * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for - * SDMA to access them. - */ -.macro init_aips mpr=0x77777777, opacr=0x00000000 - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =\mpr - str r1, [r0, #AIPS_MPR_0_7] - str r1, [r0, #AIPS_MPR_8_15] - ldr r2, =AIPS2_BASE_ADDR - str r1, [r2, #AIPS_MPR_0_7] - str r1, [r2, #AIPS_MPR_8_15] - - /* Did not change the AIPS control registers access type. */ - ldr r1, =\opacr - str r1, [r0, #AIPS_OPACR_0_7] - str r1, [r0, #AIPS_OPACR_8_15] - str r1, [r0, #AIPS_OPACR_16_23] - str r1, [r0, #AIPS_OPACR_24_31] - str r1, [r0, #AIPS_OPACR_32_39] - str r1, [r2, #AIPS_OPACR_0_7] - str r1, [r2, #AIPS_OPACR_8_15] - str r1, [r2, #AIPS_OPACR_16_23] - str r1, [r2, #AIPS_OPACR_24_31] - str r1, [r2, #AIPS_OPACR_32_39] -.endm - -/* - * MAX (Multi-Layer AHB Crossbar Switch) setup - * - * Default argument values: - * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 - * - SGPCR: always park on last master - * - MGPCR: restore default values - */ -.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 - ldr r0, =MAX_BASE_ADDR - ldr r1, =\mpr - str r1, [r0, #MAX_MPR0] /* for S0 */ - str r1, [r0, #MAX_MPR1] /* for S1 */ - str r1, [r0, #MAX_MPR2] /* for S2 */ - str r1, [r0, #MAX_MPR3] /* for S3 */ - str r1, [r0, #MAX_MPR4] /* for S4 */ - ldr r1, =\sgpcr - str r1, [r0, #MAX_SGPCR0] /* for S0 */ - str r1, [r0, #MAX_SGPCR1] /* for S1 */ - str r1, [r0, #MAX_SGPCR2] /* for S2 */ - str r1, [r0, #MAX_SGPCR3] /* for S3 */ - str r1, [r0, #MAX_SGPCR4] /* for S4 */ - ldr r1, =\mgpcr - str r1, [r0, #MAX_MGPCR0] /* for M0 */ - str r1, [r0, #MAX_MGPCR1] /* for M1 */ - str r1, [r0, #MAX_MGPCR2] /* for M2 */ - str r1, [r0, #MAX_MGPCR3] /* for M3 */ - str r1, [r0, #MAX_MGPCR4] /* for M4 */ - str r1, [r0, #MAX_MGPCR5] /* for M5 */ -.endm - -/* - * M3IF setup - * - * Default argument values: - * - CTL: - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 - * ------------ - * 0x00000040 - */ -.macro init_m3if ctl=0x00000040 - /* M3IF Control Register (M3IFCTL) */ - write32 M3IF_BASE_ADDR, \ctl -.endm - -.macro core_init - mrc p15, 0, r1, c1, c0, 0 - - /* Set branch prediction enable */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr p15, 0, r0, c1, c0, 1 - orr r1, r1, #1 << 11 - - /* Set unaligned access enable */ - orr r1, r1, #1 << 22 - - /* Set low int latency enable */ - orr r1, r1, #1 << 21 - - mcr p15, 0, r1, c1, c0, 0 - - mov r0, #0 - - mcr p15, 0, r0, c15, c2, 4 - - mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ - mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ - mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ - - /* Setup the Peripheral Port Memory Remap Register */ - ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ - mcr p15, 0, r0, c15, c2, 4 -.endm diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h deleted file mode 100644 index 775b9552c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 - -#endif /* MMC_HOST_DEF_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/spl.h deleted file mode 100644 index d0efec21a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_NOR 8 -#define BOOT_DEVICE_I2C 9 -#define BOOT_DEVICE_SPI 10 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h deleted file mode 100644 index 35c03520a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_cpu_rev(void); -void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, - u32 row, u32 col, u32 dsize, u32 refresh); -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h deleted file mode 100644 index 3db4112d1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_SYS_MX5_HCLK -#define MXC_HCLK CONFIG_SYS_MX5_HCLK -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_SYS_MX5_CLK32 -#define MXC_CLK32 CONFIG_SYS_MX5_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_ESDHC4_CLK, - MXC_FEC_CLK, - MXC_SATA_CLK, - MXC_DDR_CLK, - MXC_NFC_CLK, - MXC_PERIPH_CLK, - MXC_I2C_CLK, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); -int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); -void set_usb_phy_clk(void); -void enable_usb_phy1_clk(bool enable); -void enable_usb_phy2_clk(bool enable); -void set_usboh3_clk(void); -void enable_usboh3_clk(bool enable); -void mxc_set_sata_internal_clock(void); -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -void enable_nfc_clk(unsigned char enable); -void enable_efuse_prog_supply(bool enable); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h deleted file mode 100644 index efe57e07e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -#define MXC_CCM_BASE CCM_BASE_ADDR - -/* DPLL register mapping structure */ -struct mxc_pll_reg { - u32 ctrl; - u32 config; - u32 op; - u32 mfd; - u32 mfn; - u32 mfn_minus; - u32 mfn_plus; - u32 hfs_op; - u32 hfs_mfd; - u32 hfs_mfn; - u32 mfn_togc; - u32 destat; -}; - -/* Register maping of CCM*/ -struct mxc_ccm_reg { - u32 ccr; /* 0x0000 */ - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; /* 0x0010*/ - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; /* 0x0020 */ - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; /* 0x0030 */ - u32 chscdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; /* 0x0040 */ - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; /* 0x0050 */ - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; /* 0x0060 */ - u32 cgpr; - u32 CCGR0; - u32 CCGR1; - u32 CCGR2; /* 0x0070 */ - u32 CCGR3; - u32 CCGR4; - u32 CCGR5; - u32 CCGR6; /* 0x0080 */ -#ifdef CONFIG_MX53 - u32 CCGR7; /* 0x0084 */ -#endif - u32 cmeor; -}; - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_COSC_EN (0x1 << 12) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCR_FPM_MULT (0x1 << 11) -#endif -#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) -#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCR_FPM_EN (0x1 << 8) -#endif -#define MXC_CCM_CCR_OSCNT_OFFSET 0 -#define MXC_CCM_CCR_OSCNT_MASK 0xFF -#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) -#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) - -/* Define the bits in register CCSR */ -#if defined(CONFIG_MX51) -#define MXC_CCM_CCSR_LP_APM (0x1 << 9) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCSR_LP_APM (0x1 << 10) -#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) -#endif -#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 -#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) -#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) -#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) -#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 -#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) -#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) -#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) -#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 -#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) -#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) -#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 -#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) -#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) -#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) -#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) -#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) -#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) -#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) -#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) -#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) -#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) -#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) -#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) -#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 -#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 -#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) -#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 -#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 -#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) -#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 -#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 -#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) - -/* Define the bits in register CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) - -/* Define the bits in register CCGRx */ -#define MXC_CCM_CCGR_CG_MASK 0x3 -#define MXC_CCM_CCGR_CG_OFF 0x0 -#define MXC_CCM_CCGR_CG_RUN_ON 0x1 -#define MXC_CCM_CCGR_CG_ON 0x3 - -#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 -#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 -#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 -#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR0_TZIC_OFFSET 6 -#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR0_DAP_OFFSET 8 -#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR0_TPIU_OFFSET 10 -#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR0_CTI2_OFFSET 12 -#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR0_CTI3_OFFSET 14 -#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 -#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 -#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR0_ROMCP_OFFSET 20 -#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR0_ROM_OFFSET 22 -#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 -#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 -#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 -#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR0_IIM_OFFSET 30 -#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR1_TMAX1_OFFSET 0 -#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR1_TMAX2_OFFSET 2 -#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR1_TMAX3_OFFSET 4 -#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 -#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 -#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 -#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 -#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 -#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 -#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR1_I2C1_OFFSET 18 -#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR1_I2C2_OFFSET 20 -#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 -#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 -#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR1_I2C3_OFFSET 22 -#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) -#endif -#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 -#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 -#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR1_SCC_OFFSET 30 -#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) - -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 -#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) -#endif -#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 -#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 -#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 -#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 -#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 -#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 -#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 -#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 -#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 -#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 -#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR2_OWIRE_OFFSET 22 -#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR2_FEC_OFFSET 24 -#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 -#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 -#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR2_TVE_OFFSET 30 -#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 -#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 -#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 -#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 -#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 -#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 -#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 -#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 -#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 -#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 -#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 -#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 -#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 -#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 -#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 -#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 -#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR4_PATA_OFFSET 0 -#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 -#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 -#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR4_SATA_OFFSET 2 -#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 -#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 -#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 -#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 -#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) -#endif -#define MXC_CCM_CCGR4_SAHARA_OFFSET 14 -#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR4_RTIC_OFFSET 16 -#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 -#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 -#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 -#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 -#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 -#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR4_SRTC_OFFSET 28 -#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR4_SDMA_OFFSET 30 -#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR5_SPBA_OFFSET 0 -#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR5_GPU_OFFSET 2 -#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR5_GARB_OFFSET 4 -#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR5_VPU_OFFSET 6 -#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 -#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR5_IPU_OFFSET 10 -#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 -#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 -#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) -#endif -#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 -#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) -#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 -#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 -#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 -#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 -#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 -#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 -#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 -#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) -#endif -#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 -#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) - -#if defined(CONFIG_MX53) -#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 -#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR6_OCRAM_OFFSET 2 -#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) -#endif -#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 -#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) -#if defined(CONFIG_MX51) -#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 -#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 -#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) -#elif defined(CONFIG_MX53) -#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 -#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) -#endif -#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 -#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 -#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR6_GPU2D_OFFSET 14 -#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) -#if defined(CONFIG_MX53) -#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 -#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) -#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 -#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) -#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 -#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) -#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 -#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) -#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 -#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) -#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 -#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) -#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 -#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) -#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 -#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) - -#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 -#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) -#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 -#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) -#define MXC_CCM_CCGR7_MLB_OFFSET 4 -#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) -#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 -#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) -#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 -#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) -#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 -#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) -#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 -#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) -#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 -#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) -#endif - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) - -#define MXC_DPLLC_CTL_HFSM (1 << 7) -#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) - -#define MXC_DPLLC_OP_PDF_MASK 0xf -#define MXC_DPLLC_OP_MFI_OFFSET 4 -#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) -#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) -#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) - -#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff - -#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h deleted file mode 100644 index e2a5bc97a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_MX5_GPIO_H -#define __ASM_ARCH_MX5_GPIO_H - -#include <asm/imx-common/gpio.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h deleted file mode 100644 index 054c680a5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h +++ /dev/null @@ -1,532 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX5_IMX_REGS_H__ -#define __ASM_ARCH_MX5_IMX_REGS_H__ - -#define ARCH_MXC - -#if defined(CONFIG_MX51) -#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IPU_SOC_BASE_ADDR 0x40000000 -#define IPU_SOC_OFFSET 0x1E000000 -#define SPBA0_BASE_ADDR 0x70000000 -#define AIPS1_BASE_ADDR 0x73F00000 -#define AIPS2_BASE_ADDR 0x83F00000 -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define NFC_BASE_ADDR_AXI 0xCFFF0000 -#define CS1_BASE_ADDR 0xB8000000 -#elif defined(CONFIG_MX53) -#define IPU_SOC_BASE_ADDR 0x18000000 -#define IPU_SOC_OFFSET 0x06000000 -#define SPBA0_BASE_ADDR 0x50000000 -#define AIPS1_BASE_ADDR 0x53F00000 -#define AIPS2_BASE_ADDR 0x63F00000 -#define CSD0_BASE_ADDR 0x70000000 -#define CSD1_BASE_ADDR 0xB0000000 -#define NFC_BASE_ADDR_AXI 0xF7FF0000 -#define IRAM_BASE_ADDR 0xF8000000 -#define CS1_BASE_ADDR 0xF4000000 -#define SATA_BASE_ADDR 0x10000000 -#else -#error "CPU_TYPE not defined" -#endif - -#define IRAM_SIZE 0x00020000 /* 128 KB */ - -/* - * SPBA global module enabled #0 - */ -#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) -#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) -#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) -#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) -#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) -#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) -#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) -#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) -#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) -#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) -#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) -#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) -#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) -#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) -#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) -#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) -#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) -#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) -#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) -#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) -#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) -#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) -#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) -#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) -#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) -#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) -#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) - -#if defined(CONFIG_MX53) -#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) -#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) -#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) -#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) -#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) -#endif -/* - * AIPS 2 - */ -#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) -#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) -#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) -#ifdef CONFIG_MX53 -#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) -#endif -#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) -#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) -#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) -#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) -#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) -#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) -#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) -#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) -#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) -#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) -#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) -#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) -#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) -#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) -#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) -#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) -#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) -#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) -#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) -#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) -#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) -#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) -#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) -#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) -#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) -#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) -#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) -#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) - -#if defined(CONFIG_MX53) -#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) -#endif - -/* - * WEIM CSnGCR1 - */ -#define CSEN 1 -#define SWR (1 << 1) -#define SRD (1 << 2) -#define MUM (1 << 3) -#define WFL (1 << 4) -#define RFL (1 << 5) -#define CRE (1 << 6) -#define CREP (1 << 7) -#define BL(x) (((x) & 0x7) << 8) -#define WC (1 << 11) -#define BCD(x) (((x) & 0x3) << 12) -#define BCS(x) (((x) & 0x3) << 14) -#define DSZ(x) (((x) & 0x7) << 16) -#define SP (1 << 19) -#define CSREC(x) (((x) & 0x7) << 20) -#define AUS (1 << 23) -#define GBC(x) (((x) & 0x7) << 24) -#define WP (1 << 27) -#define PSZ(x) (((x) & 0x0f << 28) - -/* - * WEIM CSnGCR2 - */ -#define ADH(x) (((x) & 0x3)) -#define DAPS(x) (((x) & 0x0f << 4) -#define DAE (1 << 8) -#define DAP (1 << 9) -#define MUX16_BYP (1 << 12) - -/* - * WEIM CSnRCR1 - */ -#define RCSN(x) (((x) & 0x7)) -#define RCSA(x) (((x) & 0x7) << 4) -#define OEN(x) (((x) & 0x7) << 8) -#define OEA(x) (((x) & 0x7) << 12) -#define RADVN(x) (((x) & 0x7) << 16) -#define RAL (1 << 19) -#define RADVA(x) (((x) & 0x7) << 20) -#define RWSC(x) (((x) & 0x3f) << 24) - -/* - * WEIM CSnRCR2 - */ -#define RBEN(x) (((x) & 0x7)) -#define RBE (1 << 3) -#define RBEA(x) (((x) & 0x7) << 4) -#define RL(x) (((x) & 0x3) << 8) -#define PAT(x) (((x) & 0x7) << 12) -#define APR (1 << 15) - -/* - * WEIM CSnWCR1 - */ -#define WCSN(x) (((x) & 0x7)) -#define WCSA(x) (((x) & 0x7) << 3) -#define WEN(x) (((x) & 0x7) << 6) -#define WEA(x) (((x) & 0x7) << 9) -#define WBEN(x) (((x) & 0x7) << 12) -#define WBEA(x) (((x) & 0x7) << 15) -#define WADVN(x) (((x) & 0x7) << 18) -#define WADVA(x) (((x) & 0x7) << 21) -#define WWSC(x) (((x) & 0x3f) << 24) -#define WBED1 (1 << 30) -#define WAL (1 << 31) - -/* - * WEIM CSnWCR2 - */ -#define WBED 1 - -#define CS0_128 0 -#define CS0_64M_CS1_64M 1 -#define CS0_64M_CS1_32M_CS2_32M 2 -#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 - -/* - * CSPI register definitions - */ -#define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_MODE_MASK (0xf << 4) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_PHA 0 /* SCLK phase control */ -#define MXC_CSPICON_POL 4 /* SCLK polarity */ -#define MXC_CSPICON_SSPOL 12 /* SS polarity */ -#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#define MXC_SPI_BASE_ADDRESSES \ - CSPI1_BASE_ADDR, \ - CSPI2_BASE_ADDR, \ - CSPI3_BASE_ADDR, - -/* - * Number of GPIO pins per port - */ -#define GPIO_NUM_PIN 32 - -#define IIM_SREV 0x24 -#define ROM_SI_REV 0x48 - -#define NFC_BUF_SIZE 0x1000 - -/* M4IF */ -#define M4IF_FBPM0 0x40 -#define M4IF_FIDBP 0x48 -#define M4IF_GENP_WEIM_MM_MASK 0x00000001 -#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 - -/* Assuming 24MHz input clock with doubler ON */ -/* MFI PDF */ -#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_864 (180 - 1) /* PL Dither mode */ -#define DP_MFN_864 180 -#define DP_MFN_800_DIT 60 /* PL Dither mode */ - -#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_850 (48 - 1) -#define DP_MFN_850 41 - -#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_800 (3 - 1) -#define DP_MFN_800 1 - -#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) -#define DP_MFD_700 (24 - 1) -#define DP_MFN_700 7 - -#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) -#define DP_MFD_665 (96 - 1) -#define DP_MFN_665 89 - -#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) -#define DP_MFD_532 (24 - 1) -#define DP_MFN_532 13 - -#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) -#define DP_MFD_400 (3 - 1) -#define DP_MFN_400 1 - -#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) -#define DP_MFD_455 (48 - 1) -#define DP_MFN_455 23 - -#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) -#define DP_MFD_216 (4 - 1) -#define DP_MFN_216 3 - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_5 0x25 -#define CHIP_REV_3_0 0x30 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 - -#define BOARD_VER_OFFSET 0x8 - -#define IMX_IIM_BASE (IIM_BASE_ADDR) - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -struct clkctl { - u32 ccr; - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; -#if defined(CONFIG_MX53) - u32 ccgr7; -#endif - u32 cmeor; -}; - -/* DPLL registers */ -struct dpll { - u32 dp_ctl; - u32 dp_config; - u32 dp_op; - u32 dp_mfd; - u32 dp_mfn; - u32 dp_mfn_minus; - u32 dp_mfn_plus; - u32 dp_hfs_op; - u32 dp_hfs_mfd; - u32 dp_hfs_mfn; - u32 dp_mfn_togc; - u32 dp_destat; -}; -/* WEIM registers */ -struct weim { - u32 cs0gcr1; - u32 cs0gcr2; - u32 cs0rcr1; - u32 cs0rcr2; - u32 cs0wcr1; - u32 cs0wcr2; - u32 cs1gcr1; - u32 cs1gcr2; - u32 cs1rcr1; - u32 cs1rcr2; - u32 cs1wcr1; - u32 cs1wcr2; - u32 cs2gcr1; - u32 cs2gcr2; - u32 cs2rcr1; - u32 cs2rcr2; - u32 cs2wcr1; - u32 cs2wcr2; - u32 cs3gcr1; - u32 cs3gcr2; - u32 cs3rcr1; - u32 cs3rcr2; - u32 cs3wcr1; - u32 cs3wcr2; - u32 cs4gcr1; - u32 cs4gcr2; - u32 cs4rcr1; - u32 cs4rcr2; - u32 cs4wcr1; - u32 cs4wcr2; - u32 cs5gcr1; - u32 cs5gcr2; - u32 cs5rcr1; - u32 cs5rcr2; - u32 cs5wcr1; - u32 cs5wcr2; - u32 wcr; - u32 wiar; - u32 ear; -}; - -#if defined(CONFIG_MX51) -struct iomuxc { - u32 gpr0; - u32 gpr1; - u32 omux0; - u32 omux1; - u32 omux2; - u32 omux3; - u32 omux4; -}; -#elif defined(CONFIG_MX53) -struct iomuxc { - u32 gpr0; - u32 gpr1; - u32 gpr2; - u32 omux0; - u32 omux1; - u32 omux2; - u32 omux3; - u32 omux4; -}; -#endif - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr; - u32 srsr; - u32 reserved1[2]; - u32 sisr; - u32 simr; -}; - -struct srtc_regs { - u32 lpscmr; /* 0x00 */ - u32 lpsclr; /* 0x04 */ - u32 lpsar; /* 0x08 */ - u32 lpsmcr; /* 0x0c */ - u32 lpcr; /* 0x10 */ - u32 lpsr; /* 0x14 */ - u32 lppdr; /* 0x18 */ - u32 lpgr; /* 0x1c */ - u32 hpcmr; /* 0x20 */ - u32 hpclr; /* 0x24 */ - u32 hpamr; /* 0x28 */ - u32 hpalr; /* 0x2c */ - u32 hpcr; /* 0x30 */ - u32 hpisr; /* 0x34 */ - u32 hpienr; /* 0x38 */ -}; - -/* CSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 cfg; - u32 intr; - u32 dma; - u32 stat; - u32 period; -}; - -struct iim_regs { - u32 stat; - u32 statm; - u32 err; - u32 emask; - u32 fctl; - u32 ua; - u32 la; - u32 sdat; - u32 prev; - u32 srev; - u32 prg_p; - u32 scs0; - u32 scs1; - u32 scs2; - u32 scs3; - u32 res0[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; -#if defined(CONFIG_MX51) - } bank[4]; -#elif defined(CONFIG_MX53) - } bank[5]; -#endif -}; - -struct fuse_bank0_regs { - u32 fuse0_7[8]; - u32 uid[8]; - u32 fuse16_23[8]; -#if defined(CONFIG_MX51) - u32 imei[8]; -#elif defined(CONFIG_MX53) - u32 gp[8]; -#endif -}; - -struct fuse_bank1_regs { - u32 fuse0_8[9]; - u32 mac_addr[6]; - u32 fuse15_31[0x11]; -}; - -#if defined(CONFIG_MX53) -struct fuse_bank4_regs { - u32 fuse0_4[5]; - u32 gp[3]; - u32 fuse8_31[0x18]; -}; -#endif - -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h deleted file mode 100644 index 70aaa37f9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * Copyright (C) 2009-2012 Genesi USA, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * The vast majority of this file is taken from the Linux kernel at - * commit 5d23b39 - */ - -#ifndef __IOMUX_MX51_H__ -#define __IOMUX_MX51_H__ - -#include <asm/imx-common/iomux-v3.h> - -/* Pad control groupings */ -#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ - PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SRE_FAST | PAD_CTL_DVS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) - -#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) - -/* - * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL), - MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS), - MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL), - MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL), - MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL), - MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2), - MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2), - MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0 = IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1 = IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDCLK__DRAM_SDCLK = IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS0__DRAM_SDQS0 = IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS1__DRAM_SDQS1 = IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS2__DRAM_SDQS2 = IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_SDQS3__DRAM_SDQS3 = IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_CS0__DRAM_CS0 = IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_CS1__DRAM_CS1 = IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM0__DRAM_DQM0 = IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2), - MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS5__FEC_TDATA2 = IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4), - MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4), - MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5), - MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SS1__ECSPI1_SS1 = IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_RDY__ECSPI1_RDY = IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL), - MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL), - MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL), - MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL), - MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL), - MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), - MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), - MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), - MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), - MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), - MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDRAPUS = IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B1 = IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDRPUS = IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B2 = IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_PKEADDR = IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_SR_B4 = IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), - MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX51_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h deleted file mode 100644 index 1b75fd1cf..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h +++ /dev/null @@ -1,1216 +0,0 @@ -/* - * (C) Copyright 2013 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on Freescale's Linux i.MX iomux-mx53.h file: - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IOMUX_MX53_H__ -#define __IOMUX_MX53_H__ - -#include <asm/imx-common/iomux-v3.h> - -/* Pad control groupings */ -#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) - -/* - * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode> - * If <padname> refers to a GPIO, it is named GPIO_<unit> - * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH PADCTRL */ -enum { - MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__UART4_TXD_MUX = IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__FEC_RDATA_3 = IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__GPIO4_7 = IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__UART4_RXD_MUX = IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW0__FEC_TX_ER = IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__GPIO4_8 = IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__UART5_TXD_MUX = IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__FEC_RX_CLK = IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL1__USBPHY1_TXREADY = IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__GPIO4_9 = IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__UART5_RXD_MUX = IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__FEC_COL = IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW1__USBPHY1_RXVALID = IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__GPIO4_10 = IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__FEC_MDIO = IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__FEC_RDATA_2 = IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE = IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__GPIO4_11 = IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__FEC_MDC = IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__FEC_TDATA_2 = IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW2__USBPHY1_RXERROR = IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__GPIO4_12 = IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__USBOH3_H2_DP = IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__FEC_CRS = IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK = IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__GPIO4_13 = IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__USBOH3_H2_DM = IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__CCM_PLL4_BYP = IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 = IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__GPIO4_14 = IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__IPU_SISG_4 = IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL), - MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 = IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__GPIO4_15 = IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__IPU_SISG_5 = IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID = IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK = IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__GPIO4_16 = IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR = IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 = IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID = IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 = IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__GPIO4_17 = IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 = IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN15__USBPHY1_BVALID = IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 = IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__GPIO4_18 = IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 = IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION = IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 = IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__GPIO4_19 = IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 = IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN3__USBPHY1_IDDIG = IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 = IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__GPIO4_20 = IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__ESDHC1_WP = IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 = IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT = IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 = IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__GPIO4_21 = IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__CSPI_SCLK = IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 = IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 = IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY = IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 = IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__GPIO4_22 = IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__CSPI_MOSI = IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 = IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL - = IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 = IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID = IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 = IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__GPIO4_23 = IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__CSPI_MISO = IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 = IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 = IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE = IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 = IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__GPIO4_24 = IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__CSPI_SS0 = IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 = IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 = IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR = IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 = IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__GPIO4_25 = IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__CSPI_SS1 = IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 = IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 = IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK = IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 = IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__GPIO4_26 = IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__CSPI_SS2 = IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 = IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 = IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 = IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 = IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__GPIO4_27 = IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__CSPI_SS3 = IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 = IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 = IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 = IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 = IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__GPIO4_28 = IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__CSPI_RDY = IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 = IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 = IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID = IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 = IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__GPIO4_29 = IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 = IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT8__USBPHY2_AVALID = IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 = IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__GPIO4_30 = IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 = IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 = IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 = IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__GPIO4_31 = IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP = IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 - = IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 = IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 = IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 = IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__GPIO5_5 = IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT = IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 - = IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 = IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 = IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 = IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__GPIO5_6 = IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK = IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 - = IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 = IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 = IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 = IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__GPIO5_7 = IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 - = IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 = IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 = IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 = IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__GPIO5_8 = IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 - = IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 = IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 = IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 = IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__GPIO5_9 = IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 - = IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 = IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 = IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 = IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__GPIO5_10 = IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 - = IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 = IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 = IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 = IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__GPIO5_11 = IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 - = IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 = IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 = IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__GPIO5_12 = IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 - = IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 = IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 = IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 = IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__GPIO5_13 = IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 - = IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 = IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 = IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 = IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__GPIO5_14 = IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 - = IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 = IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT20__SATA_PHY_TDI = IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 = IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__GPIO5_15 = IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 = IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT21__SATA_PHY_TDO = IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 = IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__GPIO5_16 = IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 = IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT22__SATA_PHY_TCK = IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 = IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__GPIO5_17 = IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 = IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_DISP0_DAT23__SATA_PHY_TMS = IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK = IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__GPIO5_18 = IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 = IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC = IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__GPIO5_19 = IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK = IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 = IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_MCLK__TPIU_TRCTL = IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN = IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__GPIO5_20 = IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 = IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK = IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC = IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__GPIO5_21 = IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 = IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 = IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 = IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__GPIO5_22 = IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP = IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 = IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 = IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 = IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__GPIO5_23 = IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT = IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 = IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 = IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 = IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__GPIO5_24 = IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK = IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 = IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 = IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 = IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__GPIO5_25 = IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR = IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 = IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 = IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 = IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__GPIO5_26 = IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC = IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 = IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 = IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 = IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__GPIO5_27 = IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR = IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 = IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 = IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 = IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__GPIO5_28 = IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX = IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 = IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 = IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 = IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__GPIO5_29 = IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX = IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 = IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 = IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 = IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__GPIO5_30 = IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__UART4_TXD_MUX = IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 = IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 = IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 = IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 = IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__GPIO5_31 = IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__UART4_RXD_MUX = IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 = IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 = IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 = IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 = IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__GPIO6_0 = IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__UART5_TXD_MUX = IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 = IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 = IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 = IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 = IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__GPIO6_1 = IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__UART5_RXD_MUX = IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 = IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 = IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 = IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 = IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__GPIO6_2 = IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 = IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 = IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 = IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 = IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__GPIO6_3 = IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 = IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 = IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 = IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 = IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__GPIO6_4 = IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 = IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 = IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 = IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 = IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__GPIO6_5 = IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 = IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 = IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK = IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__EMI_WEIM_A_25 = IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__GPIO5_2 = IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__IPU_DI1_PIN12 = IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__CSPI_SS1 = IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL), - MX53_PAD_EIM_A25__IPU_DI0_D1_CS = IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A25__USBPHY1_BISTOK = IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 = IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__GPIO2_30 = IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS = IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL), - MX53_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D16__EMI_WEIM_D_16 = IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__GPIO3_16 = IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__IPU_DI0_PIN5 = IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK = IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL), - MX53_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D17__EMI_WEIM_D_17 = IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__GPIO3_17 = IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__IPU_DI0_PIN6 = IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN = IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL), - MX53_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__EMI_WEIM_D_18 = IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__GPIO3_18 = IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__IPU_DI0_PIN7 = IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO = IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL), - MX53_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D18__IPU_DI1_D0_CS = IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__EMI_WEIM_D_19 = IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__GPIO3_19 = IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__IPU_DI0_PIN8 = IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS = IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL), - MX53_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D19__USBOH3_USBH2_OC = IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__EMI_WEIM_D_20 = IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__GPIO3_20 = IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__IPU_DI0_PIN16 = IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__IPU_SER_DISP0_CS = IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__CSPI_SS0 = IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D20__USBOH3_USBH2_PWR = IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__EMI_WEIM_D_21 = IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__GPIO3_21 = IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__IPU_DI0_PIN17 = IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK = IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D21__CSPI_SCLK = IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D22__EMI_WEIM_D_22 = IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__GPIO3_22 = IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__IPU_DI0_PIN1 = IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN = IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D22__CSPI_MISO = IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__EMI_WEIM_D_23 = IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__GPIO3_23 = IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_DI0_D0_CS = IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_DI1_PIN2 = IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN = IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D23__IPU_DI1_PIN14 = IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 = IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__GPIO2_31 = IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__IPU_DI1_PIN3 = IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC = IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB3__IPU_DI1_PIN16 = IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__EMI_WEIM_D_24 = IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__GPIO3_24 = IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__UART3_TXD_MUX = IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D24__CSPI_SS2 = IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__EMI_WEIM_D_25 = IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__GPIO3_25 = IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__UART3_RXD_MUX = IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D25__CSPI_SS3 = IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__EMI_WEIM_D_26 = IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__GPIO3_26 = IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__UART2_TXD_MUX = IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D26__FIRI_RXD = IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_CSI0_D_1 = IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_DI1_PIN11 = IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_SISG_2 = IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 = IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__EMI_WEIM_D_27 = IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__GPIO3_27 = IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__UART2_RXD_MUX = IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D27__FIRI_TXD = IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_CSI0_D_0 = IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_DI1_PIN13 = IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_SISG_3 = IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 = IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__EMI_WEIM_D_28 = IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__GPIO3_28 = IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO = IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D28__CSPI_MOSI = IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D28__IPU_EXT_TRIG = IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D28__IPU_DI0_PIN13 = IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__EMI_WEIM_D_29 = IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__GPIO3_29 = IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS = IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__CSPI_SS0 = IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_DI1_PIN15 = IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_CSI1_VSYNC = IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D29__IPU_DI0_PIN14 = IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__EMI_WEIM_D_30 = IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__GPIO3_30 = IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D30__IPU_CSI0_D_3 = IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__IPU_DI0_PIN11 = IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 = IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D30__USBOH3_USBH2_OC = IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL), - MX53_PAD_EIM_D31__EMI_WEIM_D_31 = IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__GPIO3_31 = IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL), - MX53_PAD_EIM_D31__IPU_CSI0_D_2 = IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__IPU_DI0_PIN12 = IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 = IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_D31__USBOH3_USBH2_PWR = IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__EMI_WEIM_A_24 = IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__GPIO5_4 = IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 = IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__IPU_CSI1_D_19 = IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__IPU_SISG_2 = IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A24__USBPHY2_BVALID = IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__EMI_WEIM_A_23 = IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__GPIO6_6 = IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 = IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__IPU_CSI1_D_18 = IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__IPU_SISG_3 = IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A23__USBPHY2_ENDSESSION = IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__EMI_WEIM_A_22 = IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 = IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__IPU_CSI1_D_17 = IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A22__SRC_BT_CFG1_7 = IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__EMI_WEIM_A_21 = IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__GPIO2_17 = IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 = IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__IPU_CSI1_D_16 = IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A21__SRC_BT_CFG1_6 = IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__EMI_WEIM_A_20 = IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__GPIO2_18 = IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 = IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__IPU_CSI1_D_15 = IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A20__SRC_BT_CFG1_5 = IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__EMI_WEIM_A_19 = IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__GPIO2_19 = IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 = IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__IPU_CSI1_D_14 = IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A19__SRC_BT_CFG1_4 = IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__EMI_WEIM_A_18 = IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__GPIO2_20 = IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 = IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__IPU_CSI1_D_13 = IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A18__SRC_BT_CFG1_3 = IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__EMI_WEIM_A_17 = IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__GPIO2_21 = IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 = IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__IPU_CSI1_D_12 = IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A17__SRC_BT_CFG1_2 = IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__EMI_WEIM_A_16 = IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__GPIO2_22 = IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK = IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK = IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_A16__SRC_BT_CFG1_1 = IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 = IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__GPIO2_23 = IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL), - MX53_PAD_EIM_CS0__IPU_DI1_PIN5 = IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 = IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__GPIO2_24 = IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL), - MX53_PAD_EIM_CS1__IPU_DI1_PIN6 = IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__EMI_WEIM_OE = IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__GPIO2_25 = IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL), - MX53_PAD_EIM_OE__IPU_DI1_PIN7 = IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_OE__USBPHY2_IDDIG = IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__EMI_WEIM_RW = IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__GPIO2_26 = IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL), - MX53_PAD_EIM_RW__IPU_DI1_PIN8 = IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT = IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__EMI_WEIM_LBA = IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__GPIO2_27 = IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__IPU_DI1_PIN17 = IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 = IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 = IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__GPIO2_28 = IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 = IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__IPU_CSI1_D_11 = IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__GPC_PMIC_RDY = IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 = IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 = IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__GPIO2_29 = IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 = IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__IPU_CSI1_D_10 = IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 = IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 = IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__GPIO3_0 = IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 = IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__IPU_CSI1_D_9 = IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 = IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 = IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__GPIO3_1 = IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 = IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__IPU_CSI1_D_8 = IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 = IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 = IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__GPIO3_2 = IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 = IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__IPU_CSI1_D_7 = IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 = IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 = IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__GPIO3_3 = IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 = IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__IPU_CSI1_D_6 = IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 = IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 = IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__GPIO3_4 = IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 = IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__IPU_CSI1_D_5 = IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 = IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 = IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__GPIO3_5 = IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 = IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__IPU_CSI1_D_4 = IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 = IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 = IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__GPIO3_6 = IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 = IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__IPU_CSI1_D_3 = IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 = IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 = IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__GPIO3_7 = IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 = IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__IPU_CSI1_D_2 = IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 = IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 = IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__GPIO3_8 = IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 = IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__IPU_CSI1_D_1 = IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 = IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 = IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__GPIO3_9 = IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 = IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__IPU_CSI1_D_0 = IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 = IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 = IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__GPIO3_10 = IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__IPU_DI1_PIN15 = IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN = IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 = IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 = IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11 = IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__IPU_DI1_PIN2 = IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC = IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 = IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__GPIO3_12 = IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__IPU_DI1_PIN3 = IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC = IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 = IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13 = IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__IPU_DI1_D0_CS = IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 = IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__GPIO3_14 = IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__IPU_DI1_D1_CS = IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 = IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__GPIO3_15 = IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__IPU_DI1_PIN1 = IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_DA15__IPU_DI1_PIN4 = IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WE_B__GPIO6_12 = IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RE_B__GPIO6_13 = IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT = IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_WAIT__GPIO5_0 = IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B = IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX3_P__GPIO6_22 = IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX2_P__GPIO6_24 = IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_CLK_P__GPIO6_26 = IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX1_P__GPIO6_28 = IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX0_P__GPIO6_30 = IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX3_P__GPIO7_22 = IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_CLK_P__GPIO7_24 = IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX2_P__GPIO7_26 = IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX1_P__GPIO7_28 = IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX0_P__GPIO7_30 = IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_10__GPIO4_0 = IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_10__OSC32k_32K_OUT = IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_11__GPIO4_1 = IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_12__GPIO4_2 = IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_13__GPIO4_3 = IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_14__GPIO4_4 = IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE = IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CLE__GPIO6_7 = IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 = IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE = IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_ALE__GPIO6_8 = IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 = IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WP_B__GPIO6_9 = IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 = IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 = IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RB0__GPIO6_10 = IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 = IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 = IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS0__GPIO6_11 = IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 = IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 = IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__GPIO6_14 = IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__MLB_MLBCLK = IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 = IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 = IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__GPIO6_15 = IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__IPU_SISG_0 = IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__EMI_WEIM_CRE = IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK = IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__MLB_MLBSIG = IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 = IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 = IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__GPIO6_16 = IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__IPU_SISG_1 = IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 = IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__MLB_MLBDAT = IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL), - MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 = IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__GPIO1_22 = IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__ESAI1_SCKR = IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__FEC_COL = IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 = IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 = IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK = IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__GPIO1_23 = IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 = IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__FEC_RX_ER = IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__GPIO1_24 = IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__FEC_RX_CLK = IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL), - MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 = IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_CRS_DV__GPIO1_25 = IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__FEC_RDATA_1 = IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__GPIO1_26 = IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__ESAI1_FST = IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__MLB_MLBSIG = IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL), - MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 = IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__FEC_RDATA_0 = IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__GPIO1_27 = IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__ESAI1_HCKT = IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL), - MX53_PAD_FEC_RXD0__OSC32k_32K_OUT = IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TX_EN__GPIO1_28 = IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__FEC_TDATA_1 = IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__GPIO1_29 = IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__MLB_MLBCLK = IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL), - MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK = IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__FEC_TDATA_0 = IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__GPIO1_30 = IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL), - MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 = IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__GPIO1_31 = IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__MLB_MLBDAT = IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG = IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 = IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOW__PATA_DIOW = IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOW__GPIO6_17 = IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOW__UART1_TXD_MUX = IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 = IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMACK__PATA_DMACK = IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMACK__GPIO6_18 = IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMACK__UART1_RXD_MUX = IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 = IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__PATA_DMARQ = IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__GPIO7_0 = IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX = IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 = IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 = IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN = IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__GPIO7_1 = IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX = IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 = IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 = IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__PATA_INTRQ = IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__GPIO7_2 = IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__UART2_CTS = IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_INTRQ__CAN1_TXCAN = IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 = IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 = IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__PATA_DIOR = IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__GPIO7_3 = IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__UART2_RTS = IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DIOR__CAN1_RXCAN = IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL), - MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 = IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B = IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__GPIO7_4 = IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__ESDHC3_CMD = IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_RESET_B__UART1_CTS = IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_RESET_B__CAN2_TXCAN = IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 = IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__PATA_IORDY = IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__GPIO7_5 = IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__ESDHC3_CLK = IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_IORDY__UART1_RTS = IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_IORDY__CAN2_RXCAN = IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL), - MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 = IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__PATA_DA_0 = IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__GPIO7_6 = IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__ESDHC3_RST = IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__OWIRE_LINE = IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 = IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_1__PATA_DA_1 = IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_1__GPIO7_7 = IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_1__ESDHC4_CMD = IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DA_1__UART3_CTS = IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 = IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_2__PATA_DA_2 = IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_2__GPIO7_8 = IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DA_2__ESDHC4_CLK = IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DA_2__UART3_RTS = IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 = IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_0__PATA_CS_0 = IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_0__GPIO7_9 = IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_0__UART3_TXD_MUX = IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 = IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_1__PATA_CS_1 = IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_1__GPIO7_10 = IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_CS_1__UART3_RXD_MUX = IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL), - MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 = IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__PATA_DATA_0 = IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__GPIO2_0 = IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 = IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__ESDHC3_DAT4 = IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 = IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 = IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__PATA_DATA_1 = IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__GPIO2_1 = IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 = IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__ESDHC3_DAT5 = IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 = IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__PATA_DATA_2 = IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__GPIO2_2 = IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 = IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__ESDHC3_DAT6 = IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 = IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__PATA_DATA_3 = IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__GPIO2_3 = IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 = IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__ESDHC3_DAT7 = IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 = IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__PATA_DATA_4 = IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__GPIO2_4 = IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 = IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__ESDHC4_DAT4 = IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 = IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__PATA_DATA_5 = IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__GPIO2_5 = IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 = IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__ESDHC4_DAT5 = IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 = IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__PATA_DATA_6 = IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__GPIO2_6 = IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 = IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__ESDHC4_DAT6 = IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 = IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__PATA_DATA_7 = IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__GPIO2_7 = IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 = IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__ESDHC4_DAT7 = IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 = IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__PATA_DATA_8 = IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__GPIO2_8 = IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__ESDHC1_DAT4 = IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 = IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__ESDHC3_DAT0 = IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 = IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 = IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__PATA_DATA_9 = IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__GPIO2_9 = IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__ESDHC1_DAT5 = IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 = IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__ESDHC3_DAT1 = IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 = IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 = IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__PATA_DATA_10 = IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__GPIO2_10 = IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__ESDHC1_DAT6 = IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 = IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__ESDHC3_DAT2 = IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 = IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 = IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__PATA_DATA_11 = IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__GPIO2_11 = IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__ESDHC1_DAT7 = IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 = IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__ESDHC3_DAT3 = IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 = IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 = IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__PATA_DATA_12 = IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__GPIO2_12 = IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__ESDHC2_DAT4 = IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 = IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__ESDHC4_DAT0 = IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 = IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 = IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__PATA_DATA_13 = IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__GPIO2_13 = IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__ESDHC2_DAT5 = IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 = IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__ESDHC4_DAT1 = IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 = IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 = IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__PATA_DATA_14 = IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__GPIO2_14 = IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__ESDHC2_DAT6 = IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 = IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__ESDHC4_DAT2 = IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 = IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 = IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__PATA_DATA_15 = IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__GPIO2_15 = IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__ESDHC2_DAT7 = IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 = IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__ESDHC4_DAT3 = IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 = IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 = IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA0__GPIO1_16 = IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__GPT_CAPIN1 = IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__CSPI_MISO = IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL), - MX53_PAD_SD1_DATA0__CCM_PLL3_BYP = IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA1__GPIO1_17 = IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__GPT_CAPIN2 = IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__CSPI_SS0 = IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL), - MX53_PAD_SD1_DATA1__CCM_PLL4_BYP = IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_CMD__GPIO1_18 = IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__CSPI_MOSI = IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL), - MX53_PAD_SD1_CMD__CCM_PLL1_BYP = IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA2__GPIO1_19 = IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__GPT_CMPOUT2 = IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__PWM2_PWMO = IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__WDOG1_WDOG_B = IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__CSPI_SS1 = IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA2__CCM_PLL2_BYP = IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_CLK__GPIO1_20 = IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__OSC32k_32K_OUT = IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__CSPI_SCLK = IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL), - MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD1_DATA3__GPIO1_21 = IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__GPT_CMPOUT3 = IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__PWM1_PWMO = IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__WDOG2_WDOG_B = IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__CSPI_SS2 = IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 = IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_CLK__GPIO1_10 = IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__CSPI_SCLK = IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL), - MX53_PAD_SD2_CLK__SCC_RANDOM_V = IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_CMD__GPIO1_11 = IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__CSPI_MOSI = IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL), - MX53_PAD_SD2_CMD__SCC_RANDOM = IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA3__GPIO1_12 = IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__CSPI_SS2 = IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL), - MX53_PAD_SD2_DATA3__SJC_DONE = IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA2__GPIO1_13 = IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__CSPI_SS1 = IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL), - MX53_PAD_SD2_DATA2__SJC_FAIL = IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA1__GPIO1_14 = IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__CSPI_SS0 = IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL), - MX53_PAD_SD2_DATA1__RTIC_SEC_VIO = IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL), - MX53_PAD_SD2_DATA0__GPIO1_15 = IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__CSPI_MISO = IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL), - MX53_PAD_SD2_DATA0__RTIC_DONE_INT = IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__GPIO1_0 = IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL), - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK = IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__SRTC_ALARM_DEB = IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_0__CSU_TD = IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_1__GPIO1_1 = IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK = IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__ESDHC1_CD = IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_9__GPIO1_9 = IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_9__ESDHC1_WP = IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_9__SCC_FAIL_STATE = IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_3__GPIO1_3 = IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_3__DPLLIP1_TOG_EN = IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_6__GPIO1_6 = IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__ESDHC2_LCTL = IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_2__GPIO1_2 = IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__ESDHC2_WP = IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_4__GPIO1_4 = IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__ESDHC2_CD = IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_4__SCC_SEC_STATE = IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_5__GPIO1_5 = IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_5__CCM_PLL1_BYP = IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_7__GPIO1_7 = IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__UART2_TXD_MUX = IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL), - MX53_PAD_GPIO_7__FIRI_RXD = IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_7__CCM_PLL2_BYP = IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_8__GPIO1_8 = IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL), - MX53_PAD_GPIO_8__UART2_RXD_MUX = IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL), - MX53_PAD_GPIO_8__FIRI_TXD = IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_8__CCM_PLL3_BYP = IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_16__GPIO7_11 = IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT = IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 = IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL), - MX53_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_17__GPIO7_12 = IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_17__GPC_PMIC_RDY = IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG = IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__IPU_SNOOP2 = IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__GPIO7_13 = IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__OWIRE_LINE = IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG = IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL), - MX53_PAD_GPIO_18__ESDHC1_LCTL = IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL), - MX53_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL), -}; - -#endif /* __IOMUX_MX53_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/spl.h deleted file mode 100644 index 20c6cae93..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_SPL_H__ -#define __ASM_ARCH_SPL_H__ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_NAND 1 - -#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h deleted file mode 100644 index ac7705b3b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include "../arch-imx/cpu.h" - -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) -u32 get_cpu_rev(void); -unsigned imx_ddr_size(void); -void sdelay(unsigned long); -void set_chipselect_size(int const); - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ - -int fecmxc_initialize(bd_t *bis); -u32 get_ahb_clk(void); -u32 get_periph_clk(void); -char *get_reset_cause(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h deleted file mode 100644 index 1b4ded7fe..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -#ifdef CONFIG_SYS_MX6_HCLK -#define MXC_HCLK CONFIG_SYS_MX6_HCLK -#else -#define MXC_HCLK 24000000 -#endif - -#ifdef CONFIG_SYS_MX6_CLK32 -#define MXC_CLK32 CONFIG_SYS_MX6_CLK32 -#else -#define MXC_CLK32 32768 -#endif - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_PER_CLK, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_AXI_CLK, - MXC_EMI_SLOW_CLK, - MXC_DDR_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, - MXC_ESDHC3_CLK, - MXC_ESDHC4_CLK, - MXC_SATA_CLK, - MXC_NFC_CLK, - MXC_I2C_CLK, -}; - -enum enet_freq { - ENET_25MHz, - ENET_50MHz, - ENET_100MHz, - ENET_125MHz, -}; - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); -void enable_ocotp_clk(unsigned char enable); -void enable_usboh3_clk(unsigned char enable); -int enable_sata_clock(void); -int enable_pcie_clock(void); -int enable_i2c_clk(unsigned char enable, unsigned i2c_num); -void enable_ipu_clock(void); -int enable_fec_anatop_clock(enum enet_freq freq); -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h deleted file mode 100644 index 720207303..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h +++ /dev/null @@ -1,893 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ -#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ - -#define CCM_CCOSR 0x020c4060 -#define CCM_CCGR0 0x020C4068 -#define CCM_CCGR1 0x020C406c -#define CCM_CCGR2 0x020C4070 -#define CCM_CCGR3 0x020C4074 -#define CCM_CCGR4 0x020C4078 -#define CCM_CCGR5 0x020C407c -#define CCM_CCGR6 0x020C4080 - -#define PMU_MISC2 0x020C8170 - -#ifndef __ASSEMBLY__ -struct mxc_ccm_reg { - u32 ccr; /* 0x0000 */ - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; /* 0x0010*/ - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; /* 0x0020 */ - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; /* 0x0030 */ - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; /* 0x0040 */ - u32 resv0; - u32 cdhipr; - u32 cdcr; - u32 ctor; /* 0x0050 */ - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; /* 0x0060 */ - u32 cgpr; - u32 CCGR0; - u32 CCGR1; - u32 CCGR2; /* 0x0070 */ - u32 CCGR3; - u32 CCGR4; - u32 CCGR5; - u32 CCGR6; /* 0x0080 */ - u32 CCGR7; - u32 cmeor; - u32 resv[0xfdd]; - u32 analog_pll_sys; /* 0x4000 */ - u32 analog_pll_sys_set; - u32 analog_pll_sys_clr; - u32 analog_pll_sys_tog; - u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ - u32 analog_usb1_pll_480_ctrl_set; - u32 analog_usb1_pll_480_ctrl_clr; - u32 analog_usb1_pll_480_ctrl_tog; - u32 analog_reserved0[4]; - u32 analog_pll_528; /* 0x4030 */ - u32 analog_pll_528_set; - u32 analog_pll_528_clr; - u32 analog_pll_528_tog; - u32 analog_pll_528_ss; /* 0x4040 */ - u32 analog_reserved1[3]; - u32 analog_pll_528_num; /* 0x4050 */ - u32 analog_reserved2[3]; - u32 analog_pll_528_denom; /* 0x4060 */ - u32 analog_reserved3[3]; - u32 analog_pll_audio; /* 0x4070 */ - u32 analog_pll_audio_set; - u32 analog_pll_audio_clr; - u32 analog_pll_audio_tog; - u32 analog_pll_audio_num; /* 0x4080*/ - u32 analog_reserved4[3]; - u32 analog_pll_audio_denom; /* 0x4090 */ - u32 analog_reserved5[3]; - u32 analog_pll_video; /* 0x40a0 */ - u32 analog_pll_video_set; - u32 analog_pll_video_clr; - u32 analog_pll_video_tog; - u32 analog_pll_video_num; /* 0x40b0 */ - u32 analog_reserved6[3]; - u32 analog_pll_vedio_denon; /* 0x40c0 */ - u32 analog_reserved7[7]; - u32 analog_pll_enet; /* 0x40e0 */ - u32 analog_pll_enet_set; - u32 analog_pll_enet_clr; - u32 analog_pll_enet_tog; - u32 analog_pfd_480; /* 0x40f0 */ - u32 analog_pfd_480_set; - u32 analog_pfd_480_clr; - u32 analog_pfd_480_tog; - u32 analog_pfd_528; /* 0x4100 */ - u32 analog_pfd_528_set; - u32 analog_pfd_528_clr; - u32 analog_pfd_528_tog; -}; -#endif - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_RBC_EN (1 << 27) -#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) -#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 -#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 -#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) -#define MXC_CCM_CCR_COSC_EN (1 << 12) -#define MXC_CCM_CCR_OSCNT_MASK 0xFF -#define MXC_CCM_CCR_OSCNT_OFFSET 0 - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) -#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) - -/* Define the bits in register CSR */ -#define MXC_CCM_CSR_COSC_READY (1 << 5) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) - -/* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) -#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) -#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) -#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) -#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) -#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) -#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) -#define MXC_CCM_CCSR_STEP_SEL (1 << 8) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) -#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 -#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) -#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 -#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) -#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 -#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) -#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) -#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) -#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 -#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F - -/* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 -#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) -#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 -#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 -#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 -#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#else -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F -#endif -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 - -/* Define the bits in register CS1CDR */ -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 - -/* Define the bits in register CS2CDR */ -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 - -/* Define the bits in register CDCDR */ -#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) -#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 - -/* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 - -#define CHSCCDR_CLK_SEL_LDB_DI0 3 -#define CHSCCDR_PODF_DIVIDE_BY_3 2 -#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 - -/* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 - -/* Define the bits in register CDHIPR */ -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) -#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) -#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) -#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) -#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) -#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) -#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) -#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) -#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) -#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) -#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) -#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 -#define MXC_CCM_CLPCR_VSTBY (1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) -#define MXC_CCM_CLPCR_SBYOS (1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 -#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) -#define MXC_CCM_CLPCR_LPM_MASK 0x3 -#define MXC_CCM_CLPCR_LPM_OFFSET 0 - -/* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) -#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) -#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) -#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CISR_COSC_READY (1 << 6) -#define MXC_CCM_CISR_LRF_PLL 1 - -/* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) -#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) -#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) -#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) -#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) -#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) -#define MXC_CCM_CIMR_MASK_LRF_PLL 1 - -/* Define the bits in register CCOSR */ -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) -#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 -#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) -#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) -#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 -#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF -#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 - -/* Define the bits in registers CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) -#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) -#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 - -/* Define the bits in registers CCGRx */ -#define MXC_CCM_CCGR_CG_MASK 3 - -#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 -#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) -#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 -#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) -#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 -#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) -#define MXC_CCM_CCGR0_ASRC_OFFSET 6 -#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) -#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 -#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) -#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 -#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) -#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 -#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) -#define MXC_CCM_CCGR0_CAN1_OFFSET 14 -#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) -#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 -#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) -#define MXC_CCM_CCGR0_CAN2_OFFSET 18 -#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) -#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 -#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) -#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 -#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) -#define MXC_CCM_CCGR0_DCIC1_OFFSET 24 -#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) -#define MXC_CCM_CCGR0_DCIC2_OFFSET 26 -#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) -#define MXC_CCM_CCGR0_DTCP_OFFSET 28 -#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) - -#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 -#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 -#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 -#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 -#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) -#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 -#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) -#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 -#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) -#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 -#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) -#define MXC_CCM_CCGR1_ESAIS_OFFSET 16 -#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) -#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 -#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) -#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 -#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) -#define MXC_CCM_CCGR1_GPU2D_OFFSET 24 -#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) -#define MXC_CCM_CCGR1_GPU3D_OFFSET 26 -#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) - -#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 -#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) -#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 -#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) -#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 -#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) -#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 -#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) -#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 -#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) -#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 -#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) -#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 -#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) -#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 -#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) -#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 -#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) -#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 -#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) -#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 -#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) - -#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 -#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) -#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 -#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) -#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 -#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) -#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 -#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) -#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 -#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) -#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 -#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) -#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 -#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) -#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 -#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) -#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 -#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) -#define MXC_CCM_CCGR3_MLB_OFFSET 18 -#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) -#define MXC_CCM_CCGR3_OCRAM_OFFSET 28 -#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) -#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 -#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) - -#define MXC_CCM_CCGR4_PCIE_OFFSET 0 -#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) -#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 -#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) -#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 -#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) -#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 -#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) -#define MXC_CCM_CCGR4_PWM1_OFFSET 16 -#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) -#define MXC_CCM_CCGR4_PWM2_OFFSET 18 -#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) -#define MXC_CCM_CCGR4_PWM3_OFFSET 20 -#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) -#define MXC_CCM_CCGR4_PWM4_OFFSET 22 -#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 -#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) - -#define MXC_CCM_CCGR5_ROM_OFFSET 0 -#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) -#define MXC_CCM_CCGR5_SATA_OFFSET 4 -#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) -#define MXC_CCM_CCGR5_SDMA_OFFSET 6 -#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) -#define MXC_CCM_CCGR5_SPBA_OFFSET 12 -#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) -#define MXC_CCM_CCGR5_SPDIF_OFFSET 14 -#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) -#define MXC_CCM_CCGR5_SSI1_OFFSET 18 -#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) -#define MXC_CCM_CCGR5_SSI2_OFFSET 20 -#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) -#define MXC_CCM_CCGR5_SSI3_OFFSET 22 -#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) -#define MXC_CCM_CCGR5_UART_OFFSET 24 -#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) -#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 -#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) - -#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 -#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) -#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 -#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) -#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 -#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) -#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 -#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) -#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 -#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) -#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 -#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) -#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 -#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) - -#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 -#define BP_ANADIG_PLL_SYS_RSVD0 20 -#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 -#define BF_ANADIG_PLL_SYS_RSVD0(v) \ - (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) -#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 -#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 -#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 -#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 -#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) - -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 -#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 -#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ - (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ - (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) - -#define BM_ANADIG_PLL_528_LOCK 0x80000000 -#define BP_ANADIG_PLL_528_RSVD1 19 -#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 -#define BF_ANADIG_PLL_528_RSVD1(v) \ - (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) -#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_528_BYPASS 0x00010000 -#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_528_ENABLE 0x00002000 -#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_528_RSVD0 1 -#define BM_ANADIG_PLL_528_RSVD0 0x0000007E -#define BF_ANADIG_PLL_528_RSVD0(v) \ - (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) -#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 - -#define BP_ANADIG_PLL_528_SS_STOP 16 -#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 -#define BF_ANADIG_PLL_528_SS_STOP(v) \ - (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) -#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 -#define BP_ANADIG_PLL_528_SS_STEP 0 -#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF -#define BF_ANADIG_PLL_528_SS_STEP(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) - -#define BP_ANADIG_PLL_528_NUM_RSVD0 30 -#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) -#define BP_ANADIG_PLL_528_NUM_A 0 -#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_528_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) - -#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) -#define BP_ANADIG_PLL_528_DENOM_B 0 -#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_528_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) - -#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 -#define BP_ANADIG_PLL_AUDIO_RSVD0 22 -#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 -#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ - (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) -#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 -#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) - -#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 -#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) -#define BP_ANADIG_PLL_AUDIO_NUM_A 0 -#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) - -#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) -#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 -#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) - -#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 -#define BP_ANADIG_PLL_VIDEO_RSVD0 22 -#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 -#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ - (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) -#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 -#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) - -#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 -#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) -#define BP_ANADIG_PLL_VIDEO_NUM_A 0 -#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) - -#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) -#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 -#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) - -#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 -#define BP_ANADIG_PLL_ENET_RSVD1 21 -#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 -#define BF_ANADIG_PLL_ENET_RSVD1(v) \ - (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) -#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 -#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 -#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 -#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 -#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_ENET_RSVD0 2 -#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C -#define BF_ANADIG_PLL_ENET_RSVD0(v) \ - (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) -#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 -#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) - -#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_480_PFD3_FRAC 24 -#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ - (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) -#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_480_PFD2_FRAC 16 -#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ - (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) -#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_480_PFD1_FRAC 8 -#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ - (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) -#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_480_PFD0_FRAC 0 -#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ - (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) - -#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_528_PFD3_FRAC 24 -#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ - (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) -#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_528_PFD2_FRAC 16 -#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ - (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) -#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_528_PFD1_FRAC 8 -#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ - (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) -#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_528_PFD0_FRAC 0 -#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ - (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) - -#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h deleted file mode 100644 index e6640f39a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_MX6_GPIO_H -#define __ASM_ARCH_MX6_GPIO_H - -#include <asm/imx-common/gpio.h> - -#endif /* __ASM_ARCH_MX6_GPIO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/hab.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/hab.h deleted file mode 100644 index d724f206f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/hab.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - * -*/ - -#ifndef __SECURE_MX6Q_H__ -#define __SECURE_MX6Q_H__ - -#include <linux/types.h> - -/* -------- start of HAB API updates ------------*/ -/* The following are taken from HAB4 SIS */ - -/* Status definitions */ -enum hab_status { - HAB_STS_ANY = 0x00, - HAB_FAILURE = 0x33, - HAB_WARNING = 0x69, - HAB_SUCCESS = 0xf0 -}; - -/* Security Configuration definitions */ -enum hab_config { - HAB_CFG_RETURN = 0x33, /**< Field Return IC */ - HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ - HAB_CFG_CLOSED = 0xcc /**< Secure IC */ -}; - -/* State definitions */ -enum hab_state { - HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ - HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ - HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ - HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ - HAB_STATE_SECURE = 0xaa, /**< Secure state */ - HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ - HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ - HAB_STATE_NONE = 0xf0, /**< No security state machine */ - HAB_STATE_MAX -}; - -/*Function prototype description*/ -typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, - uint8_t* , size_t*); -typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, - enum hab_state *); -typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); -typedef enum hab_status hab_rvt_entry_t(void); -typedef enum hab_status hab_rvt_exit_t(void); -typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, - void **, size_t *, hab_loader_callback_f_t); -typedef void hapi_clock_init_t(void); - -#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) -#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) -#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) -#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) -#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) -#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) - -#define HAB_CID_ROM 0 /**< ROM Caller ID */ -#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ -/* ----------- end of HAB API updates ------------*/ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h deleted file mode 100644 index 1f19727b5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h +++ /dev/null @@ -1,669 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX6_IMX_REGS_H__ -#define __ASM_ARCH_MX6_IMX_REGS_H__ - -#define ARCH_MXC - -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define ROMCP_ARB_BASE_ADDR 0x00000000 -#define ROMCP_ARB_END_ADDR 0x000FFFFF - -#ifdef CONFIG_MX6SL -#define GPU_2D_ARB_BASE_ADDR 0x02200000 -#define GPU_2D_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#else -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00103FFF -#define APBH_DMA_ARB_BASE_ADDR 0x00110000 -#define APBH_DMA_ARB_END_ADDR 0x00117FFF -#define HDMI_ARB_BASE_ADDR 0x00120000 -#define HDMI_ARB_END_ADDR 0x00128FFF -#define GPU_3D_ARB_BASE_ADDR 0x00130000 -#define GPU_3D_ARB_END_ADDR 0x00133FFF -#define GPU_2D_ARB_BASE_ADDR 0x00134000 -#define GPU_2D_ARB_END_ADDR 0x00137FFF -#define DTCP_ARB_BASE_ADDR 0x00138000 -#define DTCP_ARB_END_ADDR 0x0013BFFF -#endif /* CONFIG_MX6SL */ - -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - -/* GPV - PL301 configuration ports */ -#ifdef CONFIG_MX6SL -#define GPV2_BASE_ADDR 0x00D00000 -#else -#define GPV2_BASE_ADDR 0x00200000 -#endif - -#define GPV3_BASE_ADDR 0x00300000 -#define GPV4_BASE_ADDR 0x00800000 -#define IRAM_BASE_ADDR 0x00900000 -#define SCU_BASE_ADDR 0x00A00000 -#define IC_INTERFACES_BASE_ADDR 0x00A00100 -#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 -#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 -#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 -#define L2_PL310_BASE 0x00A02000 -#define GPV0_BASE_ADDR 0x00B00000 -#define GPV1_BASE_ADDR 0x00C00000 -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF - -#define AIPS1_ARB_BASE_ADDR 0x02000000 -#define AIPS1_ARB_END_ADDR 0x020FFFFF -#define AIPS2_ARB_BASE_ADDR 0x02100000 -#define AIPS2_ARB_END_ADDR 0x021FFFFF -#define SATA_ARB_BASE_ADDR 0x02200000 -#define SATA_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#define HSI_ARB_BASE_ADDR 0x02208000 -#define HSI_ARB_END_ADDR 0x0220BFFF -#define IPU1_ARB_BASE_ADDR 0x02400000 -#define IPU1_ARB_END_ADDR 0x027FFFFF -#define IPU2_ARB_BASE_ADDR 0x02800000 -#define IPU2_ARB_END_ADDR 0x02BFFFFF -#define WEIM_ARB_BASE_ADDR 0x08000000 -#define WEIM_ARB_END_ADDR 0x0FFFFFFF - -#ifdef CONFIG_MX6SL -#define MMDC0_ARB_BASE_ADDR 0x80000000 -#define MMDC0_ARB_END_ADDR 0xFFFFFFFF -#define MMDC1_ARB_BASE_ADDR 0xC0000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF -#else -#define MMDC0_ARB_BASE_ADDR 0x10000000 -#define MMDC0_ARB_END_ADDR 0x7FFFFFFF -#define MMDC1_ARB_BASE_ADDR 0x80000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF -#endif - -#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR -#define IPU_SOC_OFFSET 0x00200000 - -/* Defines for Blocks connected via AIPS (SkyBlue) */ -#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR -#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR - -#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) -#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) -#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) -#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) -#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) -#ifdef CONFIG_MX6SL -#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) -#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) -#else -#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) -#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#endif - -#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) -#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) -#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) - -#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) -#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) -#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) -#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) -#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) -#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) -#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) -#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) -#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) -#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) -#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) -#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) -#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) -#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) -#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) -#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) -#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) -#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) -#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) -#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) -#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) -#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) -#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) -#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) -#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) -#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) -#ifdef CONFIG_MX6SL -#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#else -#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#endif - -#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) -#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) -#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) -#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SL -#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#else -#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#endif - -#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) -#ifdef CONFIG_MX6SL -#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) -#else -#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) -#endif - -#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) -#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) -#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) -#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) -#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) -#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) -#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) -#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) -#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) -#ifdef CONFIG_MX6SL -#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#else -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#endif - -#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) -#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) -#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) -#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) -#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) -#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) -#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) -#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) -#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) - -#define CHIP_REV_1_0 0x10 -#define IRAM_SIZE 0x00040000 -#define FEC_QUIRK_ENET_MAC - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr1; - u32 srsr; - u32 reserved1[2]; - u32 sisr; - u32 simr; - u32 sbmr2; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 gpr8; - u32 gpr9; - u32 gpr10; -}; - -/* GPR1 bitfields */ -#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 -#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) - -/* GPR3 bitfields */ -#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 -#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) -#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 -#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 -#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 -#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 -#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) -#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 -#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) -#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 -#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) -#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 -#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 -#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 -#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 -#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) -#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 -#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) -#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 -#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) -#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 -#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) - -#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 -#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 -#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 -#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 - -#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 -#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) - -#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 -#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) - -#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 -#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) - -#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 -#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) - - -struct iomuxc { - u32 gpr[14]; - u32 omux[5]; - /* mux and pad registers */ -}; - -#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 -#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) -#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 -#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) - -#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 -#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) -#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) -#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) -#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 -#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 - -#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 -#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) - -#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 -#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) -#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) - -#define IOMUXC_GPR2_BITMAP_SPWG 0 -#define IOMUXC_GPR2_BITMAP_JEIDA 1 - -#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 -#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) - -#define IOMUXC_GPR2_DATA_WIDTH_18 0 -#define IOMUXC_GPR2_DATA_WIDTH_24 1 - -#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 -#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) - -#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 -#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) -#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) - -#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 -#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) -#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) - -#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 -#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) - -#define IOMUXC_GPR2_MODE_DISABLED 0 -#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 -#define IOMUXC_GPR2_MODE_ENABLED_DI1 3 - -#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 -#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) - -#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 -#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) -#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) - -/* ECSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 cfg; - u32 intr; - u32 dma; - u32 stat; - u32 period; -}; - -/* - * CSPI register definitions - */ -#define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_MODE_MASK (0xf << 4) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_PHA 0 /* SCLK phase control */ -#define MXC_CSPICON_POL 4 /* SCLK polarity */ -#define MXC_CSPICON_SSPOL 12 /* SS polarity */ -#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) -#define MXC_SPI_BASE_ADDRESSES \ - ECSPI1_BASE_ADDR, \ - ECSPI2_BASE_ADDR, \ - ECSPI3_BASE_ADDR, \ - ECSPI4_BASE_ADDR -#else -#define MXC_SPI_BASE_ADDRESSES \ - ECSPI1_BASE_ADDR, \ - ECSPI2_BASE_ADDR, \ - ECSPI3_BASE_ADDR, \ - ECSPI4_BASE_ADDR, \ - ECSPI5_BASE_ADDR -#endif - -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd5[3]; - u32 crc_value; - u32 rsvd6[3]; - u32 version; - u32 rsvd7[0xdb]; - - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[16]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[3]; - u32 rsvd3[4]; - u32 rsvd4[4]; - u32 rsvd5[4]; - u32 cfg5; - u32 rsvd6[3]; - u32 rsvd7[4]; -}; - -struct fuse_bank4_regs { - u32 sjc_resp_low; - u32 rsvd0[3]; - u32 sjc_resp_high; - u32 rsvd1[3]; - u32 mac_addr_low; - u32 rsvd2[3]; - u32 mac_addr_high; - u32 rsvd3[0xb]; - u32 gp1; - u32 rsvd4[3]; - u32 gp2; - u32 rsvd5[3]; -}; - -struct aipstz_regs { - u32 mprot0; - u32 mprot1; - u32 rsvd[0xe]; - u32 opacr0; - u32 opacr1; - u32 opacr2; - u32 opacr3; - u32 opacr4; -}; - -struct anatop_regs { - u32 pll_sys; /* 0x000 */ - u32 pll_sys_set; /* 0x004 */ - u32 pll_sys_clr; /* 0x008 */ - u32 pll_sys_tog; /* 0x00c */ - u32 usb1_pll_480_ctrl; /* 0x010 */ - u32 usb1_pll_480_ctrl_set; /* 0x014 */ - u32 usb1_pll_480_ctrl_clr; /* 0x018 */ - u32 usb1_pll_480_ctrl_tog; /* 0x01c */ - u32 usb2_pll_480_ctrl; /* 0x020 */ - u32 usb2_pll_480_ctrl_set; /* 0x024 */ - u32 usb2_pll_480_ctrl_clr; /* 0x028 */ - u32 usb2_pll_480_ctrl_tog; /* 0x02c */ - u32 pll_528; /* 0x030 */ - u32 pll_528_set; /* 0x034 */ - u32 pll_528_clr; /* 0x038 */ - u32 pll_528_tog; /* 0x03c */ - u32 pll_528_ss; /* 0x040 */ - u32 rsvd0[3]; - u32 pll_528_num; /* 0x050 */ - u32 rsvd1[3]; - u32 pll_528_denom; /* 0x060 */ - u32 rsvd2[3]; - u32 pll_audio; /* 0x070 */ - u32 pll_audio_set; /* 0x074 */ - u32 pll_audio_clr; /* 0x078 */ - u32 pll_audio_tog; /* 0x07c */ - u32 pll_audio_num; /* 0x080 */ - u32 rsvd3[3]; - u32 pll_audio_denom; /* 0x090 */ - u32 rsvd4[3]; - u32 pll_video; /* 0x0a0 */ - u32 pll_video_set; /* 0x0a4 */ - u32 pll_video_clr; /* 0x0a8 */ - u32 pll_video_tog; /* 0x0ac */ - u32 pll_video_num; /* 0x0b0 */ - u32 rsvd5[3]; - u32 pll_video_denom; /* 0x0c0 */ - u32 rsvd6[3]; - u32 pll_mlb; /* 0x0d0 */ - u32 pll_mlb_set; /* 0x0d4 */ - u32 pll_mlb_clr; /* 0x0d8 */ - u32 pll_mlb_tog; /* 0x0dc */ - u32 pll_enet; /* 0x0e0 */ - u32 pll_enet_set; /* 0x0e4 */ - u32 pll_enet_clr; /* 0x0e8 */ - u32 pll_enet_tog; /* 0x0ec */ - u32 pfd_480; /* 0x0f0 */ - u32 pfd_480_set; /* 0x0f4 */ - u32 pfd_480_clr; /* 0x0f8 */ - u32 pfd_480_tog; /* 0x0fc */ - u32 pfd_528; /* 0x100 */ - u32 pfd_528_set; /* 0x104 */ - u32 pfd_528_clr; /* 0x108 */ - u32 pfd_528_tog; /* 0x10c */ - u32 reg_1p1; /* 0x110 */ - u32 reg_1p1_set; /* 0x114 */ - u32 reg_1p1_clr; /* 0x118 */ - u32 reg_1p1_tog; /* 0x11c */ - u32 reg_3p0; /* 0x120 */ - u32 reg_3p0_set; /* 0x124 */ - u32 reg_3p0_clr; /* 0x128 */ - u32 reg_3p0_tog; /* 0x12c */ - u32 reg_2p5; /* 0x130 */ - u32 reg_2p5_set; /* 0x134 */ - u32 reg_2p5_clr; /* 0x138 */ - u32 reg_2p5_tog; /* 0x13c */ - u32 reg_core; /* 0x140 */ - u32 reg_core_set; /* 0x144 */ - u32 reg_core_clr; /* 0x148 */ - u32 reg_core_tog; /* 0x14c */ - u32 ana_misc0; /* 0x150 */ - u32 ana_misc0_set; /* 0x154 */ - u32 ana_misc0_clr; /* 0x158 */ - u32 ana_misc0_tog; /* 0x15c */ - u32 ana_misc1; /* 0x160 */ - u32 ana_misc1_set; /* 0x164 */ - u32 ana_misc1_clr; /* 0x168 */ - u32 ana_misc1_tog; /* 0x16c */ - u32 ana_misc2; /* 0x170 */ - u32 ana_misc2_set; /* 0x174 */ - u32 ana_misc2_clr; /* 0x178 */ - u32 ana_misc2_tog; /* 0x17c */ - u32 tempsense0; /* 0x180 */ - u32 tempsense0_set; /* 0x184 */ - u32 tempsense0_clr; /* 0x188 */ - u32 tempsense0_tog; /* 0x18c */ - u32 tempsense1; /* 0x190 */ - u32 tempsense1_set; /* 0x194 */ - u32 tempsense1_clr; /* 0x198 */ - u32 tempsense1_tog; /* 0x19c */ - u32 usb1_vbus_detect; /* 0x1a0 */ - u32 usb1_vbus_detect_set; /* 0x1a4 */ - u32 usb1_vbus_detect_clr; /* 0x1a8 */ - u32 usb1_vbus_detect_tog; /* 0x1ac */ - u32 usb1_chrg_detect; /* 0x1b0 */ - u32 usb1_chrg_detect_set; /* 0x1b4 */ - u32 usb1_chrg_detect_clr; /* 0x1b8 */ - u32 usb1_chrg_detect_tog; /* 0x1bc */ - u32 usb1_vbus_det_stat; /* 0x1c0 */ - u32 usb1_vbus_det_stat_set; /* 0x1c4 */ - u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ - u32 usb1_vbus_det_stat_tog; /* 0x1cc */ - u32 usb1_chrg_det_stat; /* 0x1d0 */ - u32 usb1_chrg_det_stat_set; /* 0x1d4 */ - u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ - u32 usb1_chrg_det_stat_tog; /* 0x1dc */ - u32 usb1_loopback; /* 0x1e0 */ - u32 usb1_loopback_set; /* 0x1e4 */ - u32 usb1_loopback_clr; /* 0x1e8 */ - u32 usb1_loopback_tog; /* 0x1ec */ - u32 usb1_misc; /* 0x1f0 */ - u32 usb1_misc_set; /* 0x1f4 */ - u32 usb1_misc_clr; /* 0x1f8 */ - u32 usb1_misc_tog; /* 0x1fc */ - u32 usb2_vbus_detect; /* 0x200 */ - u32 usb2_vbus_detect_set; /* 0x204 */ - u32 usb2_vbus_detect_clr; /* 0x208 */ - u32 usb2_vbus_detect_tog; /* 0x20c */ - u32 usb2_chrg_detect; /* 0x210 */ - u32 usb2_chrg_detect_set; /* 0x214 */ - u32 usb2_chrg_detect_clr; /* 0x218 */ - u32 usb2_chrg_detect_tog; /* 0x21c */ - u32 usb2_vbus_det_stat; /* 0x220 */ - u32 usb2_vbus_det_stat_set; /* 0x224 */ - u32 usb2_vbus_det_stat_clr; /* 0x228 */ - u32 usb2_vbus_det_stat_tog; /* 0x22c */ - u32 usb2_chrg_det_stat; /* 0x230 */ - u32 usb2_chrg_det_stat_set; /* 0x234 */ - u32 usb2_chrg_det_stat_clr; /* 0x238 */ - u32 usb2_chrg_det_stat_tog; /* 0x23c */ - u32 usb2_loopback; /* 0x240 */ - u32 usb2_loopback_set; /* 0x244 */ - u32 usb2_loopback_clr; /* 0x248 */ - u32 usb2_loopback_tog; /* 0x24c */ - u32 usb2_misc; /* 0x250 */ - u32 usb2_misc_set; /* 0x254 */ - u32 usb2_misc_clr; /* 0x258 */ - u32 usb2_misc_tog; /* 0x25c */ - u32 digprog; /* 0x260 */ - u32 reserved1[7]; - u32 digprog_sololite; /* 0x280 */ -}; - -#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) -#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) -#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) -#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) -#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) -#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) - -struct iomuxc_base_regs { - u32 gpr[14]; /* 0x000 */ - u32 obsrv[5]; /* 0x038 */ - u32 swmux_ctl[197]; /* 0x04c */ - u32 swpad_ctl[250]; /* 0x360 */ - u32 swgrp[26]; /* 0x748 */ - u32 daisy[104]; /* 0x7b0..94c */ -}; - -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Miscellaneous Control */ -}; - -#endif /* __ASSEMBLER__*/ -#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h deleted file mode 100644 index f9ee0d983..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_IOMUX_H__ -#define __ASM_ARCH_IOMUX_H__ - -#define MX6_IOMUXC_GPR4 0x020e0010 -#define MX6_IOMUXC_GPR6 0x020e0018 -#define MX6_IOMUXC_GPR7 0x020e001c - -/* - * IOMUXC_GPR1 bit fields - */ -#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) -#define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) -#define IOMUXC_GPR1_OTG_ID_MASK (1<<13) -#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) -#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) - -/* - * IOMUXC_GPR8 bit fields - */ -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET 6 -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << 12) -#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 -#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) -#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 -#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) -#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET 25 - -/* - * IOMUXC_GPR12 bit fields - */ -#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) -#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) -#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) -#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) - -/* - * IOMUXC_GPR13 bit fields - */ -#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) -#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) -#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) -#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) -#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) -#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) -#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 -#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) -#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15) -#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14) -#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11) -#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7) -#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) -#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) - -#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) -#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) -#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ - | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) - -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) - -#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) - -#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) -#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) - -#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14) -#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14) - -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) -#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) - -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) - -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) - -#define IOMUXC_GPR13_SATA_PHY_1_FAST 0 -#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 -#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2 - -#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \ - |IOMUXC_GPR13_SATA_PHY_7_MASK \ - |IOMUXC_GPR13_SATA_PHY_6_MASK \ - |IOMUXC_GPR13_SATA_SPEED_MASK \ - |IOMUXC_GPR13_SATA_PHY_5_MASK \ - |IOMUXC_GPR13_SATA_PHY_4_MASK \ - |IOMUXC_GPR13_SATA_PHY_3_MASK \ - |IOMUXC_GPR13_SATA_PHY_2_MASK \ - |IOMUXC_GPR13_SATA_PHY_1_MASK) -#endif /* __ASM_ARCH_IOMUX_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h deleted file mode 100644 index 43d377af3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_MX6_DDR_H__ -#define __ASM_ARCH_MX6_DDR_H__ - -#ifdef CONFIG_MX6Q -#include "mx6q-ddr.h" -#else -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -#include "mx6dl-ddr.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX6DL or CONFIG_MX6S */ -#endif /* CONFIG_MX6Q */ - -#define MX6_MMDC_P0_MDCTL 0x021b0000 -#define MX6_MMDC_P0_MDPDC 0x021b0004 -#define MX6_MMDC_P0_MDOTC 0x021b0008 -#define MX6_MMDC_P0_MDCFG0 0x021b000c -#define MX6_MMDC_P0_MDCFG1 0x021b0010 -#define MX6_MMDC_P0_MDCFG2 0x021b0014 -#define MX6_MMDC_P0_MDMISC 0x021b0018 -#define MX6_MMDC_P0_MDSCR 0x021b001c -#define MX6_MMDC_P0_MDREF 0x021b0020 -#define MX6_MMDC_P0_MDRWD 0x021b002c -#define MX6_MMDC_P0_MDOR 0x021b0030 -#define MX6_MMDC_P0_MDASP 0x021b0040 -#define MX6_MMDC_P0_MAPSR 0x021b0404 -#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 -#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c -#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810 -#define MX6_MMDC_P0_MPODTCTRL 0x021b0818 -#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c -#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820 -#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824 -#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828 -#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c -#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840 -#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848 -#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850 -#define MX6_MMDC_P0_MPMUR0 0x021b08b8 - -#define MX6_MMDC_P1_MDCTL 0x021b4000 -#define MX6_MMDC_P1_MDPDC 0x021b4004 -#define MX6_MMDC_P1_MDOTC 0x021b4008 -#define MX6_MMDC_P1_MDCFG0 0x021b400c -#define MX6_MMDC_P1_MDCFG1 0x021b4010 -#define MX6_MMDC_P1_MDCFG2 0x021b4014 -#define MX6_MMDC_P1_MDMISC 0x021b4018 -#define MX6_MMDC_P1_MDSCR 0x021b401c -#define MX6_MMDC_P1_MDREF 0x021b4020 -#define MX6_MMDC_P1_MDRWD 0x021b402c -#define MX6_MMDC_P1_MDOR 0x021b4030 -#define MX6_MMDC_P1_MDASP 0x021b4040 -#define MX6_MMDC_P1_MAPSR 0x021b4404 -#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800 -#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c -#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810 -#define MX6_MMDC_P1_MPODTCTRL 0x021b4818 -#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c -#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820 -#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824 -#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828 -#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c -#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840 -#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848 -#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850 -#define MX6_MMDC_P1_MPMUR0 0x021b48b8 - -#endif /*__ASM_ARCH_MX6_DDR_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h deleted file mode 100644 index dcd7f8f32..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_MX6_PINS_H__ -#define __ASM_ARCH_MX6_PINS_H__ - -#include <asm/imx-common/iomux-v3.h> - -#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ - prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc) - -#ifdef CONFIG_MX6QDL -enum { -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6q_pins.h" -#undef MX6_PAD_DECL -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6dl_pins.h" -}; -#elif defined(CONFIG_MX6Q) -enum { -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6q_pins.h" -}; -#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -enum { -#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ - MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), -#include "mx6dl_pins.h" -}; -#elif defined(CONFIG_MX6SL) -#include "mx6sl_pins.h" -#else -#error "Please select cpu" -#endif /* CONFIG_MX6Q */ - -#endif /*__ASM_ARCH_MX6_PINS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h deleted file mode 100644 index 1eb4b3c8b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_MX6DLS_DDR_H__ -#define __ASM_ARCH_MX6DLS_DDR_H__ - -#ifndef CONFIG_MX6DL -#ifndef CONFIG_MX6S -#error "wrong CPU" -#endif -#endif - -#define MX6_IOM_DRAM_DQM0 0x020e0470 -#define MX6_IOM_DRAM_DQM1 0x020e0474 -#define MX6_IOM_DRAM_DQM2 0x020e0478 -#define MX6_IOM_DRAM_DQM3 0x020e047c -#define MX6_IOM_DRAM_DQM4 0x020e0480 -#define MX6_IOM_DRAM_DQM5 0x020e0484 -#define MX6_IOM_DRAM_DQM6 0x020e0488 -#define MX6_IOM_DRAM_DQM7 0x020e048c - -#define MX6_IOM_DRAM_CAS 0x020e0464 -#define MX6_IOM_DRAM_RAS 0x020e0490 -#define MX6_IOM_DRAM_RESET 0x020e0494 -#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac -#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0 -#define MX6_IOM_DRAM_SDBA2 0x020e04a0 -#define MX6_IOM_DRAM_SDCKE0 0x020e04a4 -#define MX6_IOM_DRAM_SDCKE1 0x020e04a8 -#define MX6_IOM_DRAM_SDODT0 0x020e04b4 -#define MX6_IOM_DRAM_SDODT1 0x020e04b8 - -#define MX6_IOM_DRAM_SDQS0 0x020e04bc -#define MX6_IOM_DRAM_SDQS1 0x020e04c0 -#define MX6_IOM_DRAM_SDQS2 0x020e04c4 -#define MX6_IOM_DRAM_SDQS3 0x020e04c8 -#define MX6_IOM_DRAM_SDQS4 0x020e04cc -#define MX6_IOM_DRAM_SDQS5 0x020e04d0 -#define MX6_IOM_DRAM_SDQS6 0x020e04d4 -#define MX6_IOM_DRAM_SDQS7 0x020e04d8 - -#define MX6_IOM_GRP_B0DS 0x020e0764 -#define MX6_IOM_GRP_B1DS 0x020e0770 -#define MX6_IOM_GRP_B2DS 0x020e0778 -#define MX6_IOM_GRP_B3DS 0x020e077c -#define MX6_IOM_GRP_B4DS 0x020e0780 -#define MX6_IOM_GRP_B5DS 0x020e0784 -#define MX6_IOM_GRP_B6DS 0x020e078c -#define MX6_IOM_GRP_B7DS 0x020e0748 -#define MX6_IOM_GRP_ADDDS 0x020e074c -#define MX6_IOM_DDRMODE_CTL 0x020e0750 -#define MX6_IOM_GRP_DDRPKE 0x020e0754 -#define MX6_IOM_GRP_DDRMODE 0x020e0760 -#define MX6_IOM_GRP_CTLDS 0x020e076c -#define MX6_IOM_GRP_DDR_TYPE 0x020e0774 - -#endif /*__ASM_ARCH_MX6S_DDR_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h deleted file mode 100644 index 2e414adf3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ /dev/null @@ -1,1080 +0,0 @@ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__ -#define __ASM_ARCH_MX6_MX6DL_PINS_H__ - -MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0364, 0x0050, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0364, 0x0050, 3, 0x08FC, 1, 0) -MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0364, 0x0050, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0364, 0x0050, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0368, 0x0054, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0368, 0x0054, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0368, 0x0054, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0368, 0x0054, 3, 0x0914, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0368, 0x0054, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0368, 0x0054, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x036C, 0x0058, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x036C, 0x0058, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x036C, 0x0058, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x036C, 0x0058, 3, 0x0914, 1, 0) -MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x036C, 0x0058, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x036C, 0x0058, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0370, 0x005C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0370, 0x005C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0370, 0x005C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0370, 0x005C, 3, 0x091C, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0370, 0x005C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0370, 0x005C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0374, 0x0060, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0374, 0x0060, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0374, 0x0060, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0374, 0x0060, 3, 0x091C, 1, 0) -MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0374, 0x0060, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0374, 0x0060, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0378, 0x0064, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0378, 0x0064, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0378, 0x0064, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0378, 0x0064, 3, 0x0910, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0378, 0x0064, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0378, 0x0064, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x037C, 0x0068, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x037C, 0x0068, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x037C, 0x0068, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x037C, 0x0068, 3, 0x0910, 1, 0) -MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x037C, 0x0068, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x037C, 0x0068, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0380, 0x006C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0380, 0x006C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0380, 0x006C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0380, 0x006C, 3, 0x0918, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0380, 0x006C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0380, 0x006C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0384, 0x0070, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0384, 0x0070, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0384, 0x0070, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0384, 0x0070, 3, 0x0918, 1, 0) -MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0384, 0x0070, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0388, 0x0074, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0388, 0x0074, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0388, 0x0074, 2, 0x07D8, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0388, 0x0074, 3, 0x08C0, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0388, 0x0074, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0388, 0x0074, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0388, 0x0074, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x038C, 0x0078, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x038C, 0x0078, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x038C, 0x0078, 2, 0x07E0, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x038C, 0x0078, 3, 0x08CC, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x038C, 0x0078, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x038C, 0x0078, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x038C, 0x0078, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0390, 0x007C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0390, 0x007C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0390, 0x007C, 2, 0x07DC, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0390, 0x007C, 3, 0x08C4, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0390, 0x007C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0390, 0x007C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0390, 0x007C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0394, 0x0080, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0394, 0x0080, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0394, 0x0080, 2, 0x07E4, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0394, 0x0080, 3, 0x08D0, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0394, 0x0080, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0394, 0x0080, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0394, 0x0080, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0398, 0x0084, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0398, 0x0084, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0398, 0x0084, 2, 0x07F4, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0398, 0x0084, 3, 0x08C8, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0398, 0x0084, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0398, 0x0084, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x039C, 0x0088, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x039C, 0x0088, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x039C, 0x0088, 2, 0x07FC, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x039C, 0x0088, 3, 0x08D4, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x039C, 0x0088, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x039C, 0x0088, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x03A0, 0x008C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x03A0, 0x008C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x03A0, 0x008C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x03A0, 0x008C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x03A4, 0x0090, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x03A4, 0x0090, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x03A4, 0x0090, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x03A4, 0x0090, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x03A8, 0x0094, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x03A8, 0x0094, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x03A8, 0x0094, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x03AC, 0x0098, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x03AC, 0x0098, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x03AC, 0x0098, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x03AC, 0x0098, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK, 0x03B0, 0x009C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x03B0, 0x009C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN, 0x03B0, 0x009C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE, 0x03B4, 0x00A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__LCD_RD_E, 0x03B4, 0x00A0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC, 0x03B8, 0x00A4, 1, 0x08D8, 0, 0) -MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__LCD_RS, 0x03B8, 0x00A4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__LCD_CS, 0x03BC, 0x00A8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN4__LCD_BUSY, 0x03C0, 0x00AC, 1, 0x08D8, 1, 0) -MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x03C0, 0x00AC, 3, 0x092C, 0, 0) -MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__LCD_RESET, 0x03C0, 0x00AC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13, 0x03D8, 0x00C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x03D8, 0x00C4, 3, 0x07BC, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x03DC, 0x00C8, 3, 0x07B8, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x03E0, 0x00CC, 2, 0x07E8, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x03E0, 0x00CC, 3, 0x0804, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x03E4, 0x00D0, 2, 0x07FC, 1, 0) -MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x03E4, 0x00D0, 3, 0x07C0, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x03E4, 0x00D0, 4, 0x08E8, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x03E8, 0x00D4, 2, 0x07F8, 1, 0) -MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x03E8, 0x00D4, 3, 0x07B4, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x03E8, 0x00D4, 4, 0x08EC, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x03EC, 0x00D8, 2, 0x0800, 1, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x03EC, 0x00D8, 3, 0x07C4, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x03EC, 0x00D8, 4, 0x07A4, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x03F0, 0x00DC, 2, 0x07F4, 1, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x03F0, 0x00DC, 3, 0x07B0, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x03F8, 0x00E4, 2, 0x07D8, 1, 0) -MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x03F8, 0x00E4, 3, 0x07A8, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x03FC, 0x00E8, 2, 0x07E0, 1, 0) -MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x03FC, 0x00E8, 3, 0x079C, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22, 0x0400, 0x00EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x0400, 0x00EC, 2, 0x07DC, 1, 0) -MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x0400, 0x00EC, 3, 0x07AC, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x0400, 0x00EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23, 0x0404, 0x00F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x0404, 0x00F0, 2, 0x07E4, 1, 0) -MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x0404, 0x00F0, 3, 0x0798, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x0404, 0x00F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03, 0x0408, 0x00F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0408, 0x00F4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0408, 0x00F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04, 0x040C, 0x00F8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x040C, 0x00F8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x040C, 0x00F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05, 0x0410, 0x00FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0410, 0x00FC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0410, 0x00FC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0410, 0x00FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06, 0x0414, 0x0100, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x0414, 0x0100, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x0414, 0x0100, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x0414, 0x0100, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07, 0x0418, 0x0104, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x0418, 0x0104, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x0418, 0x0104, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08, 0x041C, 0x0108, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x041C, 0x0108, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x041C, 0x0108, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x041C, 0x0108, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09, 0x0420, 0x010C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x0420, 0x010C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x0420, 0x010C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x0420, 0x010C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x04E0, 0x0110, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x04E0, 0x0110, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK, 0x04E0, 0x0110, 2, 0x08B8, 0, 0) -MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x04E0, 0x0110, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x04E0, 0x0110, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__EPDC_DATA00, 0x04E0, 0x0110, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x04E4, 0x0114, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x04E4, 0x0114, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12, 0x04E4, 0x0114, 2, 0x0890, 0, 0) -MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x04E4, 0x0114, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x04E4, 0x0114, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT, 0x04E4, 0x0114, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x04E8, 0x0118, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x04E8, 0x0118, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13, 0x04E8, 0x0118, 2, 0x0894, 0, 0) -MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x04E8, 0x0118, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x04E8, 0x0118, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0, 0x04E8, 0x0118, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x04EC, 0x011C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x04EC, 0x011C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14, 0x04EC, 0x011C, 2, 0x0898, 0, 0) -MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x04EC, 0x011C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x04EC, 0x011C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1, 0x04EC, 0x011C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x04F0, 0x0120, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x04F0, 0x0120, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15, 0x04F0, 0x0120, 2, 0x089C, 0, 0) -MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x04F0, 0x0120, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x04F0, 0x0120, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2, 0x04F0, 0x0120, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x04F4, 0x0124, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x04F4, 0x0124, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16, 0x04F4, 0x0124, 2, 0x08A0, 0, 0) -MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x04F4, 0x0124, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x04F4, 0x0124, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__EPDC_GDCLK, 0x04F4, 0x0124, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x04F8, 0x0128, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x04F8, 0x0128, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17, 0x04F8, 0x0128, 2, 0x08A4, 0, 0) -MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x04F8, 0x0128, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x04F8, 0x0128, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__EPDC_GDSP, 0x04F8, 0x0128, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x04FC, 0x012C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x04FC, 0x012C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18, 0x04FC, 0x012C, 2, 0x08A8, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x04FC, 0x012C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x04FC, 0x012C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x04FC, 0x012C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__EPDC_GDOE, 0x04FC, 0x012C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x0500, 0x0130, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x0500, 0x0130, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19, 0x0500, 0x0130, 2, 0x08AC, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x0500, 0x0130, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x0500, 0x0130, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x0500, 0x0130, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__EPDC_GDRL, 0x0500, 0x0130, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x0504, 0x0134, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x0504, 0x0134, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x0504, 0x0134, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x0504, 0x0134, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x0504, 0x0134, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x0504, 0x0134, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x0504, 0x0134, 6, 0x085C, 0, 0) -MX6_PAD_DECL(EIM_A25__EPDC_DATA15, 0x0504, 0x0134, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN, 0x0504, 0x0134, 9, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x0508, 0x0138, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x0508, 0x0138, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x0508, 0x0138, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9, 0x0508, 0x0138, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x050C, 0x013C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x050C, 0x013C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x050C, 0x013C, 2, 0x07F4, 2, 0) -MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x050C, 0x013C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__EPDC_DATA06, 0x050C, 0x013C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0510, 0x0140, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0510, 0x0140, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0510, 0x0140, 2, 0x07FC, 2, 0) -MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0510, 0x0140, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__EPDC_DATA08, 0x0510, 0x0140, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x0514, 0x0144, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x0514, 0x0144, 1, 0x07D8, 2, 0) -MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x0514, 0x0144, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18, 0x0514, 0x0144, 3, 0x08A8, 1, 0) -MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x0514, 0x0144, 4, 0x0864, 0, 0) -MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x0514, 0x0144, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0) -MX6_PAD_DECL(EIM_D16__EPDC_DATA10, 0x0514, 0x0144, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x0518, 0x0148, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x0518, 0x0148, 1, 0x07DC, 2, 0) -MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x0518, 0x0148, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK, 0x0518, 0x0148, 3, 0x08B8, 1, 0) -MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x0518, 0x0148, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x0518, 0x0148, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0) -MX6_PAD_DECL(EIM_D17__EPDC_VCOM0, 0x0518, 0x0148, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x051C, 0x014C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x051C, 0x014C, 1, 0x07E0, 2, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x051C, 0x014C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17, 0x051C, 0x014C, 3, 0x08A4, 1, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x051C, 0x014C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x051C, 0x014C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0) -MX6_PAD_DECL(EIM_D18__EPDC_VCOM1, 0x051C, 0x014C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x0520, 0x0150, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x0520, 0x0150, 1, 0x07E8, 1, 0) -MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x0520, 0x0150, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16, 0x0520, 0x0150, 3, 0x08A0, 1, 0) -MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x0520, 0x0150, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x0520, 0x0150, 4, 0x08F8, 0, 0) -MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x0520, 0x0150, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x0520, 0x0150, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EPDC_DATA12, 0x0520, 0x0150, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x0524, 0x0154, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x0524, 0x0154, 1, 0x0808, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x0524, 0x0154, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15, 0x0524, 0x0154, 3, 0x089C, 1, 0) -MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x0524, 0x0154, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x0524, 0x0154, 4, 0x08F8, 1, 0) -MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x0524, 0x0154, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x0524, 0x0154, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x0528, 0x0158, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x0528, 0x0158, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x0528, 0x0158, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11, 0x0528, 0x0158, 3, 0x088C, 0, 0) -MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x0528, 0x0158, 4, 0x0920, 0, 0) -MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x0528, 0x0158, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0) -MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x0528, 0x0158, 7, 0x08F0, 0, 0) -MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x052C, 0x015C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x052C, 0x015C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x052C, 0x015C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10, 0x052C, 0x015C, 3, 0x0888, 0, 0) -MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x052C, 0x015C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x052C, 0x015C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x052C, 0x015C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__EPDC_SDCE6, 0x052C, 0x015C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x0530, 0x0160, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x0530, 0x0160, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x0530, 0x0160, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x0530, 0x0160, 2, 0x0908, 0, 0) -MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x0530, 0x0160, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN, 0x0530, 0x0160, 4, 0x08B0, 0, 0) -MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x0530, 0x0160, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x0530, 0x0160, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x0530, 0x0160, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__EPDC_DATA11, 0x0530, 0x0160, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x0534, 0x0164, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x0534, 0x0164, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x0534, 0x0164, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x0534, 0x0164, 2, 0x090C, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x0534, 0x0164, 3, 0x07EC, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x0534, 0x0164, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x0534, 0x0164, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x0534, 0x0164, 6, 0x07BC, 1, 0) -MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x0534, 0x0164, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__EPDC_SDCE7, 0x0534, 0x0164, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x0538, 0x0168, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x0538, 0x0168, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x0538, 0x0168, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x0538, 0x0168, 2, 0x090C, 1, 0) -MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x0538, 0x0168, 3, 0x07F0, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x0538, 0x0168, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x0538, 0x0168, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x0538, 0x0168, 6, 0x07B8, 1, 0) -MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x0538, 0x0168, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__EPDC_SDCE8, 0x0538, 0x0168, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x053C, 0x016C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x053C, 0x016C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x053C, 0x016C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14, 0x053C, 0x016C, 3, 0x0898, 1, 0) -MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x053C, 0x016C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x053C, 0x016C, 4, 0x0904, 0, 0) -MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x053C, 0x016C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x053C, 0x016C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x053C, 0x016C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__EPDC_SDOED, 0x053C, 0x016C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x0540, 0x0170, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x0540, 0x0170, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x0540, 0x0170, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13, 0x0540, 0x0170, 3, 0x0894, 1, 0) -MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x0540, 0x0170, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x0540, 0x0170, 4, 0x0904, 1, 0) -MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x0540, 0x0170, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x0540, 0x0170, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x0540, 0x0170, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__EPDC_SDOE, 0x0540, 0x0170, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x0544, 0x0174, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0) -MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x0544, 0x0174, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12, 0x0544, 0x0174, 3, 0x0890, 1, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x0544, 0x0174, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x0544, 0x0174, 4, 0x0900, 0, 0) -MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x0544, 0x0174, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x0544, 0x0174, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x0544, 0x0174, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3, 0x0544, 0x0174, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x0548, 0x0178, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x0548, 0x0178, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x0548, 0x0178, 2, 0x0808, 1, 0) -MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x0548, 0x0178, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x0548, 0x0178, 4, 0x0900, 1, 0) -MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x0548, 0x0178, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC, 0x0548, 0x0178, 6, 0x08BC, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x0548, 0x0178, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE, 0x0548, 0x0178, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x054C, 0x017C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x054C, 0x017C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x054C, 0x017C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x054C, 0x017C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x054C, 0x017C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x054C, 0x017C, 4, 0x0908, 1, 0) -MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x054C, 0x017C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x054C, 0x017C, 6, 0x0924, 0, 0) -MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ, 0x054C, 0x017C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x0550, 0x0180, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x0550, 0x0180, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x0550, 0x0180, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x0550, 0x0180, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x0550, 0x0180, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x0550, 0x0180, 4, 0x0908, 2, 0) -MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x0550, 0x0180, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x0550, 0x0180, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P, 0x0550, 0x0180, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN, 0x0550, 0x0180, 9, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0554, 0x0184, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0554, 0x0184, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09, 0x0554, 0x0184, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0554, 0x0184, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0554, 0x0184, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N, 0x0554, 0x0184, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x0558, 0x0188, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x0558, 0x0188, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08, 0x0558, 0x0188, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x0558, 0x0188, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x0558, 0x0188, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__EPDC_SDLE, 0x0558, 0x0188, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x055C, 0x018C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x055C, 0x018C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN, 0x055C, 0x018C, 2, 0x08B0, 1, 0) -MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x055C, 0x018C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x055C, 0x018C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__EPDC_DATA01, 0x055C, 0x018C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0560, 0x0190, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0560, 0x0190, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC, 0x0560, 0x0190, 2, 0x08B4, 0, 0) -MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0560, 0x0190, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0560, 0x0190, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__EPDC_DATA03, 0x0560, 0x0190, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0564, 0x0194, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0564, 0x0194, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC, 0x0564, 0x0194, 2, 0x08BC, 1, 0) -MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0564, 0x0194, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0564, 0x0194, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__EPDC_DATA02, 0x0564, 0x0194, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x0568, 0x0198, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x0568, 0x0198, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x0568, 0x0198, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x0568, 0x0198, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__EPDC_DATA13, 0x0568, 0x0198, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x056C, 0x019C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x056C, 0x019C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x056C, 0x019C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x056C, 0x019C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__EPDC_DATA14, 0x056C, 0x019C, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0570, 0x01A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0570, 0x01A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0570, 0x01A0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0570, 0x01A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0570, 0x01A0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__EPDC_DATA09, 0x0570, 0x01A0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0574, 0x01A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0574, 0x01A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07, 0x0574, 0x01A4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0574, 0x01A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0574, 0x01A4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__EPDC_BDR0, 0x0574, 0x01A4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0578, 0x01A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0578, 0x01A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06, 0x0578, 0x01A8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0578, 0x01A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0578, 0x01A8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__EPDC_BDR1, 0x0578, 0x01A8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x057C, 0x01AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x057C, 0x01AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05, 0x057C, 0x01AC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x057C, 0x01AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x057C, 0x01AC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0, 0x057C, 0x01AC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x0580, 0x01B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x0580, 0x01B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04, 0x0580, 0x01B0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x0580, 0x01B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x0580, 0x01B0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1, 0x0580, 0x01B0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0584, 0x01B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0584, 0x01B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03, 0x0584, 0x01B4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0584, 0x01B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0584, 0x01B4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2, 0x0584, 0x01B4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0588, 0x01B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0588, 0x01B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02, 0x0588, 0x01B8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0588, 0x01B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0588, 0x01B8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3, 0x0588, 0x01B8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x058C, 0x01BC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x058C, 0x01BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01, 0x058C, 0x01BC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x058C, 0x01BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x058C, 0x01BC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4, 0x058C, 0x01BC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x0590, 0x01C0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x0590, 0x01C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00, 0x0590, 0x01C0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x0590, 0x01C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x0590, 0x01C0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5, 0x0590, 0x01C0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0594, 0x01C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0594, 0x01C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11, 0x0594, 0x01C4, 2, 0x088C, 1, 0) -MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0594, 0x01C4, 4, 0x07D4, 0, 0) -MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0594, 0x01C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0594, 0x01C4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM, 0x0594, 0x01C4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0598, 0x01C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0598, 0x01C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10, 0x0598, 0x01C8, 2, 0x0888, 1, 0) -MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0598, 0x01C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0598, 0x01C8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR, 0x0598, 0x01C8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x059C, 0x01CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x059C, 0x01CC, 1, 0x07E4, 2, 0) -MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19, 0x059C, 0x01CC, 3, 0x08AC, 1, 0) -MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x059C, 0x01CC, 4, 0x0860, 0, 0) -MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x059C, 0x01CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0) -MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x059C, 0x01CC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__EPDC_DATA05, 0x059C, 0x01CC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x05A0, 0x01D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x05A0, 0x01D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x05A0, 0x01D0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x05A0, 0x01D0, 2, 0x0908, 3, 0) -MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x05A0, 0x01D0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC, 0x05A0, 0x01D0, 4, 0x08B4, 1, 0) -MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x05A0, 0x01D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x05A0, 0x01D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x05A0, 0x01D0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0, 0x05A0, 0x01D0, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN, 0x05A0, 0x01D0, 9, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x05A4, 0x01D4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x05A4, 0x01D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x05A4, 0x01D4, 2, 0x0804, 1, 0) -MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x05A4, 0x01D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x05A4, 0x01D4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__EPDC_DATA04, 0x05A4, 0x01D4, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x05A8, 0x01D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x05A8, 0x01D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x05A8, 0x01D8, 2, 0x07F8, 2, 0) -MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x05A8, 0x01D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ, 0x05A8, 0x01D8, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__EIM_RW, 0x05AC, 0x01DC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x05AC, 0x01DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x05AC, 0x01DC, 2, 0x0800, 2, 0) -MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x05AC, 0x01DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x05AC, 0x01DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__EPDC_DATA07, 0x05AC, 0x01DC, 8, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x05B0, 0x01E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x05B0, 0x01E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x05B0, 0x01E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x05B0, 0x01E0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x05B4, 0x01E4, 1, 0x0828, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x05B4, 0x01E4, 2, 0x0840, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x05B4, 0x01E4, 3, 0x08F4, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x05B4, 0x01E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x05B8, 0x01E8, 0, 0x08E0, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x05B8, 0x01E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x05B8, 0x01E8, 2, 0x0858, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x05B8, 0x01E8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x05B8, 0x01E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x05BC, 0x01EC, 1, 0x0810, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x05BC, 0x01EC, 2, 0x083C, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x05BC, 0x01EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x05BC, 0x01EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x05BC, 0x01EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x05C0, 0x01F0, 2, 0x082C, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x05C0, 0x01F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x05C0, 0x01F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x05C4, 0x01F4, 0, 0x0790, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x05C4, 0x01F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x05C4, 0x01F4, 2, 0x0834, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x05C4, 0x01F4, 3, 0x08F0, 1, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x05C4, 0x01F4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x05C4, 0x01F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x05C8, 0x01F8, 1, 0x0818, 0, 0) -MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x05C8, 0x01F8, 2, 0x0838, 0, 0) -MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x05CC, 0x01FC, 0, 0x08E4, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x05CC, 0x01FC, 1, 0x081C, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x05CC, 0x01FC, 2, 0x0830, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x05D0, 0x0200, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x05D0, 0x0200, 2, 0x0850, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x05D0, 0x0200, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL, 0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x05D4, 0x0204, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x05D4, 0x0204, 2, 0x0854, 0, 0) -MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x05D4, 0x0204, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x05D8, 0x0208, 0, 0x08DC, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x05D8, 0x0208, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x05D8, 0x0208, 2, 0x084C, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x05D8, 0x0208, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x05D8, 0x0208, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__I2C4_SDA, 0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0) -MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05DC, 0x020C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05DC, 0x020C, 2, 0x08C0, 1, 0) -MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05DC, 0x020C, 3, 0x0794, 0, 0) -MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05DC, 0x020C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05DC, 0x020C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05DC, 0x020C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05E0, 0x0210, 0, 0x083C, 1, 0) -MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05E0, 0x0210, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05E0, 0x0210, 2, 0x08CC, 1, 0) -MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05E0, 0x0210, 3, 0x0790, 1, 0) -MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05E0, 0x0210, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05E0, 0x0210, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05E0, 0x0210, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x05E4, 0x0214, 0, 0x0850, 1, 0) -MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x05E4, 0x0214, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0) -MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x05E4, 0x0214, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x05E4, 0x0214, 4, 0x08F0, 2, 0) -MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x05E4, 0x0214, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0) -MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x05E4, 0x0214, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x05E8, 0x0218, 0, 0x0844, 0, 0) -MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x05E8, 0x0218, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x05E8, 0x0218, 2, 0x07D4, 1, 0) -MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x05E8, 0x0218, 3, 0x08E8, 1, 0) -MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x05E8, 0x0218, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x05E8, 0x0218, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x05EC, 0x021C, 0, 0x0848, 0, 0) -MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x05EC, 0x021C, 1, 0x0814, 0, 0) -MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x05EC, 0x021C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x05EC, 0x021C, 3, 0x08EC, 1, 0) -MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x05EC, 0x021C, 4, 0x0794, 1, 0) -MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x05EC, 0x021C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x05EC, 0x021C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x05F0, 0x0220, 0, 0x08C0, 2, 0) -MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x05F0, 0x0220, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x05F0, 0x0220, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x05F0, 0x0220, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x05F0, 0x0220, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x05F0, 0x0220, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x05F0, 0x0220, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x05F4, 0x0224, 0, 0x0830, 1, 0) -MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x05F4, 0x0224, 2, 0x08D0, 1, 0) -MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x05F4, 0x0224, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__SD2_WP, 0x05F4, 0x0224, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x05F4, 0x0224, 7, 0x08E0, 1, 0) -MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05F8, 0x0228, 0, 0x0834, 1, 0) -MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0) -MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05F8, 0x0228, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05F8, 0x0228, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05F8, 0x0228, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05F8, 0x0228, 6, 0x0924, 1, 0) -MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05F8, 0x0228, 7, 0x08DC, 1, 0) -MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x05FC, 0x022C, 0, 0x0838, 1, 0) -MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x05FC, 0x022C, 2, 0x08C8, 1, 0) -MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x05FC, 0x022C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x05FC, 0x022C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x0600, 0x0230, 0, 0x084C, 1, 0) -MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x0600, 0x0230, 2, 0x08D4, 1, 0) -MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x0600, 0x0230, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x0600, 0x0230, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0) -MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x0600, 0x0230, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0604, 0x0234, 0, 0x0840, 1, 0) -MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0) -MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0604, 0x0234, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0604, 0x0234, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0604, 0x0234, 7, 0x08E4, 1, 0) -MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0608, 0x0238, 0, 0x0854, 1, 0) -MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0608, 0x0238, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0608, 0x0238, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0608, 0x0238, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0608, 0x0238, 4, 0x0904, 2, 0) -MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0608, 0x0238, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0608, 0x0238, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0608, 0x0238, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__I2C4_SCL, 0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0) -MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x060C, 0x023C, 0, 0x0858, 1, 0) -MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x060C, 0x023C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x060C, 0x023C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x060C, 0x023C, 3, 0x07C8, 0, 0) -MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x060C, 0x023C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x060C, 0x023C, 4, 0x0904, 3, 0) -MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x060C, 0x023C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x060C, 0x023C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x060C, 0x023C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__I2C4_SDA, 0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0) -MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x0610, 0x0240, 0, 0x082C, 1, 0) -MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x0610, 0x0240, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x0610, 0x0240, 2, 0x08C4, 1, 0) -MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x0610, 0x0240, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x0610, 0x0240, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x0610, 0x0240, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__SD1_WP, 0x0610, 0x0240, 6, 0x092C, 1, 0) -MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x062C, 0x0244, 0, 0x07D8, 3, 0) -MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x062C, 0x0244, 1, 0x0824, 0, 0) -MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x062C, 0x0244, 2, 0x07C0, 1, 0) -MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x062C, 0x0244, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x062C, 0x0244, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x062C, 0x0244, 4, 0x0914, 2, 0) -MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x062C, 0x0244, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x062C, 0x0244, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x0630, 0x0248, 0, 0x07DC, 3, 0) -MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x0630, 0x0248, 1, 0x0810, 1, 0) -MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x0630, 0x0248, 2, 0x07C4, 1, 0) -MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x0630, 0x0248, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x0630, 0x0248, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x0630, 0x0248, 4, 0x091C, 2, 0) -MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x0630, 0x0248, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x0630, 0x0248, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x0634, 0x024C, 0, 0x07E8, 2, 0) -MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x0634, 0x024C, 1, 0x0820, 0, 0) -MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x0634, 0x024C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x0634, 0x024C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x0634, 0x024C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x0634, 0x024C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x0634, 0x024C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x0638, 0x0250, 0, 0x07F0, 1, 0) -MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x0638, 0x0250, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x0638, 0x0250, 2, 0x0860, 1, 0) -MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x0638, 0x0250, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0) -MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x0638, 0x0250, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x0638, 0x0250, 6, 0x08F0, 3, 0) -MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x063C, 0x0254, 0, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x063C, 0x0254, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x063C, 0x0254, 2, 0x0920, 1, 0) -MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x063C, 0x0254, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x063C, 0x0254, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x063C, 0x0254, 4, 0x0918, 2, 0) -MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x063C, 0x0254, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x0640, 0x0258, 0, 0x07E0, 3, 0) -MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x0640, 0x0258, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x0640, 0x0258, 2, 0x07B4, 1, 0) -MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x0640, 0x0258, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x0640, 0x0258, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x0640, 0x0258, 4, 0x0914, 3, 0) -MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x0640, 0x0258, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x0640, 0x0258, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x0644, 0x025C, 0, 0x07E4, 3, 0) -MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x0644, 0x025C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x0644, 0x025C, 2, 0x07B0, 1, 0) -MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x0644, 0x025C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x0644, 0x025C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x0644, 0x025C, 4, 0x091C, 3, 0) -MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x0644, 0x025C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x0644, 0x025C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x0648, 0x0260, 0, 0x07EC, 1, 0) -MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x0648, 0x0260, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x0648, 0x0260, 2, 0x07C8, 1, 0) -MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x0648, 0x0260, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x0648, 0x0260, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x0648, 0x0260, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x0648, 0x0260, 6, 0x085C, 1, 0) -MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x064C, 0x0264, 1, 0x0794, 2, 0) -MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x064C, 0x0264, 2, 0x0864, 1, 0) -MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x064C, 0x0264, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0) -MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x064C, 0x0264, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x064C, 0x0264, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x0650, 0x0268, 0, 0x07CC, 0, 0) -MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x0650, 0x0268, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x0650, 0x0268, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x0650, 0x0268, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x0650, 0x0268, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x0650, 0x0268, 4, 0x0918, 3, 0) -MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x0650, 0x0268, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x0654, 0x026C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x0654, 0x026C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x0654, 0x026C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x0658, 0x0270, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x0658, 0x0270, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x065C, 0x0274, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x065C, 0x0274, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x0660, 0x0278, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x0660, 0x0278, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x0660, 0x0278, 2, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x0660, 0x0278, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x0664, 0x027C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x0664, 0x027C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x0664, 0x027C, 2, 0x0844, 1, 0) -MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x0664, 0x027C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x0664, 0x027C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x0664, 0x027C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x0668, 0x0280, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x0668, 0x0280, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x0668, 0x0280, 2, 0x0848, 1, 0) -MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x0668, 0x0280, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x0668, 0x0280, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__I2C4_SDA, 0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0) -MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x066C, 0x0284, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x066C, 0x0284, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x066C, 0x0284, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x0670, 0x0288, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x0670, 0x0288, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x0670, 0x0288, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x0674, 0x028C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x0674, 0x028C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x0674, 0x028C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x0678, 0x0290, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x0678, 0x0290, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x0678, 0x0290, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x067C, 0x0294, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x067C, 0x0294, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x067C, 0x0294, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x0680, 0x0298, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x0680, 0x0298, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x0680, 0x0298, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x0684, 0x029C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x0684, 0x029C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x0684, 0x029C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0688, 0x02A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0688, 0x02A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0688, 0x02A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x068C, 0x02A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x068C, 0x02A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x0690, 0x02A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x0690, 0x02A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL, 0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0) -MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0694, 0x02AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0694, 0x02AC, 1, 0x0818, 1, 0) -MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0694, 0x02AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x0698, 0x02B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x0698, 0x02B0, 1, 0x081C, 1, 0) -MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x0698, 0x02B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x069C, 0x02B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x069C, 0x02B4, 1, 0x0820, 1, 0) -MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x069C, 0x02B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x06A0, 0x02B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x06A0, 0x02B8, 1, 0x0824, 1, 0) -MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x06A4, 0x02BC, 1, 0x0828, 1, 0) -MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) -MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x06A8, 0x02C0, 1, 0x0814, 1, 0) -MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x06B0, 0x02C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP) -MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0) -MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x06C0, 0x02D8, 2, 0x08F4, 1, 0) -MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x06C0, 0x02D8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x06C4, 0x02DC, 0, 0x0928, 1, 0) -MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x06C4, 0x02DC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x06C8, 0x02E0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x06C8, 0x02E0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x06CC, 0x02E4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x06D0, 0x02E8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x06D4, 0x02EC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x06D8, 0x02F0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x06D8, 0x02F0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x06DC, 0x02F4, 0, 0x0930, 1, 0) -MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x06DC, 0x02F4, 2, 0x08C0, 3, 0) -MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x06DC, 0x02F4, 3, 0x07A4, 1, 0) -MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x06E0, 0x02F8, 2, 0x08CC, 2, 0) -MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x06E0, 0x02F8, 3, 0x07A0, 1, 0) -MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x06E4, 0x02FC, 3, 0x0798, 1, 0) -MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x06E4, 0x02FC, 4, 0x08D4, 2, 0) -MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x06E4, 0x02FC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x06E8, 0x0300, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x06E8, 0x0300, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x06E8, 0x0300, 3, 0x07AC, 1, 0) -MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x06E8, 0x0300, 4, 0x08C8, 2, 0) -MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x06E8, 0x0300, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x06EC, 0x0304, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x06EC, 0x0304, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x06EC, 0x0304, 3, 0x079C, 1, 0) -MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x06EC, 0x0304, 4, 0x08D0, 2, 0) -MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x06EC, 0x0304, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x06F0, 0x0308, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x06F0, 0x0308, 2, 0x08C4, 2, 0) -MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x06F0, 0x0308, 3, 0x07A8, 1, 0) -MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x06F0, 0x0308, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06F4, 0x030C, 0, 0x0934, 1, 0) -MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06F4, 0x030C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06F4, 0x030C, 1, 0x0900, 2, 0) -MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06F4, 0x030C, 2, 0x07C8, 2, 0) -MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06F4, 0x030C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06F8, 0x0310, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06F8, 0x0310, 1, 0x0900, 3, 0) -MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06F8, 0x0310, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06F8, 0x0310, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06FC, 0x0314, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06FC, 0x0314, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06FC, 0x0314, 1, 0x08F8, 2, 0) -MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06FC, 0x0314, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06FC, 0x0314, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x0700, 0x0318, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x0700, 0x0318, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x0700, 0x0318, 1, 0x08F8, 3, 0) -MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x0700, 0x0318, 2, 0x07CC, 1, 0) -MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x0700, 0x0318, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x0704, 0x031C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x0704, 0x031C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x0708, 0x0320, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x0708, 0x0320, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x0708, 0x0320, 1, 0x0908, 4, 0) -MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x0708, 0x0320, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x070C, 0x0324, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x070C, 0x0324, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x070C, 0x0324, 1, 0x0904, 4, 0) -MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x070C, 0x0324, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0710, 0x0328, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0710, 0x0328, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0710, 0x0328, 1, 0x0904, 5, 0) -MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0710, 0x0328, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0714, 0x032C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0714, 0x032C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0714, 0x032C, 1, 0x08FC, 2, 0) -MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0714, 0x032C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0718, 0x0330, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0718, 0x0330, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0718, 0x0330, 1, 0x08FC, 3, 0) -MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0718, 0x0330, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x071C, 0x0334, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x071C, 0x0334, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x071C, 0x0334, 1, 0x0908, 5, 0) -MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x071C, 0x0334, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x0720, 0x0338, 0, 0x0938, 1, 0) -MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x0720, 0x0338, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x0720, 0x0338, 2, 0x090C, 2, 0) -MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x0720, 0x0338, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x0724, 0x033C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x0724, 0x033C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x0724, 0x033C, 2, 0x090C, 3, 0) -MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x0724, 0x033C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0728, 0x0340, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0728, 0x0340, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0728, 0x0340, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x072C, 0x0344, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x072C, 0x0344, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x072C, 0x0344, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x0730, 0x0348, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x0730, 0x0348, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0734, 0x034C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0734, 0x034C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0738, 0x0350, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0738, 0x0350, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0738, 0x0350, 2, 0x0904, 6, 0) -MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0738, 0x0350, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x073C, 0x0354, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x073C, 0x0354, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x073C, 0x0354, 2, 0x0900, 4, 0) -MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x073C, 0x0354, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x0740, 0x0358, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x0740, 0x0358, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x0740, 0x0358, 2, 0x0900, 5, 0) -MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x0740, 0x0358, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0744, 0x035C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0744, 0x035C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0744, 0x035C, 2, 0x0904, 7, 0) -MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0744, 0x035C, 5, 0x0000, 0, 0) - -#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h deleted file mode 100644 index 0aa94cffe..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_MX6Q_DDR_H__ -#define __ASM_ARCH_MX6Q_DDR_H__ - -#ifndef CONFIG_MX6Q -#error "wrong CPU" -#endif - -#define MX6_IOM_DRAM_DQM0 0x020e05ac -#define MX6_IOM_DRAM_DQM1 0x020e05b4 -#define MX6_IOM_DRAM_DQM2 0x020e0528 -#define MX6_IOM_DRAM_DQM3 0x020e0520 -#define MX6_IOM_DRAM_DQM4 0x020e0514 -#define MX6_IOM_DRAM_DQM5 0x020e0510 -#define MX6_IOM_DRAM_DQM6 0x020e05bc -#define MX6_IOM_DRAM_DQM7 0x020e05c4 - -#define MX6_IOM_DRAM_CAS 0x020e056c -#define MX6_IOM_DRAM_RAS 0x020e0578 -#define MX6_IOM_DRAM_RESET 0x020e057c -#define MX6_IOM_DRAM_SDCLK_0 0x020e0588 -#define MX6_IOM_DRAM_SDCLK_1 0x020e0594 -#define MX6_IOM_DRAM_SDBA2 0x020e058c -#define MX6_IOM_DRAM_SDCKE0 0x020e0590 -#define MX6_IOM_DRAM_SDCKE1 0x020e0598 -#define MX6_IOM_DRAM_SDODT0 0x020e059c -#define MX6_IOM_DRAM_SDODT1 0x020e05a0 - -#define MX6_IOM_DRAM_SDQS0 0x020e05a8 -#define MX6_IOM_DRAM_SDQS1 0x020e05b0 -#define MX6_IOM_DRAM_SDQS2 0x020e0524 -#define MX6_IOM_DRAM_SDQS3 0x020e051c -#define MX6_IOM_DRAM_SDQS4 0x020e0518 -#define MX6_IOM_DRAM_SDQS5 0x020e050c -#define MX6_IOM_DRAM_SDQS6 0x020e05b8 -#define MX6_IOM_DRAM_SDQS7 0x020e05c0 - -#define MX6_IOM_GRP_B0DS 0x020e0784 -#define MX6_IOM_GRP_B1DS 0x020e0788 -#define MX6_IOM_GRP_B2DS 0x020e0794 -#define MX6_IOM_GRP_B3DS 0x020e079c -#define MX6_IOM_GRP_B4DS 0x020e07a0 -#define MX6_IOM_GRP_B5DS 0x020e07a4 -#define MX6_IOM_GRP_B6DS 0x020e07a8 -#define MX6_IOM_GRP_B7DS 0x020e0748 -#define MX6_IOM_GRP_ADDDS 0x020e074c -#define MX6_IOM_DDRMODE_CTL 0x020e0750 -#define MX6_IOM_GRP_DDRPKE 0x020e0758 -#define MX6_IOM_GRP_DDRMODE 0x020e0774 -#define MX6_IOM_GRP_CTLDS 0x020e078c -#define MX6_IOM_GRP_DDR_TYPE 0x020e0798 - -#endif /*__ASM_ARCH_MX6Q_DDR_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h deleted file mode 100644 index a8456a284..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ /dev/null @@ -1,1036 +0,0 @@ -/* - * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Auto Generate file, please don't edit it - */ - -#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__ -#define __ASM_ARCH_MX6_MX6Q_PINS_H__ - -MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0) -MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0) -MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0) -MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0) -MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0) -MX6_PAD_DECL(SD2_DAT2__KEY_ROW6, 0x0364, 0x0050, 4, 0x08F8, 0, 0) -MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13, 0x0364, 0x0050, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__SD2_DATA0, 0x0368, 0x0054, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO, 0x0368, 0x0054, 1, 0x082C, 0, 0) -MX6_PAD_DECL(SD2_DAT0__AUD4_RXD, 0x0368, 0x0054, 3, 0x07B4, 0, 0) -MX6_PAD_DECL(SD2_DAT0__KEY_ROW7, 0x0368, 0x0054, 4, 0x08FC, 0, 0) -MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15, 0x0368, 0x0054, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT, 0x0368, 0x0054, 6, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA, 0x036C, 0x0058, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK, 0x036C, 0x0058, 2, 0x0918, 0, 0) -MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19, 0x036C, 0x0058, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M, 0x036C, 0x0058, 7, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY, 0x0370, 0x005C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20, 0x0370, 0x005C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG, 0x0374, 0x0060, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21, 0x0374, 0x0060, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA, 0x0378, 0x0064, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22, 0x0378, 0x0064, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE, 0x037C, 0x0068, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23, 0x037C, 0x0068, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA, 0x0380, 0x006C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0, 0) -MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24, 0x0380, 0x006C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY, 0x0384, 0x0070, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD0__RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0, 0) -MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25, 0x0384, 0x0070, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE, 0x0388, 0x0074, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26, 0x0388, 0x0074, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK, 0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0) -MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG, 0x038C, 0x0078, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD1__RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0, 0) -MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27, 0x038C, 0x0078, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA, 0x0390, 0x007C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD2__RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0, 0) -MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28, 0x0390, 0x007C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE, 0x0394, 0x0080, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RD3__RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0, 0) -MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29, 0x0394, 0x0080, 5, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE, 0x0398, 0x0084, 0, 0x0000, 0, 0) -MX6_PAD_DECL(RGMII_RXC__RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0, 0) -MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30, 0x0398, 0x0084, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__EIM_ADDR25, 0x039C, 0x0088, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI4_SS1, 0x039C, 0x0088, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__ECSPI2_RDY, 0x039C, 0x0088, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12, 0x039C, 0x0088, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS, 0x039C, 0x0088, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__GPIO5_IO02, 0x039C, 0x0088, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE, 0x039C, 0x0088, 6, 0x088C, 0, 0) -MX6_PAD_DECL(EIM_EB2__EIM_EB2_B, 0x03A0, 0x008C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0, 0x03A0, 0x008C, 1, 0x0800, 0, 0) -MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19, 0x03A0, 0x008C, 3, 0x08D4, 0, 0) -MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL, 0x03A0, 0x008C, 4, 0x0890, 0, 0) -MX6_PAD_DECL(EIM_EB2__GPIO2_IO30, 0x03A0, 0x008C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB2__I2C2_SCL, 0x03A0, 0x008C, 22, 0x08A0, 0, 0) -MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30, 0x03A0, 0x008C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__EIM_DATA16, 0x03A4, 0x0090, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK, 0x03A4, 0x0090, 1, 0x07F4, 0, 0) -MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05, 0x03A4, 0x0090, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18, 0x03A4, 0x0090, 3, 0x08D0, 0, 0) -MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA, 0x03A4, 0x0090, 4, 0x0894, 0, 0) -MX6_PAD_DECL(EIM_D16__GPIO3_IO16, 0x03A4, 0x0090, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D16__I2C2_SDA, 0x03A4, 0x0090, 22, 0x08A4, 0, 0) -MX6_PAD_DECL(EIM_D17__EIM_DATA17, 0x03A8, 0x0094, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__ECSPI1_MISO, 0x03A8, 0x0094, 1, 0x07F8, 0, 0) -MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06, 0x03A8, 0x0094, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK, 0x03A8, 0x0094, 3, 0x08E0, 0, 0) -MX6_PAD_DECL(EIM_D17__DCIC1_OUT, 0x03A8, 0x0094, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__GPIO3_IO17, 0x03A8, 0x0094, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D17__I2C3_SCL, 0x03A8, 0x0094, 22, 0x08A8, 0, 0) -MX6_PAD_DECL(EIM_D18__EIM_DATA18, 0x03AC, 0x0098, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI, 0x03AC, 0x0098, 1, 0x07FC, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07, 0x03AC, 0x0098, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17, 0x03AC, 0x0098, 3, 0x08CC, 0, 0) -MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS, 0x03AC, 0x0098, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__GPIO3_IO18, 0x03AC, 0x0098, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D18__I2C3_SDA, 0x03AC, 0x0098, 22, 0x08AC, 0, 0) -MX6_PAD_DECL(EIM_D19__EIM_DATA19, 0x03B0, 0x009C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__ECSPI1_SS1, 0x03B0, 0x009C, 1, 0x0804, 0, 0) -MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08, 0x03B0, 0x009C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16, 0x03B0, 0x009C, 3, 0x08C8, 0, 0) -MX6_PAD_DECL(EIM_D19__UART1_CTS_B, 0x03B0, 0x009C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__UART1_RTS_B, 0x03B0, 0x009C, 4, 0x091C, 0, 0) -MX6_PAD_DECL(EIM_D19__GPIO3_IO19, 0x03B0, 0x009C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D19__EPIT1_OUT, 0x03B0, 0x009C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EIM_DATA20, 0x03B4, 0x00A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__ECSPI4_SS0, 0x03B4, 0x00A0, 1, 0x0824, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16, 0x03B4, 0x00A0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15, 0x03B4, 0x00A0, 3, 0x08C4, 0, 0) -MX6_PAD_DECL(EIM_D20__UART1_CTS_B, 0x03B4, 0x00A0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__UART1_RTS_B, 0x03B4, 0x00A0, 4, 0x091C, 1, 0) -MX6_PAD_DECL(EIM_D20__GPIO3_IO20, 0x03B4, 0x00A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D20__EPIT2_OUT, 0x03B4, 0x00A0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__EIM_DATA21, 0x03B8, 0x00A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK, 0x03B8, 0x00A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17, 0x03B8, 0x00A4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11, 0x03B8, 0x00A4, 3, 0x08B4, 0, 0) -MX6_PAD_DECL(EIM_D21__USB_OTG_OC, 0x03B8, 0x00A4, 4, 0x0944, 0, 0) -MX6_PAD_DECL(EIM_D21__GPIO3_IO21, 0x03B8, 0x00A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D21__I2C1_SCL, 0x03B8, 0x00A4, 22, 0x0898, 0, 0) -MX6_PAD_DECL(EIM_D21__SPDIF_IN, 0x03B8, 0x00A4, 7, 0x0914, 0, 0) -MX6_PAD_DECL(EIM_D22__EIM_DATA22, 0x03BC, 0x00A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__ECSPI4_MISO, 0x03BC, 0x00A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01, 0x03BC, 0x00A8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10, 0x03BC, 0x00A8, 3, 0x08B0, 0, 0) -MX6_PAD_DECL(EIM_D22__USB_OTG_PWR, 0x03BC, 0x00A8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__GPIO3_IO22, 0x03BC, 0x00A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D22__SPDIF_OUT, 0x03BC, 0x00A8, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__EIM_DATA23, 0x03C0, 0x00AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS, 0x03C0, 0x00AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_CTS_B, 0x03C0, 0x00AC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__UART3_RTS_B, 0x03C0, 0x00AC, 2, 0x092C, 0, 0) -MX6_PAD_DECL(EIM_D23__UART1_DCD_B, 0x03C0, 0x00AC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN, 0x03C0, 0x00AC, 4, 0x08D8, 0, 0) -MX6_PAD_DECL(EIM_D23__GPIO3_IO23, 0x03C0, 0x00AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02, 0x03C0, 0x00AC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14, 0x03C0, 0x00AC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__EIM_EB3_B, 0x03C4, 0x00B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY, 0x03C4, 0x00B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_CTS_B, 0x03C4, 0x00B0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__UART3_RTS_B, 0x03C4, 0x00B0, 2, 0x092C, 1, 0) -MX6_PAD_DECL(EIM_EB3__UART1_RI_B, 0x03C4, 0x00B0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC, 0x03C4, 0x00B0, 4, 0x08DC, 0, 0) -MX6_PAD_DECL(EIM_EB3__GPIO2_IO31, 0x03C4, 0x00B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03, 0x03C4, 0x00B0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31, 0x03C4, 0x00B0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__EIM_DATA24, 0x03C8, 0x00B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI4_SS2, 0x03C8, 0x00B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_TX_DATA, 0x03C8, 0x00B4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__UART3_RX_DATA, 0x03C8, 0x00B4, 2, 0x0930, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI1_SS2, 0x03C8, 0x00B4, 3, 0x0808, 0, 0) -MX6_PAD_DECL(EIM_D24__ECSPI2_SS2, 0x03C8, 0x00B4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__GPIO3_IO24, 0x03C8, 0x00B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D24__AUD5_RXFS, 0x03C8, 0x00B4, 6, 0x07D8, 0, 0) -MX6_PAD_DECL(EIM_D24__UART1_DTR_B, 0x03C8, 0x00B4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__EIM_DATA25, 0x03CC, 0x00B8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI4_SS3, 0x03CC, 0x00B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_TX_DATA, 0x03CC, 0x00B8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__UART3_RX_DATA, 0x03CC, 0x00B8, 2, 0x0930, 1, 0) -MX6_PAD_DECL(EIM_D25__ECSPI1_SS3, 0x03CC, 0x00B8, 3, 0x080C, 0, 0) -MX6_PAD_DECL(EIM_D25__ECSPI2_SS3, 0x03CC, 0x00B8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__GPIO3_IO25, 0x03CC, 0x00B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D25__AUD5_RXC, 0x03CC, 0x00B8, 6, 0x07D4, 0, 0) -MX6_PAD_DECL(EIM_D25__UART1_DSR_B, 0x03CC, 0x00B8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__EIM_DATA26, 0x03D0, 0x00BC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11, 0x03D0, 0x00BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01, 0x03D0, 0x00BC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14, 0x03D0, 0x00BC, 3, 0x08C0, 0, 0) -MX6_PAD_DECL(EIM_D26__UART2_TX_DATA, 0x03D0, 0x00BC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__UART2_RX_DATA, 0x03D0, 0x00BC, 4, 0x0928, 0, 0) -MX6_PAD_DECL(EIM_D26__GPIO3_IO26, 0x03D0, 0x00BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_SISG2, 0x03D0, 0x00BC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22, 0x03D0, 0x00BC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__EIM_DATA27, 0x03D4, 0x00C0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13, 0x03D4, 0x00C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00, 0x03D4, 0x00C0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13, 0x03D4, 0x00C0, 3, 0x08BC, 0, 0) -MX6_PAD_DECL(EIM_D27__UART2_TX_DATA, 0x03D4, 0x00C0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__UART2_RX_DATA, 0x03D4, 0x00C0, 4, 0x0928, 1, 0) -MX6_PAD_DECL(EIM_D27__GPIO3_IO27, 0x03D4, 0x00C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_SISG3, 0x03D4, 0x00C0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23, 0x03D4, 0x00C0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__EIM_DATA28, 0x03D8, 0x00C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__I2C1_SDA, 0x03D8, 0x00C4, 17, 0x089C, 0, 0) -MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI, 0x03D8, 0x00C4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12, 0x03D8, 0x00C4, 3, 0x08B8, 0, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B, 0x03D8, 0x00C4, 4, 0x0924, 0, 0) -MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B, 0x03D8, 0x00C4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__GPIO3_IO28, 0x03D8, 0x00C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG, 0x03D8, 0x00C4, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13, 0x03D8, 0x00C4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__EIM_DATA29, 0x03DC, 0x00C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15, 0x03DC, 0x00C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__ECSPI4_SS0, 0x03DC, 0x00C8, 2, 0x0824, 1, 0) -MX6_PAD_DECL(EIM_D29__UART2_CTS_B, 0x03DC, 0x00C8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__UART2_RTS_B, 0x03DC, 0x00C8, 4, 0x0924, 1, 0) -MX6_PAD_DECL(EIM_D29__GPIO3_IO29, 0x03DC, 0x00C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC, 0x03DC, 0x00C8, 6, 0x08E4, 0, 0) -MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14, 0x03DC, 0x00C8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__EIM_DATA30, 0x03E0, 0x00CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21, 0x03E0, 0x00CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11, 0x03E0, 0x00CC, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03, 0x03E0, 0x00CC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_CTS_B, 0x03E0, 0x00CC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__UART3_RTS_B, 0x03E0, 0x00CC, 4, 0x092C, 2, 0) -MX6_PAD_DECL(EIM_D30__GPIO3_IO30, 0x03E0, 0x00CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D30__USB_H1_OC, 0x03E0, 0x00CC, 6, 0x0948, 0, 0) -MX6_PAD_DECL(EIM_D31__EIM_DATA31, 0x03E4, 0x00D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20, 0x03E4, 0x00D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12, 0x03E4, 0x00D0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02, 0x03E4, 0x00D0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_CTS_B, 0x03E4, 0x00D0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__UART3_RTS_B, 0x03E4, 0x00D0, 4, 0x092C, 3, 0) -MX6_PAD_DECL(EIM_D31__GPIO3_IO31, 0x03E4, 0x00D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_D31__USB_H1_PWR, 0x03E4, 0x00D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__EIM_ADDR24, 0x03E8, 0x00D4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19, 0x03E8, 0x00D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19, 0x03E8, 0x00D4, 2, 0x08D4, 1, 0) -MX6_PAD_DECL(EIM_A24__IPU2_SISG2, 0x03E8, 0x00D4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__IPU1_SISG2, 0x03E8, 0x00D4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__GPIO5_IO04, 0x03E8, 0x00D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24, 0x03E8, 0x00D4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__EIM_ADDR23, 0x03EC, 0x00D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18, 0x03EC, 0x00D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18, 0x03EC, 0x00D8, 2, 0x08D0, 1, 0) -MX6_PAD_DECL(EIM_A23__IPU2_SISG3, 0x03EC, 0x00D8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__IPU1_SISG3, 0x03EC, 0x00D8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__GPIO6_IO06, 0x03EC, 0x00D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23, 0x03EC, 0x00D8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__EIM_ADDR22, 0x03F0, 0x00DC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17, 0x03F0, 0x00DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17, 0x03F0, 0x00DC, 2, 0x08CC, 1, 0) -MX6_PAD_DECL(EIM_A22__GPIO2_IO16, 0x03F0, 0x00DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22, 0x03F0, 0x00DC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__EIM_ADDR21, 0x03F4, 0x00E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16, 0x03F4, 0x00E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16, 0x03F4, 0x00E0, 2, 0x08C8, 1, 0) -MX6_PAD_DECL(EIM_A21__GPIO2_IO17, 0x03F4, 0x00E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21, 0x03F4, 0x00E0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__EIM_ADDR20, 0x03F8, 0x00E4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15, 0x03F8, 0x00E4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15, 0x03F8, 0x00E4, 2, 0x08C4, 1, 0) -MX6_PAD_DECL(EIM_A20__GPIO2_IO18, 0x03F8, 0x00E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20, 0x03F8, 0x00E4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__EIM_ADDR19, 0x03FC, 0x00E8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14, 0x03FC, 0x00E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14, 0x03FC, 0x00E8, 2, 0x08C0, 1, 0) -MX6_PAD_DECL(EIM_A19__GPIO2_IO19, 0x03FC, 0x00E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19, 0x03FC, 0x00E8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__EIM_ADDR18, 0x0400, 0x00EC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13, 0x0400, 0x00EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13, 0x0400, 0x00EC, 2, 0x08BC, 1, 0) -MX6_PAD_DECL(EIM_A18__GPIO2_IO20, 0x0400, 0x00EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18, 0x0400, 0x00EC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__EIM_ADDR17, 0x0404, 0x00F0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12, 0x0404, 0x00F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12, 0x0404, 0x00F0, 2, 0x08B8, 1, 0) -MX6_PAD_DECL(EIM_A17__GPIO2_IO21, 0x0404, 0x00F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17, 0x0404, 0x00F0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__EIM_ADDR16, 0x0408, 0x00F4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK, 0x0408, 0x00F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK, 0x0408, 0x00F4, 2, 0x08E0, 1, 0) -MX6_PAD_DECL(EIM_A16__GPIO2_IO22, 0x0408, 0x00F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16, 0x0408, 0x00F4, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__EIM_CS0_B, 0x040C, 0x00F8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05, 0x040C, 0x00F8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK, 0x040C, 0x00F8, 2, 0x0810, 0, 0) -MX6_PAD_DECL(EIM_CS0__GPIO2_IO23, 0x040C, 0x00F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__EIM_CS1_B, 0x0410, 0x00FC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06, 0x0410, 0x00FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI, 0x0410, 0x00FC, 2, 0x0818, 0, 0) -MX6_PAD_DECL(EIM_CS1__GPIO2_IO24, 0x0410, 0x00FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__EIM_OE_B, 0x0414, 0x0100, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07, 0x0414, 0x0100, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_OE__ECSPI2_MISO, 0x0414, 0x0100, 2, 0x0814, 0, 0) -MX6_PAD_DECL(EIM_OE__GPIO2_IO25, 0x0414, 0x0100, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08, 0x0418, 0x0104, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__ECSPI2_SS0, 0x0418, 0x0104, 2, 0x081C, 0, 0) -MX6_PAD_DECL(EIM_RW__GPIO2_IO26, 0x0418, 0x0104, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29, 0x0418, 0x0104, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__EIM_LBA_B, 0x041C, 0x0108, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17, 0x041C, 0x0108, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1, 0x041C, 0x0108, 2, 0x0820, 0, 0) -MX6_PAD_DECL(EIM_LBA__GPIO2_IO27, 0x041C, 0x0108, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26, 0x041C, 0x0108, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__EIM_EB0_B, 0x0420, 0x010C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11, 0x0420, 0x010C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11, 0x0420, 0x010C, 2, 0x08B4, 1, 0) -MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY, 0x0420, 0x010C, 4, 0x07F0, 0, 0) -MX6_PAD_DECL(EIM_EB0__GPIO2_IO28, 0x0420, 0x010C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27, 0x0420, 0x010C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__EIM_EB1_B, 0x0424, 0x0110, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10, 0x0424, 0x0110, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10, 0x0424, 0x0110, 2, 0x08B0, 1, 0) -MX6_PAD_DECL(EIM_EB1__GPIO2_IO29, 0x0424, 0x0110, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28, 0x0424, 0x0110, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__EIM_AD00, 0x0428, 0x0114, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09, 0x0428, 0x0114, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09, 0x0428, 0x0114, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__GPIO3_IO00, 0x0428, 0x0114, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00, 0x0428, 0x0114, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__EIM_AD01, 0x042C, 0x0118, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08, 0x042C, 0x0118, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08, 0x042C, 0x0118, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__GPIO3_IO01, 0x042C, 0x0118, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01, 0x042C, 0x0118, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__EIM_AD02, 0x0430, 0x011C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07, 0x0430, 0x011C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07, 0x0430, 0x011C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__GPIO3_IO02, 0x0430, 0x011C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02, 0x0430, 0x011C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__EIM_AD03, 0x0434, 0x0120, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06, 0x0434, 0x0120, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06, 0x0434, 0x0120, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__GPIO3_IO03, 0x0434, 0x0120, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03, 0x0434, 0x0120, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__EIM_AD04, 0x0438, 0x0124, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05, 0x0438, 0x0124, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05, 0x0438, 0x0124, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__GPIO3_IO04, 0x0438, 0x0124, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04, 0x0438, 0x0124, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__EIM_AD05, 0x043C, 0x0128, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04, 0x043C, 0x0128, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04, 0x043C, 0x0128, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__GPIO3_IO05, 0x043C, 0x0128, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05, 0x043C, 0x0128, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__EIM_AD06, 0x0440, 0x012C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03, 0x0440, 0x012C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03, 0x0440, 0x012C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__GPIO3_IO06, 0x0440, 0x012C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06, 0x0440, 0x012C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__EIM_AD07, 0x0444, 0x0130, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02, 0x0444, 0x0130, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02, 0x0444, 0x0130, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__GPIO3_IO07, 0x0444, 0x0130, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07, 0x0444, 0x0130, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__EIM_AD08, 0x0448, 0x0134, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01, 0x0448, 0x0134, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01, 0x0448, 0x0134, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__GPIO3_IO08, 0x0448, 0x0134, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08, 0x0448, 0x0134, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__EIM_AD09, 0x044C, 0x0138, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00, 0x044C, 0x0138, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00, 0x044C, 0x0138, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__GPIO3_IO09, 0x044C, 0x0138, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09, 0x044C, 0x0138, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__EIM_AD10, 0x0450, 0x013C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15, 0x0450, 0x013C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN, 0x0450, 0x013C, 2, 0x08D8, 1, 0) -MX6_PAD_DECL(EIM_DA10__GPIO3_IO10, 0x0450, 0x013C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10, 0x0450, 0x013C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__EIM_AD11, 0x0454, 0x0140, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02, 0x0454, 0x0140, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC, 0x0454, 0x0140, 2, 0x08DC, 1, 0) -MX6_PAD_DECL(EIM_DA11__GPIO3_IO11, 0x0454, 0x0140, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11, 0x0454, 0x0140, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__EIM_AD12, 0x0458, 0x0144, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03, 0x0458, 0x0144, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC, 0x0458, 0x0144, 2, 0x08E4, 1, 0) -MX6_PAD_DECL(EIM_DA12__GPIO3_IO12, 0x0458, 0x0144, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12, 0x0458, 0x0144, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__EIM_AD13, 0x045C, 0x0148, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS, 0x045C, 0x0148, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__GPIO3_IO13, 0x045C, 0x0148, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13, 0x045C, 0x0148, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__EIM_AD14, 0x0460, 0x014C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS, 0x0460, 0x014C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__GPIO3_IO14, 0x0460, 0x014C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14, 0x0460, 0x014C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__EIM_AD15, 0x0464, 0x0150, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01, 0x0464, 0x0150, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04, 0x0464, 0x0150, 2, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__GPIO3_IO15, 0x0464, 0x0150, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15, 0x0464, 0x0150, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B, 0x0468, 0x0154, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B, 0x0468, 0x0154, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00, 0x0468, 0x0154, 5, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25, 0x0468, 0x0154, 7, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16, 0x046C, 0x0158, 1, 0x0000, 0, 0) -MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31, 0x046C, 0x0158, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16, 0x0470, 0x015C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__AUD6_TXC, 0x0474, 0x0160, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17, 0x0474, 0x0160, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02, 0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02, 0x0478, 0x0164, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__AUD6_TXD, 0x0478, 0x0164, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18, 0x0478, 0x0164, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03, 0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03, 0x047C, 0x0168, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS, 0x047C, 0x0168, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19, 0x047C, 0x0168, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04, 0x0480, 0x016C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04, 0x0480, 0x016C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__AUD6_RXD, 0x0480, 0x016C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DI0_PIN4__SD1_WP, 0x0480, 0x016C, 3, 0x094C, 0, 0) -MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20, 0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00, 0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00, 0x0484, 0x0170, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK, 0x0484, 0x0170, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21, 0x0484, 0x0170, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01, 0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01, 0x0488, 0x0174, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x0488, 0x0174, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x0488, 0x0174, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02, 0x048C, 0x0178, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x048C, 0x0178, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x048C, 0x0178, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03, 0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03, 0x0490, 0x017C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0, 0x0490, 0x017C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24, 0x0490, 0x017C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04, 0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04, 0x0494, 0x0180, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1, 0x0494, 0x0180, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25, 0x0494, 0x0180, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05, 0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05, 0x0498, 0x0184, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2, 0x0498, 0x0184, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS, 0x0498, 0x0184, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26, 0x0498, 0x0184, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06, 0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06, 0x049C, 0x0188, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3, 0x049C, 0x0188, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC, 0x049C, 0x0188, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27, 0x049C, 0x0188, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07, 0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07, 0x04A0, 0x018C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY, 0x04A0, 0x018C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28, 0x04A0, 0x018C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08, 0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08, 0x04A4, 0x0190, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT, 0x04A4, 0x0190, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__WDOG1_B, 0x04A4, 0x0190, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29, 0x04A4, 0x0190, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09, 0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09, 0x04A8, 0x0194, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT, 0x04A8, 0x0194, 2, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__WDOG2_B, 0x04A8, 0x0194, 3, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30, 0x04A8, 0x0194, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10, 0x04AC, 0x0198, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x04AC, 0x0198, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11, 0x04B0, 0x019C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05, 0x04B0, 0x019C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12, 0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12, 0x04B4, 0x01A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06, 0x04B4, 0x01A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13, 0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13, 0x04B8, 0x01A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS, 0x04B8, 0x01A4, 3, 0x07D8, 1, 0) -MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07, 0x04B8, 0x01A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14, 0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14, 0x04BC, 0x01A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC, 0x04BC, 0x01A8, 3, 0x07D4, 1, 0) -MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08, 0x04BC, 0x01A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15, 0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15, 0x04C0, 0x01AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1, 0x04C0, 0x01AC, 2, 0x0804, 1, 0) -MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1, 0x04C0, 0x01AC, 3, 0x0820, 1, 0) -MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09, 0x04C0, 0x01AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16, 0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16, 0x04C4, 0x01B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI, 0x04C4, 0x01B0, 2, 0x0818, 1, 0) -MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC, 0x04C4, 0x01B0, 3, 0x07DC, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0, 0x04C4, 0x01B0, 4, 0x090C, 0, 0) -MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10, 0x04C4, 0x01B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17, 0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17, 0x04C8, 0x01B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO, 0x04C8, 0x01B4, 2, 0x0814, 1, 0) -MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD, 0x04C8, 0x01B4, 3, 0x07D0, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1, 0x04C8, 0x01B4, 4, 0x0910, 0, 0) -MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11, 0x04C8, 0x01B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18, 0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18, 0x04CC, 0x01B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0, 0x04CC, 0x01B8, 2, 0x081C, 1, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS, 0x04CC, 0x01B8, 3, 0x07E0, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS, 0x04CC, 0x01B8, 4, 0x07C0, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12, 0x04CC, 0x01B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B, 0x04CC, 0x01B8, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19, 0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19, 0x04D0, 0x01BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK, 0x04D0, 0x01BC, 2, 0x0810, 1, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD, 0x04D0, 0x01BC, 3, 0x07CC, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x04D0, 0x01BC, 4, 0x07BC, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x04D0, 0x01BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x04D0, 0x01BC, 7, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20, 0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20, 0x04D4, 0x01C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK, 0x04D4, 0x01C0, 2, 0x07F4, 1, 0) -MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC, 0x04D4, 0x01C0, 3, 0x07C4, 0, 0) -MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14, 0x04D4, 0x01C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21, 0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21, 0x04D8, 0x01C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI, 0x04D8, 0x01C4, 2, 0x07FC, 1, 0) -MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD, 0x04D8, 0x01C4, 3, 0x07B8, 1, 0) -MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15, 0x04D8, 0x01C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22, 0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22, 0x04DC, 0x01C8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO, 0x04DC, 0x01C8, 2, 0x07F8, 1, 0) -MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS, 0x04DC, 0x01C8, 3, 0x07C8, 1, 0) -MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16, 0x04DC, 0x01C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23, 0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm) -MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23, 0x04E0, 0x01CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0, 0x04E0, 0x01CC, 2, 0x0800, 1, 0) -MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD, 0x04E0, 0x01CC, 3, 0x07B4, 1, 0) -MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17, 0x04E0, 0x01CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK, 0x04E4, 0x01D0, 2, 0x086C, 0, 0) -MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT, 0x04E4, 0x01D0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22, 0x04E4, 0x01D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK, 0x04E4, 0x01D0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK, 0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS, 0x04E8, 0x01D4, 2, 0x085C, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23, 0x04E8, 0x01D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID, 0x04EC, 0x01D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK, 0x04EC, 0x01D8, 2, 0x0864, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN, 0x04EC, 0x01D8, 3, 0x0914, 1, 0) -MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT, 0x04EC, 0x01D8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24, 0x04EC, 0x01D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN, 0x04F0, 0x01DC, 1, 0x0858, 1, 0) -MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK, 0x04F0, 0x01DC, 2, 0x0870, 0, 0) -MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK, 0x04F0, 0x01DC, 3, 0x0918, 1, 0) -MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25, 0x04F0, 0x01DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__MLB_SIG, 0x04F4, 0x01E0, 0, 0x0908, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1, 0x04F4, 0x01E0, 1, 0x084C, 1, 0) -MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS, 0x04F4, 0x01E0, 2, 0x0860, 0, 0) -MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT, 0x04F4, 0x01E0, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26, 0x04F4, 0x01E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0, 0x04F8, 0x01E4, 1, 0x0848, 1, 0) -MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK, 0x04F8, 0x01E4, 2, 0x0868, 0, 0) -MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT, 0x04F8, 0x01E4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27, 0x04F8, 0x01E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2, 0x04FC, 0x01E8, 2, 0x0880, 0, 0) -MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28, 0x04FC, 0x01E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__MLB_CLK, 0x0500, 0x01EC, 0, 0x0900, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1, 0x0500, 0x01EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3, 0x0500, 0x01EC, 2, 0x087C, 0, 0) -MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN, 0x0500, 0x01EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29, 0x0500, 0x01EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0, 0x0504, 0x01F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1, 0x0504, 0x01F0, 2, 0x0884, 0, 0) -MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30, 0x0504, 0x01F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__MLB_DATA, 0x0508, 0x01F4, 0, 0x0904, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0, 0x0508, 0x01F4, 2, 0x0888, 0, 0) -MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN, 0x0508, 0x01F4, 4, 0x0000, 0, 0) -MX6_PAD_DECL(ENET_MDC__GPIO1_IO31, 0x0508, 0x01F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK, 0x05C8, 0x01F8, 0, 0x07F4, 2, 0) -MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3, 0x05C8, 0x01F8, 1, 0x0854, 1, 0) -MX6_PAD_DECL(KEY_COL0__AUD5_TXC, 0x05C8, 0x01F8, 2, 0x07DC, 1, 0) -MX6_PAD_DECL(KEY_COL0__KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA, 0x05C8, 0x01F8, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA, 0x05C8, 0x01F8, 4, 0x0938, 0, 0) -MX6_PAD_DECL(KEY_COL0__GPIO4_IO06, 0x05C8, 0x01F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL0__DCIC1_OUT, 0x05C8, 0x01F8, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI, 0x05CC, 0x01FC, 0, 0x07FC, 2, 0) -MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3, 0x05CC, 0x01FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__AUD5_TXD, 0x05CC, 0x01FC, 2, 0x07D0, 1, 0) -MX6_PAD_DECL(KEY_ROW0__KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA, 0x05CC, 0x01FC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA, 0x05CC, 0x01FC, 4, 0x0938, 1, 0) -MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07, 0x05CC, 0x01FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT, 0x05CC, 0x01FC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO, 0x05D0, 0x0200, 0, 0x07F8, 2, 0) -MX6_PAD_DECL(KEY_COL1__ENET_MDIO, 0x05D0, 0x0200, 1, 0x0840, 1, 0) -MX6_PAD_DECL(KEY_COL1__AUD5_TXFS, 0x05D0, 0x0200, 2, 0x07E0, 1, 0) -MX6_PAD_DECL(KEY_COL1__KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA, 0x05D0, 0x0200, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA, 0x05D0, 0x0200, 4, 0x0940, 0, 0) -MX6_PAD_DECL(KEY_COL1__GPIO4_IO08, 0x05D0, 0x0200, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL1__SD1_VSELECT, 0x05D0, 0x0200, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0, 0x05D4, 0x0204, 0, 0x0800, 2, 0) -MX6_PAD_DECL(KEY_ROW1__ENET_COL, 0x05D4, 0x0204, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__AUD5_RXD, 0x05D4, 0x0204, 2, 0x07CC, 1, 0) -MX6_PAD_DECL(KEY_ROW1__KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA, 0x05D4, 0x0204, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA, 0x05D4, 0x0204, 4, 0x0940, 1, 0) -MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09, 0x05D4, 0x0204, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT, 0x05D4, 0x0204, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1, 0x05D8, 0x0208, 0, 0x0804, 2, 0) -MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2, 0x05D8, 0x0208, 1, 0x0850, 1, 0) -MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX, 0x05D8, 0x0208, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__ENET_MDC, 0x05D8, 0x0208, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__GPIO4_IO10, 0x05D8, 0x0208, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE, 0x05D8, 0x0208, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2, 0x05DC, 0x020C, 0, 0x0808, 1, 0) -MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2, 0x05DC, 0x020C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX, 0x05DC, 0x020C, 2, 0x07E4, 0, 0) -MX6_PAD_DECL(KEY_ROW2__KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT, 0x05DC, 0x020C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11, 0x05DC, 0x020C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE, 0x05DC, 0x020C, 6, 0x088C, 1, 0) -MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3, 0x05E0, 0x0210, 0, 0x080C, 1, 0) -MX6_PAD_DECL(KEY_COL3__ENET_CRS, 0x05E0, 0x0210, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL, 0x05E0, 0x0210, 2, 0x0890, 1, 0) -MX6_PAD_DECL(KEY_COL3__KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__I2C2_SCL, 0x05E0, 0x0210, 20, 0x08A0, 1, 0) -MX6_PAD_DECL(KEY_COL3__GPIO4_IO12, 0x05E0, 0x0210, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL3__SPDIF_IN, 0x05E0, 0x0210, 6, 0x0914, 2, 0) -MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK, 0x05E4, 0x0214, 1, 0x07B0, 0, 0) -MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA, 0x05E4, 0x0214, 2, 0x0894, 1, 0) -MX6_PAD_DECL(KEY_ROW3__KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__I2C2_SDA, 0x05E4, 0x0214, 20, 0x08A4, 1, 0) -MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13, 0x05E4, 0x0214, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT, 0x05E4, 0x0214, 6, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX, 0x05E8, 0x0218, 0, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__IPU1_SISG4, 0x05E8, 0x0218, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__USB_OTG_OC, 0x05E8, 0x0218, 2, 0x0944, 1, 0) -MX6_PAD_DECL(KEY_COL4__KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_CTS_B, 0x05E8, 0x0218, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_COL4__UART5_RTS_B, 0x05E8, 0x0218, 4, 0x093C, 0, 0) -MX6_PAD_DECL(KEY_COL4__GPIO4_IO14, 0x05E8, 0x0218, 5, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX, 0x05EC, 0x021C, 0, 0x07E8, 0, 0) -MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5, 0x05EC, 0x021C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR, 0x05EC, 0x021C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B, 0x05EC, 0x021C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B, 0x05EC, 0x021C, 4, 0x093C, 1, 0) -MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15, 0x05EC, 0x021C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__CCM_CLKO1, 0x05F0, 0x0220, 0, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__KEY_COL5, 0x05F0, 0x0220, 2, 0x08E8, 0, 0) -MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK, 0x05F0, 0x0220, 3, 0x07B0, 1, 0) -MX6_PAD_DECL(GPIO_0__EPIT1_OUT, 0x05F0, 0x0220, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__GPIO1_IO00, 0x05F0, 0x0220, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__USB_H1_PWR, 0x05F0, 0x0220, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_0__SNVS_VIO_5, 0x05F0, 0x0220, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK, 0x05F4, 0x0224, 0, 0x086C, 1, 0) -MX6_PAD_DECL(GPIO_1__WDOG2_B, 0x05F4, 0x0224, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__KEY_ROW5, 0x05F4, 0x0224, 2, 0x08F4, 0, 0) -MX6_PAD_DECL(GPIO_1__USB_OTG_ID, 0x05F4, 0x0224, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__PWM2_OUT, 0x05F4, 0x0224, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__GPIO1_IO01, 0x05F4, 0x0224, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_1__SD1_CD_B, 0x05F4, 0x0224, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__ESAI_RX_FS, 0x05F8, 0x0228, 0, 0x085C, 1, 0) -MX6_PAD_DECL(GPIO_9__WDOG1_B, 0x05F8, 0x0228, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__KEY_COL6, 0x05F8, 0x0228, 2, 0x08EC, 0, 0) -MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B, 0x05F8, 0x0228, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__PWM1_OUT, 0x05F8, 0x0228, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__GPIO1_IO09, 0x05F8, 0x0228, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_9__SD1_WP, 0x05F8, 0x0228, 6, 0x094C, 1, 0) -MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK, 0x05FC, 0x022C, 0, 0x0864, 1, 0) -MX6_PAD_DECL(GPIO_3__I2C3_SCL, 0x05FC, 0x022C, 18, 0x08A8, 1, 0) -MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M, 0x05FC, 0x022C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__CCM_CLKO2, 0x05FC, 0x022C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__GPIO1_IO03, 0x05FC, 0x022C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_3__USB_H1_OC, 0x05FC, 0x022C, 6, 0x0948, 1, 0) -MX6_PAD_DECL(GPIO_3__MLB_CLK, 0x05FC, 0x022C, 7, 0x0900, 1, 0) -MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK, 0x0600, 0x0230, 0, 0x0870, 1, 0) -MX6_PAD_DECL(GPIO_6__I2C3_SDA, 0x0600, 0x0230, 18, 0x08AC, 1, 0) -MX6_PAD_DECL(GPIO_6__GPIO1_IO06, 0x0600, 0x0230, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__SD2_LCTL, 0x0600, 0x0230, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_6__MLB_SIG, 0x0600, 0x0230, 7, 0x0908, 1, 0) -MX6_PAD_DECL(GPIO_2__ESAI_TX_FS, 0x0604, 0x0234, 0, 0x0860, 1, 0) -MX6_PAD_DECL(GPIO_2__KEY_ROW6, 0x0604, 0x0234, 2, 0x08F8, 1, 0) -MX6_PAD_DECL(GPIO_2__GPIO1_IO02, 0x0604, 0x0234, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__SD2_WP, 0x0604, 0x0234, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_2__MLB_DATA, 0x0604, 0x0234, 7, 0x0904, 1, 0) -MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK, 0x0608, 0x0238, 0, 0x0868, 1, 0) -MX6_PAD_DECL(GPIO_4__KEY_COL7, 0x0608, 0x0238, 2, 0x08F0, 1, 0) -MX6_PAD_DECL(GPIO_4__GPIO1_IO04, 0x0608, 0x0238, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_4__SD2_CD_B, 0x0608, 0x0238, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3, 0x060C, 0x023C, 0, 0x087C, 1, 0) -MX6_PAD_DECL(GPIO_5__KEY_ROW7, 0x060C, 0x023C, 2, 0x08FC, 1, 0) -MX6_PAD_DECL(GPIO_5__CCM_CLKO1, 0x060C, 0x023C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__GPIO1_IO05, 0x060C, 0x023C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_5__I2C3_SCL, 0x060C, 0x023C, 22, 0x08A8, 2, 0) -MX6_PAD_DECL(GPIO_5__ARM_EVENTI, 0x060C, 0x023C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1, 0x0610, 0x0240, 0, 0x0884, 1, 0) -MX6_PAD_DECL(GPIO_7__ECSPI5_RDY, 0x0610, 0x0240, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__EPIT1_OUT, 0x0610, 0x0240, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX, 0x0610, 0x0240, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_TX_DATA, 0x0610, 0x0240, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__UART2_RX_DATA, 0x0610, 0x0240, 4, 0x0928, 2, 0) -MX6_PAD_DECL(GPIO_7__GPIO1_IO07, 0x0610, 0x0240, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__SPDIF_LOCK, 0x0610, 0x0240, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE, 0x0610, 0x0240, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0, 0x0614, 0x0244, 0, 0x0888, 1, 0) -MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K, 0x0614, 0x0244, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__EPIT2_OUT, 0x0614, 0x0244, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX, 0x0614, 0x0244, 3, 0x07E4, 1, 0) -MX6_PAD_DECL(GPIO_8__UART2_TX_DATA, 0x0614, 0x0244, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__UART2_RX_DATA, 0x0614, 0x0244, 4, 0x0928, 3, 0) -MX6_PAD_DECL(GPIO_8__GPIO1_IO08, 0x0614, 0x0244, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK, 0x0614, 0x0244, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE, 0x0614, 0x0244, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2, 0x0618, 0x0248, 0, 0x0880, 1, 0) -MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN, 0x0618, 0x0248, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__ENET_REF_CLK, 0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0) -MX6_PAD_DECL(GPIO_16__SD1_LCTL, 0x0618, 0x0248, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__SPDIF_IN, 0x0618, 0x0248, 4, 0x0914, 3, 0) -MX6_PAD_DECL(GPIO_16__GPIO7_IO11, 0x0618, 0x0248, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_16__I2C3_SDA, 0x0618, 0x0248, 22, 0x08AC, 2, 0) -MX6_PAD_DECL(GPIO_16__JTAG_DE_B, 0x0618, 0x0248, 7, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__ESAI_TX0, 0x061C, 0x024C, 0, 0x0874, 0, 0) -MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN, 0x061C, 0x024C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY, 0x061C, 0x024C, 2, 0x07F0, 1, 0) -MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0, 0x061C, 0x024C, 3, 0x090C, 1, 0) -MX6_PAD_DECL(GPIO_17__SPDIF_OUT, 0x061C, 0x024C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_17__GPIO7_IO12, 0x061C, 0x024C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__ESAI_TX1, 0x0620, 0x0250, 0, 0x0878, 0, 0) -MX6_PAD_DECL(GPIO_18__ENET_RX_CLK, 0x0620, 0x0250, 1, 0x0844, 1, 0) -MX6_PAD_DECL(GPIO_18__SD3_VSELECT, 0x0620, 0x0250, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1, 0x0620, 0x0250, 3, 0x0910, 1, 0) -MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK, 0x0620, 0x0250, 4, 0x07B0, 2, 0) -MX6_PAD_DECL(GPIO_18__GPIO7_IO13, 0x0620, 0x0250, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL, 0x0620, 0x0250, 6, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__KEY_COL5, 0x0624, 0x0254, 0, 0x08E8, 1, 0) -MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT, 0x0624, 0x0254, 1, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__SPDIF_OUT, 0x0624, 0x0254, 2, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__CCM_CLKO1, 0x0624, 0x0254, 3, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ECSPI1_RDY, 0x0624, 0x0254, 4, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__GPIO4_IO05, 0x0624, 0x0254, 5, 0x0000, 0, 0) -MX6_PAD_DECL(GPIO_19__ENET_TX_ER, 0x0624, 0x0254, 6, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18, 0x0628, 0x0258, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO, 0x0628, 0x0258, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC, 0x062C, 0x025C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1, 0x062C, 0x025C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19, 0x062C, 0x025C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL, 0x062C, 0x025C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00, 0x0630, 0x0260, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20, 0x0630, 0x0260, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK, 0x0630, 0x0260, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01, 0x0634, 0x0264, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21, 0x0634, 0x0264, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00, 0x0634, 0x0264, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04, 0x0638, 0x0268, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02, 0x0638, 0x0268, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK, 0x0638, 0x0268, 2, 0x07F4, 3, 0) -MX6_PAD_DECL(CSI0_DAT4__KEY_COL5, 0x0638, 0x0268, 3, 0x08E8, 2, 0) -MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC, 0x0638, 0x0268, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22, 0x0638, 0x0268, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01, 0x0638, 0x0268, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05, 0x063C, 0x026C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03, 0x063C, 0x026C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI, 0x063C, 0x026C, 2, 0x07FC, 3, 0) -MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5, 0x063C, 0x026C, 3, 0x08F4, 1, 0) -MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD, 0x063C, 0x026C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23, 0x063C, 0x026C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02, 0x063C, 0x026C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06, 0x0640, 0x0270, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04, 0x0640, 0x0270, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO, 0x0640, 0x0270, 2, 0x07F8, 3, 0) -MX6_PAD_DECL(CSI0_DAT6__KEY_COL6, 0x0640, 0x0270, 3, 0x08EC, 1, 0) -MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS, 0x0640, 0x0270, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24, 0x0640, 0x0270, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03, 0x0640, 0x0270, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07, 0x0644, 0x0274, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05, 0x0644, 0x0274, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0, 0x0644, 0x0274, 2, 0x0800, 3, 0) -MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6, 0x0644, 0x0274, 3, 0x08F8, 2, 0) -MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD, 0x0644, 0x0274, 4, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25, 0x0644, 0x0274, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04, 0x0644, 0x0274, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08, 0x0648, 0x0278, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06, 0x0648, 0x0278, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK, 0x0648, 0x0278, 2, 0x0810, 2, 0) -MX6_PAD_DECL(CSI0_DAT8__KEY_COL7, 0x0648, 0x0278, 3, 0x08F0, 2, 0) -MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA, 0x0648, 0x0278, 20, 0x089C, 1, 0) -MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26, 0x0648, 0x0278, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05, 0x0648, 0x0278, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09, 0x064C, 0x027C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07, 0x064C, 0x027C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI, 0x064C, 0x027C, 2, 0x0818, 2, 0) -MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7, 0x064C, 0x027C, 3, 0x08FC, 2, 0) -MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL, 0x064C, 0x027C, 20, 0x0898, 1, 0) -MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27, 0x064C, 0x027C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06, 0x064C, 0x027C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0650, 0x0280, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0650, 0x0280, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0650, 0x0280, 2, 0x0814, 2, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0650, 0x0280, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0650, 0x0280, 3, 0x0920, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0650, 0x0280, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0650, 0x0280, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0654, 0x0284, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0654, 0x0284, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0654, 0x0284, 2, 0x081C, 2, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA, 0x0654, 0x0284, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA, 0x0654, 0x0284, 3, 0x0920, 1, 0) -MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29, 0x0654, 0x0284, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08, 0x0654, 0x0284, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12, 0x0658, 0x0288, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08, 0x0658, 0x0288, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA, 0x0658, 0x0288, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA, 0x0658, 0x0288, 3, 0x0938, 2, 0) -MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30, 0x0658, 0x0288, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09, 0x0658, 0x0288, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13, 0x065C, 0x028C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09, 0x065C, 0x028C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA, 0x065C, 0x028C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA, 0x065C, 0x028C, 3, 0x0938, 3, 0) -MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31, 0x065C, 0x028C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10, 0x065C, 0x028C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14, 0x0660, 0x0290, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10, 0x0660, 0x0290, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA, 0x0660, 0x0290, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA, 0x0660, 0x0290, 3, 0x0940, 2, 0) -MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00, 0x0660, 0x0290, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11, 0x0660, 0x0290, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15, 0x0664, 0x0294, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11, 0x0664, 0x0294, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA, 0x0664, 0x0294, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA, 0x0664, 0x0294, 3, 0x0940, 3, 0) -MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01, 0x0664, 0x0294, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12, 0x0664, 0x0294, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16, 0x0668, 0x0298, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12, 0x0668, 0x0298, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B, 0x0668, 0x0298, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B, 0x0668, 0x0298, 3, 0x0934, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02, 0x0668, 0x0298, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13, 0x0668, 0x0298, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17, 0x066C, 0x029C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13, 0x066C, 0x029C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B, 0x066C, 0x029C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B, 0x066C, 0x029C, 3, 0x0934, 1, 0) -MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03, 0x066C, 0x029C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14, 0x066C, 0x029C, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18, 0x0670, 0x02A0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14, 0x0670, 0x02A0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B, 0x0670, 0x02A0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B, 0x0670, 0x02A0, 3, 0x093C, 2, 0) -MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04, 0x0670, 0x02A0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15, 0x0670, 0x02A0, 7, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19, 0x0674, 0x02A4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15, 0x0674, 0x02A4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B, 0x0674, 0x02A4, 3, 0x0000, 0, 0) -MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B, 0x0674, 0x02A4, 3, 0x093C, 3, 0) -MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05, 0x0674, 0x02A4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__SD3_DATA7, 0x0690, 0x02A8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA, 0x0690, 0x02A8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA, 0x0690, 0x02A8, 1, 0x0920, 2, 0) -MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17, 0x0690, 0x02A8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__SD3_DATA6, 0x0694, 0x02AC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA, 0x0694, 0x02AC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA, 0x0694, 0x02AC, 1, 0x0920, 3, 0) -MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18, 0x0694, 0x02AC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__SD3_DATA5, 0x0698, 0x02B0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA, 0x0698, 0x02B0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA, 0x0698, 0x02B0, 1, 0x0928, 4, 0) -MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00, 0x0698, 0x02B0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) -MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) -MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__GPIO7_IO02, 0x06A0, 0x02B8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__UART2_CTS_B, 0x06A4, 0x02BC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CLK__UART2_RTS_B, 0x06A4, 0x02BC, 1, 0x0924, 3, 0) -MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX, 0x06A4, 0x02BC, 2, 0x07E4, 2, 0) -MX6_PAD_DECL(SD3_CLK__GPIO7_IO03, 0x06A4, 0x02BC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__SD3_DATA0, 0x06A8, 0x02C0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B, 0x06A8, 0x02C0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B, 0x06A8, 0x02C0, 1, 0x091C, 2, 0) -MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX, 0x06A8, 0x02C0, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04, 0x06A8, 0x02C0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__SD3_DATA1, 0x06AC, 0x02C4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B, 0x06AC, 0x02C4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B, 0x06AC, 0x02C4, 1, 0x091C, 3, 0) -MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX, 0x06AC, 0x02C4, 2, 0x07E8, 1, 0) -MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05, 0x06AC, 0x02C4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__SD3_DATA2, 0x06B0, 0x02C8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06, 0x06B0, 0x02C8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__SD3_DATA3, 0x06B4, 0x02CC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B, 0x06B4, 0x02CC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B, 0x06B4, 0x02CC, 1, 0x092C, 4, 0) -MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07, 0x06B4, 0x02CC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__SD3_RESET, 0x06B8, 0x02D0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_CTS_B, 0x06B8, 0x02D0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_RST__UART3_RTS_B, 0x06B8, 0x02D0, 1, 0x092C, 5, 0) -MX6_PAD_DECL(SD3_RST__GPIO7_IO08, 0x06B8, 0x02D0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__NAND_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4, 0x06BC, 0x02D4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07, 0x06BC, 0x02D4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__NAND_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__SD4_RESET, 0x06C0, 0x02D8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08, 0x06C0, 0x02D8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5, 0x06C4, 0x02DC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09, 0x06C4, 0x02DC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__NAND_READY_B, 0x06C8, 0x02E0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01, 0x06C8, 0x02E0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10, 0x06C8, 0x02E0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B, 0x06CC, 0x02E4, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11, 0x06CC, 0x02E4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B, 0x06D0, 0x02E8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT, 0x06D0, 0x02E8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT, 0x06D0, 0x02E8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14, 0x06D0, 0x02E8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B, 0x06D4, 0x02EC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0, 0x06D4, 0x02EC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__ESAI_TX0, 0x06D4, 0x02EC, 2, 0x0874, 1, 0) -MX6_PAD_DECL(NANDF_CS2__EIM_CRE, 0x06D4, 0x02EC, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2, 0x06D4, 0x02EC, 4, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15, 0x06D4, 0x02EC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0, 0x06D4, 0x02EC, 6, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B, 0x06D8, 0x02F0, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1, 0x06D8, 0x02F0, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) -MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) -MX6_PAD_DECL(SD4_CMD__GPIO7_IO09, 0x06DC, 0x02F4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__NAND_WE_B, 0x06E0, 0x02F8, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA, 0x06E0, 0x02F8, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA, 0x06E0, 0x02F8, 2, 0x0930, 3, 0) -MX6_PAD_DECL(SD4_CLK__GPIO7_IO10, 0x06E0, 0x02F8, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__NAND_DATA00, 0x06E4, 0x02FC, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__SD1_DATA4, 0x06E4, 0x02FC, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D0__GPIO2_IO00, 0x06E4, 0x02FC, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__NAND_DATA01, 0x06E8, 0x0300, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__SD1_DATA5, 0x06E8, 0x0300, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D1__GPIO2_IO01, 0x06E8, 0x0300, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__NAND_DATA02, 0x06EC, 0x0304, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__SD1_DATA6, 0x06EC, 0x0304, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D2__GPIO2_IO02, 0x06EC, 0x0304, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__NAND_DATA03, 0x06F0, 0x0308, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__SD1_DATA7, 0x06F0, 0x0308, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D3__GPIO2_IO03, 0x06F0, 0x0308, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__NAND_DATA04, 0x06F4, 0x030C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__SD2_DATA4, 0x06F4, 0x030C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D4__GPIO2_IO04, 0x06F4, 0x030C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__NAND_DATA05, 0x06F8, 0x0310, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__SD2_DATA5, 0x06F8, 0x0310, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D5__GPIO2_IO05, 0x06F8, 0x0310, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__NAND_DATA06, 0x06FC, 0x0314, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__SD2_DATA6, 0x06FC, 0x0314, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D6__GPIO2_IO06, 0x06FC, 0x0314, 5, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__NAND_DATA07, 0x0700, 0x0318, 0, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__SD2_DATA7, 0x0700, 0x0318, 1, 0x0000, 0, 0) -MX6_PAD_DECL(NANDF_D7__GPIO2_IO07, 0x0700, 0x0318, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__SD4_DATA0, 0x0704, 0x031C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__NAND_DQS, 0x0704, 0x031C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08, 0x0704, 0x031C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__SD4_DATA1, 0x0708, 0x0320, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__PWM3_OUT, 0x0708, 0x0320, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09, 0x0708, 0x0320, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__SD4_DATA2, 0x070C, 0x0324, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__PWM4_OUT, 0x070C, 0x0324, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10, 0x070C, 0x0324, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__SD4_DATA3, 0x0710, 0x0328, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11, 0x0710, 0x0328, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__SD4_DATA4, 0x0714, 0x032C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA, 0x0714, 0x032C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA, 0x0714, 0x032C, 2, 0x0928, 6, 0) -MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12, 0x0714, 0x032C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__SD4_DATA5, 0x0718, 0x0330, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B, 0x0718, 0x0330, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B, 0x0718, 0x0330, 2, 0x0924, 4, 0) -MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13, 0x0718, 0x0330, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__SD4_DATA6, 0x071C, 0x0334, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B, 0x071C, 0x0334, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B, 0x071C, 0x0334, 2, 0x0924, 5, 0) -MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14, 0x071C, 0x0334, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__SD4_DATA7, 0x0720, 0x0338, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA, 0x0720, 0x0338, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA, 0x0720, 0x0338, 2, 0x0928, 7, 0) -MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15, 0x0720, 0x0338, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__SD1_DATA1, 0x0724, 0x033C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0, 0x0724, 0x033C, 1, 0x0834, 1, 0) -MX6_PAD_DECL(SD1_DAT1__PWM3_OUT, 0x0724, 0x033C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2, 0x0724, 0x033C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17, 0x0724, 0x033C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__SD1_DATA0, 0x0728, 0x0340, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO, 0x0728, 0x0340, 1, 0x082C, 1, 0) -MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1, 0x0728, 0x0340, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16, 0x0728, 0x0340, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__SD1_DATA3, 0x072C, 0x0344, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2, 0x072C, 0x0344, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3, 0x072C, 0x0344, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) -MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__GPIO1_IO18, 0x0730, 0x0348, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__SD1_DATA2, 0x0734, 0x034C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1, 0x0734, 0x034C, 1, 0x0838, 1, 0) -MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2, 0x0734, 0x034C, 2, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__PWM2_OUT, 0x0734, 0x034C, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_B, 0x0734, 0x034C, 4, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19, 0x0734, 0x034C, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB, 0x0734, 0x034C, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK, 0x0738, 0x0350, 1, 0x0828, 0, 0) -MX6_PAD_DECL(SD1_CLK__GPT_CLKIN, 0x0738, 0x0350, 3, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CLK__GPIO1_IO20, 0x0738, 0x0350, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CLK__SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) -MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) -MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) -MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) -MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) -MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) -MX6_PAD_DECL(SD2_CMD__GPIO1_IO11, 0x0740, 0x0358, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__SD2_DATA3, 0x0744, 0x035C, 0, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3, 0x0744, 0x035C, 1, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_DAT3__KEY_COL6, 0x0744, 0x035C, 2, 0x08EC, 2, 0) -MX6_PAD_DECL(SD2_DAT3__AUD4_TXC, 0x0744, 0x035C, 3, 0x07C4, 1, 0) -MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12, 0x0744, 0x035C, 5, 0x0000, 0, 0) - -#endif /* __ASM_ARCH_MX6_MX6Q_PINS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h deleted file mode 100644 index 5f9c90ad8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__ -#define __ASM_ARCH_MX6_MX6SL_PINS_H__ - -#include <asm/imx-common/iomux-v3.h> - -enum { - MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), - MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), - MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), - - MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0), - MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0), - MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0), - MX6_PAD_FEC_RXD0__FEC_RX_DATA0 = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0), - MX6_PAD_FEC_RXD1__FEC_RX_DATA1 = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0), - MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0), - MX6_PAD_FEC_TXD0__FEC_TX_DATA0 = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0), - MX6_PAD_FEC_TXD1__FEC_TX_DATA1 = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0), - MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), - MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), - MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), -}; -#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h deleted file mode 100644 index e5e3eff59..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ /dev/null @@ -1,1060 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - */ - -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MXC_HDMI_H__ -#define __MXC_HDMI_H__ - -#ifdef CONFIG_IMX_HDMI -void imx_enable_hdmi_phy(void); -void imx_setup_hdmi(void); -#endif - -/* - * Hdmi controller registers - */ -struct hdmi_regs { - /*Identification Registers */ - u8 design_id; /* 0x000 */ - u8 revision_id; /* 0x001 */ - u8 product_id0; /* 0x002 */ - u8 product_id1; /* 0x003 */ - u8 config0_id; /* 0x004 */ - u8 config1_id; /* 0x005 */ - u8 config2_id; /* 0x006 */ - u8 config3_id; /* 0x007 */ - u8 reserved1[0xf8]; - /* Interrupt Registers */ - u8 ih_fc_stat0; /* 0x100 */ - u8 ih_fc_stat1; /* 0x101 */ - u8 ih_fc_stat2; /* 0x102 */ - u8 ih_as_stat0; /* 0x103 */ - u8 ih_phy_stat0; /* 0x104 */ - u8 ih_i2cm_stat0; /* 0x105 */ - u8 ih_cec_stat0; /* 0x106 */ - u8 ih_vp_stat0; /* 0x107 */ - u8 ih_i2cmphy_stat0; /* 0x108 */ - u8 ih_ahbdmaaud_stat0; /* 0x109 */ - u8 reserved2[0x76]; - u8 ih_mute_fc_stat0; /* 0x180 */ - u8 ih_mute_fc_stat1; /* 0x181 */ - u8 ih_mute_fc_stat2; /* 0x182 */ - u8 ih_mute_as_stat0; /* 0x183 */ - u8 ih_mute_phy_stat0; /* 0x184 */ - u8 ih_mute_i2cm_stat0; /* 0x185 */ - u8 ih_mute_cec_stat0; /* 0x186 */ - u8 ih_mute_vp_stat0; /* 0x187 */ - u8 ih_mute_i2cmphy_stat0; /* 0x188 */ - u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */ - u8 reserved3[0x75]; - u8 ih_mute; /* 0x1ff */ - /* Video Sample Registers */ - u8 tx_invid0; /* 0x200 */ - u8 tx_instuffing; /* 0x201 */ - u8 tx_gydata0; /* 0x202 */ - u8 tx_gydata1; /* 0x203 */ - u8 tx_rcrdata0; /* 0x204 */ - u8 tx_rcrdata1; /* 0x205 */ - u8 tx_bcbdata0; /* 0x206 */ - u8 tx_bcbdata1; /* 0x207 */ - u8 reserved4[0x5f8]; - /* Video Packetizer Registers */ - u8 vp_status; /* 0x800 */ - u8 vp_pr_cd; /* 0x801 */ - u8 vp_stuff; /* 0x802 */ - u8 vp_remap; /* 0x803 */ - u8 vp_conf; /* 0x804 */ - u8 vp_stat; /* 0x805 */ - u8 vp_int; /* 0x806 */ - u8 vp_mask; /* 0x807 */ - u8 vp_pol; /* 0x808 */ - u8 reserved5[0x7f7]; - /* Frame Composer Registers */ - u8 fc_invidconf; /* 0x1000 */ - u8 fc_inhactv0; /* 0x1001 */ - u8 fc_inhactv1; /* 0x1002 */ - u8 fc_inhblank0; /* 0x1003 */ - u8 fc_inhblank1; /* 0x1004 */ - u8 fc_invactv0; /* 0x1005 */ - u8 fc_invactv1; /* 0x1006 */ - u8 fc_invblank; /* 0x1007 */ - u8 fc_hsyncindelay0; /* 0x1008 */ - u8 fc_hsyncindelay1; /* 0x1009 */ - u8 fc_hsyncinwidth0; /* 0x100a */ - u8 fc_hsyncinwidth1; /* 0x100b */ - u8 fc_vsyncindelay; /* 0x100c */ - u8 fc_vsyncinwidth; /* 0x100d */ - u8 fc_infreq0; /* 0x100e */ - u8 fc_infreq1; /* 0x100f */ - u8 fc_infreq2; /* 0x1010 */ - u8 fc_ctrldur; /* 0x1011 */ - u8 fc_exctrldur; /* 0x1012 */ - u8 fc_exctrlspac; /* 0x1013 */ - u8 fc_ch0pream; /* 0x1014 */ - u8 fc_ch1pream; /* 0x1015 */ - u8 fc_ch2pream; /* 0x1016 */ - u8 fc_aviconf3; /* 0x1017 */ - u8 fc_gcp; /* 0x1018 */ - u8 fc_aviconf0; /* 0x1019 */ - u8 fc_aviconf1; /* 0x101a */ - u8 fc_aviconf2; /* 0x101b */ - u8 fc_avivid; /* 0x101c */ - u8 fc_avietb0; /* 0x101d */ - u8 fc_avietb1; /* 0x101e */ - u8 fc_avisbb0; /* 0x101f */ - u8 fc_avisbb1; /* 0x1020 */ - u8 fc_avielb0; /* 0x1021 */ - u8 fc_avielb1; /* 0x1022 */ - u8 fc_avisrb0; /* 0x1023 */ - u8 fc_avisrb1; /* 0x1024 */ - u8 fc_audiconf0; /* 0x1025 */ - u8 fc_audiconf1; /* 0x1026 */ - u8 fc_audiconf2; /* 0x1027 */ - u8 fc_audiconf3; /* 0x1028 */ - u8 fc_vsdieeeid0; /* 0x1029 */ - u8 fc_vsdsize; /* 0x102a */ - u8 reserved6[5]; - u8 fc_vsdieeeid1; /* 0x1030 */ - u8 fc_vsdieeeid2; /* 0x1031 */ - u8 fc_vsdpayload0; /* 0x1032 */ - u8 fc_vsdpayload1; /* 0x1033 */ - u8 fc_vsdpayload2; /* 0x1034 */ - u8 fc_vsdpayload3; /* 0x1035 */ - u8 fc_vsdpayload4; /* 0x1036 */ - u8 fc_vsdpayload5; /* 0x1037 */ - u8 fc_vsdpayload6; /* 0x1038 */ - u8 fc_vsdpayload7; /* 0x1039 */ - u8 fc_vsdpayload8; /* 0x103a */ - u8 fc_vsdpayload9; /* 0x103b */ - u8 fc_vsdpayload10; /* 0x103c */ - u8 fc_vsdpayload11; /* 0x103d */ - u8 fc_vsdpayload12; /* 0x103e */ - u8 fc_vsdpayload13; /* 0x103f */ - u8 fc_vsdpayload14; /* 0x1040 */ - u8 fc_vsdpayload15; /* 0x1041 */ - u8 fc_vsdpayload16; /* 0x1042 */ - u8 fc_vsdpayload17; /* 0x1043 */ - u8 fc_vsdpayload18; /* 0x1044 */ - u8 fc_vsdpayload19; /* 0x1045 */ - u8 fc_vsdpayload20; /* 0x1046 */ - u8 fc_vsdpayload21; /* 0x1047 */ - u8 fc_vsdpayload22; /* 0x1048 */ - u8 fc_vsdpayload23; /* 0x1049 */ - u8 fc_spdvendorname0; /* 0x104a */ - u8 fc_spdvendorname1; /* 0x104b */ - u8 fc_spdvendorname2; /* 0x104c */ - u8 fc_spdvendorname3; /* 0x104d */ - u8 fc_spdvendorname4; /* 0x104e */ - u8 fc_spdvendorname5; /* 0x104f */ - u8 fc_spdvendorname6; /* 0x1050 */ - u8 fc_spdvendorname7; /* 0x1051 */ - u8 fc_sdpproductname0; /* 0x1052 */ - u8 fc_sdpproductname1; /* 0x1053 */ - u8 fc_sdpproductname2; /* 0x1054 */ - u8 fc_sdpproductname3; /* 0x1055 */ - u8 fc_sdpproductname4; /* 0x1056 */ - u8 fc_sdpproductname5; /* 0x1057 */ - u8 fc_sdpproductname6; /* 0x1058 */ - u8 fc_sdpproductname7; /* 0x1059 */ - u8 fc_sdpproductname8; /* 0x105a */ - u8 fc_sdpproductname9; /* 0x105b */ - u8 fc_sdpproductname10; /* 0x105c */ - u8 fc_sdpproductname11; /* 0x105d */ - u8 fc_sdpproductname12; /* 0x105e */ - u8 fc_sdpproductname13; /* 0x105f */ - u8 fc_sdpproductname14; /* 0x1060 */ - u8 fc_spdproductname15; /* 0x1061 */ - u8 fc_spddeviceinf; /* 0x1062 */ - u8 fc_audsconf; /* 0x1063 */ - u8 fc_audsstat; /* 0x1064 */ - u8 reserved7[0xb]; - u8 fc_datach0fill; /* 0x1070 */ - u8 fc_datach1fill; /* 0x1071 */ - u8 fc_datach2fill; /* 0x1072 */ - u8 fc_ctrlqhigh; /* 0x1073 */ - u8 fc_ctrlqlow; /* 0x1074 */ - u8 fc_acp0; /* 0x1075 */ - u8 fc_acp28; /* 0x1076 */ - u8 fc_acp27; /* 0x1077 */ - u8 fc_acp26; /* 0x1078 */ - u8 fc_acp25; /* 0x1079 */ - u8 fc_acp24; /* 0x107a */ - u8 fc_acp23; /* 0x107b */ - u8 fc_acp22; /* 0x107c */ - u8 fc_acp21; /* 0x107d */ - u8 fc_acp20; /* 0x107e */ - u8 fc_acp19; /* 0x107f */ - u8 fc_acp18; /* 0x1080 */ - u8 fc_acp17; /* 0x1081 */ - u8 fc_acp16; /* 0x1082 */ - u8 fc_acp15; /* 0x1083 */ - u8 fc_acp14; /* 0x1084 */ - u8 fc_acp13; /* 0x1085 */ - u8 fc_acp12; /* 0x1086 */ - u8 fc_acp11; /* 0x1087 */ - u8 fc_acp10; /* 0x1088 */ - u8 fc_acp9; /* 0x1089 */ - u8 fc_acp8; /* 0x108a */ - u8 fc_acp7; /* 0x108b */ - u8 fc_acp6; /* 0x108c */ - u8 fc_acp5; /* 0x108d */ - u8 fc_acp4; /* 0x108e */ - u8 fc_acp3; /* 0x108f */ - u8 fc_acp2; /* 0x1090 */ - u8 fc_acp1; /* 0x1091 */ - u8 fc_iscr1_0; /* 0x1092 */ - u8 fc_iscr1_16; /* 0x1093 */ - u8 fc_iscr1_15; /* 0x1094 */ - u8 fc_iscr1_14; /* 0x1095 */ - u8 fc_iscr1_13; /* 0x1096 */ - u8 fc_iscr1_12; /* 0x1097 */ - u8 fc_iscr1_11; /* 0x1098 */ - u8 fc_iscr1_10; /* 0x1099 */ - u8 fc_iscr1_9; /* 0x109a */ - u8 fc_iscr1_8; /* 0x109b */ - u8 fc_iscr1_7; /* 0x109c */ - u8 fc_iscr1_6; /* 0x109d */ - u8 fc_iscr1_5; /* 0x109e */ - u8 fc_iscr1_4; /* 0x109f */ - u8 fc_iscr1_3; /* 0x10a0 */ - u8 fc_iscr1_2; /* 0x10a1 */ - u8 fc_iscr1_1; /* 0x10a2 */ - u8 fc_iscr2_15; /* 0x10a3 */ - u8 fc_iscr2_14; /* 0x10a4 */ - u8 fc_iscr2_13; /* 0x10a5 */ - u8 fc_iscr2_12; /* 0x10a6 */ - u8 fc_iscr2_11; /* 0x10a7 */ - u8 fc_iscr2_10; /* 0x10a8 */ - u8 fc_iscr2_9; /* 0x10a9 */ - u8 fc_iscr2_8; /* 0x10aa */ - u8 fc_iscr2_7; /* 0x10ab */ - u8 fc_iscr2_6; /* 0x10ac */ - u8 fc_iscr2_5; /* 0x10ad */ - u8 fc_iscr2_4; /* 0x10ae */ - u8 fc_iscr2_3; /* 0x10af */ - u8 fc_iscr2_2; /* 0x10b0 */ - u8 fc_iscr2_1; /* 0x10b1 */ - u8 fc_iscr2_0; /* 0x10b2 */ - u8 fc_datauto0; /* 0x10b3 */ - u8 fc_datauto1; /* 0x10b4 */ - u8 fc_datauto2; /* 0x10b5 */ - u8 fc_datman; /* 0x10b6 */ - u8 fc_datauto3; /* 0x10b7 */ - u8 fc_rdrb0; /* 0x10b8 */ - u8 fc_rdrb1; /* 0x10b9 */ - u8 fc_rdrb2; /* 0x10ba */ - u8 fc_rdrb3; /* 0x10bb */ - u8 fc_rdrb4; /* 0x10bc */ - u8 fc_rdrb5; /* 0x10bd */ - u8 fc_rdrb6; /* 0x10be */ - u8 fc_rdrb7; /* 0x10bf */ - u8 reserved8[0x10]; - u8 fc_stat0; /* 0x10d0 */ - u8 fc_int0; /* 0x10d1 */ - u8 fc_mask0; /* 0x10d2 */ - u8 fc_pol0; /* 0x10d3 */ - u8 fc_stat1; /* 0x10d4 */ - u8 fc_int1; /* 0x10d5 */ - u8 fc_mask1; /* 0x10d6 */ - u8 fc_pol1; /* 0x10d7 */ - u8 fc_stat2; /* 0x10d8 */ - u8 fc_int2; /* 0x10d9 */ - u8 fc_mask2; /* 0x10da */ - u8 fc_pol2; /* 0x10db */ - u8 reserved9[0x4]; - u8 fc_prconf; /* 0x10e0 */ - u8 reserved10[0x1f]; - u8 fc_gmd_stat; /* 0x1100 */ - u8 fc_gmd_en; /* 0x1101 */ - u8 fc_gmd_up; /* 0x1102 */ - u8 fc_gmd_conf; /* 0x1103 */ - u8 fc_gmd_hb; /* 0x1104 */ - u8 fc_gmd_pb0; /* 0x1105 */ - u8 fc_gmd_pb1; /* 0x1106 */ - u8 fc_gmd_pb2; /* 0x1107 */ - u8 fc_gmd_pb3; /* 0x1108 */ - u8 fc_gmd_pb4; /* 0x1109 */ - u8 fc_gmd_pb5; /* 0x110a */ - u8 fc_gmd_pb6; /* 0x110b */ - u8 fc_gmd_pb7; /* 0x110c */ - u8 fc_gmd_pb8; /* 0x110d */ - u8 fc_gmd_pb9; /* 0x110e */ - u8 fc_gmd_pb10; /* 0x110f */ - u8 fc_gmd_pb11; /* 0x1110 */ - u8 fc_gmd_pb12; /* 0x1111 */ - u8 fc_gmd_pb13; /* 0x1112 */ - u8 fc_gmd_pb14; /* 0x1113 */ - u8 fc_gmd_pb15; /* 0x1114 */ - u8 fc_gmd_pb16; /* 0x1115 */ - u8 fc_gmd_pb17; /* 0x1116 */ - u8 fc_gmd_pb18; /* 0x1117 */ - u8 fc_gmd_pb19; /* 0x1118 */ - u8 fc_gmd_pb20; /* 0x1119 */ - u8 fc_gmd_pb21; /* 0x111a */ - u8 fc_gmd_pb22; /* 0x111b */ - u8 fc_gmd_pb23; /* 0x111c */ - u8 fc_gmd_pb24; /* 0x111d */ - u8 fc_gmd_pb25; /* 0x111e */ - u8 fc_gmd_pb26; /* 0x111f */ - u8 fc_gmd_pb27; /* 0x1120 */ - u8 reserved11[0xdf]; - u8 fc_dbgforce; /* 0x1200 */ - u8 fc_dbgaud0ch0; /* 0x1201 */ - u8 fc_dbgaud1ch0; /* 0x1202 */ - u8 fc_dbgaud2ch0; /* 0x1203 */ - u8 fc_dbgaud0ch1; /* 0x1204 */ - u8 fc_dbgaud1ch1; /* 0x1205 */ - u8 fc_dbgaud2ch1; /* 0x1206 */ - u8 fc_dbgaud0ch2; /* 0x1207 */ - u8 fc_dbgaud1ch2; /* 0x1208 */ - u8 fc_dbgaud2ch2; /* 0x1209 */ - u8 fc_dbgaud0ch3; /* 0x120a */ - u8 fc_dbgaud1ch3; /* 0x120b */ - u8 fc_dbgaud2ch3; /* 0x120c */ - u8 fc_dbgaud0ch4; /* 0x120d */ - u8 fc_dbgaud1ch4; /* 0x120e */ - u8 fc_dbgaud2ch4; /* 0x120f */ - u8 fc_dbgaud0ch5; /* 0x1210 */ - u8 fc_dbgaud1ch5; /* 0x1211 */ - u8 fc_dbgaud2ch5; /* 0x1212 */ - u8 fc_dbgaud0ch6; /* 0x1213 */ - u8 fc_dbgaud1ch6; /* 0x1214 */ - u8 fc_dbgaud2ch6; /* 0x1215 */ - u8 fc_dbgaud0ch7; /* 0x1216 */ - u8 fc_dbgaud1ch7; /* 0x1217 */ - u8 fc_dbgaud2ch7; /* 0x1218 */ - u8 fc_dbgtmds0; /* 0x1219 */ - u8 fc_dbgtmds1; /* 0x121a */ - u8 fc_dbgtmds2; /* 0x121b */ - u8 reserved12[0x1de4]; - /* Hdmi Source Phy Registers */ - u8 phy_conf0; /* 0x3000 */ - u8 phy_tst0; /* 0x3001 */ - u8 phy_tst1; /* 0x3002 */ - u8 phy_tst2; /* 0x3003 */ - u8 phy_stat0; /* 0x3004 */ - u8 phy_int0; /* 0x3005 */ - u8 phy_mask0; /* 0x3006 */ - u8 phy_pol0; /* 0x3007 */ - u8 reserved13[0x18]; - /* Hdmi Master Phy Registers */ - u8 phy_i2cm_slave_addr; /* 0x3020 */ - u8 phy_i2cm_address_addr; /* 0x3021 */ - u8 phy_i2cm_datao_1_addr; /* 0x3022 */ - u8 phy_i2cm_datao_0_addr; /* 0x3023 */ - u8 phy_i2cm_datai_1_addr; /* 0x3024 */ - u8 phy_i2cm_datai_0_addr; /* 0x3025 */ - u8 phy_i2cm_operation_addr; /* 0x3026 */ - u8 phy_i2cm_int_addr; /* 0x3027 */ - u8 phy_i2cm_ctlint_addr; /* 0x3028 */ - u8 phy_i2cm_div_addr; /* 0x3029 */ - u8 phy_i2cm_softrstz_addr; /* 0x302a */ - u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */ - u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */ - u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */ - u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */ - u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */ - u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */ - u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */ - u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */ - u8 reserved14[0xcd]; - /* Audio Sampler Registers */ - u8 aud_conf0; /* 0x3100 */ - u8 aud_conf1; /* 0x3101 */ - u8 aud_int; /* 0x3102 */ - u8 aud_conf2; /* 0x3103 */ - u8 reserved15[0xfc]; - u8 aud_n1; /* 0x3200 */ - u8 aud_n2; /* 0x3201 */ - u8 aud_n3; /* 0x3202 */ - u8 aud_cts1; /* 0x3203 */ - u8 aud_cts2; /* 0x3204 */ - u8 aud_cts3; /* 0x3205 */ - u8 aud_inputclkfs; /* 0x3206 */ - u8 reserved16[0xfb]; - u8 aud_spdifint; /* 0x3302 */ - u8 reserved17[0xfd]; - u8 aud_conf0_hbr; /* 0x3400 */ - u8 aud_hbr_status; /* 0x3401 */ - u8 aud_hbr_int; /* 0x3402 */ - u8 aud_hbr_pol; /* 0x3403 */ - u8 aud_hbr_mask; /* 0x3404 */ - u8 reserved18[0xfb]; - /* - * Generic Parallel Audio Interface Registers - * Not used as GPAUD interface is not enabled in hw - */ - u8 gp_conf0; /* 0x3500 */ - u8 gp_conf1; /* 0x3501 */ - u8 gp_conf2; /* 0x3502 */ - u8 gp_stat; /* 0x3503 */ - u8 gp_int; /* 0x3504 */ - u8 gp_mask; /* 0x3505 */ - u8 gp_pol; /* 0x3506 */ - u8 reserved19[0xf9]; - /* Audio DMA Registers */ - u8 ahb_dma_conf0; /* 0x3600 */ - u8 ahb_dma_start; /* 0x3601 */ - u8 ahb_dma_stop; /* 0x3602 */ - u8 ahb_dma_thrsld; /* 0x3603 */ - u8 ahb_dma_straddr0; /* 0x3604 */ - u8 ahb_dma_straddr1; /* 0x3605 */ - u8 ahb_dma_straddr2; /* 0x3606 */ - u8 ahb_dma_straddr3; /* 0x3607 */ - u8 ahb_dma_stpaddr0; /* 0x3608 */ - u8 ahb_dma_stpaddr1; /* 0x3609 */ - u8 ahb_dma_stpaddr2; /* 0x360a */ - u8 ahb_dma_stpaddr3; /* 0x360b */ - u8 ahb_dma_bstaddr0; /* 0x360c */ - u8 ahb_dma_bstaddr1; /* 0x360d */ - u8 ahb_dma_bstaddr2; /* 0x360e */ - u8 ahb_dma_bstaddr3; /* 0x360f */ - u8 ahb_dma_mblength0; /* 0x3610 */ - u8 ahb_dma_mblength1; /* 0x3611 */ - u8 ahb_dma_stat; /* 0x3612 */ - u8 ahb_dma_int; /* 0x3613 */ - u8 ahb_dma_mask; /* 0x3614 */ - u8 ahb_dma_pol; /* 0x3615 */ - u8 ahb_dma_conf1; /* 0x3616 */ - u8 ahb_dma_buffstat; /* 0x3617 */ - u8 ahb_dma_buffint; /* 0x3618 */ - u8 ahb_dma_buffmask; /* 0x3619 */ - u8 ahb_dma_buffpol; /* 0x361a */ - u8 reserved20[0x9e5]; - /* Main Controller Registers */ - u8 mc_sfrdiv; /* 0x4000 */ - u8 mc_clkdis; /* 0x4001 */ - u8 mc_swrstz; /* 0x4002 */ - u8 mc_opctrl; /* 0x4003 */ - u8 mc_flowctrl; /* 0x4004 */ - u8 mc_phyrstz; /* 0x4005 */ - u8 mc_lockonclock; /* 0x4006 */ - u8 mc_heacphy_rst; /* 0x4007 */ - u8 reserved21[0xf8]; - /* Colorspace Converter Registers */ - u8 csc_cfg; /* 0x4100 */ - u8 csc_scale; /* 0x4101 */ - u8 csc_coef_a1_msb; /* 0x4102 */ - u8 csc_coef_a1_lsb; /* 0x4103 */ - u8 csc_coef_a2_msb; /* 0x4104 */ - u8 csc_coef_a2_lsb; /* 0x4105 */ - u8 csc_coef_a3_msb; /* 0x4106 */ - u8 csc_coef_a3_lsb; /* 0x4107 */ - u8 csc_coef_a4_msb; /* 0x4108 */ - u8 csc_coef_a4_lsb; /* 0x4109 */ - u8 csc_coef_b1_msb; /* 0x410a */ - u8 csc_coef_b1_lsb; /* 0x410b */ - u8 csc_coef_b2_msb; /* 0x410c */ - u8 csc_coef_b2_lsb; /* 0x410d */ - u8 csc_coef_b3_msb; /* 0x410e */ - u8 csc_coef_b3_lsb; /* 0x410f */ - u8 csc_coef_b4_msb; /* 0x4110 */ - u8 csc_coef_b4_lsb; /* 0x4111 */ - u8 csc_coef_c1_msb; /* 0x4112 */ - u8 csc_coef_c1_lsb; /* 0x4113 */ - u8 csc_coef_c2_msb; /* 0x4114 */ - u8 csc_coef_c2_lsb; /* 0x4115 */ - u8 csc_coef_c3_msb; /* 0x4116 */ - u8 csc_coef_c3_lsb; /* 0x4117 */ - u8 csc_coef_c4_msb; /* 0x4118 */ - u8 csc_coef_c4_lsb; /* 0x4119 */ - u8 reserved22[0xee6]; - /* HDCP Encryption Engine Registers */ - u8 a_hdcpcfg0; /* 0x5000 */ - u8 a_hdcpcfg1; /* 0x5001 */ - u8 a_hdcpobs0; /* 0x5002 */ - u8 a_hdcpobs1; /* 0x5003 */ - u8 a_hdcpobs2; /* 0x5004 */ - u8 a_hdcpobs3; /* 0x5005 */ - u8 a_apiintclr; /* 0x5006 */ - u8 a_apiintstat; /* 0x5007 */ - u8 a_apiintmsk; /* 0x5008 */ - u8 a_vidpolcfg; /* 0x5009 */ - u8 a_oesswcfg; /* 0x500a */ - u8 a_timer1setup0; /* 0x500b */ - u8 a_timer1setup1; /* 0x500c */ - u8 a_timer2setup0; /* 0x500d */ - u8 a_timer2setup1; /* 0x500e */ - u8 a_100mscfg; /* 0x500f */ - u8 a_2scfg0; /* 0x5010 */ - u8 a_2scfg1; /* 0x5011 */ - u8 a_5scfg0; /* 0x5012 */ - u8 a_5scfg1; /* 0x5013 */ - u8 a_srmverlsb; /* 0x5014 */ - u8 a_srmvermsb; /* 0x5015 */ - u8 a_srmctrl; /* 0x5016 */ - u8 a_sfrsetup; /* 0x5017 */ - u8 a_i2chsetup; /* 0x5018 */ - u8 a_intsetup; /* 0x5019 */ - u8 a_presetup; /* 0x501a */ - u8 reserved23[0x5]; - u8 a_srm_base; /* 0x5020 */ - u8 reserved24[0x2cdf]; - /* CEC Engine Registers */ - u8 cec_ctrl; /* 0x7d00 */ - u8 cec_stat; /* 0x7d01 */ - u8 cec_mask; /* 0x7d02 */ - u8 cec_polarity; /* 0x7d03 */ - u8 cec_int; /* 0x7d04 */ - u8 cec_addr_l; /* 0x7d05 */ - u8 cec_addr_h; /* 0x7d06 */ - u8 cec_tx_cnt; /* 0x7d07 */ - u8 cec_rx_cnt; /* 0x7d08 */ - u8 reserved25[0x7]; - u8 cec_tx_data0; /* 0x7d10 */ - u8 cec_tx_data1; /* 0x7d11 */ - u8 cec_tx_data2; /* 0x7d12 */ - u8 cec_tx_data3; /* 0x7d13 */ - u8 cec_tx_data4; /* 0x7d14 */ - u8 cec_tx_data5; /* 0x7d15 */ - u8 cec_tx_data6; /* 0x7d16 */ - u8 cec_tx_data7; /* 0x7d17 */ - u8 cec_tx_data8; /* 0x7d18 */ - u8 cec_tx_data9; /* 0x7d19 */ - u8 cec_tx_data10; /* 0x7d1a */ - u8 cec_tx_data11; /* 0x7d1b */ - u8 cec_tx_data12; /* 0x7d1c */ - u8 cec_tx_data13; /* 0x7d1d */ - u8 cec_tx_data14; /* 0x7d1e */ - u8 cec_tx_data15; /* 0x7d1f */ - u8 cec_rx_data0; /* 0x7d20 */ - u8 cec_rx_data1; /* 0x7d21 */ - u8 cec_rx_data2; /* 0x7d22 */ - u8 cec_rx_data3; /* 0x7d23 */ - u8 cec_rx_data4; /* 0x7d24 */ - u8 cec_rx_data5; /* 0x7d25 */ - u8 cec_rx_data6; /* 0x7d26 */ - u8 cec_rx_data7; /* 0x7d27 */ - u8 cec_rx_data8; /* 0x7d28 */ - u8 cec_rx_data9; /* 0x7d29 */ - u8 cec_rx_data10; /* 0x7d2a */ - u8 cec_rx_data11; /* 0x7d2b */ - u8 cec_rx_data12; /* 0x7d2c */ - u8 cec_rx_data13; /* 0x7d2d */ - u8 cec_rx_data14; /* 0x7d2e */ - u8 cec_rx_data15; /* 0x7d2f */ - u8 cec_lock; /* 0x7d30 */ - u8 cec_wkupctrl; /* 0x7d31 */ - u8 reserved26[0xce]; - /* I2C Master Registers (E-DDC) */ - u8 i2cm_slave; /* 0x7e00 */ - u8 i2cmess; /* 0x7e01 */ - u8 i2cm_datao; /* 0x7e02 */ - u8 i2cm_datai; /* 0x7e03 */ - u8 i2cm_operation; /* 0x7e04 */ - u8 i2cm_int; /* 0x7e05 */ - u8 i2cm_ctlint; /* 0x7e06 */ - u8 i2cm_div; /* 0x7e07 */ - u8 i2cm_segaddr; /* 0x7e08 */ - u8 i2cm_softrstz; /* 0x7e09 */ - u8 i2cm_segptr; /* 0x7e0a */ - u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */ - u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */ - u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */ - u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */ - u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */ - u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */ - u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */ - u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */ - u8 reserved27[0x1ed]; - /* Random Number Generator Registers (RNG) */ - u8 rng_base; /* 0x8000 */ -}; - -/* - * Register field definitions - */ -enum { -/* IH_FC_INT2 field values */ - HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, - HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_FC_STAT2 field values */ - HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_PHY_STAT0 field values */ - HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, - HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, - HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, - HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, - HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, - HDMI_IH_PHY_STAT0_HPD = 0x1, - -/* IH_MUTE_I2CMPHY_STAT0 field values */ - HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, - HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, - -/* IH_AHBDMAAUD_STAT0 field values */ - HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, - HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, - HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, - HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, - HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, - HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, - -/* IH_MUTE_FC_STAT2 field values */ - HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_MUTE_AHBDMAAUD_STAT0 field values */ - HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, - -/* IH_MUTE field values */ - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, - -/* TX_INVID0 field values */ - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, - HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, - HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, - -/* TX_INSTUFFING field values */ - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, - -/* VP_PR_CD field values */ - HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, - HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, - -/* VP_STUFF field values */ - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, - HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, - HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, - HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, - HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, - HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, - HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, - HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, - HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, - HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, - HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, - -/* VP_CONF field values */ - HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, - HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, - HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, - HDMI_VP_CONF_PP_EN_ENMASK = 0x20, - HDMI_VP_CONF_PP_EN_ENABLE = 0x20, - HDMI_VP_CONF_PP_EN_DISABLE = 0x00, - HDMI_VP_CONF_PR_EN_MASK = 0x10, - HDMI_VP_CONF_PR_EN_ENABLE = 0x10, - HDMI_VP_CONF_PR_EN_DISABLE = 0x00, - HDMI_VP_CONF_YCC422_EN_MASK = 0x8, - HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, - HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, - HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, - HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, - HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, - -/* VP_REMAP field values */ - HDMI_VP_REMAP_MASK = 0x3, - HDMI_VP_REMAP_YCC422_24bit = 0x2, - HDMI_VP_REMAP_YCC422_20bit = 0x1, - HDMI_VP_REMAP_YCC422_16bit = 0x0, - -/* FC_INVIDCONF field values */ - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, - HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, - -/* FC_AUDICONF0 field values */ - HDMI_FC_AUDICONF0_CC_OFFSET = 4, - HDMI_FC_AUDICONF0_CC_MASK = 0x70, - HDMI_FC_AUDICONF0_CT_OFFSET = 0, - HDMI_FC_AUDICONF0_CT_MASK = 0xF, - -/* FC_AUDICONF1 field values */ - HDMI_FC_AUDICONF1_SS_OFFSET = 3, - HDMI_FC_AUDICONF1_SS_MASK = 0x18, - HDMI_FC_AUDICONF1_SF_OFFSET = 0, - HDMI_FC_AUDICONF1_SF_MASK = 0x7, - -/* FC_AUDICONF3 field values */ - HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, - HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, - HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, - HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, - HDMI_FC_AUDICONF3_LSV_OFFSET = 0, - HDMI_FC_AUDICONF3_LSV_MASK = 0xF, - -/* FC_AUDSCHNLS0 field values */ - HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, - HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, - HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, - HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, - -/* FC_AUDSCHNLS3-6 field values */ - HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, - HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, - HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, - HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, - HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, - HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, - HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, - HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, - - HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, - HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, - HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, - HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, - HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, - HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, - HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, - HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, - -/* HDMI_FC_AUDSCHNLS7 field values */ - HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, - HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, - -/* HDMI_FC_AUDSCHNLS8 field values */ - HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, - HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, - HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, - HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, - -/* FC_AUDSCONF field values */ - HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, - HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, - -/* FC_STAT2 field values */ - HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_INT2 field values */ - HDMI_FC_INT2_OVERFLOW_MASK = 0x03, - HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_MASK2 field values */ - HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, - HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_PRCONF field values */ - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, - -/* FC_AVICONF0-FC_AVICONF3 field values */ - HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, - HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, - HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, - HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, - HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, - HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, - HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, - HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, - HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, - HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, - - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, - HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, - HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, - HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, - HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, - HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, - - HDMI_FC_AVICONF2_SCALING_MASK = 0x03, - HDMI_FC_AVICONF2_SCALING_NONE = 0x00, - HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, - HDMI_FC_AVICONF2_SCALING_VERT = 0x02, - HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, - HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, - HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, - HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, - HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, - HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, - HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, - HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, - - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, - HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, - HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, - -/* FC_DBGFORCE field values */ - HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, - HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, - -/* PHY_CONF0 field values */ - HDMI_PHY_CONF0_PDZ_MASK = 0x80, - HDMI_PHY_CONF0_PDZ_OFFSET = 7, - HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, - HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, - HDMI_PHY_CONF0_SPARECTRL = 0x20, - HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, - HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, - HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, - HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, - HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, - HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, - HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, - -/* PHY_TST0 field values */ - HDMI_PHY_TST0_TSTCLR_MASK = 0x20, - HDMI_PHY_TST0_TSTCLR_OFFSET = 5, - HDMI_PHY_TST0_TSTEN_MASK = 0x10, - HDMI_PHY_TST0_TSTEN_OFFSET = 4, - HDMI_PHY_TST0_TSTCLK_MASK = 0x1, - HDMI_PHY_TST0_TSTCLK_OFFSET = 0, - -/* PHY_STAT0 field values */ - HDMI_PHY_RX_SENSE3 = 0x80, - HDMI_PHY_RX_SENSE2 = 0x40, - HDMI_PHY_RX_SENSE1 = 0x20, - HDMI_PHY_RX_SENSE0 = 0x10, - HDMI_PHY_HPD = 0x02, - HDMI_PHY_TX_PHY_LOCK = 0x01, - -/* Convenience macro RX_SENSE | HPD */ - HDMI_DVI_STAT = 0xF2, - -/* PHY_I2CM_SLAVE_ADDR field values */ - HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, - HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, - -/* PHY_I2CM_OPERATION_ADDR field values */ - HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, - HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, - -/* HDMI_PHY_I2CM_INT_ADDR */ - HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, - HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, - -/* HDMI_PHY_I2CM_CTLINT_ADDR */ - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, - -/* AUD_CTS3 field values */ - HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, - HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, - HDMI_AUD_CTS3_N_SHIFT_1 = 0, - HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, - HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, - HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, - HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, - HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, - /* note that the CTS3 MANUAL bit has been removed - from our part. Can't set it, will read as 0. */ - HDMI_AUD_CTS3_CTS_MANUAL = 0x10, - HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, - -/* AHB_DMA_CONF0 field values */ - HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, - HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, - HDMI_AHB_DMA_CONF0_HBR = 0x10, - HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, - HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, - HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, - HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, - HDMI_AHB_DMA_CONF0_INCR4 = 0x0, - HDMI_AHB_DMA_CONF0_INCR8 = 0x2, - HDMI_AHB_DMA_CONF0_INCR16 = 0x4, - HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, - -/* HDMI_AHB_DMA_START field values */ - HDMI_AHB_DMA_START_START_OFFSET = 0, - HDMI_AHB_DMA_START_START_MASK = 0x01, - -/* HDMI_AHB_DMA_STOP field values */ - HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, - HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, - -/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ - HDMI_AHB_DMA_DONE = 0x80, - HDMI_AHB_DMA_RETRY_SPLIT = 0x40, - HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, - HDMI_AHB_DMA_ERROR = 0x10, - HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, - HDMI_AHB_DMA_FIFO_FULL = 0x02, - HDMI_AHB_DMA_FIFO_EMPTY = 0x01, - -/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */ - HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, - HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, - -/* MC_CLKDIS field values */ - HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, - HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, - HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, - HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, - HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, - -/* MC_SWRSTZ field values */ - HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, - -/* MC_FLOWCTRL field values */ - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, - -/* MC_PHYRSTZ field values */ - HDMI_MC_PHYRSTZ_ASSERT = 0x0, - HDMI_MC_PHYRSTZ_DEASSERT = 0x1, - -/* MC_HEACPHY_RST field values */ - HDMI_MC_HEACPHY_RST_ASSERT = 0x1, - HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, - -/* CSC_CFG field values */ - HDMI_CSC_CFG_INTMODE_MASK = 0x30, - HDMI_CSC_CFG_INTMODE_OFFSET = 4, - HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, - HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, - HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, - HDMI_CSC_CFG_DECMODE_MASK = 0x3, - HDMI_CSC_CFG_DECMODE_OFFSET = 0, - HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, - -/* CSC_SCALE field values */ - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, - HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, - -/* A_HDCPCFG0 field values */ - HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, - HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, - HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, - HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, - HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, - HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, - HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, - HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, - HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, - HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, - HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, - HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, - HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, - HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, - HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, - HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, - HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, - HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, - HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, - HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, - HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, - HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, - HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, - HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, - -/* A_HDCPCFG1 field values */ - HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, - HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, - HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, - HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, - HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, - -/* A_VIDPOLCFG field values */ - HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, - HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, - HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, - HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, - HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, - HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, - HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, - HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, - HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, - HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, - HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, -}; - -#endif /* __MXC_HDMI_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h deleted file mode 100644 index 38851a135..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/imx-common/regs-common.h> -#include "../arch-imx/cpu.h" - -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) -u32 get_cpu_rev(void); - -/* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12)&0xff) - -/* use with MXC_CPU_ constants */ -#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu) - -const char *get_imx_type(u32 imxtype); -unsigned imx_ddr_size(void); - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ - -int fecmxc_initialize(bd_t *bis); -u32 get_ahb_clk(void); -u32 get_periph_clk(void); - -int mxs_reset_block(struct mxs_register_32 *reg); -int mxs_wait_mask_set(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); -int mxs_wait_mask_clr(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h deleted file mode 100644 index fc9d75b50..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 Clock - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CLOCK_H__ -#define __CLOCK_H__ - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_EMI_CLK, - MXC_GPMI_CLK, - MXC_IO0_CLK, - MXC_IO1_CLK, - MXC_XTAL_CLK, - MXC_SSP0_CLK, -#ifdef CONFIG_MX28 - MXC_SSP1_CLK, - MXC_SSP2_CLK, - MXC_SSP3_CLK, -#endif -}; - -enum mxs_ioclock { - MXC_IOCLK0 = 0, - MXC_IOCLK1, -}; - -enum mxs_sspclock { - MXC_SSPCLK0 = 0, -#ifdef CONFIG_MX28 - MXC_SSPCLK1, - MXC_SSPCLK2, - MXC_SSPCLK3, -#endif -}; - -uint32_t mxc_get_clock(enum mxc_clock clk); - -void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq); -void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); -void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq); -void mxs_set_lcdclk(uint32_t freq); - -/* Compatibility with the FEC Ethernet driver */ -#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) - -#endif /* __CLOCK_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h deleted file mode 100644 index 3bdf879b1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Freescale i.MX28 GPIO - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_GPIO_H__ -#define __MX28_GPIO_H__ - -#ifdef CONFIG_MXS_GPIO -void mxs_gpio_init(void); -#else -inline void mxs_gpio_init(void) {} -#endif - -#endif /* __MX28_GPIO_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h deleted file mode 100644 index 86914ef74..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 Registers - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IMX_REGS_H__ -#define __IMX_REGS_H__ - -#include <asm/imx-common/regs-apbh.h> -#include <asm/arch/regs-base.h> -#include <asm/imx-common/regs-bch.h> -#include <asm/arch/regs-digctl.h> -#include <asm/imx-common/regs-gpmi.h> -#include <asm/arch/regs-i2c.h> -#include <asm/arch/regs-lcdif.h> -#include <asm/arch/regs-lradc.h> -#include <asm/arch/regs-ocotp.h> -#include <asm/arch/regs-pinctrl.h> -#include <asm/arch/regs-rtc.h> -#include <asm/arch/regs-ssp.h> -#include <asm/arch/regs-timrot.h> -#include <asm/arch/regs-usb.h> -#include <asm/arch/regs-usbphy.h> - -#ifdef CONFIG_MX23 -#include <asm/arch/regs-clkctrl-mx23.h> -#include <asm/arch/regs-power-mx23.h> -#endif - -#ifdef CONFIG_MX28 -#include <asm/arch/regs-clkctrl-mx28.h> -#include <asm/arch/regs-power-mx28.h> -#endif - -#endif /* __IMX_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h deleted file mode 100644 index 7cb5e7168..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) - -#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) - -#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) - -#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) - -#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) - -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) - -#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) - -#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h deleted file mode 100644 index b42820de7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX28_H__ -#define __MACH_IOMUX_MX28_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) - -#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) - -#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) - -#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) -#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) -#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) -#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) - -#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) - -#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) - -#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) -#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) -#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) -#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) -#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) - -#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) - -#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) -#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) -#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) - -#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) -#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) -#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) -#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) -#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) - -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) - -#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) - -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) - -#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) - -#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h deleted file mode 100644 index 3d1149130..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_MXS_IOMUX_H__ -#define __MACH_MXS_IOMUX_H__ - -#ifndef __ASSEMBLY__ - -#include <asm/types.h> - -/* - * IOMUX/PAD Bit field definitions - * - * PAD_BANK: 0..2 (3) - * PAD_PIN: 3..7 (5) - * PAD_MUXSEL: 8..9 (2) - * PAD_MA: 10..11 (2) - * PAD_MA_VALID: 12 (1) - * PAD_VOL: 13 (1) - * PAD_VOL_VALID: 14 (1) - * PAD_PULL: 15 (1) - * PAD_PULL_VALID: 16 (1) - * RESERVED: 17..31 (15) - */ -typedef u32 iomux_cfg_t; - -#define MXS_PAD_BANK_SHIFT 0 -#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) -#define MXS_PAD_PIN_SHIFT 3 -#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) -#define MXS_PAD_MUXSEL_SHIFT 8 -#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) -#define MXS_PAD_MA_SHIFT 10 -#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) -#define MXS_PAD_MA_VALID_SHIFT 12 -#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) -#define MXS_PAD_VOL_SHIFT 13 -#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) -#define MXS_PAD_VOL_VALID_SHIFT 14 -#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) -#define MXS_PAD_PULL_SHIFT 15 -#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) -#define MXS_PAD_PULL_VALID_SHIFT 16 -#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) - -#define PAD_MUXSEL_0 0 -#define PAD_MUXSEL_1 1 -#define PAD_MUXSEL_2 2 -#define PAD_MUXSEL_GPIO 3 - -#define PAD_4MA 0 -#define PAD_8MA 1 -#define PAD_12MA 2 -#define PAD_16MA 3 - -#define PAD_1V8 0 -#if defined(CONFIG_MX28) -#define PAD_3V3 1 -#else -#define PAD_3V3 0 -#endif - -#define PAD_NOPULL 0 -#define PAD_PULLUP 1 - -#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) - -#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) -#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) - -#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) -#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) - -/* generic pad control used in most cases */ -#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) - -#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ - (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ - ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ - ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ - ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ - ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ - ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) - -/* - * A pad becomes naked, when none of mA, vol or pull - * validity bits is set. - */ -#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ - MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) - -static inline unsigned int PAD_BANK(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; -} - -static inline unsigned int PAD_PIN(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; -} - -static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; -} - -static inline unsigned int PAD_MA(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; -} - -static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; -} - -static inline unsigned int PAD_VOL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; -} - -static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; -} - -static inline unsigned int PAD_PULL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; -} - -static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; -} - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad); - -/* - * configures multiple pads - * convenient way to call the above function with tables - */ -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); - -#endif /* __ASSEMBLY__ */ -#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h deleted file mode 100644 index 213df514b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 Peripheral Base Addresses - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MXS_REGS_BASE_H__ -#define __MXS_REGS_BASE_H__ - -/* - * Register base addresses for i.MX23 - */ -#if defined(CONFIG_MX23) -#define MXS_ICOLL_BASE 0x80000000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_ECC8_BASE 0x80008000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_ETM_BASE 0x80014000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_EMI_BASE 0x80020000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_TVENC_BASE 0x80038000 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_AUDIOOUT_BASE 0x80048000 -#define MXS_AUDIOIN_BASE 0x8004C000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_RTC_BASE 0x8005C000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006C000 -#define MXS_UARTAPP1_BASE 0x8006E000 -#define MXS_UARTDBG_BASE 0x80070000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_DRAM_BASE 0x800E0000 - -/* - * Register base addresses for i.MX28 - */ -#elif defined(CONFIG_MX28) -#define MXS_ICOL_BASE 0x80000000 -#define MXS_HSADC_BASE 0x80002000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_PERFMON_BASE 0x80006000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80012000 -#define MXS_SSP2_BASE 0x80014000 -#define MXS_SSP3_BASE 0x80016000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_ETM_BASE 0x80022000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_AHB0_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_CAN0_BASE 0x80032000 -#define MXS_CAN1_BASE 0x80034000 -#define MXS_SIMDBG_BASE 0x8003C000 -#define MXS_SIMGPMISEL_BASE 0x8003C200 -#define MXS_SIMSSPSEL_BASE 0x8003C300 -#define MXS_SIMMEMSEL_BASE 0x8003C400 -#define MXS_GPIOMON_BASE 0x8003C500 -#define MXS_SIMENET_BASE 0x8003C700 -#define MXS_ARMJTAG_BASE 0x8003C800 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_RTC_BASE 0x80056000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_I2C1_BASE 0x8005A000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006A000 -#define MXS_UARTAPP1_BASE 0x8006C000 -#define MXS_UARTAPP2_BASE 0x8006E000 -#define MXS_UARTAPP3_BASE 0x80070000 -#define MXS_UARTAPP4_BASE 0x80072000 -#define MXS_UARTDBG_BASE 0x80074000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBPHY1_BASE 0x8007E000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_USBCTRL1_BASE 0x80090000 -#define MXS_DFLPT_BASE 0x800C0000 -#define MXS_DRAM_BASE 0x800E0000 -#define MXS_ENET0_BASE 0x800F0000 -#define MXS_ENET1_BASE 0x800F4000 -#else -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 -#endif - -#endif /* __MXS_REGS_BASE_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h deleted file mode 100644 index d155e3a5d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Freescale i.MX23 CLKCTRL Register Definitions - * - * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX23_REGS_CLKCTRL_H__ -#define __MX23_REGS_CLKCTRL_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ - mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ - - uint32_t reserved1[4]; - - mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */ - mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x120 */ - mxs_reg_32(hw_clkctrl_status) /* 0x130 */ - mxs_reg_32(hw_clkctrl_version) /* 0x140 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_BUSY (1 << 29) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) -#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_PIX_CLKGATE (1 << 31) -#define CLKCTRL_PIX_BUSY (1 << 29) -#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) -#define CLKCTRL_PIX_DIV_MASK 0xfff -#define CLKCTRL_PIX_DIV_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_IR_CLKGATE (1 << 31) -#define CLKCTRL_IR_AUTO_DIV (1 << 29) -#define CLKCTRL_IR_IR_BUSY (1 << 28) -#define CLKCTRL_IR_IROV_BUSY (1 << 27) -#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) -#define CLKCTRL_IR_IROV_DIV_OFFSET 16 -#define CLKCTRL_IR_IR_DIV_MASK 0x3ff -#define CLKCTRL_IR_IR_DIV_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) -#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) -#define CLKCTRL_ETM_DIV_MASK 0x3f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_PIX 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_VID 3 - -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) - -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h deleted file mode 100644 index 1490ffd52..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Freescale i.MX28 CLKCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_CLKCTRL_H__ -#define __MX28_REGS_CLKCTRL_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ - uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ - mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ - mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ - mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ - - uint32_t reserved[16]; - - mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mxs_reg_32(hw_clkctrl_version) /* 0x200 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) -#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) -#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) -#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_SAIF1_CLKGATE (1 << 31) -#define CLKCTRL_SAIF1_BUSY (1 << 29) -#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF1_DIV_MASK 0xffff -#define CLKCTRL_SAIF1_DIV_OFFSET 0 - -#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) -#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) -#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) -#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff -#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) -#define CLKCTRL_ETM_DIV_MASK 0x7f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_ENET_SLEEP (1 << 31) -#define CLKCTRL_ENET_DISABLE (1 << 30) -#define CLKCTRL_ENET_STATUS (1 << 29) -#define CLKCTRL_ENET_BUSY_TIME (1 << 27) -#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) -#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 -#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) -#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 -#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) -#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) -#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) -#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) -#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) -#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) -#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) - -#define CLKCTRL_HSADC_RESETB (1 << 30) -#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) -#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 - -#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) -#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) -#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) -#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_IO1 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_PIX 0 -#define CLKCTRL_FRAC1_HSADC 1 -#define CLKCTRL_FRAC1_GPMI 2 - -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) - -#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) -#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) -#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) -#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h deleted file mode 100644 index 860be9e28..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Freescale i.MX28 DIGCTL Register Definitions - * - * Copyright (C) 2012 Robert Delien <robert@delien.nl> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_DIGCTL_H__ -#define __MX28_REGS_DIGCTL_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_digctl_regs { - mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ - mxs_reg_32(hw_digctl_status) /* 0x010 */ - mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ - mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ - mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ - mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ - uint32_t hw_digctl_writeonce; /* 0x060 */ - uint32_t reserved_writeonce[3]; - mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ - mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ - uint32_t hw_digctl_entropy; /* 0x090 */ - uint32_t reserved_entropy[3]; - uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ - uint32_t reserved_entropy_latched[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ - uint32_t hw_digctl_dbgrd; /* 0x0d0 */ - uint32_t reserved_hw_digctl_dbgrd[3]; - uint32_t hw_digctl_dbg; /* 0x0e0 */ - uint32_t reserved_hw_digctl_dbg[3]; - - uint32_t reserved2[4]; - - mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ - mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ - mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ - mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ - mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ - mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ - mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ - mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ - mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ - mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ - mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ - mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ - mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ - mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ - mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ - - uint32_t reserved3[36]; - - uint32_t hw_digctl_scratch0; /* 0x280 */ - uint32_t reserved_hw_digctl_scratch0[3]; - uint32_t hw_digctl_scratch1; /* 0x290 */ - uint32_t reserved_hw_digctl_scratch1[3]; - uint32_t hw_digctl_armcache; /* 0x2a0 */ - uint32_t reserved_hw_digctl_armcache[3]; - mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ - uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; - uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; - uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; - uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; - uint32_t hw_digctl_fsl; /* 0x300 */ - uint32_t reserved_hw_digctl_fsl[3]; - uint32_t hw_digctl_chipid; /* 0x310 */ - uint32_t reserved_hw_digctl_chipid[3]; - - uint32_t reserved4[4]; - - uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ - uint32_t reserved_hw_digctl_ahb_stats_select[3]; - - uint32_t reserved5[12]; - - uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ - uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; - uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ - uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; - uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ - uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; - uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ - uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; - uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; - uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; - uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ - uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; - uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; - uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; - - uint32_t reserved6[64]; - - uint32_t hw_digctl_mpte0_loc; /* 0x500 */ - uint32_t reserved_hw_digctl_mpte0_loc[3]; - uint32_t hw_digctl_mpte1_loc; /* 0x510 */ - uint32_t reserved_hw_digctl_mpte1_loc[3]; - uint32_t hw_digctl_mpte2_loc; /* 0x520 */ - uint32_t reserved_hw_digctl_mpte2_loc[3]; - uint32_t hw_digctl_mpte3_loc; /* 0x530 */ - uint32_t reserved_hw_digctl_mpte3_loc[3]; - uint32_t hw_digctl_mpte4_loc; /* 0x540 */ - uint32_t reserved_hw_digctl_mpte4_loc[3]; - uint32_t hw_digctl_mpte5_loc; /* 0x550 */ - uint32_t reserved_hw_digctl_mpte5_loc[3]; - uint32_t hw_digctl_mpte6_loc; /* 0x560 */ - uint32_t reserved_hw_digctl_mpte6_loc[3]; - uint32_t hw_digctl_mpte7_loc; /* 0x570 */ - uint32_t reserved_hw_digctl_mpte7_loc[3]; - uint32_t hw_digctl_mpte8_loc; /* 0x580 */ - uint32_t reserved_hw_digctl_mpte8_loc[3]; - uint32_t hw_digctl_mpte9_loc; /* 0x590 */ - uint32_t reserved_hw_digctl_mpte9_loc[3]; - uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ - uint32_t reserved_hw_digctl_mpte10_loc[3]; - uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ - uint32_t reserved_hw_digctl_mpte11_loc[3]; - uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ - uint32_t reserved_hw_digctl_mpte12_loc[3]; - uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ - uint32_t reserved_hw_digctl_mpte13_loc[3]; - uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ - uint32_t reserved_hw_digctl_mpte14_loc[3]; - uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ - uint32_t reserved_hw_digctl_mpte15_loc[3]; -}; -#endif - -/* Product code identification */ -#define HW_DIGCTL_CHIPID_MASK (0xffff << 16) -#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) -#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) - -#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h deleted file mode 100644 index a58303efb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Freescale i.MX28 I2C Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_I2C_H__ -#define __MX28_REGS_I2C_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_i2c_regs { - mxs_reg_32(hw_i2c_ctrl0) - mxs_reg_32(hw_i2c_timing0) - mxs_reg_32(hw_i2c_timing1) - mxs_reg_32(hw_i2c_timing2) - mxs_reg_32(hw_i2c_ctrl1) - mxs_reg_32(hw_i2c_stat) - mxs_reg_32(hw_i2c_queuectrl) - mxs_reg_32(hw_i2c_queuestat) - mxs_reg_32(hw_i2c_queuecmd) - mxs_reg_32(hw_i2c_queuedata) - mxs_reg_32(hw_i2c_data) - mxs_reg_32(hw_i2c_debug0) - mxs_reg_32(hw_i2c_debug1) - mxs_reg_32(hw_i2c_version) -}; -#endif - -#define I2C_CTRL_SFTRST (1 << 31) -#define I2C_CTRL_CLKGATE (1 << 30) -#define I2C_CTRL_RUN (1 << 29) -#define I2C_CTRL_PREACK (1 << 27) -#define I2C_CTRL_ACKNOWLEDGE (1 << 26) -#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) -#define I2C_CTRL_MULTI_MASTER (1 << 23) -#define I2C_CTRL_CLOCK_HELD (1 << 22) -#define I2C_CTRL_RETAIN_CLOCK (1 << 21) -#define I2C_CTRL_POST_SEND_STOP (1 << 20) -#define I2C_CTRL_PRE_SEND_START (1 << 19) -#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_CTRL_MASTER_MODE (1 << 17) -#define I2C_CTRL_DIRECTION (1 << 16) -#define I2C_CTRL_XFER_COUNT_MASK 0xffff -#define I2C_CTRL_XFER_COUNT_OFFSET 0 - -#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 -#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff -#define I2C_TIMING0_RCV_COUNT_OFFSET 0 - -#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING1_LOW_COUNT_OFFSET 16 -#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff -#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 - -#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) -#define I2C_TIMING2_BUS_FREE_OFFSET 16 -#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff -#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 - -#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) -#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) -#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) -#define I2C_CTRL1_ACK_MODE (1 << 27) -#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) -#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) -#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 -#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) -#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) -#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) -#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) -#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) -#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) -#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) -#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) -#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) -#define I2C_CTRL1_SLAVE_IRQ (1 << 0) - -#define I2C_STAT_MASTER_PRESENT (1 << 31) -#define I2C_STAT_SLAVE_PRESENT (1 << 30) -#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) -#define I2C_STAT_GOT_A_NAK (1 << 28) -#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) -#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 -#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) -#define I2C_STAT_SLAVE_FOUND (1 << 14) -#define I2C_STAT_SLAVE_SEARCHING (1 << 13) -#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) -#define I2C_STAT_BUS_BUSY (1 << 11) -#define I2C_STAT_CLK_GEN_BUSY (1 << 10) -#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) -#define I2C_STAT_SLAVE_BUSY (1 << 8) -#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) -#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) -#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) -#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) -#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) -#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) -#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) -#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) - -#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) -#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 -#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) -#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 -#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) -#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) -#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) -#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) -#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) -#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) - -#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) -#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 -#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) -#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) -#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f -#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 - -#define I2C_QUEUECMD_PREACK (1 << 27) -#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) -#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) -#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) -#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) -#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) -#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) -#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) -#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_QUEUECMD_MASTER_MODE (1 << 17) -#define I2C_QUEUECMD_DIRECTION (1 << 16) -#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff -#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 - -#define I2C_QUEUEDATA_DATA_MASK 0xffffffff -#define I2C_QUEUEDATA_DATA_OFFSET 0 - -#define I2C_DATA_DATA_MASK 0xffffffff -#define I2C_DATA_DATA_OFFSET 0 - -#define I2C_DEBUG0_DMAREQ (1 << 31) -#define I2C_DEBUG0_DMAENDCMD (1 << 30) -#define I2C_DEBUG0_DMAKICK (1 << 29) -#define I2C_DEBUG0_DMATERMINATE (1 << 28) -#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) -#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 -#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) -#define I2C_DEBUG0_DMA_STATE_OFFSET 16 -#define I2C_DEBUG0_START_TOGGLE (1 << 15) -#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) -#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) -#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) -#define I2C_DEBUG0_STATE_LATCH (1 << 11) -#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) -#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff -#define I2C_DEBUG0_STATE_STATE_OFFSET 0 - -#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) -#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 -#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) -#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 -#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) -#define I2C_DEBUG1_LST_MODE_OFFSET 9 -#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) -#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) -#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) -#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) -#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) -#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) - -#define I2C_VERSION_MAJOR_MASK (0xff << 24) -#define I2C_VERSION_MAJOR_OFFSET 24 -#define I2C_VERSION_MINOR_MASK (0xff << 16) -#define I2C_VERSION_MINOR_OFFSET 16 -#define I2C_VERSION_STEP_MASK 0xffff -#define I2C_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_I2C_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lcdif.h deleted file mode 100644 index 8915d84d0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lcdif.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Freescale i.MX28 LCDIF Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_LCDIF_H__ -#define __MX28_REGS_LCDIF_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_lcdif_regs { - mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ - mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ -#if defined(CONFIG_MX28) - mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ -#endif - mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ - mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */ - mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */ - -#if defined(CONFIG_MX23) - uint32_t reserved1[4]; -#endif - - mxs_reg_32(hw_lcdif_timing) /* 0x60 */ - mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ - mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ - mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ - mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ - mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ - mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ - mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ - mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ - mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ - mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ - mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ - mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */ - -#if defined(CONFIG_MX23) - uint32_t reserved2[12]; -#endif - mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ - mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ -#if defined(CONFIG_MX28) - mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ -#endif - mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ - mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */ - mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ - mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ - mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ -}; -#endif - -#define LCDIF_CTRL_SFTRST (1 << 31) -#define LCDIF_CTRL_CLKGATE (1 << 30) -#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) -#define LCDIF_CTRL_READ_WRITEB (1 << 28) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) -#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) -#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) -#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 -#define LCDIF_CTRL_DVI_MODE (1 << 20) -#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) -#define LCDIF_CTRL_VSYNC_MODE (1 << 18) -#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) -#define LCDIF_CTRL_DATA_SELECT (1 << 16) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) -#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) -#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) -#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) -#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) -#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 -#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) -#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) -#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) -#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) -#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) -#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) -#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) -#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) -#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) -#define LCDIF_CTRL_RUN (1 << 0) - -#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) -#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) -#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) -#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) -#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) -#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) -#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) -#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) -#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 -#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) -#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) -#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) -#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) -#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) -#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) -#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) -#define LCDIF_CTRL1_MODE86 (1 << 1) -#define LCDIF_CTRL1_RESET (1 << 0) - -#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) -#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) -#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 -#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) -#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) -#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) -#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) -#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) -#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) -#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) -#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 -#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) -#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 - -#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) -#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 -#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) -#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 - -#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff -#define LCDIF_CUR_BUF_ADDR_OFFSET 0 - -#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff -#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 - -#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) -#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 -#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) -#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 -#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) -#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 -#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) -#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 - -#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) -#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) -#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) -#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) -#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) -#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) -#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) -#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) -#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff -#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 - -#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff -#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 - -#if defined(CONFIG_MX23) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 -#elif defined(CONFIG_MX28) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) -#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 -#endif -#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff -#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 - -#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) -#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) -#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) -#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 - -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) -#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 -#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff -#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 - -#endif /* __MX28_REGS_LCDIF_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h deleted file mode 100644 index 74f9f7670..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Freescale i.MX28 LRADC Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_LRADC_H__ -#define __MX28_REGS_LRADC_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_lradc_regs { - mxs_reg_32(hw_lradc_ctrl0); - mxs_reg_32(hw_lradc_ctrl1); - mxs_reg_32(hw_lradc_ctrl2); - mxs_reg_32(hw_lradc_ctrl3); - mxs_reg_32(hw_lradc_status); - mxs_reg_32(hw_lradc_ch0); - mxs_reg_32(hw_lradc_ch1); - mxs_reg_32(hw_lradc_ch2); - mxs_reg_32(hw_lradc_ch3); - mxs_reg_32(hw_lradc_ch4); - mxs_reg_32(hw_lradc_ch5); - mxs_reg_32(hw_lradc_ch6); - mxs_reg_32(hw_lradc_ch7); - mxs_reg_32(hw_lradc_delay0); - mxs_reg_32(hw_lradc_delay1); - mxs_reg_32(hw_lradc_delay2); - mxs_reg_32(hw_lradc_delay3); - mxs_reg_32(hw_lradc_debug0); - mxs_reg_32(hw_lradc_debug1); - mxs_reg_32(hw_lradc_conversion); - mxs_reg_32(hw_lradc_ctrl4); - mxs_reg_32(hw_lradc_treshold0); - mxs_reg_32(hw_lradc_treshold1); - mxs_reg_32(hw_lradc_version); -}; -#endif - -#define LRADC_CTRL0_SFTRST (1 << 31) -#define LRADC_CTRL0_CLKGATE (1 << 30) -#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) -#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) -#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) -#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) -#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) -#define LRADC_CTRL0_YNLRSW (1 << 21) -#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) -#define LRADC_CTRL0_YPLLSW_OFFSET 19 -#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) -#define LRADC_CTRL0_XNURSW_OFFSET 17 -#define LRADC_CTRL0_XPULSW (1 << 16) -#define LRADC_CTRL0_SCHEDULE_MASK 0xff -#define LRADC_CTRL0_SCHEDULE_OFFSET 0 - -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) -#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) -#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) -#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) -#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) -#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) -#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) -#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) -#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) -#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) -#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) -#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) -#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) -#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) -#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) -#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) -#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) - -#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) -#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 -#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) -#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) -#define LRADC_CTRL2_VTHSENSE_OFFSET 13 -#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) -#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) -#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 -#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) -#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) -#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) -#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) -#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) -#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) -#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) -#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) -#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 -#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) -#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) -#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) -#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) -#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) -#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) -#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) - -#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) -#define LRADC_CTRL3_DISCARD_OFFSET 24 -#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) -#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) -#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) -#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) -#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) -#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) -#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 -#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) -#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) -#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) -#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) -#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) -#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 -#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) -#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) -#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) -#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) -#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) -#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) - -#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) -#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) -#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) -#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) -#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) -#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) -#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) -#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) -#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) -#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) -#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) -#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) -#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) -#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) -#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) -#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) - -#define LRADC_CH_TOGGLE (1 << 31) -#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) -#define LRADC_CH_ACCUMULATE (1 << 29) -#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) -#define LRADC_CH_NUM_SAMPLES_OFFSET 24 -#define LRADC_CH_VALUE_MASK 0x3ffff -#define LRADC_CH_VALUE_OFFSET 0 - -#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) -#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 -#define LRADC_DELAY_KICK (1 << 20) -#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) -#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 -#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) -#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 -#define LRADC_DELAY_DELAY_MASK 0x7ff -#define LRADC_DELAY_DELAY_OFFSET 0 - -#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) -#define LRADC_DEBUG0_READONLY_OFFSET 16 -#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) -#define LRADC_DEBUG0_STATE_OFFSET 0 - -#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) -#define LRADC_DEBUG1_REQUEST_OFFSET 16 -#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) -#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 -#define LRADC_DEBUG1_TESTMODE6 (1 << 2) -#define LRADC_DEBUG1_TESTMODE5 (1 << 1) -#define LRADC_DEBUG1_TESTMODE (1 << 0) - -#define LRADC_CONVERSION_AUTOMATIC (1 << 20) -#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 -#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) -#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff -#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 - -#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) -#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) -#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) -#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) -#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) -#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) -#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) -#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) -#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) -#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) -#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) -#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) -#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) -#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) -#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) - -#define LRADC_THRESHOLD_ENABLE (1 << 24) -#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) -#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) -#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) -#define LRADC_THRESHOLD_SETTING_OFFSET 18 -#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) -#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) -#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) -#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) -#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff -#define LRADC_THRESHOLD_VALUE_OFFSET 0 - -#define LRADC_VERSION_MAJOR_MASK (0xff << 24) -#define LRADC_VERSION_MAJOR_OFFSET 24 -#define LRADC_VERSION_MINOR_MASK (0xff << 16) -#define LRADC_VERSION_MINOR_OFFSET 16 -#define LRADC_VERSION_STEP_MASK 0xffff -#define LRADC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_LRADC_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h deleted file mode 100644 index bd80ac77f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Freescale i.MX28 OCOTP Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_OCOTP_H__ -#define __MX28_REGS_OCOTP_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_ocotp_regs { - mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ - mxs_reg_32(hw_ocotp_data) /* 0x10 */ - mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ - mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ - mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ - mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ - mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ - mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ - mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ - mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ - mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ - mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ - mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ - mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ - mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ - mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ - mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ - mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ - mxs_reg_32(hw_ocotp_lock) /* 0x120 */ - mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ - mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ - mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ - mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ - mxs_reg_32(hw_ocotp_un0) /* 0x170 */ - mxs_reg_32(hw_ocotp_un1) /* 0x180 */ - mxs_reg_32(hw_ocotp_un2) /* 0x190 */ - mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ - mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ - mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ - mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ - mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ - mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ - mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ - mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ - mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ - mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ - mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ - mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ - mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ - mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ - mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ - mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ - mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ -}; -#endif - -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) -#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 -#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) -#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) -#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) -#define OCOTP_CTRL_ERROR (1 << 9) -#define OCOTP_CTRL_BUSY (1 << 8) -#define OCOTP_CTRL_ADDR_MASK 0x3f -#define OCOTP_CTRL_ADDR_OFFSET 0 - -#define OCOTP_DATA_DATA_MASK 0xffffffff -#define OCOTP_DATA_DATA_OFFSET 0 - -#define OCOTP_CUST_BITS_MASK 0xffffffff -#define OCOTP_CUST_BITS_OFFSET 0 - -#define OCOTP_CRYPTO_BITS_MASK 0xffffffff -#define OCOTP_CRYPTO_BITS_OFFSET 0 - -#define OCOTP_HWCAP_BITS_MASK 0xffffffff -#define OCOTP_HWCAP_BITS_OFFSET 0 - -#define OCOTP_SWCAP_BITS_MASK 0xffffffff -#define OCOTP_SWCAP_BITS_OFFSET 0 - -#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) -#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) - -#define OCOTP_LOCK_ROM7 (1 << 31) -#define OCOTP_LOCK_ROM6 (1 << 30) -#define OCOTP_LOCK_ROM5 (1 << 29) -#define OCOTP_LOCK_ROM4 (1 << 28) -#define OCOTP_LOCK_ROM3 (1 << 27) -#define OCOTP_LOCK_ROM2 (1 << 26) -#define OCOTP_LOCK_ROM1 (1 << 25) -#define OCOTP_LOCK_ROM0 (1 << 24) -#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) -#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) -#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) -#define OCOTP_LOCK_PIN (1 << 20) -#define OCOTP_LOCK_OPS (1 << 19) -#define OCOTP_LOCK_UN2 (1 << 18) -#define OCOTP_LOCK_UN1 (1 << 17) -#define OCOTP_LOCK_UN0 (1 << 16) -#define OCOTP_LOCK_SRK (1 << 15) -#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) -#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 -#define OCOTP_LOCK_SRK_SHADOW (1 << 11) -#define OCOTP_LOCK_ROM_SHADOW (1 << 10) -#define OCOTP_LOCK_CUSTCAP (1 << 9) -#define OCOTP_LOCK_HWSW (1 << 8) -#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) -#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) -#define OCOTP_LOCK_CRYPTODCP (1 << 5) -#define OCOTP_LOCK_CRYPTOKEY (1 << 4) -#define OCOTP_LOCK_CUST3 (1 << 3) -#define OCOTP_LOCK_CUST2 (1 << 2) -#define OCOTP_LOCK_CUST1 (1 << 1) -#define OCOTP_LOCK_CUST0 (1 << 0) - -#define OCOTP_OPS_BITS_MASK 0xffffffff -#define OCOTP_OPS_BITS_OFFSET 0 - -#define OCOTP_UN_BITS_MASK 0xffffffff -#define OCOTP_UN_BITS_OFFSET 0 - -#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) -#define OCOTP_ROM_BOOT_MODE_OFFSET 24 -#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) -#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 -#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) -#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 -#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) -#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 -#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) -#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 -#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) -#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 -#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) -#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) -#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) -#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) -#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) - -#define OCOTP_SRK_BITS_MASK 0xffffffff -#define OCOTP_SRK_BITS_OFFSET 0 - -#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) -#define OCOTP_VERSION_MAJOR_OFFSET 24 -#define OCOTP_VERSION_MINOR_MASK (0xff << 16) -#define OCOTP_VERSION_MINOR_OFFSET 16 -#define OCOTP_VERSION_STEP_MASK 0xffff -#define OCOTP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h deleted file mode 100644 index 251fe6616..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h +++ /dev/null @@ -1,1271 +0,0 @@ -/* - * Freescale i.MX28 PINCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_PINCTRL_H__ -#define __MX28_REGS_PINCTRL_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_pinctrl_regs { - mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ - - uint32_t reserved1[60]; - - mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ - mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ - mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ - mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ - mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ - mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ - mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ - mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ - mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ - mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ - mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ - mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ - mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ - mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ - - uint32_t reserved2[72]; - - mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ - mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ - mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ - mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ - mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ - mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ - mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ - mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ - mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ - mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ - mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ - mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ - mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ - mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ - mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ - mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ - mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ - mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ - mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ - mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ - - uint32_t reserved3[112]; - - mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ - mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ - mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ - mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ - mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ - mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ - mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ - - uint32_t reserved4[36]; - - mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ - mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ - mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ - mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ - mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ - - uint32_t reserved5[108]; - - mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ - mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ - mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ - mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ - mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ - - uint32_t reserved6[108]; - - mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ - mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ - mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ - mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ - mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ - - uint32_t reserved7[300]; - - mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ - mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ - mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ - mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ - mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ - - uint32_t reserved8[44]; - - mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ - mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ - mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ - mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ - mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ - - uint32_t reserved9[44]; - - mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ - mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ - mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ - mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ - mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ - - uint32_t reserved10[44]; - - mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ - mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ - mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ - mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ - mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ - - uint32_t reserved11[44]; - - mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ - mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ - mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ - mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ - mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ - - uint32_t reserved12[380]; - - mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ - - uint32_t reserved13[76]; - - mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ -}; -#endif - -#define PINCTRL_CTRL_SFTRST (1 << 31) -#define PINCTRL_CTRL_CLKGATE (1 << 30) -#define PINCTRL_CTRL_PRESENT4 (1 << 24) -#define PINCTRL_CTRL_PRESENT3 (1 << 23) -#define PINCTRL_CTRL_PRESENT2 (1 << 22) -#define PINCTRL_CTRL_PRESENT1 (1 << 21) -#define PINCTRL_CTRL_PRESENT0 (1 << 20) -#define PINCTRL_CTRL_IRQOUT4 (1 << 4) -#define PINCTRL_CTRL_IRQOUT3 (1 << 3) -#define PINCTRL_CTRL_IRQOUT2 (1 << 2) -#define PINCTRL_CTRL_IRQOUT1 (1 << 1) -#define PINCTRL_CTRL_IRQOUT0 (1 << 0) - -#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) -#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 -#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 - -#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 -#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 - -#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) -#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) -#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) -#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) -#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) -#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) -#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) -#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) -#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) -#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) -#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) -#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) -#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) -#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) -#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) -#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) -#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) -#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) -#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) -#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) -#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) - -#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) -#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) -#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) -#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) -#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) -#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) -#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) -#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) -#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) -#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) -#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) -#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) -#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) -#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) -#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) -#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) -#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) -#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) -#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) -#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) -#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) -#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) -#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) -#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) -#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) -#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) -#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) -#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) -#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) -#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) -#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) -#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) - -#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) -#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) -#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) -#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) -#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) -#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) -#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) -#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) -#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) -#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) -#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) -#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) -#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) -#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) -#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) -#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) -#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) -#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) -#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) -#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) -#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) -#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) -#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) -#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) -#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) - -#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) -#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) -#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) -#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) -#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) -#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) -#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) -#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) -#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) -#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) -#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) -#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) -#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) -#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) -#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) -#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) -#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) -#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) -#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) -#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) -#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) -#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) -#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) -#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) -#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) -#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) -#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) -#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) -#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) -#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) - -#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) -#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) -#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) -#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) -#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) -#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) -#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) -#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) -#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) -#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) -#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) -#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) -#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) -#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) -#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) -#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) -#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) -#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) - -#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) -#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) -#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) -#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) -#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) -#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) -#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) -#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) -#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) -#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) -#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) -#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) -#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) -#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) -#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) -#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) -#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) -#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) -#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) -#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) -#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) -#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) -#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) -#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) -#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) - -#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) -#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) -#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) -#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) -#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) -#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) -#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) -#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) -#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) -#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) -#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) -#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) -#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) -#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) -#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) -#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) -#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) -#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) -#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) -#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) -#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) -#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) -#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) -#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) - -#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff -#define PINCTRL_DOUT0_DOUT_OFFSET 0 - -#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff -#define PINCTRL_DOUT1_DOUT_OFFSET 0 - -#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff -#define PINCTRL_DOUT2_DOUT_OFFSET 0 - -#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff -#define PINCTRL_DOUT3_DOUT_OFFSET 0 - -#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff -#define PINCTRL_DOUT4_DOUT_OFFSET 0 - -#define PINCTRL_DIN0_DIN_MASK 0x1fffffff -#define PINCTRL_DIN0_DIN_OFFSET 0 - -#define PINCTRL_DIN1_DIN_MASK 0xffffffff -#define PINCTRL_DIN1_DIN_OFFSET 0 - -#define PINCTRL_DIN2_DIN_MASK 0xfffffff -#define PINCTRL_DIN2_DIN_OFFSET 0 - -#define PINCTRL_DIN3_DIN_MASK 0x7fffffff -#define PINCTRL_DIN3_DIN_OFFSET 0 - -#define PINCTRL_DIN4_DIN_MASK 0x1fffff -#define PINCTRL_DIN4_DIN_OFFSET 0 - -#define PINCTRL_DOE0_DOE_MASK 0x1fffffff -#define PINCTRL_DOE0_DOE_OFFSET 0 - -#define PINCTRL_DOE1_DOE_MASK 0xffffffff -#define PINCTRL_DOE1_DOE_OFFSET 0 - -#define PINCTRL_DOE2_DOE_MASK 0xfffffff -#define PINCTRL_DOE2_DOE_OFFSET 0 - -#define PINCTRL_DOE3_DOE_MASK 0x7fffffff -#define PINCTRL_DOE3_DOE_OFFSET 0 - -#define PINCTRL_DOE4_DOE_MASK 0x1fffff -#define PINCTRL_DOE4_DOE_OFFSET 0 - -#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff -#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff -#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff -#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff -#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff -#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 - -#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff -#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff -#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff -#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff -#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff -#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 - -#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff -#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff -#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff -#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff -#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff -#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff -#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff -#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff -#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff -#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff -#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff -#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff -#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff -#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff -#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff -#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 - -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 - -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 - -#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h deleted file mode 100644 index ce2f425c1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Freescale i.MX23 Power Controller Register Definitions - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX23_REGS_POWER_H__ -#define __MX23_REGS_POWER_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_power_reset) - - uint32_t reserved2[4]; - - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) -}; -#endif - -#define POWER_CTRL_CLKGATE (1 << 30) -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_USE_EXTERN_R (1 << 17) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xff << 16) -#define POWER_SPEED_STATUS_OFFSET 16 -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_POWER_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h deleted file mode 100644 index 9528e3ce9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Freescale i.MX28 Power Controller Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_POWER_H__ -#define __MX28_REGS_POWER_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved[4]; - - mxs_reg_32(hw_power_reset) - mxs_reg_32(hw_power_debug) - mxs_reg_32(hw_power_thermal) - mxs_reg_32(hw_power_usb1ctrl) - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) - mxs_reg_32(hw_power_anaclkctrl) - mxs_reg_32(hw_power_refctrl) -}; -#endif - -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_LIION_4P1 (1 << 18) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) -#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) -#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_THERMAL_WARNING (1 << 19) -#define POWER_STS_VDDMEM_BO (1 << 18) -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xffff << 8) -#define POWER_SPEED_STATUS_OFFSET 8 -#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) -#define POWER_SPEED_STATUS_SEL_OFFSET 6 -#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) -#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) -#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_THERMAL_TEST (1 << 8) -#define POWER_THERMAL_PWD (1 << 7) -#define POWER_THERMAL_LOW_POWER (1 << 6) -#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) -#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 -#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) -#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 -#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 - -#define POWER_USB1CTRL_AVALID1 (1 << 3) -#define POWER_USB1CTRL_BVALID1 (1 << 2) -#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) -#define POWER_USB1CTRL_SESSEND1 (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) -#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) -#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 -#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) -#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) -#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) -#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) -#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) -#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) -#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 -#define POWER_ANACLKCTRL_INDIV_MASK 0x7 -#define POWER_ANACLKCTRL_INDIV_OFFSET 0 - -#define POWER_REFCTRL_FASTSETTLING (1 << 26) -#define POWER_REFCTRL_RAISE_REF (1 << 25) -#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) -#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) -#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 -#define POWER_REFCTRL_LOW_PWR (1 << 19) -#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) -#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 -#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) -#define POWER_REFCTRL_ADJ_ANA (1 << 13) -#define POWER_REFCTRL_ADJ_VAG (1 << 12) -#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) -#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 -#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) -#define POWER_REFCTRL_VAG_VAL_OFFSET 4 - -#endif /* __MX28_REGS_POWER_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h deleted file mode 100644 index 03e2e5dd6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Freescale i.MX28 RTC Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_RTC_H__ -#define __MX28_REGS_RTC_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_rtc_regs { - mxs_reg_32(hw_rtc_ctrl) - mxs_reg_32(hw_rtc_stat) - mxs_reg_32(hw_rtc_milliseconds) - mxs_reg_32(hw_rtc_seconds) - mxs_reg_32(hw_rtc_rtc_alarm) - mxs_reg_32(hw_rtc_watchdog) - mxs_reg_32(hw_rtc_persistent0) - mxs_reg_32(hw_rtc_persistent1) - mxs_reg_32(hw_rtc_persistent2) - mxs_reg_32(hw_rtc_persistent3) - mxs_reg_32(hw_rtc_persistent4) - mxs_reg_32(hw_rtc_persistent5) - mxs_reg_32(hw_rtc_debug) - mxs_reg_32(hw_rtc_version) -}; -#endif - -#define RTC_CTRL_SFTRST (1 << 31) -#define RTC_CTRL_CLKGATE (1 << 30) -#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) -#define RTC_CTRL_FORCE_UPDATE (1 << 5) -#define RTC_CTRL_WATCHDOGEN (1 << 4) -#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) -#define RTC_CTRL_ALARM_IRQ (1 << 2) -#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) -#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) - -#define RTC_STAT_RTC_PRESENT (1 << 31) -#define RTC_STAT_ALARM_PRESENT (1 << 30) -#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) -#define RTC_STAT_XTAL32000_PRESENT (1 << 28) -#define RTC_STAT_XTAL32768_PRESENT (1 << 27) -#define RTC_STAT_STALE_REGS_MASK (0xff << 16) -#define RTC_STAT_STALE_REGS_OFFSET 16 -#define RTC_STAT_NEW_REGS_MASK (0xff << 8) -#define RTC_STAT_NEW_REGS_OFFSET 8 - -#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff -#define RTC_MILLISECONDS_COUNT_OFFSET 0 - -#define RTC_SECONDS_COUNT_MASK 0xffffffff -#define RTC_SECONDS_COUNT_OFFSET 0 - -#define RTC_ALARM_VALUE_MASK 0xffffffff -#define RTC_ALARM_VALUE_OFFSET 0 - -#define RTC_WATCHDOG_COUNT_MASK 0xffffffff -#define RTC_WATCHDOG_COUNT_OFFSET 0 - -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) -#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) -#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) -#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) -#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) -#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) -#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) -#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 -#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) -#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) -#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) -#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 -#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) -#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) -#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) -#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) -#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) -#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) -#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) -#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) -#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) -#define RTC_PERSISTENT0_LCK_SECS (1 << 3) -#define RTC_PERSISTENT0_ALARM_EN (1 << 2) -#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) -#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) - -#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT1_GENERAL_OFFSET 0 -#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 -#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 -#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 -#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 -#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 -#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 - -#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT2_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT3_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT4_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT5_GENERAL_OFFSET 0 - -#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) -#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) - -#define RTC_VERSION_MAJOR_MASK (0xff << 24) -#define RTC_VERSION_MAJOR_OFFSET 24 -#define RTC_VERSION_MINOR_MASK (0xff << 16) -#define RTC_VERSION_MINOR_OFFSET 16 -#define RTC_VERSION_STEP_MASK 0xffff -#define RTC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_RTC_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h deleted file mode 100644 index e991216d0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Freescale i.MX28 SSP Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_SSP_H__ -#define __MX28_REGS_SSP_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_status) - - uint32_t reserved1[12]; - - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#elif defined(CONFIG_MX28) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_xfer_size) - mxs_reg_32(hw_ssp_block_size) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_ddr_ctrl) - mxs_reg_32(hw_ssp_dll_ctrl) - mxs_reg_32(hw_ssp_status) - mxs_reg_32(hw_ssp_dll_sts) - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#endif - -static inline int mxs_ssp_bus_id_valid(int bus) -{ -#if defined(CONFIG_MX23) - const unsigned int mxs_ssp_chan_count = 2; -#elif defined(CONFIG_MX28) - const unsigned int mxs_ssp_chan_count = 4; -#endif - - if (bus >= mxs_ssp_chan_count) - return 0; - - if (bus < 0) - return 0; - - return 1; -} - -static inline int mxs_ssp_clock_by_bus(unsigned int clock) -{ -#if defined(CONFIG_MX23) - return 0; -#elif defined(CONFIG_MX28) - return clock; -#endif -} - -static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) -{ - switch (port) { - case 0: - return (struct mxs_ssp_regs *)MXS_SSP0_BASE; - case 1: - return (struct mxs_ssp_regs *)MXS_SSP1_BASE; -#ifdef CONFIG_MX28 - case 2: - return (struct mxs_ssp_regs *)MXS_SSP2_BASE; - case 3: - return (struct mxs_ssp_regs *)MXS_SSP3_BASE; -#endif - default: - return NULL; - } -} -#endif - -#define SSP_CTRL0_SFTRST (1 << 31) -#define SSP_CTRL0_CLKGATE (1 << 30) -#define SSP_CTRL0_RUN (1 << 29) -#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) -#define SSP_CTRL0_LOCK_CS (1 << 27) -#define SSP_CTRL0_IGNORE_CRC (1 << 26) -#define SSP_CTRL0_READ (1 << 25) -#define SSP_CTRL0_DATA_XFER (1 << 24) -#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) -#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 -#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) -#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) -#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) -#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) -#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) -#define SSP_CTRL0_LONG_RESP (1 << 19) -#define SSP_CTRL0_CHECK_RESP (1 << 18) -#define SSP_CTRL0_GET_RESP (1 << 17) -#define SSP_CTRL0_ENABLE (1 << 16) - -#ifdef CONFIG_MX23 -#define SSP_CTRL0_XFER_COUNT_OFFSET 0 -#define SSP_CTRL0_XFER_COUNT_MASK 0xffff -#endif - -#define SSP_CMD0_SOFT_TERMINATE (1 << 26) -#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) -#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) -#define SSP_CMD0_BOOT_ACK_EN (1 << 23) -#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) -#define SSP_CMD0_CONT_CLKING_EN (1 << 21) -#define SSP_CMD0_APPEND_8CYC (1 << 20) -#if defined(CONFIG_MX23) -#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) -#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 -#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) -#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 -#endif -#define SSP_CMD0_CMD_MASK 0xff -#define SSP_CMD0_CMD_OFFSET 0 -#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 -#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 -#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 -#define SSP_CMD0_CMD_MMC_SWITCH 0x06 -#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 -#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 -#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a -#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b -#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e -#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 -#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 -#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 -#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a -#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_MMC_ERASE 0x26 -#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 -#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 -#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 -#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 -#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_SD_SET_DSR 0x04 -#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 -#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 -#define SSP_CMD0_CMD_SD_SEND_CID 0x0a -#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_SD_ERASE 0x26 -#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 -#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 -#define SSP_CMD0_CMD_SD_APP_CMD 0x37 -#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 - -#define SSP_CMD1_CMD_ARG_MASK 0xffffffff -#define SSP_CMD1_CMD_ARG_OFFSET 0 - -#if defined(CONFIG_MX28) -#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff -#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 - -#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) -#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 -#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf -#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 -#endif - -#define SSP_COMPREF_REFERENCE_MASK 0xffffffff -#define SSP_COMPREF_REFERENCE_OFFSET 0 - -#define SSP_COMPMASK_MASK_MASK 0xffffffff -#define SSP_COMPMASK_MASK_OFFSET 0 - -#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) -#define SSP_TIMING_TIMEOUT_OFFSET 16 -#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) -#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 -#define SSP_TIMING_CLOCK_RATE_MASK 0xff -#define SSP_TIMING_CLOCK_RATE_OFFSET 0 - -#define SSP_CTRL1_SDIO_IRQ (1 << 31) -#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) -#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) -#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) -#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) -#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) -#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) -#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) -#define SSP_CTRL1_DMA_ENABLE (1 << 13) -#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) -#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) -#define SSP_CTRL1_PHASE (1 << 10) -#define SSP_CTRL1_POLARITY (1 << 9) -#define SSP_CTRL1_SLAVE_MODE (1 << 8) -#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) -#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 -#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) -#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) -#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) -#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) -#define SSP_CTRL1_SSP_MODE_MASK 0xf -#define SSP_CTRL1_SSP_MODE_OFFSET 0 -#define SSP_CTRL1_SSP_MODE_SPI 0x0 -#define SSP_CTRL1_SSP_MODE_SSI 0x1 -#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 -#define SSP_CTRL1_SSP_MODE_MS 0x4 - -#define SSP_DATA_DATA_MASK 0xffffffff -#define SSP_DATA_DATA_OFFSET 0 - -#define SSP_SDRESP0_RESP0_MASK 0xffffffff -#define SSP_SDRESP0_RESP0_OFFSET 0 - -#define SSP_SDRESP1_RESP1_MASK 0xffffffff -#define SSP_SDRESP1_RESP1_OFFSET 0 - -#define SSP_SDRESP2_RESP2_MASK 0xffffffff -#define SSP_SDRESP2_RESP2_OFFSET 0 - -#define SSP_SDRESP3_RESP3_MASK 0xffffffff -#define SSP_SDRESP3_RESP3_OFFSET 0 - -#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) -#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 -#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) -#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) - -#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) -#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 -#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) -#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 -#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) -#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 -#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) -#define SSP_DLL_CTRL_RESET (1 << 1) -#define SSP_DLL_CTRL_ENABLE (1 << 0) - -#define SSP_STATUS_PRESENT (1 << 31) -#define SSP_STATUS_MS_PRESENT (1 << 30) -#define SSP_STATUS_SD_PRESENT (1 << 29) -#define SSP_STATUS_CARD_DETECT (1 << 28) -#define SSP_STATUS_DMABURST (1 << 22) -#define SSP_STATUS_DMASENSE (1 << 21) -#define SSP_STATUS_DMATERM (1 << 20) -#define SSP_STATUS_DMAREQ (1 << 19) -#define SSP_STATUS_DMAEND (1 << 18) -#define SSP_STATUS_SDIO_IRQ (1 << 17) -#define SSP_STATUS_RESP_CRC_ERR (1 << 16) -#define SSP_STATUS_RESP_ERR (1 << 15) -#define SSP_STATUS_RESP_TIMEOUT (1 << 14) -#define SSP_STATUS_DATA_CRC_ERR (1 << 13) -#define SSP_STATUS_TIMEOUT (1 << 12) -#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) -#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) -#define SSP_STATUS_FIFO_OVRFLW (1 << 9) -#define SSP_STATUS_FIFO_FULL (1 << 8) -#define SSP_STATUS_FIFO_EMPTY (1 << 5) -#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) -#define SSP_STATUS_CMD_BUSY (1 << 3) -#define SSP_STATUS_DATA_BUSY (1 << 2) -#define SSP_STATUS_BUSY (1 << 0) - -#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) -#define SSP_DLL_STS_REF_SEL_OFFSET 8 -#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) -#define SSP_DLL_STS_SLV_SEL_OFFSET 2 -#define SSP_DLL_STS_REF_LOCK (1 << 1) -#define SSP_DLL_STS_SLV_LOCK (1 << 0) - -#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) -#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 -#define SSP_DEBUG_DATA_STALL (1 << 27) -#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) -#define SSP_DEBUG_DAT_SM_OFFSET 24 -#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) -#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) -#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) -#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) -#define SSP_DEBUG_MSTK_SM_OFFSET 20 -#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) -#define SSP_DEBUG_CMD_OE (1 << 19) -#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) -#define SSP_DEBUG_DMA_SM_OFFSET 16 -#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) -#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) -#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) -#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) -#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) -#define SSP_DEBUG_MMC_SM_OFFSET 12 -#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) -#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) -#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) -#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) -#define SSP_DEBUG_CMD_SM_OFFSET 10 -#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) -#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) -#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) -#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) -#define SSP_DEBUG_SSP_CMD (1 << 9) -#define SSP_DEBUG_SSP_RESP (1 << 8) -#define SSP_DEBUG_SSP_RXD_MASK 0xff -#define SSP_DEBUG_SSP_RXD_OFFSET 0 - -#define SSP_VERSION_MAJOR_MASK (0xff << 24) -#define SSP_VERSION_MAJOR_OFFSET 24 -#define SSP_VERSION_MINOR_MASK (0xff << 16) -#define SSP_VERSION_MINOR_OFFSET 16 -#define SSP_VERSION_STEP_MASK 0xffff -#define SSP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_SSP_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h deleted file mode 100644 index 713c630dc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * Freescale i.MX28 TIMROT Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_TIMROT_H__ -#define __MX28_REGS_TIMROT_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_timrot_regs { - mxs_reg_32(hw_timrot_rotctrl) - mxs_reg_32(hw_timrot_rotcount) -#if defined(CONFIG_MX23) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_timcount0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_timcount1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_timcount2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_timcount3) -#elif defined(CONFIG_MX28) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_running_count0) - mxs_reg_32(hw_timrot_fixed_count0) - mxs_reg_32(hw_timrot_match_count0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_running_count1) - mxs_reg_32(hw_timrot_fixed_count1) - mxs_reg_32(hw_timrot_match_count1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_running_count2) - mxs_reg_32(hw_timrot_fixed_count2) - mxs_reg_32(hw_timrot_match_count2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_running_count3) - mxs_reg_32(hw_timrot_fixed_count3) - mxs_reg_32(hw_timrot_match_count3) -#endif - mxs_reg_32(hw_timrot_version) -}; -#endif - -#define TIMROT_ROTCTRL_SFTRST (1 << 31) -#define TIMROT_ROTCTRL_CLKGATE (1 << 30) -#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) -#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) -#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) -#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) -#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) -#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) -#define TIMROT_ROTCTRL_STATE_OFFSET 22 -#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) -#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 -#define TIMROT_ROTCTRL_RELATIVE (1 << 12) -#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 -#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) -#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) -#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) -#endif -#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 -#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) -#endif -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf -#endif -#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 -#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 -#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 -#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 -#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 -#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 -#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 -#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 -#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa -#endif - -#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff -#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 - -#define TIMROT_TIMCTRLn_IRQ (1 << 15) -#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) -#if defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) -#endif -#define TIMROT_TIMCTRLn_POLARITY (1 << 8) -#define TIMROT_TIMCTRLn_UPDATE (1 << 7) -#define TIMROT_TIMCTRLn_RELOAD (1 << 6) -#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRLn_SELECT_MASK 0xf -#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 -#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc -#elif defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 -#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 -#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf -#endif - -#if defined(CONFIG_MX23) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 -#elif defined(CONFIG_MX28) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 -#endif - -#if defined(CONFIG_MX23) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#elif defined(CONFIG_MX28) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#endif - -#if defined(CONFIG_MX28) -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 -#endif - -#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 -#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) -#elif defined(CONFIG_MX28) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) -#endif -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_IRQ (1 << 15) -#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) -#endif -#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) -#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 -#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) -#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) -#define TIMROT_TIMCTRL3_UPDATE (1 << 7) -#define TIMROT_TIMCTRL3_RELOAD (1 << 6) -#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRL3_SELECT_MASK 0xf -#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 -#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 -#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 -#endif - -#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) -#define TIMROT_VERSION_MAJOR_OFFSET 24 -#define TIMROT_VERSION_MINOR_MASK (0xff << 16) -#define TIMROT_VERSION_MINOR_OFFSET 16 -#define TIMROT_VERSION_STEP_MASK 0xffff -#define TIMROT_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h deleted file mode 100644 index 7ceb810dc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Freescale MXS UARTAPP Register Definitions - * - * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_ARM___MXS_UARTAPP_H -#define __ARCH_ARM___MXS_UARTAPP_H - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_uartapp_regs { - mxs_reg_32(hw_uartapp_ctrl0) - mxs_reg_32(hw_uartapp_ctrl1) - mxs_reg_32(hw_uartapp_ctrl2) - mxs_reg_32(hw_uartapp_linectrl) - mxs_reg_32(hw_uartapp_linectrl2) - mxs_reg_32(hw_uartapp_intr) - mxs_reg_32(hw_uartapp_data) - mxs_reg_32(hw_uartapp_stat) - mxs_reg_32(hw_uartapp_debug) - mxs_reg_32(hw_uartapp_version) - mxs_reg_32(hw_uartapp_autobaud) -}; -#endif - -#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) -#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) -#define UARTAPP_CTRL0_RUN_MASK (1 << 29) -#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) -#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) -#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 -#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) -#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL1_RUN_MASK (1 << 28) - -#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) -#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) -#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) -#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) -#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) -#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) -#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) -#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) -#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 -#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) - -#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) -#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 -#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) -#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) -#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) -#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) -#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) -#define UARTAPP_CTRL2_RTS_MASK (1 << 11) -#define UARTAPP_CTRL2_DTR_MASK (1 << 10) -#define UARTAPP_CTRL2_RXE_MASK (1 << 9) -#define UARTAPP_CTRL2_TXE_MASK (1 << 8) -#define UARTAPP_CTRL2_LBE_MASK (1 << 7) -#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) - -#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) -#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) -#define UARTAPP_CTRL2_UARTEN_MASK 0x01 - -#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) -#define UARTAPP_LINECTRL_BRK_MASK 1 - -#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) - -#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) -#define UARTAPP_INTR_OEIEN_MASK (1 << 26) -#define UARTAPP_INTR_BEIEN_MASK (1 << 25) -#define UARTAPP_INTR_PEIEN_MASK (1 << 24) -#define UARTAPP_INTR_FEIEN_MASK (1 << 23) -#define UARTAPP_INTR_RTIEN_MASK (1 << 22) -#define UARTAPP_INTR_TXIEN_MASK (1 << 21) -#define UARTAPP_INTR_RXIEN_MASK (1 << 20) -#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) -#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) -#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) -#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) - -#define UARTAPP_INTR_ABDIS_MASK (1 << 11) -#define UARTAPP_INTR_OEIS_MASK (1 << 10) -#define UARTAPP_INTR_BEIS_MASK (1 << 9) -#define UARTAPP_INTR_PEIS_MASK (1 << 8) -#define UARTAPP_INTR_FEIS_MASK (1 << 7) -#define UARTAPP_INTR_RTIS_MASK (1 << 6) -#define UARTAPP_INTR_TXIS_MASK (1 << 5) -#define UARTAPP_INTR_RXIS_MASK (1 << 4) -#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) -#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) -#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) -#define UARTAPP_INTR_RIMIS_MASK 0x1 - -#define UARTAPP_DATA_DATA_OFFSET 0 -#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF -#define UARTAPP_STAT_PRESENT_MASK (1 << 31) -#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) -#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) - -#define UARTAPP_STAT_HISPEED_MASK (1 << 30) -#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) -#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) - -#define UARTAPP_STAT_BUSY_MASK (1 << 29) -#define UARTAPP_STAT_CTS_MASK (1 << 28) -#define UARTAPP_STAT_TXFE_MASK (1 << 27) -#define UARTAPP_STAT_RXFF_MASK (1 << 26) -#define UARTAPP_STAT_TXFF_MASK (1 << 25) -#define UARTAPP_STAT_RXFE_MASK (1 << 24) -#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 -#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) - -#define UARTAPP_STAT_OERR_MASK (1 << 19) -#define UARTAPP_STAT_BERR_MASK (1 << 18) -#define UARTAPP_STAT_PERR_MASK (1 << 17) -#define UARTAPP_STAT_FERR_MASK (1 << 16) -#define UARTAPP_STAT_RXCOUNT_OFFSET 0 -#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF - -#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 -#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) - -#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 -#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) - -#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) -#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) -#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) -#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) -#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) -#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 - -#define UARTAPP_VERSION_MAJOR_OFFSET 24 -#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) - -#define UARTAPP_VERSION_MINOR_OFFSET 16 -#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) - -#define UARTAPP_VERSION_STEP_OFFSET 0 -#define UARTAPP_VERSION_STEP_MASK 0xFFFF - -#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 -#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) - -#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 -#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) - -#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) -#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) -#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) -#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) -#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 -#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h deleted file mode 100644 index 8313bec78..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Freescale i.MX28 USB OTG Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct mxs_usb_regs { - uint32_t hw_usbctrl_id; /* 0x000 */ - uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ - uint32_t hw_usbctrl_hwhost; /* 0x008 */ - uint32_t hw_usbctrl_hwdevice; /* 0x00c */ - uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ - uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ - - uint32_t reserved1[26]; - - uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ - uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ - uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ - uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ - uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ - - uint32_t reserved2[27]; - - uint32_t hw_usbctrl_caplength; /* 0x100 */ - uint32_t hw_usbctrl_hcsparams; /* 0x104 */ - uint32_t hw_usbctrl_hccparams; /* 0x108 */ - - uint32_t reserved3[5]; - - uint32_t hw_usbctrl_dciversion; /* 0x120 */ - uint32_t hw_usbctrl_dccparams; /* 0x124 */ - - uint32_t reserved4[6]; - - uint32_t hw_usbctrl_usbcmd; /* 0x140 */ - uint32_t hw_usbctrl_usbsts; /* 0x144 */ - uint32_t hw_usbctrl_usbintr; /* 0x148 */ - uint32_t hw_usbctrl_frindex; /* 0x14c */ - - uint32_t reserved5; - - union { - uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ - uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ - }; - union { - uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ - uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ - }; - - uint32_t hw_usbctrl_ttctrl; /* 0x15c */ - uint32_t hw_usbctrl_burstsize; /* 0x160 */ - uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ - - uint32_t reserved6; - - uint32_t hw_usbctrl_ic_usb; /* 0x16c */ - uint32_t hw_usbctrl_ulpi; /* 0x170 */ - - uint32_t reserved7; - - uint32_t hw_usbctrl_endptnak; /* 0x178 */ - uint32_t hw_usbctrl_endptnaken; /* 0x17c */ - - uint32_t reserved8; - - uint32_t hw_usbctrl_portsc1; /* 0x184 */ - - uint32_t reserved9[7]; - - uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ - uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ - uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ - uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ - uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ - uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ - uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ - uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ - uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ - uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ - uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ - uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ - uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ - uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ - uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ -}; - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) - -#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 -#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) -#define HW_USBCTRL_ID_VERSION_OFFSET 25 -#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) -#define HW_USBCTRL_ID_REVISION_OFFSET 21 -#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) -#define HW_USBCTRL_ID_TAG_OFFSET 16 -#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) -#define HW_USBCTRL_ID_NID_OFFSET 8 -#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) -#define HW_USBCTRL_ID_ID_OFFSET 0 -#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) - -#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 -#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) -#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 -#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) -#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 -#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) -#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) -#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 -#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) -#define HW_USBCTRL_HWGENERAL_RT (1 << 0) - -#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 -#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) -#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 -#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) -#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 -#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) -#define HW_USBCTRL_HWHOST_HC (1 << 0) - -#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 -#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) -#define HW_USBCTRL_HWDEVICE_DC (1 << 0) - -#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) -#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 -#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) -#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 -#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 -#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff - -#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 -#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 -#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff - -#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 -#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff - -#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) -#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) -#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff - -#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 - -#endif /* __REGS_USB_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h deleted file mode 100644 index eabefc644..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Freescale i.MX28 USB PHY Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REGS_USBPHY_H__ -#define __REGS_USBPHY_H__ - -struct mxs_usbphy_regs { - mxs_reg_32(hw_usbphy_pwd) - mxs_reg_32(hw_usbphy_tx) - mxs_reg_32(hw_usbphy_rx) - mxs_reg_32(hw_usbphy_ctrl) - mxs_reg_32(hw_usbphy_status) - mxs_reg_32(hw_usbphy_debug) - mxs_reg_32(hw_usbphy_debug0_status) - mxs_reg_32(hw_usbphy_debug1) - mxs_reg_32(hw_usbphy_version) - mxs_reg_32(hw_usbphy_ip) -}; - -#define USBPHY_PWD_RXPWDRX (1 << 20) -#define USBPHY_PWD_RXPWDDIFF (1 << 19) -#define USBPHY_PWD_RXPWD1PT1 (1 << 18) -#define USBPHY_PWD_RXPWDENV (1 << 17) -#define USBPHY_PWD_TXPWDV2I (1 << 12) -#define USBPHY_PWD_TXPWDIBIAS (1 << 11) -#define USBPHY_PWD_TXPWDFS (1 << 10) - -#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 -#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) -#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) -#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) -#define USBPHY_TX_TXENCAL45DP (1 << 21) -#define USBPHY_TX_TXCAL45DP_OFFSET 16 -#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) -#define USBPHY_TX_TXENCAL45DM (1 << 13) -#define USBPHY_TX_TXCAL45DM_OFFSET 8 -#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) -#define USBPHY_TX_D_CAL_OFFSET 0 -#define USBPHY_TX_D_CAL_MASK 0xf - -#define USBPHY_RX_RXDBYPASS (1 << 22) -#define USBPHY_RX_DISCONADJ_OFFSET 4 -#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) -#define USBPHY_RX_ENVADJ_OFFSET 0 -#define USBPHY_RX_ENVADJ_MASK 0x7 - -#define USBPHY_CTRL_SFTRST (1 << 31) -#define USBPHY_CTRL_CLKGATE (1 << 30) -#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) -#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) -#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) -#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) -#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) -#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) -#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) -#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) -#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) -#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) -#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) -#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) -#define USBPHY_CTRL_RESUME_IRQ (1 << 10) -#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) -#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) -#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) -#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) -#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) -#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) - -#define USBPHY_STATUS_RESUME_STATUS (1 << 10) -#define USBPHY_STATUS_OTGID_STATUS (1 << 8) -#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) - -#define USBPHY_DEBUG_CLKGATE (1 << 30) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) -#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) -#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) -#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 -#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) -#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 -#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) -#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 -#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) -#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) - -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff - -#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) -#define USBPHY_DEBUG1_ENTX2TX (1 << 12) -#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 -#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf - -#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) -#define USBPHY_VERSION_MAJOR_OFFSET 24 -#define USBPHY_VERSION_MINOR_MASK (0xff << 16) -#define USBPHY_VERSION_MINOR_OFFSET 16 -#define USBPHY_VERSION_STEP_MASK 0xffff -#define USBPHY_VERSION_STEP_OFFSET 0 - -#define USBPHY_IP_DIV_SEL_OFFSET 23 -#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) -#define USBPHY_IP_LFR_SEL_OFFSET 21 -#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) -#define USBPHY_IP_CP_SEL_OFFSET 19 -#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) -#define USBPHY_IP_TSTI_TX_DP (1 << 18) -#define USBPHY_IP_TSTI_TX_DM (1 << 17) -#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) -#define USBPHY_IP_EN_USB_CLKS (1 << 2) -#define USBPHY_IP_PLL_LOCKED (1 << 1) -#define USBPHY_IP_PLL_POWER (1 << 0) - -#endif /* __REGS_USBPHY_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h deleted file mode 100644 index 09dfc90a9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 specific functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SYS_PROTO_H__ -#define __SYS_PROTO_H__ - -int mxs_reset_block(struct mxs_register_32 *reg); -int mxs_wait_mask_set(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); -int mxs_wait_mask_clr(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); - -int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); - -#ifdef CONFIG_SPL_BUILD - -#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) -#include <asm/arch/iomux-mx28.h> -#endif - -void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, - const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); -#endif - -struct mxs_pair { - uint8_t boot_pads; - uint8_t boot_mask; - const char *mode; -}; - -static const struct mxs_pair mxs_boot_modes[] = { -#if defined(CONFIG_MX23) - { 0x00, 0x0f, "USB" }, - { 0x01, 0x1f, "I2C, master" }, - { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, - { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, - { 0x04, 0x1f, "NAND" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0" }, - { 0x0a, 0x1f, "SSP SD/MMC #1" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#elif defined(CONFIG_MX28) - { 0x00, 0x0f, "USB #0" }, - { 0x01, 0x1f, "I2C #0, master, 3V3" }, - { 0x11, 0x1f, "I2C #0, master, 1V8" }, - { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, - { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, - { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, - { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, - { 0x04, 0x1f, "NAND, 3V3" }, - { 0x14, 0x1f, "NAND, 1V8" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, - { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, - { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, - { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, - { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#endif -}; - -struct mxs_spl_data { - uint8_t boot_mode_idx; - uint32_t mem_dram_size; -}; - -int mxs_dram_init(void); - -#endif /* __SYS_PROTO_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/gpio.h deleted file mode 100644 index 311758ae1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/gpio.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __NMK_GPIO_H__ -#define __NMK_GPIO_H__ - -/* - * These functions are called from the soft-i2c driver, but - * are also used by board files to set output bits. - */ - -enum nmk_af { /* alternate function settings */ - GPIO_GPIO = 0, - GPIO_ALT_A, - GPIO_ALT_B, - GPIO_ALT_C -}; - -extern void nmk_gpio_af(int gpio, int alternate_function); -extern void nmk_gpio_dir(int gpio, int dir); -extern void nmk_gpio_set(int gpio, int val); -extern int nmk_gpio_get(int gpio); - -#endif /* __NMK_GPIO_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h deleted file mode 100644 index f89f24224..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MTU_H -#define __ASM_ARCH_MTU_H - -/* - * The MTU device hosts four different counters, with 4 set of - * registers. These are register names. - */ - -#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ -#define MTU_RIS 0x04 /* Raw interrupt status */ -#define MTU_MIS 0x08 /* Masked interrupt status */ -#define MTU_ICR 0x0C /* Interrupt clear register */ - -/* per-timer registers take 0..3 as argument */ -#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ -#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ -#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ -#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ - -/* bits for the control register */ -#define MTU_CRn_ENA 0x80 -#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CRn_PRESCALE_MASK 0x0c -#define MTU_CRn_PRESCALE_1 0x00 -#define MTU_CRn_PRESCALE_16 0x04 -#define MTU_CRn_PRESCALE_256 0x08 -#define MTU_CRn_32BITS 0x02 -#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ - -/* Other registers are usual amba/primecell registers, currently not used */ -#define MTU_ITCR 0xff0 -#define MTU_ITOP 0xff4 - -#define MTU_PERIPH_ID0 0xfe0 -#define MTU_PERIPH_ID1 0xfe4 -#define MTU_PERIPH_ID2 0xfe8 -#define MTU_PERIPH_ID3 0xfeC - -#define MTU_PCELL0 0xff0 -#define MTU_PCELL1 0xff4 -#define MTU_PCELL2 0xff8 -#define MTU_PCELL3 0xffC - -#endif /* __ASM_ARCH_MTU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h deleted file mode 100644 index 9d001ff2a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * am35x_def.h - TI's AM35x specific definitions. - * - * Based on arch/arm/include/asm/arch-omap3/cpu.h - * - * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> - * - * Copyright (c) 2010 Texas Instruments Incorporated - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _AM35X_DEF_H_ -#define _AM35X_DEF_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ - -/* LVL_INTR_CLEAR bits */ -#define USBOTGSS_INT_CLR (1 << 4) - -/* IP_SW_RESET bits */ -#define USBOTGSS_SW_RST (1 << 0) /* reset USBOTG */ -#define CPGMACSS_SW_RST (1 << 1) /* reset CPGMAC */ - -/* DEVCONF2 bits */ -#define CONF2_PHY_GPIOMODE (1 << 23) -#define CONF2_OTGMODE (3 << 14) -#define CONF2_NO_OVERRIDE (0 << 14) -#define CONF2_FORCE_HOST (1 << 14) -#define CONF2_FORCE_DEVICE (2 << 14) -#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) -#define CONF2_SESENDEN (1 << 13) -#define CONF2_VBDTCTEN (1 << 12) -#define CONF2_REFFREQ_24MHZ (2 << 8) -#define CONF2_REFFREQ_26MHZ (7 << 8) -#define CONF2_REFFREQ_13MHZ (6 << 8) -#define CONF2_REFFREQ (0xf << 8) -#define CONF2_PHYCLKGD (1 << 7) -#define CONF2_VBUSSENSE (1 << 6) -#define CONF2_PHY_PLLON (1 << 5) -#define CONF2_RESET (1 << 4) -#define CONF2_PHYPWRDN (1 << 3) -#define CONF2_OTGPWRDN (1 << 2) -#define CONF2_DATPOL (1 << 1) - -/* General register mappings of system control module */ -#define AM35X_SCM_GEN_BASE 0x48002270 -struct am35x_scm_general { - u32 res1[0xC4]; /* 0x000 - 0x30C */ - u32 devconf2; /* 0x310 */ - u32 devconf3; /* 0x314 */ - u32 res2[0x2]; /* 0x318 - 0x31C */ - u32 cba_priority; /* 0x320 */ - u32 lvl_intr_clr; /* 0x324 */ - u32 ip_sw_reset; /* 0x328 */ - u32 ipss_clk_ctrl; /* 0x32C */ -}; -#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) - -#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 - -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#endif /* _AM35X_DEF_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h deleted file mode 100644 index 1912cc9a6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _CLOCKS_H_ -#define _CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#define FCK_IVA2_ON 0x00000001 -#define FCK_CORE1_ON 0x03fffe29 -#define ICK_CORE1_ON 0x3ffffffb -#define ICK_CORE2_ON 0x0000001f -#define FCK_WKUP_ON 0x000000e9 -#define ICK_WKUP_ON 0x0000003f -#define FCK_DSS_ON 0x00000005 -#define ICK_DSS_ON 0x00000001 -#define FCK_CAM_ON 0x00000001 -#define ICK_CAM_ON 0x00000001 - -/* Used to index into DPLL parameter tables */ -typedef struct { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -} dpll_param; - -struct dpll_per_36x_param { - unsigned int sys_clk; - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m2div; -}; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); -extern dpll_param *get_per2_dpll_param(void); - -extern dpll_param *get_36x_mpu_dpll_param(void); -extern dpll_param *get_36x_iva_dpll_param(void); -extern dpll_param *get_36x_core_dpll_param(void); -extern dpll_param *get_36x_per_dpll_param(void); -extern dpll_param *get_36x_per2_dpll_param(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h deleted file mode 100644 index df73c4b2e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _CLOCKS_OMAP3_H_ -#define _CLOCKS_OMAP3_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* - * The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -#define CORE_FUSB_DIV 2 /* 41.5MHz: */ -#define CORE_L4_DIV 2 /* 83MHz : L4 */ -#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ -#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ -#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) - -/* MPU DPLL */ - -#define MPU_M_12_ES1 0x0FE -#define MPU_N_12_ES1 0x07 -#define MPU_FSEL_12_ES1 0x05 -#define MPU_M2_12_ES1 0x01 - -#define MPU_M_12_ES2 0x0FA -#define MPU_N_12_ES2 0x05 -#define MPU_FSEL_12_ES2 0x07 -#define MPU_M2_ES2 0x01 - -#define MPU_M_12 0x085 -#define MPU_N_12 0x05 -#define MPU_FSEL_12 0x07 -#define MPU_M2_12 0x01 - -#define MPU_M_13_ES1 0x17D -#define MPU_N_13_ES1 0x0C -#define MPU_FSEL_13_ES1 0x03 -#define MPU_M2_13_ES1 0x01 - -#define MPU_M_13_ES2 0x258 -#define MPU_N_13_ES2 0x0C -#define MPU_FSEL_13_ES2 0x03 -#define MPU_M2_13_ES2 0x01 - -#define MPU_M_13 0x10A -#define MPU_N_13 0x0C -#define MPU_FSEL_13 0x03 -#define MPU_M2_13 0x01 - -#define MPU_M_19P2_ES1 0x179 -#define MPU_N_19P2_ES1 0x12 -#define MPU_FSEL_19P2_ES1 0x04 -#define MPU_M2_19P2_ES1 0x01 - -#define MPU_M_19P2_ES2 0x271 -#define MPU_N_19P2_ES2 0x17 -#define MPU_FSEL_19P2_ES2 0x03 -#define MPU_M2_19P2_ES2 0x01 - -#define MPU_M_19P2 0x14C -#define MPU_N_19P2 0x17 -#define MPU_FSEL_19P2 0x03 -#define MPU_M2_19P2 0x01 - -#define MPU_M_26_ES1 0x17D -#define MPU_N_26_ES1 0x19 -#define MPU_FSEL_26_ES1 0x03 -#define MPU_M2_26_ES1 0x01 - -#define MPU_M_26_ES2 0x0FA -#define MPU_N_26_ES2 0x0C -#define MPU_FSEL_26_ES2 0x07 -#define MPU_M2_26_ES2 0x01 - -#define MPU_M_26 0x085 -#define MPU_N_26 0x0C -#define MPU_FSEL_26 0x07 -#define MPU_M2_26 0x01 - -#define MPU_M_38P4_ES1 0x1FA -#define MPU_N_38P4_ES1 0x32 -#define MPU_FSEL_38P4_ES1 0x03 -#define MPU_M2_38P4_ES1 0x01 - -#define MPU_M_38P4_ES2 0x271 -#define MPU_N_38P4_ES2 0x2F -#define MPU_FSEL_38P4_ES2 0x03 -#define MPU_M2_38P4_ES2 0x01 - -#define MPU_M_38P4 0x14C -#define MPU_N_38P4 0x2F -#define MPU_FSEL_38P4 0x03 -#define MPU_M2_38P4 0x01 - -/* IVA DPLL */ - -#define IVA_M_12_ES1 0x07D -#define IVA_N_12_ES1 0x05 -#define IVA_FSEL_12_ES1 0x07 -#define IVA_M2_12_ES1 0x01 - -#define IVA_M_12_ES2 0x0B4 -#define IVA_N_12_ES2 0x05 -#define IVA_FSEL_12_ES2 0x07 -#define IVA_M2_12_ES2 0x01 - -#define IVA_M_12 0x085 -#define IVA_N_12 0x05 -#define IVA_FSEL_12 0x07 -#define IVA_M2_12 0x01 - -#define IVA_M_13_ES1 0x0FA -#define IVA_N_13_ES1 0x0C -#define IVA_FSEL_13_ES1 0x03 -#define IVA_M2_13_ES1 0x01 - -#define IVA_M_13_ES2 0x168 -#define IVA_N_13_ES2 0x0C -#define IVA_FSEL_13_ES2 0x03 -#define IVA_M2_13_ES2 0x01 - -#define IVA_M_13 0x10A -#define IVA_N_13 0x0C -#define IVA_FSEL_13 0x03 -#define IVA_M2_13 0x01 - -#define IVA_M_19P2_ES1 0x082 -#define IVA_N_19P2_ES1 0x09 -#define IVA_FSEL_19P2_ES1 0x07 -#define IVA_M2_19P2_ES1 0x01 - -#define IVA_M_19P2_ES2 0x0E1 -#define IVA_N_19P2_ES2 0x0B -#define IVA_FSEL_19P2_ES2 0x06 -#define IVA_M2_19P2_ES2 0x01 - -#define IVA_M_19P2 0x14C -#define IVA_N_19P2 0x17 -#define IVA_FSEL_19P2 0x03 -#define IVA_M2_19P2 0x01 - -#define IVA_M_26_ES1 0x07D -#define IVA_N_26_ES1 0x0C -#define IVA_FSEL_26_ES1 0x07 -#define IVA_M2_26_ES1 0x01 - -#define IVA_M_26_ES2 0x0B4 -#define IVA_N_26_ES2 0x0C -#define IVA_FSEL_26_ES2 0x07 -#define IVA_M2_26_ES2 0x01 - -#define IVA_M_26 0x085 -#define IVA_N_26 0x0C -#define IVA_FSEL_26 0x07 -#define IVA_M2_26 0x01 - -#define IVA_M_38P4_ES1 0x13F -#define IVA_N_38P4_ES1 0x30 -#define IVA_FSEL_38P4_ES1 0x03 -#define IVA_M2_38P4_ES1 0x01 - -#define IVA_M_38P4_ES2 0x0E1 -#define IVA_N_38P4_ES2 0x17 -#define IVA_FSEL_38P4_ES2 0x06 -#define IVA_M2_38P4_ES2 0x01 - -#define IVA_M_38P4 0x14C -#define IVA_N_38P4 0x2F -#define IVA_FSEL_38P4 0x03 -#define IVA_M2_38P4 0x01 - -/* CORE DPLL */ - -#define CORE_M_12 0xA6 -#define CORE_N_12 0x05 -#define CORE_FSEL_12 0x07 -#define CORE_M2_12 0x01 /* M3 of 2 */ - -#define CORE_M_12_ES1 0x19F -#define CORE_N_12_ES1 0x0E -#define CORE_FSL_12_ES1 0x03 -#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ - -#define CORE_M_13 0x14C -#define CORE_N_13 0x0C -#define CORE_FSEL_13 0x03 -#define CORE_M2_13 0x01 /* M3 of 2 */ - -#define CORE_M_13_ES1 0x1B2 -#define CORE_N_13_ES1 0x10 -#define CORE_FSL_13_ES1 0x03 -#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_19P2 0x19F -#define CORE_N_19P2 0x17 -#define CORE_FSEL_19P2 0x03 -#define CORE_M2_19P2 0x01 /* M3 of 2 */ - -#define CORE_M_19P2_ES1 0x19F -#define CORE_N_19P2_ES1 0x17 -#define CORE_FSL_19P2_ES1 0x03 -#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_26 0xA6 -#define CORE_N_26 0x0C -#define CORE_FSEL_26 0x07 -#define CORE_M2_26 0x01 /* M3 of 2 */ - -#define CORE_M_26_ES1 0x1B2 -#define CORE_N_26_ES1 0x21 -#define CORE_FSL_26_ES1 0x03 -#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ - -#define CORE_M_38P4 0x19F -#define CORE_N_38P4 0x2F -#define CORE_FSEL_38P4 0x03 -#define CORE_M2_38P4 0x01 /* M3 of 2 */ - -#define CORE_M_38P4_ES1 0x19F -#define CORE_N_38P4_ES1 0x2F -#define CORE_FSL_38P4_ES1 0x03 -#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ - -/* PER DPLL */ - -#define PER_M_12 0xD8 -#define PER_N_12 0x05 -#define PER_FSEL_12 0x07 -#define PER_M2_12 0x09 - -#define PER_M_13 0x1B0 -#define PER_N_13 0x0C -#define PER_FSEL_13 0x03 -#define PER_M2_13 0x09 - -#define PER_M_19P2 0xE1 -#define PER_N_19P2 0x09 -#define PER_FSEL_19P2 0x07 -#define PER_M2_19P2 0x09 - -#define PER_M_26 0xD8 -#define PER_N_26 0x0C -#define PER_FSEL_26 0x07 -#define PER_M2_26 0x09 - -#define PER_M_38P4 0xE1 -#define PER_N_38P4 0x13 -#define PER_FSEL_38P4 0x07 -#define PER_M2_38P4 0x09 - -/* PER2 DPLL */ -#define PER2_M_12 0x78 -#define PER2_N_12 0x0B -#define PER2_FSEL_12 0x03 -#define PER2_M2_12 0x01 - -#define PER2_M_13 0x78 -#define PER2_N_13 0x0C -#define PER2_FSEL_13 0x03 -#define PER2_M2_13 0x01 - -#define PER2_M_19P2 0x2EE -#define PER2_N_19P2 0x0B -#define PER2_FSEL_19P2 0x06 -#define PER2_M2_19P2 0x0A - -#define PER2_M_26 0x78 -#define PER2_N_26 0x0C -#define PER2_FSEL_26 0x03 -#define PER2_M2_26 0x01 - -#define PER2_M_38P4 0x2EE -#define PER2_N_38P4 0x0B -#define PER2_FSEL_38P4 0x06 -#define PER2_M2_38P4 0x0A - -/* 36XX PER DPLL */ - -#define PER_36XX_M_12 0x1B0 -#define PER_36XX_N_12 0x05 -#define PER_36XX_FSEL_12 0x07 -#define PER_36XX_M2_12 0x09 - -#define PER_36XX_M_13 0x360 -#define PER_36XX_N_13 0x0C -#define PER_36XX_FSEL_13 0x03 -#define PER_36XX_M2_13 0x09 - -#define PER_36XX_M_19P2 0x1C2 -#define PER_36XX_N_19P2 0x09 -#define PER_36XX_FSEL_19P2 0x07 -#define PER_36XX_M2_19P2 0x09 - -#define PER_36XX_M_26 0x1B0 -#define PER_36XX_N_26 0x0C -#define PER_36XX_FSEL_26 0x07 -#define PER_36XX_M2_26 0x09 - -#define PER_36XX_M_38P4 0x1C2 -#define PER_36XX_N_38P4 0x13 -#define PER_36XX_FSEL_38P4 0x07 -#define PER_36XX_M2_38P4 0x09 - -/* 36XX PER2 DPLL */ - -#define PER2_36XX_M_12 0x50 -#define PER2_36XX_N_12 0x00 -#define PER2_36XX_M2_12 0x08 - -#define PER2_36XX_M_13 0x1BB -#define PER2_36XX_N_13 0x05 -#define PER2_36XX_M2_13 0x08 - -#define PER2_36XX_M_19P2 0x32 -#define PER2_36XX_N_19P2 0x00 -#define PER2_36XX_M2_19P2 0x08 - -#define PER2_36XX_M_26 0x1BB -#define PER2_36XX_N_26 0x0B -#define PER2_36XX_M2_26 0x08 - -#define PER2_36XX_M_38P4 0x19 -#define PER2_36XX_N_38P4 0x00 -#define PER2_36XX_M2_38P4 0x08 - -#endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h deleted file mode 100644 index 4d06ef83f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h +++ /dev/null @@ -1,511 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -/* Register offsets of common modules */ -/* Control */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct ctrl { - u8 res1[0xC0]; - u16 gpmc_nadv_ale; /* 0xC0 */ - u16 gpmc_noe; /* 0xC2 */ - u16 gpmc_nwe; /* 0xC4 */ - u8 res2[0x22A]; - u32 status; /* 0x2F0 */ - u32 gpstatus; /* 0x2F4 */ - u8 res3[0x08]; - u32 rpubkey_0; /* 0x300 */ - u32 rpubkey_1; /* 0x304 */ - u32 rpubkey_2; /* 0x308 */ - u32 rpubkey_3; /* 0x30C */ - u32 rpubkey_4; /* 0x310 */ - u8 res4[0x04]; - u32 randkey_0; /* 0x318 */ - u32 randkey_1; /* 0x31C */ - u32 randkey_2; /* 0x320 */ - u32 randkey_3; /* 0x324 */ - u8 res5[0x124]; - u32 ctrl_omap_stat; /* 0x44C */ -}; -#else /* __ASSEMBLY__ */ -#define CONTROL_STATUS 0x2F0 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct ctrl_id { - u8 res1[0x4]; - u32 idcode; /* 0x04 */ - u32 prod_id; /* 0x08 */ - u32 sku_id; /* 0x0c */ - u8 res2[0x08]; - u32 die_id_0; /* 0x18 */ - u32 die_id_1; /* 0x1C */ - u32 die_id_2; /* 0x20 */ - u32 die_id_3; /* 0x24 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* device type */ -#define DEVICE_MASK (0x7 << 8) -#define SYSBOOT_MASK 0x1F -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* device speed */ -#define SKUID_CLK_MASK 0xf -#define SKUID_CLK_600MHZ 0x0 -#define SKUID_CLK_720MHZ 0x8 - -#define GPMC_BASE (OMAP34XX_GPMC_BASE) -#define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) - -#ifndef __KERNEL_STRICT_NAMES -#ifdef __ASSEMBLY__ -#define GPMC_CONFIG1 0x00 -#define GPMC_CONFIG2 0x04 -#define GPMC_CONFIG3 0x08 -#define GPMC_CONFIG4 0x0C -#define GPMC_CONFIG5 0x10 -#define GPMC_CONFIG6 0x14 -#define GPMC_CONFIG7 0x18 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* GPMC Mapping */ -#define FLASH_BASE 0x10000000 /* NOR flash, */ - /* aligned to 256 Meg */ -#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ - /* aligned to 64 Meg */ -#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ - /* aligned to 256 Meg */ -#define DEBUG_BASE 0x08000000 /* debug board */ -#define NAND_BASE 0x30000000 /* NAND addr */ - /* (actual size small port) */ -#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -#define ONENAND_MAP 0x20000000 /* OneNand addr */ - /* (actual size small port) */ -/* SMS */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct sms { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x34]; - u32 rg_att0; /* 0x48 */ - u8 res3[0x84]; - u32 class_arb0; /* 0xD0 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define BURSTCOMPLETE_GROUP7 (0x1 << 31) - -/* SDRC */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct sdrc_cs { - u32 mcfg; /* 0x80 || 0xB0 */ - u32 mr; /* 0x84 || 0xB4 */ - u8 res1[0x4]; - u32 emr2; /* 0x8C || 0xBC */ - u8 res2[0x14]; - u32 rfr_ctrl; /* 0x84 || 0xD4 */ - u32 manual; /* 0xA8 || 0xD8 */ - u8 res3[0x4]; -}; - -struct sdrc_actim { - u32 ctrla; /* 0x9C || 0xC4 */ - u32 ctrlb; /* 0xA0 || 0xC8 */ -}; - -struct sdrc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u32 status; /* 0x14 */ - u8 res2[0x28]; - u32 cs_cfg; /* 0x40 */ - u32 sharing; /* 0x44 */ - u8 res3[0x18]; - u32 dlla_ctrl; /* 0x60 */ - u32 dlla_status; /* 0x64 */ - u32 dllb_ctrl; /* 0x68 */ - u32 dllb_status; /* 0x6C */ - u32 power; /* 0x70 */ - u8 res4[0xC]; - struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ -}; - -/* EMIF4 */ -typedef struct emif4 { - unsigned int emif_mod_id_rev; - unsigned int sdram_sts; - unsigned int sdram_config; - unsigned int res1; - unsigned int sdram_refresh_ctrl; - unsigned int sdram_refresh_ctrl_shdw; - unsigned int sdram_time1; - unsigned int sdram_time1_shdw; - unsigned int sdram_time2; - unsigned int sdram_time2_shdw; - unsigned int sdram_time3; - unsigned int sdram_time3_shdw; - unsigned char res2[8]; - unsigned int sdram_pwr_mgmt; - unsigned int sdram_pwr_mgmt_shdw; - unsigned char res3[32]; - unsigned int sdram_iodft_tlgc; - unsigned char res4[128]; - unsigned int ddr_phyctrl1; - unsigned int ddr_phyctrl1_shdw; - unsigned int ddr_phyctrl2; -} emif4_t; - -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define DLLPHASE_90 (0x1 << 1) -#define LOADDLL (0x1 << 2) -#define ENADLL (0x1 << 3) -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) - -#define PAGEPOLICY_HIGH (0x1 << 0) -#define SRFRONRESET (0x1 << 7) -#define PWDNEN (0x1 << 2) -#define WAKEUPPROC (0x1 << 26) - -#define DDR_SDRAM (0x1 << 0) -#define DEEPPD (0x1 << 3) -#define B32NOT16 (0x1 << 4) -#define BANKALLOCATION (0x2 << 6) -#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ -#define ADDRMUXLEGACY (0x1 << 19) -#define CASWIDTH_10BITS (0x5 << 20) -#define RASWIDTH_13BITS (0x2 << 24) -#define BURSTLENGTH4 (0x2 << 0) -#define CASL3 (0x3 << 4) -#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) -#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) -#define ARE_ARCV_1 (0x1 << 0) -#define ARCV (0x4e2 << 8) /* Autorefresh count */ -#define OMAP34XX_SDRC_CS0 0x80000000 -#define OMAP34XX_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET (0x1 << 1) -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -/* DMA */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct dma4_chan { - u32 ccr; - u32 clnk_ctrl; - u32 cicr; - u32 csr; - u32 csdp; - u32 cen; - u32 cfn; - u32 cssa; - u32 cdsa; - u32 csel; - u32 csfl; - u32 cdel; - u32 cdfl; - u32 csac; - u32 cdac; - u32 ccen; - u32 ccfn; - u32 color; -}; - -struct dma4 { - u32 revision; - u8 res1[0x4]; - u32 irqstatus_l[0x4]; - u32 irqenable_l[0x4]; - u32 sysstatus; - u32 ocp_sysconfig; - u8 res2[0x34]; - u32 caps_0; - u8 res3[0x4]; - u32 caps_2; - u32 caps_3; - u32 caps_4; - u32 gcr; - u8 res4[0x4]; - struct dma4_chan chan[32]; -}; - -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* timer regs offsets (32 bit regs) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u32 tistat; /* 0x14 r */ - u32 tisr; /* 0x18 rw */ - u32 tier; /* 0x1c rw */ - u32 twer; /* 0x20 rw */ - u32 tclr; /* 0x24 rw */ - u32 tcrr; /* 0x28 rw */ - u32 tldr; /* 0x2c rw */ - u32 ttgr; /* 0x30 rw */ - u32 twpc; /* 0x34 r*/ - u32 tmar; /* 0x38 rw*/ - u32 tcar1; /* 0x3c r */ - u32 tcicr; /* 0x40 rw */ - u32 tcar2; /* 0x44 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define PRCM_BASE 0x48004000 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct prcm { - u32 fclken_iva2; /* 0x00 */ - u32 clken_pll_iva2; /* 0x04 */ - u8 res1[0x1c]; - u32 idlest_pll_iva2; /* 0x24 */ - u8 res2[0x18]; - u32 clksel1_pll_iva2 ; /* 0x40 */ - u32 clksel2_pll_iva2; /* 0x44 */ - u8 res3[0x8bc]; - u32 clken_pll_mpu; /* 0x904 */ - u8 res4[0x1c]; - u32 idlest_pll_mpu; /* 0x924 */ - u8 res5[0x18]; - u32 clksel1_pll_mpu; /* 0x940 */ - u32 clksel2_pll_mpu; /* 0x944 */ - u8 res6[0xb8]; - u32 fclken1_core; /* 0xa00 */ - u32 res_fclken2_core; - u32 fclken3_core; /* 0xa08 */ - u8 res7[0x4]; - u32 iclken1_core; /* 0xa10 */ - u32 iclken2_core; /* 0xa14 */ - u32 iclken3_core; /* 0xa18 */ - u8 res8[0x24]; - u32 clksel_core; /* 0xa40 */ - u8 res9[0xbc]; - u32 fclken_gfx; /* 0xb00 */ - u8 res10[0xc]; - u32 iclken_gfx; /* 0xb10 */ - u8 res11[0x2c]; - u32 clksel_gfx; /* 0xb40 */ - u8 res12[0xbc]; - u32 fclken_wkup; /* 0xc00 */ - u8 res13[0xc]; - u32 iclken_wkup; /* 0xc10 */ - u8 res14[0xc]; - u32 idlest_wkup; /* 0xc20 */ - u8 res15[0x1c]; - u32 clksel_wkup; /* 0xc40 */ - u8 res16[0xbc]; - u32 clken_pll; /* 0xd00 */ - u32 clken2_pll; /* 0xd04 */ - u8 res17[0x18]; - u32 idlest_ckgen; /* 0xd20 */ - u32 idlest2_ckgen; /* 0xd24 */ - u8 res18[0x18]; - u32 clksel1_pll; /* 0xd40 */ - u32 clksel2_pll; /* 0xd44 */ - u32 clksel3_pll; /* 0xd48 */ - u32 clksel4_pll; /* 0xd4c */ - u32 clksel5_pll; /* 0xd50 */ - u8 res19[0xac]; - u32 fclken_dss; /* 0xe00 */ - u8 res20[0xc]; - u32 iclken_dss; /* 0xe10 */ - u8 res21[0x2c]; - u32 clksel_dss; /* 0xe40 */ - u8 res22[0xbc]; - u32 fclken_cam; /* 0xf00 */ - u8 res23[0xc]; - u32 iclken_cam; /* 0xf10 */ - u8 res24[0x2c]; - u32 clksel_cam; /* 0xf40 */ - u8 res25[0xbc]; - u32 fclken_per; /* 0x1000 */ - u8 res26[0xc]; - u32 iclken_per; /* 0x1010 */ - u8 res27[0x2c]; - u32 clksel_per; /* 0x1040 */ - u8 res28[0xfc]; - u32 clksel1_emu; /* 0x1140 */ - u8 res29[0x2bc]; - u32 fclken_usbhost; /* 0x1400 */ - u8 res30[0xc]; - u32 iclken_usbhost; /* 0x1410 */ -}; -#else /* __ASSEMBLY__ */ -#define CM_CLKSEL_CORE 0x48004a40 -#define CM_CLKSEL_GFX 0x48004b40 -#define CM_CLKSEL_WKUP 0x48004c40 -#define CM_CLKEN_PLL 0x48004d00 -#define CM_CLKSEL1_PLL 0x48004d40 -#define CM_CLKSEL1_EMU 0x48005140 -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define PRM_BASE 0x48306000 - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct prm { - u8 res1[0xd40]; - u32 clksel; /* 0xd40 */ - u8 res2[0x50c]; - u32 rstctrl; /* 0x1250 */ - u8 res3[0x1c]; - u32 clksrc_ctrl; /* 0x1270 */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define PRM_RSTCTRL 0x48307250 -#define PRM_RSTCTRL_RESET 0x04 -#define PRM_RSTST 0x48307258 -#define PRM_RSTST_WARM_RESET_MASK 0x7D2 -#define SYSCLKDIV_1 (0x1 << 6) -#define SYSCLKDIV_2 (0x1 << 7) - -#define CLKSEL_GPT1 (0x1 << 0) - -#define EN_GPT1 (0x1 << 0) -#define EN_32KSYNC (0x1 << 2) - -#define ST_WDT2 (0x1 << 5) - -#define ST_MPU_CLK (0x1 << 0) - -#define ST_CORE_CLK (0x1 << 0) - -#define ST_PERIPH_CLK (0x1 << 1) - -#define ST_IVA2_CLK (0x1 << 0) - -#define RESETDONE (0x1 << 0) - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct pm { - u8 res1[0x48]; - u32 req_info_permission_0; /* 0x48 */ - u8 res2[0x4]; - u32 read_permission_0; /* 0x50 */ - u8 res3[0x4]; - u32 wirte_permission_0; /* 0x58 */ - u8 res4[0x4]; - u32 addr_match_1; /* 0x58 */ - u8 res5[0x4]; - u32 req_info_permission_1; /* 0x68 */ - u8 res6[0x14]; - u32 addr_match_2; /* 0x80 */ -}; -#endif /*__ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - -#define NOT_EARLY 0 - -/* I2C base */ -#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) -#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) -#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) - -/* MUSB base */ -#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) - -/* OMAP3 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0014 -#define OMAP_GPIO_IRQSTATUS1 0x0018 -#define OMAP_GPIO_IRQSTATUS2 0x0028 -#define OMAP_GPIO_IRQENABLE2 0x002c -#define OMAP_GPIO_IRQENABLE1 0x001c -#define OMAP_GPIO_WAKE_EN 0x0020 -#define OMAP_GPIO_CTRL 0x0030 -#define OMAP_GPIO_OE 0x0034 -#define OMAP_GPIO_DATAIN 0x0038 -#define OMAP_GPIO_DATAOUT 0x003c -#define OMAP_GPIO_LEVELDETECT0 0x0040 -#define OMAP_GPIO_LEVELDETECT1 0x0044 -#define OMAP_GPIO_RISINGDETECT 0x0048 -#define OMAP_GPIO_FALLINGDETECT 0x004c -#define OMAP_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP_GPIO_SETIRQENABLE1 0x0064 -#define OMAP_GPIO_CLEARWKUENA 0x0080 -#define OMAP_GPIO_SETWKUENA 0x0084 -#define OMAP_GPIO_CLEARDATAOUT 0x0090 -#define OMAP_GPIO_SETDATAOUT 0x0094 - -#endif /* _CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h deleted file mode 100644 index 5f0ad35d7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __SDMA_H -#define __SDMA_H - -/* Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Functions */ -void omap3_dma_init(void); -int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, - uint32_t sze); -int omap3_dma_start_transfer(uint32_t chan); -int omap3_dma_wait_for_transfer(uint32_t chan); -int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); -int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); - -/* Register settings */ -#define CSDP_DATA_TYPE_8BIT 0x0 -#define CSDP_DATA_TYPE_16BIT 0x1 -#define CSDP_DATA_TYPE_32BIT 0x2 -#define CSDP_SRC_BURST_SINGLE (0x0 << 7) -#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7) -#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7) -#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7) -#define CSDP_DST_BURST_SINGLE (0x0 << 14) -#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14) -#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14) -#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14) -#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18) -#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18) -#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19) -#define CSDP_DST_ENDIAN_BIG (0x1 << 19) -#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20) -#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20) -#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21) -#define CSDP_SRC_ENDIAN_BIG (0x1 << 21) - -#define CCR_READ_PRIORITY_LOW (0x0 << 6) -#define CCR_READ_PRIORITY_HIGH (0x1 << 6) -#define CCR_ENABLE_DISABLED (0x0 << 7) -#define CCR_ENABLE_ENABLE (0x1 << 7) -#define CCR_SRC_AMODE_CONSTANT (0x0 << 12) -#define CCR_SRC_AMODE_POST_INC (0x1 << 12) -#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12) -#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12) -#define CCR_DST_AMODE_CONSTANT (0x0 << 14) -#define CCR_DST_AMODE_POST_INC (0x1 << 14) -#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) -#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) - -#define CCR_RD_ACTIVE_MASK (1 << 9) -#define CCR_WR_ACTIVE_MASK (1 << 10) - -#define CSR_TRANS_ERR (1 << 8) -#define CSR_SUPERVISOR_ERR (1 << 10) -#define CSR_MISALIGNED_ADRS_ERR (1 << 11) - -/* others */ -#define CHAN_NR_MIN 0 -#define CHAN_NR_MAX 31 - -#endif /* __SDMA_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h deleted file mode 100644 index 8bf6b4895..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * Referred to Linux Kernel DSS driver files for OMAP3 by - * Tomi Valkeinen from drivers/video/omap2/dss/ - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 and any - * later version the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef DSS_H -#define DSS_H - -/* DSS Base Registers */ -#define OMAP3_DSS_BASE 0x48050000 -#define OMAP3_DISPC_BASE 0x48050400 -#define OMAP3_VENC_BASE 0x48050C00 - -/* DSS Registers */ -struct dss_regs { - u32 revision; /* 0x00 */ - u8 res1[12]; /* 0x04 */ - u32 sysconfig; /* 0x10 */ - u32 sysstatus; /* 0x14 */ - u32 irqstatus; /* 0x18 */ - u8 res2[36]; /* 0x1C */ - u32 control; /* 0x40 */ - u32 sdi_control; /* 0x44 */ - u32 pll_control; /* 0x48 */ -}; - -/* DISPC Registers */ -struct dispc_regs { - u32 revision; /* 0x00 */ - u8 res1[12]; /* 0x04 */ - u32 sysconfig; /* 0x10 */ - u32 sysstatus; /* 0x14 */ - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res2[32]; /* 0x20 */ - u32 control; /* 0x40 */ - u32 config; /* 0x44 */ - u32 reserve_2; /* 0x48 */ - u32 default_color0; /* 0x4C */ - u32 default_color1; /* 0x50 */ - u32 trans_color0; /* 0x54 */ - u32 trans_color1; /* 0x58 */ - u32 line_status; /* 0x5C */ - u32 line_number; /* 0x60 */ - u32 timing_h; /* 0x64 */ - u32 timing_v; /* 0x68 */ - u32 pol_freq; /* 0x6C */ - u32 divisor; /* 0x70 */ - u32 global_alpha; /* 0x74 */ - u32 size_dig; /* 0x78 */ - u32 size_lcd; /* 0x7C */ - u32 gfx_ba0; /* 0x80 */ - u32 gfx_ba1; /* 0x84 */ - u32 gfx_position; /* 0x88 */ - u32 gfx_size; /* 0x8C */ - u8 unused[16]; /* 0x90 */ - u32 gfx_attributes; /* 0xA0 */ - u32 gfx_fifo_threshold; /* 0xA4 */ - u32 gfx_fifo_size_status; /* 0xA8 */ - u32 gfx_row_inc; /* 0xAC */ - u32 gfx_pixel_inc; /* 0xB0 */ - u32 gfx_window_skip; /* 0xB4 */ - u32 gfx_table_ba; /* 0xB8 */ -}; - -/* VENC Registers */ -struct venc_regs { - u32 rev_id; /* 0x00 */ - u32 status; /* 0x04 */ - u32 f_control; /* 0x08 */ - u32 reserve_1; /* 0x0C */ - u32 vidout_ctrl; /* 0x10 */ - u32 sync_ctrl; /* 0x14 */ - u32 reserve_2; /* 0x18 */ - u32 llen; /* 0x1C */ - u32 flens; /* 0x20 */ - u32 hfltr_ctrl; /* 0x24 */ - u32 cc_carr_wss_carr; /* 0x28 */ - u32 c_phase; /* 0x2C */ - u32 gain_u; /* 0x30 */ - u32 gain_v; /* 0x34 */ - u32 gain_y; /* 0x38 */ - u32 black_level; /* 0x3C */ - u32 blank_level; /* 0x40 */ - u32 x_color; /* 0x44 */ - u32 m_control; /* 0x48 */ - u32 bstamp_wss_data; /* 0x4C */ - u32 s_carr; /* 0x50 */ - u32 line21; /* 0x54 */ - u32 ln_sel; /* 0x58 */ - u32 l21__wc_ctl; /* 0x5C */ - u32 htrigger_vtrigger; /* 0x60 */ - u32 savid__eavid; /* 0x64 */ - u32 flen__fal; /* 0x68 */ - u32 lal__phase_reset; /* 0x6C */ - u32 hs_int_start_stop_x; /* 0x70 */ - u32 hs_ext_start_stop_x; /* 0x74 */ - u32 vs_int_start_x; /* 0x78 */ - u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ - u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ - u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ - u32 vs_ext_stop_y; /* 0x88 */ - u32 reserve_3; /* 0x8C */ - u32 avid_start_stop_x; /* 0x90 */ - u32 avid_start_stop_y; /* 0x94 */ - u32 reserve_4; /* 0x98 */ - u32 reserve_5; /* 0x9C */ - u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ - u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ - u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ - u32 reserve_6; /* 0xAC */ - u32 tvdetgp_int_start_stop_x; /* 0xB0 */ - u32 tvdetgp_int_start_stop_y; /* 0xB4 */ - u32 gen_ctrl; /* 0xB8 */ - u32 reserve_7; /* 0xBC */ - u32 reserve_8; /* 0xC0 */ - u32 output_control; /* 0xC4 */ - u32 dac_b__dac_c; /* 0xC8 */ - u32 height_width; /* 0xCC */ -}; - -/* Few Register Offsets */ -#define TFTSTN_SHIFT 3 -#define DATALINES_SHIFT 8 - -#define GFX_ENABLE 1 -#define GFX_FORMAT_SHIFT 1 -#define LOADMODE_SHIFT 1 - -#define DSS_SOFTRESET (1 << 1) -#define DSS_RESETDONE 1 - -/* Enabling Display controller */ -#define LCD_ENABLE 1 -#define DIG_ENABLE (1 << 1) -#define GO_LCD (1 << 5) -#define GO_DIG (1 << 6) -#define GP_OUT0 (1 << 15) -#define GP_OUT1 (1 << 16) - -/* Configure VENC DSS Params */ -#define VENC_CLK_ENABLE (1 << 3) -#define DAC_DEMEN (1 << 4) -#define DAC_POWERDN (1 << 5) -#define VENC_OUT_SEL (1 << 6) -#define DIG_LPP_SHIFT 16 - -/* LCD display type */ -#define PASSIVE_DISPLAY 0 -#define ACTIVE_DISPLAY 1 - -/* TFTDATALINES */ -#define LCD_INTERFACE_12_BIT 0 -#define LCD_INTERFACE_16_BIT 1 -#define LCD_INTERFACE_18_BIT 2 -#define LCD_INTERFACE_24_BIT 3 - -/* Polarity */ -#define DSS_IVS (1 << 12) -#define DSS_IHS (1 << 13) -#define DSS_IPC (1 << 14) -#define DSS_IEO (1 << 15) -#define DSS_ONOFF (1 << 17) - -/* GFX format */ -#define GFXFORMAT_BITMAP1 (0x0 << 1) -#define GFXFORMAT_BITMAP2 (0x1 << 1) -#define GFXFORMAT_BITMAP4 (0x2 << 1) -#define GFXFORMAT_BITMAP8 (0x3 << 1) -#define GFXFORMAT_RGB12 (0x4 << 1) -#define GFXFORMAT_ARGB16 (0x5 << 1) -#define GFXFORMAT_RGB16 (0x6 << 1) -#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1) -#define GFXFORMAT_RGB24_PACKED (0x9 << 1) -#define GFXFORMAT_ARGB32 (0xC << 1) -#define GFXFORMAT_RGBA32 (0xD << 1) -#define GFXFORMAT_RGBx32 (0xE << 1) - -/* Panel Configuration */ -struct panel_config { - u32 timing_h; - u32 timing_v; - u32 pol_freq; - u32 divisor; - u32 lcd_size; - u32 panel_type; - u32 data_lines; - u32 load_mode; - u32 panel_color; - u32 gfx_format; - void *frame_buffer; -}; - -#define DSS_HBP(bp) (((bp) - 1) << 20) -#define DSS_HFP(fp) (((fp) - 1) << 8) -#define DSS_HSW(sw) ((sw) - 1) -#define DSS_VBP(bp) ((bp) << 20) -#define DSS_VFP(fp) ((fp) << 8) -#define DSS_VSW(sw) ((sw) - 1) - -#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) -#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) -#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1)) - -/* Generic DSS Functions */ -void omap3_dss_venc_config(const struct venc_regs *venc_cfg, - u32 height, u32 width); -void omap3_dss_panel_config(const struct panel_config *panel_cfg); -void omap3_dss_enable(void); - -#endif /* DSS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h deleted file mode 100644 index d96275578..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2011 - * Alexander Holler <holler@ahsoftware.de> - * - * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37 - * - * See there for additional Copyrights. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _OMAP3_EHCI_H_ -#define _OMAP3_EHCI_H_ - -/* USB/EHCI registers */ -#define OMAP_USBTLL_BASE 0x48062000UL -#define OMAP_UHH_BASE 0x48064000UL -#define OMAP_EHCI_BASE 0x48064800UL - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -/* UHH Register Set */ -#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_CACTIVITY | \ - OMAP_UHH_SYSCONFIG_SIDLEMODE | \ - OMAP_UHH_SYSCONFIG_ENAWAKEUP | \ - OMAP_UHH_SYSCONFIG_MIDLEMODE) - -#endif /* _OMAP3_EHCI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h deleted file mode 100644 index 374d82120..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Modifications: - * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. - */ - -#ifndef _AM3517_EMAC_H_ -#define _AM3517_EMAC_H_ - -#define EMAC_BASE_ADDR 0x5C010000 -#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 -#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 -#define EMAC_MDIO_BASE_ADDR 0x5C030000 -#define EMAC_HW_RAM_ADDR 0x01E20000 - -#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ -#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ - -/* SOFTRESET macro definition interferes with emac_regs structure definition */ -#undef SOFTRESET - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#define DAVINCI_EMAC_VERSION2 - -#endif /* _AM3517_EMAC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h deleted file mode 100644 index c8fdf6208..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Auther: - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EMIF_H_ -#define _EMIF_H_ - -/* - * Configuration values - */ -#define EMIF4_TIM1_T_RP (0x3 << 25) -#define EMIF4_TIM1_T_RCD (0x3 << 21) -#define EMIF4_TIM1_T_WR (0x3 << 17) -#define EMIF4_TIM1_T_RAS (0x8 << 12) -#define EMIF4_TIM1_T_RC (0xA << 6) -#define EMIF4_TIM1_T_RRD (0x2 << 3) -#define EMIF4_TIM1_T_WTR (0x2) - -#define EMIF4_TIM2_T_XP (0x2 << 28) -#define EMIF4_TIM2_T_ODT (0x0 << 25) -#define EMIF4_TIM2_T_XSNR (0x1C << 16) -#define EMIF4_TIM2_T_XSRD (0xC8 << 6) -#define EMIF4_TIM2_T_RTP (0x1 << 3) -#define EMIF4_TIM2_T_CKE (0x2) - -#define EMIF4_TIM3_T_RFC (0x25 << 4) -#define EMIF4_TIM3_T_RAS_MAX (0x7) - -#define EMIF4_PWR_IDLE_MODE (0x2 << 30) -#define EMIF4_PWR_DPD_DIS (0x0 << 10) -#define EMIF4_PWR_DPD_EN (0x1 << 10) -#define EMIF4_PWR_LP_MODE (0x0 << 8) -#define EMIF4_PWR_PM_TIM (0x0) - -#define EMIF4_INITREF_DIS (0x0 << 31) -#define EMIF4_REFRESH_RATE (0x50F) - -#define EMIF4_CFG_SDRAM_TYP (0x2 << 29) -#define EMIF4_CFG_IBANK_POS (0x0 << 27) -#define EMIF4_CFG_DDR_TERM (0x0 << 24) -#define EMIF4_CFG_DDR2_DDQS (0x1 << 23) -#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20) -#define EMIF4_CFG_SDR_DRV (0x0 << 18) -#define EMIF4_CFG_NARROW_MD (0x0 << 14) -#define EMIF4_CFG_CL (0x5 << 10) -#define EMIF4_CFG_ROWSIZE (0x0 << 7) -#define EMIF4_CFG_IBANK (0x3 << 4) -#define EMIF4_CFG_EBANK (0x0 << 3) -#define EMIF4_CFG_PGSIZE (0x2) - -/* - * EMIF4 PHY Control 1 register configuration - */ -#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7) -#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7) -#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6) -#define EMIF4_DDR1_PWRDN_EN (0x1 << 6) -#define EMIF4_DDR1_READ_LAT (0x6 << 0) - -#endif /* endif _EMIF_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h deleted file mode 100644 index f664c1199..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0 - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP3_H -#define _GPIO_OMAP3_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 192 - -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - -#endif /* _GPIO_OMAP3_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h deleted file mode 100644 index b3702909c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _OMAP3_I2C_H_ -#define _OMAP3_I2C_H_ - -#define I2C_BUS_MAX 3 -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short iv; /* 0x0C */ - unsigned short res4; - unsigned short syss; /* 0x10 */ - unsigned short res4a; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; -}; - -#endif /* _OMAP3_I2C_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h deleted file mode 100644 index 18041913c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -#define CS0 0x0 -#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -}; -#endif /* __ASSEMBLY__ */ - -#define EARLY_INIT 1 - -/* - * For a full explanation of these registers and values please see - * the Technical Reference Manual (TRM) for any of the processors in - * this family. - */ - -/* Slower full frequency range default timings for x32 operation*/ -#define SDRC_SHARING 0x00000100 -#define SDRC_MR_0_SDR 0x00000031 - -/* - * SDRC autorefresh control values. This register consists of autorefresh - * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The - * counter is a result of ( tREFI / tCK ) - 50. - */ -#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ -#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -/* rkw - need to find of 90/72 degree recommendation for speed like before */ -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ -#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ -#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ -#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ -#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ -#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ -#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ -#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ -#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ - -#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ - ACTIM_CTRLA_TRFC(trfc) | \ - ACTIM_CTRLA_TRC(trc) | \ - ACTIM_CTRLA_TRAS(tras) | \ - ACTIM_CTRLA_TRP(trp) | \ - ACTIM_CTRLA_TRCD(trcd) | \ - ACTIM_CTRLA_TRRD(trrd) | \ - ACTIM_CTRLA_TDPL(tdpl) | \ - ACTIM_CTRLA_TDAL(tdal) - -/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ -#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ -#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ -#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ -#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ - -#define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ - ACTIM_CTRLB_TWTR(twtr) | \ - ACTIM_CTRLB_TCKE(tcke) | \ - ACTIM_CTRLB_TXP(txp) | \ - ACTIM_CTRLB_TXSR(txsr) - -/* - * Values used in the MCFG register. Only values we use today - * are defined and the rest can be found in the TRM. Unless otherwise - * noted all fields are one bit. - */ -#define V_MCFG_RAMTYPE_DDR (0x1) -#define V_MCFG_DEEPPD_EN (0x1 << 3) -#define V_MCFG_B32NOT16_32 (0x1 << 4) -#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ -#define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */ -#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) -#define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */ -#define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10) -#define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */ - -/* Macro to construct MCFG */ -#define MCFG(ramsize, raswidth) \ - V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \ - V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \ - V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \ - V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR - -/* Hynix part of Overo (165MHz optimized) 6.06ns */ -#define HYNIX_TDAL_165 6 -#define HYNIX_TDPL_165 3 -#define HYNIX_TRRD_165 2 -#define HYNIX_TRCD_165 3 -#define HYNIX_TRP_165 3 -#define HYNIX_TRAS_165 7 -#define HYNIX_TRC_165 10 -#define HYNIX_TRFC_165 21 -#define HYNIX_V_ACTIMA_165 \ - ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ - HYNIX_TRAS_165, HYNIX_TRP_165, \ - HYNIX_TRCD_165, HYNIX_TRRD_165, \ - HYNIX_TDPL_165, HYNIX_TDAL_165) - -#define HYNIX_TWTR_165 1 -#define HYNIX_TCKE_165 1 -#define HYNIX_TXP_165 2 -#define HYNIX_XSR_165 24 -#define HYNIX_V_ACTIMB_165 \ - ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ - HYNIX_TXP_165, HYNIX_XSR_165) - -#define HYNIX_RASWIDTH_165 13 -#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) - -/* Hynix part of AM/DM37xEVM (200MHz optimized) */ -#define HYNIX_TDAL_200 6 -#define HYNIX_TDPL_200 3 -#define HYNIX_TRRD_200 2 -#define HYNIX_TRCD_200 4 -#define HYNIX_TRP_200 3 -#define HYNIX_TRAS_200 8 -#define HYNIX_TRC_200 11 -#define HYNIX_TRFC_200 18 -#define HYNIX_V_ACTIMA_200 \ - ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ - HYNIX_TRAS_200, HYNIX_TRP_200, \ - HYNIX_TRCD_200, HYNIX_TRRD_200, \ - HYNIX_TDPL_200, HYNIX_TDAL_200) - -#define HYNIX_TWTR_200 2 -#define HYNIX_TCKE_200 1 -#define HYNIX_TXP_200 1 -#define HYNIX_XSR_200 28 -#define HYNIX_V_ACTIMB_200 \ - ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ - HYNIX_TXP_200, HYNIX_XSR_200) - -#define HYNIX_RASWIDTH_200 14 -#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) - -/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ -#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define INFINEON_TRRD_165 2 /* 12/6 = 2 */ -#define INFINEON_TRCD_165 3 /* 18/6 = 3 */ -#define INFINEON_TRP_165 3 /* 18/6 = 3 */ -#define INFINEON_TRAS_165 7 /* 42/6 = 7 */ -#define INFINEON_TRC_165 10 /* 60/6 = 10 */ -#define INFINEON_TRFC_165 12 /* 72/6 = 12 */ - -#define INFINEON_V_ACTIMA_165 \ - ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ - INFINEON_TRAS_165, INFINEON_TRP_165, \ - INFINEON_TRCD_165, INFINEON_TRRD_165, \ - INFINEON_TDPL_165, INFINEON_TDAL_165) - -#define INFINEON_TWTR_165 1 -#define INFINEON_TCKE_165 2 -#define INFINEON_TXP_165 2 -#define INFINEON_XSR_165 20 /* 120/6 = 20 */ - -#define INFINEON_V_ACTIMB_165 \ - ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ - INFINEON_TXP_165, INFINEON_XSR_165) - -/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ -#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define MICRON_TRRD_165 2 /* 12/6 = 2 */ -#define MICRON_TRCD_165 3 /* 18/6 = 3 */ -#define MICRON_TRP_165 3 /* 18/6 = 3 */ -#define MICRON_TRAS_165 7 /* 42/6 = 7 */ -#define MICRON_TRC_165 10 /* 60/6 = 10 */ -#define MICRON_TRFC_165 21 /* 125/6 = 21 */ - -#define MICRON_V_ACTIMA_165 \ - ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ - MICRON_TRAS_165, MICRON_TRP_165, \ - MICRON_TRCD_165, MICRON_TRRD_165, \ - MICRON_TDPL_165, MICRON_TDAL_165) - -#define MICRON_TWTR_165 1 -#define MICRON_TCKE_165 1 -#define MICRON_XSR_165 23 /* 138/6 = 23 */ -#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ - -#define MICRON_V_ACTIMB_165 \ - ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ - MICRON_TXP_165, MICRON_XSR_165) - -#define MICRON_RASWIDTH_165 13 -#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) - -#define MICRON_BL_165 0x2 -#define MICRON_SIL_165 0x0 -#define MICRON_CASL_165 0x3 -#define MICRON_WBST_165 0x0 -#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ - (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ - (MICRON_BL_165)) - -/* Micron part (200MHz optimized) 5 ns */ -#define MICRON_TDAL_200 6 -#define MICRON_TDPL_200 3 -#define MICRON_TRRD_200 2 -#define MICRON_TRCD_200 3 -#define MICRON_TRP_200 3 -#define MICRON_TRAS_200 8 -#define MICRON_TRC_200 11 -#define MICRON_TRFC_200 15 -#define MICRON_V_ACTIMA_200 \ - ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ - MICRON_TRAS_200, MICRON_TRP_200, \ - MICRON_TRCD_200, MICRON_TRRD_200, \ - MICRON_TDPL_200, MICRON_TDAL_200) - -#define MICRON_TWTR_200 2 -#define MICRON_TCKE_200 4 -#define MICRON_TXP_200 2 -#define MICRON_XSR_200 23 -#define MICRON_V_ACTIMB_200 \ - ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ - MICRON_TXP_200, MICRON_XSR_200) - -#define MICRON_RASWIDTH_200 14 -#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) - -/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ -#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ - /* 15/6 + 18/6 = 5.5 -> 6 */ -#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ -#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ -#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ -#define NUMONYX_TRP_165 3 /* 18/6 = 3 */ -#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ -#define NUMONYX_TRC_165 10 /* 60/6 = 10 */ -#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ - -#define NUMONYX_V_ACTIMA_165 \ - ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ - NUMONYX_TRAS_165, NUMONYX_TRP_165, \ - NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ - NUMONYX_TDPL_165, NUMONYX_TDAL_165) - -#define NUMONYX_TWTR_165 2 -#define NUMONYX_TCKE_165 2 -#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ -#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ - -#define NUMONYX_V_ACTIMB_165 \ - ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ - NUMONYX_TXP_165, NUMONYX_XSR_165) - -#define NUMONYX_RASWIDTH_165 15 -#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) - -/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */ -#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */ - /* 15/5 + 15/5 = 3 + 3 -> 6 */ -#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */ -#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */ -#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */ -#define NUMONYX_TRP_200 3 /* 15/5 = 3 */ -#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */ -#define NUMONYX_TRC_200 11 /* 55/5 = 11 */ -#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */ - -#define NUMONYX_V_ACTIMA_200 \ - ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \ - NUMONYX_TRAS_200, NUMONYX_TRP_200, \ - NUMONYX_TRCD_200, NUMONYX_TRRD_200, \ - NUMONYX_TDPL_200, NUMONYX_TDAL_200) - -#define NUMONYX_TWTR_200 2 -#define NUMONYX_TCKE_200 2 -#define NUMONYX_TXP_200 3 -#define NUMONYX_XSR_200 40 - -#define NUMONYX_V_ACTIMB_200 \ - ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \ - NUMONYX_TXP_200, NUMONYX_XSR_200) - -#define NUMONYX_RASWIDTH_200 15 -#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200) - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * MNAND - Micron Large page x16 NAND - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP34XX_GPMC_CSx PART - * #define OMAP34XX_GPMC_CSx_SIZE Size - * #define OMAP34XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define GPMC_BASEADDR_MASK 0x3F - -#define GPMC_CS_ENABLE 0x1 - -#define SMNAND_GPMC_CONFIG1 0x00000800 -#define SMNAND_GPMC_CONFIG2 0x00141400 -#define SMNAND_GPMC_CONFIG3 0x00141400 -#define SMNAND_GPMC_CONFIG4 0x0F010F01 -#define SMNAND_GPMC_CONFIG5 0x010C1414 -#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -#define SMNAND_GPMC_CONFIG7 0x00000C44 - -#define M_NAND_GPMC_CONFIG1 0x00001800 -#define M_NAND_GPMC_CONFIG2 0x00141400 -#define M_NAND_GPMC_CONFIG3 0x00141400 -#define M_NAND_GPMC_CONFIG4 0x0F010F01 -#define M_NAND_GPMC_CONFIG5 0x010C1414 -#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 -#define M_NAND_GPMC_CONFIG7 0x00000C44 - -#define STNOR_GPMC_CONFIG1 0x3 -#define STNOR_GPMC_CONFIG2 0x00151501 -#define STNOR_GPMC_CONFIG3 0x00060602 -#define STNOR_GPMC_CONFIG4 0x11091109 -#define STNOR_GPMC_CONFIG5 0x01141F1F -#define STNOR_GPMC_CONFIG6 0x000004c4 - -#define SIBNOR_GPMC_CONFIG1 0x1200 -#define SIBNOR_GPMC_CONFIG2 0x001f1f00 -#define SIBNOR_GPMC_CONFIG3 0x00080802 -#define SIBNOR_GPMC_CONFIG4 0x1C091C09 -#define SIBNOR_GPMC_CONFIG5 0x01131F1F -#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -#define MPDB_GPMC_CONFIG1 0x00011000 -#define MPDB_GPMC_CONFIG2 0x001f1f01 -#define MPDB_GPMC_CONFIG3 0x00080803 -#define MPDB_GPMC_CONFIG4 0x1c0b1c0a -#define MPDB_GPMC_CONFIG5 0x041f1F1F -#define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -#define P2_GPMC_CONFIG1 0x0 -#define P2_GPMC_CONFIG2 0x0 -#define P2_GPMC_CONFIG3 0x0 -#define P2_GPMC_CONFIG4 0x0 -#define P2_GPMC_CONFIG5 0x0 -#define P2_GPMC_CONFIG6 0x0 - -#define ONENAND_GPMC_CONFIG1 0x00001200 -#define ONENAND_GPMC_CONFIG2 0x000F0F01 -#define ONENAND_GPMC_CONFIG3 0x00030301 -#define ONENAND_GPMC_CONFIG4 0x0F040F04 -#define ONENAND_GPMC_CONFIG5 0x010F1010 -#define ONENAND_GPMC_CONFIG6 0x1F060000 - -#define NET_GPMC_CONFIG1 0x00001000 -#define NET_GPMC_CONFIG2 0x001e1e01 -#define NET_GPMC_CONFIG3 0x00080300 -#define NET_GPMC_CONFIG4 0x1c091c09 -#define NET_GPMC_CONFIG5 0x04181f1f -#define NET_GPMC_CONFIG6 0x00000FCF -#define NET_GPMC_CONFIG7 0x00000f6c - -/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ -#define NET_LAN9221_GPMC_CONFIG1 0x00001000 -#define NET_LAN9221_GPMC_CONFIG2 0x00060700 -#define NET_LAN9221_GPMC_CONFIG3 0x00020201 -#define NET_LAN9221_GPMC_CONFIG4 0x06000700 -#define NET_LAN9221_GPMC_CONFIG5 0x0006090A -#define NET_LAN9221_GPMC_CONFIG6 0x87030000 -#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE - -#ifndef __ASSEMBLY__ - -/* Function prototypes */ -void mem_init(void); - -u32 is_mem_sdr(void); -u32 mem_ok(u32 cs); - -u32 get_sdr_cs_size(u32); -u32 get_sdr_cs_offset(u32); - -#endif /* __ASSEMBLY__ */ - -#endif /* endif _MEM_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h deleted file mode 100644 index 0ba621a1b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* T2 Register definitions */ -#define T2_BASE 0x48002000 - -typedef struct t2 { - unsigned char res1[0x274]; /* 0x000 */ - unsigned int devconf0; /* 0x274 */ - unsigned char res2[0x060]; /* 0x278 */ - unsigned int devconf1; /* 0x2D8 */ - unsigned char res3[0x16C]; /* 0x2DC */ - unsigned int ctl_prog_io1; /* 0x448 */ - unsigned char res4[0x0D4]; /* 0x44C */ - unsigned int pbias_lite; /* 0x520 */ -} t2_t; - -#define MMCSDIO1ADPCLKISEL (1 << 24) -#define MMCSDIO2ADPCLKISEL (1 << 6) - -#define EN_MMC1 (1 << 24) -#define EN_MMC2 (1 << 25) -#define EN_MMC3 (1 << 30) - -#define PBIASLITEPWRDNZ0 (1 << 1) -#define PBIASSPEEDCTRL0 (1 << 2) -#define PBIASLITEPWRDNZ1 (1 << 9) - -#define CTLPROGIO1SPEEDCTRL (1 << 20) - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC1_BASE 0x4809C000 -#define OMAP_HSMMC2_BASE 0x480B4000 -#define OMAP_HSMMC3_BASE 0x480AD000 - - -#endif /* MMC_HOST_DEF_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h deleted file mode 100644 index cee4ed311..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2012 - * Ilya Yanok, <ilya.yanok@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_OMAP3_MUSB_H -#define __ASM_ARCH_OMAP3_MUSB_H -extern void am35x_musb_reset(void); -extern void am35x_musb_phy_power(u8 on); -extern void am35x_musb_clear_irq(void); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h deleted file mode 100644 index 2f8320629..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _MUX_H_ -#define _MUX_H_ - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - */ - -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -/* - * To get the actual address the offset has to added - * with OMAP34XX_CTRL_BASE to get the actual address - */ - -/*SDRC*/ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -/*GPMC*/ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_NCS0 0x00AE -#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_NCS6 0x00BA -#define CONTROL_PADCONF_GPMC_NCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_NOE 0x00C2 -#define CONTROL_PADCONF_GPMC_NWE 0x00C4 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_NWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/*DSS*/ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/*CAMERA*/ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/*Audio Interface */ -#define CONTROL_PADCONF_MCBSP2_FSX 0x013C -#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E -#define CONTROL_PADCONF_MCBSP2_DR 0x0140 -#define CONTROL_PADCONF_MCBSP2_DX 0x0142 -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/*Wireless LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/*Bluetooth*/ -#define CONTROL_PADCONF_MCBSP3_DX 0x016C -#define CONTROL_PADCONF_MCBSP3_DR 0x016E -#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/*Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_MCBSP4_DR 0x0186 -#define CONTROL_PADCONF_MCBSP4_DX 0x0188 -#define CONTROL_PADCONF_MCBSP4_FSX 0x018A -#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C -#define CONTROL_PADCONF_MCBSP1_FSR 0x018E -#define CONTROL_PADCONF_MCBSP1_DX 0x0190 -#define CONTROL_PADCONF_MCBSP1_DR 0x0192 -#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 -#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 -#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 -/*Serial Interface*/ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE -#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC -#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE -/*Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA -/*Die to Die */ -#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 -#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 -#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 -#define CONTROL_PADCONF_D2D_MCAD3 0x01EA -#define CONTROL_PADCONF_D2D_MCAD4 0x01EC -#define CONTROL_PADCONF_D2D_MCAD5 0x01EE -#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 -#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 -#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 -#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 -#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 -#define CONTROL_PADCONF_D2D_MCAD11 0x01FA -#define CONTROL_PADCONF_D2D_MCAD12 0x01FC -#define CONTROL_PADCONF_D2D_MCAD13 0x01FE -#define CONTROL_PADCONF_D2D_MCAD14 0x0200 -#define CONTROL_PADCONF_D2D_MCAD15 0x0202 -#define CONTROL_PADCONF_D2D_MCAD16 0x0204 -#define CONTROL_PADCONF_D2D_MCAD17 0x0206 -#define CONTROL_PADCONF_D2D_MCAD18 0x0208 -#define CONTROL_PADCONF_D2D_MCAD19 0x020A -#define CONTROL_PADCONF_D2D_MCAD20 0x020C -#define CONTROL_PADCONF_D2D_MCAD21 0x020E -#define CONTROL_PADCONF_D2D_MCAD22 0x0210 -#define CONTROL_PADCONF_D2D_MCAD23 0x0212 -#define CONTROL_PADCONF_D2D_MCAD24 0x0214 -#define CONTROL_PADCONF_D2D_MCAD25 0x0216 -#define CONTROL_PADCONF_D2D_MCAD26 0x0218 -#define CONTROL_PADCONF_D2D_MCAD27 0x021A -#define CONTROL_PADCONF_D2D_MCAD28 0x021C -#define CONTROL_PADCONF_D2D_MCAD29 0x021E -#define CONTROL_PADCONF_D2D_MCAD30 0x0220 -#define CONTROL_PADCONF_D2D_MCAD31 0x0222 -#define CONTROL_PADCONF_D2D_MCAD32 0x0224 -#define CONTROL_PADCONF_D2D_MCAD33 0x0226 -#define CONTROL_PADCONF_D2D_MCAD34 0x0228 -#define CONTROL_PADCONF_D2D_MCAD35 0x022A -#define CONTROL_PADCONF_D2D_MCAD36 0x022C -#define CONTROL_PADCONF_D2D_CLK26MI 0x022E -#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 -#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 -#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 -#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 -#define CONTROL_PADCONF_D2D_SPINT 0x0238 -#define CONTROL_PADCONF_D2D_FRINT 0x023A -#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C -#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E -#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 -#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 -#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 -#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 -#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 -#define CONTROL_PADCONF_D2D_N3GTMS 0x024A -#define CONTROL_PADCONF_D2D_N3GTCK 0x024C -#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E -#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 -#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C -#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 -#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 -#define CONTROL_PADCONF_D2D_MWRITE 0x0256 -#define CONTROL_PADCONF_D2D_SWRITE 0x0258 -#define CONTROL_PADCONF_D2D_MREAD 0x025A -#define CONTROL_PADCONF_D2D_SREAD 0x025C -#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E -#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 -#define CONTROL_PADCONF_SDRC_CKE0 0x0262 -#define CONTROL_PADCONF_SDRC_CKE1 0x0264 - -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 - -/* AM/DM37xx specific */ -#define CONTROL_PADCONF_GPIO127 0x0A54 -#define CONTROL_PADCONF_GPIO126 0x0A56 -#define CONTROL_PADCONF_GPIO128 0x0A58 -#define CONTROL_PADCONF_GPIO129 0x0A5A - -/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration - * of the extended drain cells */ -#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) -#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) - -#define MUX_VAL(OFFSET,VALUE)\ - writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h deleted file mode 100644 index 002ef7e79..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _OMAP3_REGS_H -#define _OMAP3_REGS_H - -/* - * Register definitions for OMAP3 processors. - */ - -/* - * GPMC_CONFIG1 - GPMC_CONFIG7 - */ - -/* Values for GPMC_CONFIG1 - signal control parameters */ -#define WRAPBURST (1 << 31) -#define READMULTIPLE (1 << 30) -#define READTYPE (1 << 29) -#define WRITEMULTIPLE (1 << 28) -#define WRITETYPE (1 << 27) -#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) -#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) -#define WAITREADMONITORING (1 << 22) -#define WAITWRITEMONITORING (1 << 21) -#define WAITMONITORINGTIME(x) (((x) & 3) << 18) -#define WAITPINSELECT(x) (((x) & 3) << 16) -#define DEVICESIZE(x) (((x) & 3) << 12) -#define DEVICESIZE_8BIT DEVICESIZE(0) -#define DEVICESIZE_16BIT DEVICESIZE(1) -#define DEVICETYPE(x) (((x) & 3) << 10) -#define DEVICETYPE_NOR DEVICETYPE(0) -#define DEVICETYPE_NAND DEVICETYPE(2) -#define MUXADDDATA (1 << 9) -#define TIMEPARAGRANULARITY (1 << 4) -#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) - -/* Values for GPMC_CONFIG2 - CS timing */ -#define CSWROFFTIME(x) (((x) & 0x1f) << 16) -#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) -#define CSEXTRADELAY (1 << 7) -#define CSONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG3 - nADV timing */ -#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) -#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) -#define ADVEXTRADELAY (1 << 7) -#define ADVONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG4 - nWE and nOE timing */ -#define WEOFFTIME(x) (((x) & 0x1f) << 24) -#define WEEXTRADELAY (1 << 23) -#define WEONTIME(x) (((x) & 0xf) << 16) -#define OEOFFTIME(x) (((x) & 0x1f) << 8) -#define OEEXTRADELAY (1 << 7) -#define OEONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ -#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) -#define RDACCESSTIME(x) (((x) & 0x1f) << 16) -#define WRCYCLETIME(x) (((x) & 0x1f) << 8) -#define RDCYCLETIME(x) (((x) & 0x1f) << 0) - -/* Values for GPMC_CONFIG6 - misc timings */ -#define WRACCESSTIME(x) (((x) & 0x1f) << 24) -#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) -#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) -#define CYCLE2CYCLESAMECSEN (1 << 7) -#define CYCLE2CYCLEDIFFCSEN (1 << 6) -#define BUSTURNAROUND(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG7 - CS address mapping configuration */ -#define MASKADDRESS(x) (((x) & 0xf) << 8) -#define CSVALID (1 << 6) -#define BASEADDRESS(x) (((x) & 0x3f) << 0) - -#endif /* _OMAP3_REGS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3.h deleted file mode 100644 index 194b93bf5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _OMAP3_H_ -#define _OMAP3_H_ - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* GPMC */ -#define OMAP34XX_GPMC_BASE 0x6E000000 - -/* SMS */ -#define OMAP34XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP34XX_SDRC_BASE 0x6D000000 - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 -#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 -#define OMAP34XX_ID_L4_IO_BASE 0x4830A200 -#define OMAP34XX_L4_PER 0x49000000 -#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE - -/* DMA4/SDMA */ -#define OMAP34XX_DMA4_BASE 0x48056000 - -/* CONTROL */ -#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) - -#ifndef __ASSEMBLY__ -/* Signal Integrity Parameter Control Registers */ -struct control_prog_io { - unsigned char res[0x408]; - unsigned int io2; /* 0x408 */ - unsigned char res2[0x38]; - unsigned int io0; /* 0x444 */ - unsigned int io1; /* 0x448 */ -}; -#endif /* __ASSEMBLY__ */ - -/* Bit definition for CONTROL_PROG_IO1 */ -#define PRG_I2C2_PULLUPRESX 0x00000001 - -/* UART */ -#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) -#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) -#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) -#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) - -/* General Purpose Timers */ -#define OMAP34XX_GPT1 0x48318000 -#define OMAP34XX_GPT2 0x49032000 -#define OMAP34XX_GPT3 0x49034000 -#define OMAP34XX_GPT4 0x49036000 -#define OMAP34XX_GPT5 0x49038000 -#define OMAP34XX_GPT6 0x4903A000 -#define OMAP34XX_GPT7 0x4903C000 -#define OMAP34XX_GPT8 0x4903E000 -#define OMAP34XX_GPT9 0x49040000 -#define OMAP34XX_GPT10 0x48086000 -#define OMAP34XX_GPT11 0x48088000 -#define OMAP34XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x4830C000 -#define WD2_BASE 0x48314000 -#define WD3_BASE 0x49030000 - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE 0x48320000 - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#endif /* __ASSEMBLY__ */ - -#ifndef __ASSEMBLY__ -struct gpio { - unsigned char res1[0x34]; - unsigned int oe; /* 0x34 */ - unsigned int datain; /* 0x38 */ - unsigned char res2[0x54]; - unsigned int cleardataout; /* 0x90 */ - unsigned int setdataout; /* 0x94 */ -}; -#endif /* __ASSEMBLY__ */ - -#define GPIO0 (0x1 << 0) -#define GPIO1 (0x1 << 1) -#define GPIO2 (0x1 << 2) -#define GPIO3 (0x1 << 3) -#define GPIO4 (0x1 << 4) -#define GPIO5 (0x1 << 5) -#define GPIO6 (0x1 << 6) -#define GPIO7 (0x1 << 7) -#define GPIO8 (0x1 << 8) -#define GPIO9 (0x1 << 9) -#define GPIO10 (0x1 << 10) -#define GPIO11 (0x1 << 11) -#define GPIO12 (0x1 << 12) -#define GPIO13 (0x1 << 13) -#define GPIO14 (0x1 << 14) -#define GPIO15 (0x1 << 15) -#define GPIO16 (0x1 << 16) -#define GPIO17 (0x1 << 17) -#define GPIO18 (0x1 << 18) -#define GPIO19 (0x1 << 19) -#define GPIO20 (0x1 << 20) -#define GPIO21 (0x1 << 21) -#define GPIO22 (0x1 << 22) -#define GPIO23 (0x1 << 23) -#define GPIO24 (0x1 << 24) -#define GPIO25 (0x1 << 25) -#define GPIO26 (0x1 << 26) -#define GPIO27 (0x1 << 27) -#define GPIO28 (0x1 << 28) -#define GPIO29 (0x1 << 29) -#define GPIO30 (0x1 << 30) -#define GPIO31 (0x1 << 31) - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ - SRAM_OFFSET2) -#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64) - -#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */ -#define NON_SECURE_SRAM_END 0x40210000 - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -/* scratch area - accessible on both EMU and GP */ -#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START - -#define DEBUG_LED1 149 /* gpio */ -#define DEBUG_LED2 150 /* gpio */ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module */ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -/* - * 343x real hardware: - * ES1 = rev 0 - * - * ES2 onwards, the value maps to contents of IDCODE register [31:28]. - * - * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. - */ -#define CPU_3XX_ES10 0 -#define CPU_3XX_ES20 1 -#define CPU_3XX_ES21 2 -#define CPU_3XX_ES30 3 -#define CPU_3XX_ES31 4 -#define CPU_3XX_ES312 7 -#define CPU_3XX_MAX_REV 8 - -/* - * 37xx real hardware: - * ES1.0 onwards, the value maps to contents of IDCODE register [31:28]. - */ - -#define CPU_37XX_ES10 0 -#define CPU_37XX_ES11 1 -#define CPU_37XX_ES12 2 -#define CPU_37XX_MAX_REV 3 - -#define CPU_3XX_ID_SHIFT 28 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -/* - * Hawkeye values - */ -#define HAWKEYE_OMAP34XX 0xb7ae -#define HAWKEYE_AM35XX 0xb868 -#define HAWKEYE_OMAP36XX 0xb891 - -#define HAWKEYE_SHIFT 12 - -/* - * Define CPU families - */ -#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ -#define CPU_AM35XX 0x3500 /* AM35xx devices */ -#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ - -/* - * Control status register values corresponding to cpu variants - */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - -#define AM3505 0x5c00 -#define AM3517 0x1c00 - -#define OMAP3730 0x0c00 - -/* - * ROM code API related flags - */ -#define OMAP3_GP_ROMCODE_API_L2_INVAL 1 -#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 - -/* - * EMU device PPA HAL related flags - */ -#define OMAP3_EMU_HAL_API_L2_INVAL 40 -#define OMAP3_EMU_HAL_API_WRITE_ACR 42 - -#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 30 -#define OMAP_ABB_CLOCK_CYCLES 8 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h deleted file mode 100644 index 835053278..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_ONENAND 3 -#define BOOT_DEVICE_MMC2 5 /*emmc*/ -#define BOOT_DEVICE_MMC1 6 -#define BOOT_DEVICE_XIPWAIT 7 -#define BOOT_DEVICE_MMC2_2 0xFF - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h deleted file mode 100644 index 5866bf23e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ -#include <linux/mtd/omap_gpmc.h> -#include <asm/omap_common.h> - -typedef struct { - u32 mtype; - char *board_string; - char *nand_string; -} omap3_sysinfo; - -struct emu_hal_params { - u32 num_params; - u32 param1; -}; - -/* Board SDRC timing values */ -struct board_sdrc_timings { - u32 mcfg; - u32 ctrla; - u32 ctrlb; - u32 rfr_ctrl; - u32 mr; -}; - -void prcm_init(void); -void per_clocks_enable(void); -void ehci_clocks_enable(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32, u32); - -void get_board_mem_timings(struct board_sdrc_timings *timings); -void identify_nand_chip(int *mfr, int *id); -void emif4_init(void); -void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size); - -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_family(void); -u32 get_cpu_rev(void); -u32 get_sku_id(void); -u32 get_sysboot_value(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 is_running_in_sdram(void); -u32 is_running_in_sram(void); -u32 is_running_in_flash(void); -u32 get_device_type(void); -void secureworld_exit(void); -void try_unlock_memory(void); -u32 get_boot_type(void); -void invalidate_dcache(u32); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void make_cs1_contiguous(void); -void omap_nand_switch_ecc(uint32_t, uint32_t); -void power_init_r(void); -void dieid_num_r(void); -void get_dieid(u32 *id); -void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); -u32 warm_reset(void); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h deleted file mode 100644 index f3a682a19..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _CLOCKS_OMAP4_H_ -#define _CLOCKS_OMAP4_H_ -#include <common.h> -#include <asm/omap_common.h> - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* PMIC */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -/* TWL6030 SMPS */ -#define SMPS_REG_ADDR_VCORE1 0x55 -#define SMPS_REG_ADDR_VCORE2 0x5B -#define SMPS_REG_ADDR_VCORE3 0x61 -/* TWL6032 SMPS */ -#define SMPS_REG_ADDR_SMPS1 0x55 -#define SMPS_REG_ADDR_SMPS2 0x5B -#define SMPS_REG_ADDR_SMPS5 0x49 - -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - -#define AUXCLK_CLKDIV_2 1 -#define AUXCLK_CLKDIV_16 0xF - -/* ALTCLKSRC */ -#define ALTCLKSRC_MODE_MASK 3 -#define ALTCLKSRC_ENABLE_INT_MASK 4 -#define ALTCLKSRC_ENABLE_EXT_MASK 8 - -#define ALTCLKSRC_MODE_ACTIVE 1 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -/* Clock Defines */ -#define V_OSCK 38400000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -struct omap4_scrm_regs { - u32 revision; /* 0x0000 */ - u32 pad00[63]; - u32 clksetuptime; /* 0x0100 */ - u32 pmicsetuptime; /* 0x0104 */ - u32 pad01[2]; - u32 altclksrc; /* 0x0110 */ - u32 pad02[2]; - u32 c2cclkm; /* 0x011c */ - u32 pad03[56]; - u32 extclkreq; /* 0x0200 */ - u32 accclkreq; /* 0x0204 */ - u32 pwrreq; /* 0x0208 */ - u32 pad04[1]; - u32 auxclkreq0; /* 0x0210 */ - u32 auxclkreq1; /* 0x0214 */ - u32 auxclkreq2; /* 0x0218 */ - u32 auxclkreq3; /* 0x021c */ - u32 auxclkreq4; /* 0x0220 */ - u32 auxclkreq5; /* 0x0224 */ - u32 pad05[3]; - u32 c2cclkreq; /* 0x0234 */ - u32 pad06[54]; - u32 auxclk0; /* 0x0310 */ - u32 auxclk1; /* 0x0314 */ - u32 auxclk2; /* 0x0318 */ - u32 auxclk3; /* 0x031c */ - u32 auxclk4; /* 0x0320 */ - u32 auxclk5; /* 0x0324 */ - u32 pad07[54]; - u32 rsttime_reg; /* 0x0400 */ - u32 pad08[6]; - u32 c2crstctrl; /* 0x041c */ - u32 extpwronrstctrl; /* 0x0420 */ - u32 pad09[59]; - u32 extwarmrstst_reg; /* 0x0510 */ - u32 apewarmrstst_reg; /* 0x0514 */ - u32 pad10[1]; - u32 c2cwarmrstst_reg; /* 0x051C */ -}; -#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h deleted file mode 100644 index c21fb5471..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2006-2010 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u32 tistat; /* 0x14 r */ - u32 tisr; /* 0x18 rw */ - u32 tier; /* 0x1c rw */ - u32 twer; /* 0x20 rw */ - u32 tclr; /* 0x24 rw */ - u32 tcrr; /* 0x28 rw */ - u32 tldr; /* 0x2c rw */ - u32 ttgr; /* 0x30 rw */ - u32 twpc; /* 0x34 r */ - u32 tmar; /* 0x38 rw */ - u32 tcar1; /* 0x3c r */ - u32 tcicr; /* 0x40 rw */ - u32 tcar2; /* 0x44 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* GPMC BASE */ -#define GPMC_BASE (OMAP44XX_GPMC_BASE) - -/* I2C base */ -#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) -#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) -#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) -#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) - -/* MUSB base */ -#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) - -/* OMAP4 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x0118 -#define OMAP_GPIO_IRQSTATUS2 0x0128 -#define OMAP_GPIO_IRQENABLE2 0x012c -#define OMAP_GPIO_IRQENABLE1 0x011c -#define OMAP_GPIO_WAKE_EN 0x0120 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 -#define OMAP_GPIO_SETIRQENABLE1 0x0164 -#define OMAP_GPIO_CLEARWKUENA 0x0180 -#define OMAP_GPIO_SETWKUENA 0x0184 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4A306000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) -#define PRM_RSTST_WARM_RESET_MASK 0x07EA - -#endif /* _CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h deleted file mode 100644 index 984c8b9f7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * OMAP EHCI port support - * Based on LINUX KERNEL - * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com - * Author: Govindraj R <govindraj.raja@ti.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _OMAP4_EHCI_H_ -#define _OMAP4_EHCI_H_ - -#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) -#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000) -#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000) - -/* UHH, TLL and opt clocks */ -#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL - -#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ - OMAP_UHH_SYSCONFIG_NOSTDBY) - -#endif /* _OMAP4_EHCI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h deleted file mode 100644 index 72ba1d71a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0 - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP4_H -#define _GPIO_OMAP4_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 192 - -#define OMAP44XX_GPIO1_BASE 0x4A310000 -#define OMAP44XX_GPIO2_BASE 0x48055000 -#define OMAP44XX_GPIO3_BASE 0x48057000 -#define OMAP44XX_GPIO4_BASE 0x48059000 -#define OMAP44XX_GPIO5_BASE 0x4805B000 -#define OMAP44XX_GPIO6_BASE 0x4805D000 - -#endif /* _GPIO_OMAP4_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h deleted file mode 100644 index adc8eb23f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004-2010 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _OMAP4_I2C_H_ -#define _OMAP4_I2C_H_ - -#define I2C_BUS_MAX 4 -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short revnb_lo; /* 0x00 */ - unsigned short res1; - unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; - unsigned short irqstatus_raw; /* 0x24 */ - unsigned short res4; - unsigned short stat; /* 0x28 */ - unsigned short res5; - unsigned short ie; /* 0x2C */ - unsigned short res6; - unsigned short irqenable_clr; /* 0x30 */ - unsigned short res7; - unsigned short iv; /* 0x34 */ - unsigned short res8[45]; - unsigned short syss; /* 0x90 */ - unsigned short res9; - unsigned short buf; /* 0x94 */ - unsigned short res10; - unsigned short cnt; /* 0x98 */ - unsigned short res11; - unsigned short data; /* 0x9C */ - unsigned short res13; - unsigned short res14; /* 0xA0 */ - unsigned short res15; - unsigned short con; /* 0xA4 */ - unsigned short res16; - unsigned short oa; /* 0xA8 */ - unsigned short res17; - unsigned short sa; /* 0xAC */ - unsigned short res18; - unsigned short psc; /* 0xB0 */ - unsigned short res19; - unsigned short scll; /* 0xB4 */ - unsigned short res20; - unsigned short sclh; /* 0xB8 */ - unsigned short res21; - unsigned short systest; /* 0xBC */ - unsigned short res22; - unsigned short bufstat; /* 0xC0 */ - unsigned short res23; -}; - -#endif /* _OMAP4_I2C_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h deleted file mode 100644 index 9c8ccb6c8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC1_BASE 0x4809C100 -#define OMAP_HSMMC2_BASE 0x480B4100 -#define OMAP_HSMMC3_BASE 0x480AD100 - -#endif /* MMC_HOST_DEF_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h deleted file mode 100644 index b22277813..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _MUX_OMAP4_H_ -#define _MUX_OMAP4_H_ - -#include <asm/types.h> - -struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define GPMC_AD0 0x0040 -#define GPMC_AD1 0x0042 -#define GPMC_AD2 0x0044 -#define GPMC_AD3 0x0046 -#define GPMC_AD4 0x0048 -#define GPMC_AD5 0x004A -#define GPMC_AD6 0x004C -#define GPMC_AD7 0x004E -#define GPMC_AD8 0x0050 -#define GPMC_AD9 0x0052 -#define GPMC_AD10 0x0054 -#define GPMC_AD11 0x0056 -#define GPMC_AD12 0x0058 -#define GPMC_AD13 0x005A -#define GPMC_AD14 0x005C -#define GPMC_AD15 0x005E -#define GPMC_A16 0x0060 -#define GPMC_A17 0x0062 -#define GPMC_A18 0x0064 -#define GPMC_A19 0x0066 -#define GPMC_A20 0x0068 -#define GPMC_A21 0x006A -#define GPMC_A22 0x006C -#define GPMC_A23 0x006E -#define GPMC_A24 0x0070 -#define GPMC_A25 0x0072 -#define GPMC_NCS0 0x0074 -#define GPMC_NCS1 0x0076 -#define GPMC_NCS2 0x0078 -#define GPMC_NCS3 0x007A -#define GPMC_NWP 0x007C -#define GPMC_CLK 0x007E -#define GPMC_NADV_ALE 0x0080 -#define GPMC_NOE 0x0082 -#define GPMC_NWE 0x0084 -#define GPMC_NBE0_CLE 0x0086 -#define GPMC_NBE1 0x0088 -#define GPMC_WAIT0 0x008A -#define GPMC_WAIT1 0x008C -#define C2C_DATA11 0x008E -#define C2C_DATA12 0x0090 -#define C2C_DATA13 0x0092 -#define C2C_DATA14 0x0094 -#define C2C_DATA15 0x0096 -#define HDMI_HPD 0x0098 -#define HDMI_CEC 0x009A -#define HDMI_DDC_SCL 0x009C -#define HDMI_DDC_SDA 0x009E -#define CSI21_DX0 0x00A0 -#define CSI21_DY0 0x00A2 -#define CSI21_DX1 0x00A4 -#define CSI21_DY1 0x00A6 -#define CSI21_DX2 0x00A8 -#define CSI21_DY2 0x00AA -#define CSI21_DX3 0x00AC -#define CSI21_DY3 0x00AE -#define CSI21_DX4 0x00B0 -#define CSI21_DY4 0x00B2 -#define CSI22_DX0 0x00B4 -#define CSI22_DY0 0x00B6 -#define CSI22_DX1 0x00B8 -#define CSI22_DY1 0x00BA -#define CAM_SHUTTER 0x00BC -#define CAM_STROBE 0x00BE -#define CAM_GLOBALRESET 0x00C0 -#define USBB1_ULPITLL_CLK 0x00C2 -#define USBB1_ULPITLL_STP 0x00C4 -#define USBB1_ULPITLL_DIR 0x00C6 -#define USBB1_ULPITLL_NXT 0x00C8 -#define USBB1_ULPITLL_DAT0 0x00CA -#define USBB1_ULPITLL_DAT1 0x00CC -#define USBB1_ULPITLL_DAT2 0x00CE -#define USBB1_ULPITLL_DAT3 0x00D0 -#define USBB1_ULPITLL_DAT4 0x00D2 -#define USBB1_ULPITLL_DAT5 0x00D4 -#define USBB1_ULPITLL_DAT6 0x00D6 -#define USBB1_ULPITLL_DAT7 0x00D8 -#define USBB1_HSIC_DATA 0x00DA -#define USBB1_HSIC_STROBE 0x00DC -#define USBC1_ICUSB_DP 0x00DE -#define USBC1_ICUSB_DM 0x00E0 -#define SDMMC1_CLK 0x00E2 -#define SDMMC1_CMD 0x00E4 -#define SDMMC1_DAT0 0x00E6 -#define SDMMC1_DAT1 0x00E8 -#define SDMMC1_DAT2 0x00EA -#define SDMMC1_DAT3 0x00EC -#define SDMMC1_DAT4 0x00EE -#define SDMMC1_DAT5 0x00F0 -#define SDMMC1_DAT6 0x00F2 -#define SDMMC1_DAT7 0x00F4 -#define ABE_MCBSP2_CLKX 0x00F6 -#define ABE_MCBSP2_DR 0x00F8 -#define ABE_MCBSP2_DX 0x00FA -#define ABE_MCBSP2_FSX 0x00FC -#define ABE_MCBSP1_CLKX 0x00FE -#define ABE_MCBSP1_DR 0x0100 -#define ABE_MCBSP1_DX 0x0102 -#define ABE_MCBSP1_FSX 0x0104 -#define ABE_PDM_UL_DATA 0x0106 -#define ABE_PDM_DL_DATA 0x0108 -#define ABE_PDM_FRAME 0x010A -#define ABE_PDM_LB_CLK 0x010C -#define ABE_CLKS 0x010E -#define ABE_DMIC_CLK1 0x0110 -#define ABE_DMIC_DIN1 0x0112 -#define ABE_DMIC_DIN2 0x0114 -#define ABE_DMIC_DIN3 0x0116 -#define UART2_CTS 0x0118 -#define UART2_RTS 0x011A -#define UART2_RX 0x011C -#define UART2_TX 0x011E -#define HDQ_SIO 0x0120 -#define I2C1_SCL 0x0122 -#define I2C1_SDA 0x0124 -#define I2C2_SCL 0x0126 -#define I2C2_SDA 0x0128 -#define I2C3_SCL 0x012A -#define I2C3_SDA 0x012C -#define I2C4_SCL 0x012E -#define I2C4_SDA 0x0130 -#define MCSPI1_CLK 0x0132 -#define MCSPI1_SOMI 0x0134 -#define MCSPI1_SIMO 0x0136 -#define MCSPI1_CS0 0x0138 -#define MCSPI1_CS1 0x013A -#define MCSPI1_CS2 0x013C -#define MCSPI1_CS3 0x013E -#define UART3_CTS_RCTX 0x0140 -#define UART3_RTS_SD 0x0142 -#define UART3_RX_IRRX 0x0144 -#define UART3_TX_IRTX 0x0146 -#define SDMMC5_CLK 0x0148 -#define SDMMC5_CMD 0x014A -#define SDMMC5_DAT0 0x014C -#define SDMMC5_DAT1 0x014E -#define SDMMC5_DAT2 0x0150 -#define SDMMC5_DAT3 0x0152 -#define MCSPI4_CLK 0x0154 -#define MCSPI4_SIMO 0x0156 -#define MCSPI4_SOMI 0x0158 -#define MCSPI4_CS0 0x015A -#define UART4_RX 0x015C -#define UART4_TX 0x015E -#define USBB2_ULPITLL_CLK 0x0160 -#define USBB2_ULPITLL_STP 0x0162 -#define USBB2_ULPITLL_DIR 0x0164 -#define USBB2_ULPITLL_NXT 0x0166 -#define USBB2_ULPITLL_DAT0 0x0168 -#define USBB2_ULPITLL_DAT1 0x016A -#define USBB2_ULPITLL_DAT2 0x016C -#define USBB2_ULPITLL_DAT3 0x016E -#define USBB2_ULPITLL_DAT4 0x0170 -#define USBB2_ULPITLL_DAT5 0x0172 -#define USBB2_ULPITLL_DAT6 0x0174 -#define USBB2_ULPITLL_DAT7 0x0176 -#define USBB2_HSIC_DATA 0x0178 -#define USBB2_HSIC_STROBE 0x017A -#define UNIPRO_TX0 0x017C -#define UNIPRO_TY0 0x017E -#define UNIPRO_TX1 0x0180 -#define UNIPRO_TY1 0x0182 -#define UNIPRO_TX2 0x0184 -#define UNIPRO_TY2 0x0186 -#define UNIPRO_RX0 0x0188 -#define UNIPRO_RY0 0x018A -#define UNIPRO_RX1 0x018C -#define UNIPRO_RY1 0x018E -#define UNIPRO_RX2 0x0190 -#define UNIPRO_RY2 0x0192 -#define USBA0_OTG_CE 0x0194 -#define USBA0_OTG_DP 0x0196 -#define USBA0_OTG_DM 0x0198 -#define FREF_CLK1_OUT 0x019A -#define FREF_CLK2_OUT 0x019C -#define SYS_NIRQ1 0x019E -#define SYS_NIRQ2 0x01A0 -#define SYS_BOOT0 0x01A2 -#define SYS_BOOT1 0x01A4 -#define SYS_BOOT2 0x01A6 -#define SYS_BOOT3 0x01A8 -#define SYS_BOOT4 0x01AA -#define SYS_BOOT5 0x01AC -#define DPM_EMU0 0x01AE -#define DPM_EMU1 0x01B0 -#define DPM_EMU2 0x01B2 -#define DPM_EMU3 0x01B4 -#define DPM_EMU4 0x01B6 -#define DPM_EMU5 0x01B8 -#define DPM_EMU6 0x01BA -#define DPM_EMU7 0x01BC -#define DPM_EMU8 0x01BE -#define DPM_EMU9 0x01C0 -#define DPM_EMU10 0x01C2 -#define DPM_EMU11 0x01C4 -#define DPM_EMU12 0x01C6 -#define DPM_EMU13 0x01C8 -#define DPM_EMU14 0x01CA -#define DPM_EMU15 0x01CC -#define DPM_EMU16 0x01CE -#define DPM_EMU17 0x01D0 -#define DPM_EMU18 0x01D2 -#define DPM_EMU19 0x01D4 -#define WAKEUPEVENT_0 0x01D8 -#define WAKEUPEVENT_1 0x01DC -#define WAKEUPEVENT_2 0x01E0 -#define WAKEUPEVENT_3 0x01E4 -#define WAKEUPEVENT_4 0x01E8 -#define WAKEUPEVENT_5 0x01EC -#define WAKEUPEVENT_6 0x01F0 - -#define WKUP_REVISION 0x0000 -#define WKUP_HWINFO 0x0004 -#define WKUP_SYSCONFIG 0x0010 -#define PAD0_SIM_IO 0x0040 -#define PAD1_SIM_CLK 0x0042 -#define PAD0_SIM_RESET 0x0044 -#define PAD1_SIM_CD 0x0046 -#define PAD0_SIM_PWRCTRL 0x0048 -#define PAD1_SR_SCL 0x004A -#define PAD0_SR_SDA 0x004C -#define PAD1_FREF_XTAL_IN 0x004E -#define PAD0_FREF_SLICER_IN 0x0050 -#define PAD1_FREF_CLK_IOREQ 0x0052 -#define PAD0_FREF_CLK0_OUT 0x0054 -#define PAD1_FREF_CLK3_REQ 0x0056 -#define PAD0_FREF_CLK3_OUT 0x0058 -#define PAD1_FREF_CLK4_REQ 0x005A -#define PAD0_FREF_CLK4_OUT 0x005C -#define PAD1_SYS_32K 0x005E -#define PAD0_SYS_NRESPWRON 0x0060 -#define PAD1_SYS_NRESWARM 0x0062 -#define PAD0_SYS_PWR_REQ 0x0064 -#define PAD1_SYS_PWRON_RESET 0x0066 -#define PAD0_SYS_BOOT6 0x0068 -#define PAD1_SYS_BOOT7 0x006A -#define PAD0_JTAG_NTRST 0x006C -#define PAD1_JTAG_TCK 0x006D -#define PAD0_JTAG_RTCK 0x0070 -#define PAD1_JTAG_TMS_TMSC 0x0072 -#define PAD0_JTAG_TDI 0x0074 -#define PAD1_JTAG_TDO 0x0076 -#define PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_SPARE_RW 0x0614 -#define CONTROL_SPARE_R 0x0618 -#define CONTROL_SPARE_R_C0 0x061C - -#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A -#endif /* _MUX_OMAP4_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h deleted file mode 100644 index f66da0d60..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Authors: - * Aneesh V <aneesh@ti.com> - * - * Derived from OMAP3 work by - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _OMAP4_H_ -#define _OMAP4_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP44XX_L4_CORE_BASE 0x4A000000 -#define OMAP44XX_L4_WKUP_BASE 0x4A300000 -#define OMAP44XX_L4_PER_BASE 0x48000000 - -#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 -#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END - -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE 0x4A002204 -#define STD_FUSE_DIE_ID_0 0x4A002200 -#define STD_FUSE_DIE_ID_1 0x4A002208 -#define STD_FUSE_DIE_ID_2 0x4A00220c -#define STD_FUSE_DIE_ID_3 0x4A002210 - -#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F -#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F -#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F -#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F -#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F -#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F -#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F -#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F - -/* UART */ -#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) -#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) -#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) - -/* General Purpose Timers */ -#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) -#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) -#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) - -/* Watchdog Timer2 - MPU watchdog */ -#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) - -/* GPMC */ -#define OMAP44XX_GPMC_BASE 0x50000000 - -/* - * Hardware Register Details - */ - -/* Watchdog Timer */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* GP Timer */ -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* Control Module */ -#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) -#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f -#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 -#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 - -/* LPDDR2 IO regs */ -#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C -#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E -#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C -#define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F - -/* CONTROL_EFUSE_2 */ -#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 - -#define MMC1_PWRDNZ (1 << 26) -#define MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define MMC1_PBIASLITE_VMODE (1 << 21) - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#define DEVICE_TYPE_SHIFT (0x8) -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#define DEVICE_GP 0x3 - -#endif /* __ASSEMBLY__ */ - -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ -#define NON_SECURE_SRAM_START 0x40304000 -#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_ROM_VECT_BASE 0x4030D000 - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 50 -#define OMAP_ABB_CLOCK_CYCLES 16 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h deleted file mode 100644 index fb842a226..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 0xFF - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h deleted file mode 100644 index 80172f379..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/arch/omap.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <asm/omap_common.h> -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/mux_omap4.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; -extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; -extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; -extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; -struct omap_sysinfo { - char *board_string; -}; -extern const struct omap_sysinfo sysinfo; - -void gpmc_init(void); -void watchdog_init(void); -u32 get_device_type(void); -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); -void set_muxconf_regs_essential(void); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void set_pl310_ctrl_reg(u32 val); -void setup_clocks_for_console(void); -void prcm_init(void); -void bypass_dpll(u32 const base); -void freq_update_core(void); -u32 get_sys_clk_freq(void); -u32 omap4_ddr_clk(void); -void cancel_out(u32 *num, u32 *den, u32 den_limit); -void sdram_init(void); -u32 omap_sdram_size(void); -u32 cortex_rev(void); -void save_omap_boot_params(void); -void init_omap_revision(void); -void do_io_settings(void); -void sri2c_init(void); -void gpi2c_init(void); -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); -u32 warm_reset(void); -void force_emif_self_refresh(void); -void setup_warmreset_time(void); - -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h deleted file mode 100644 index 2dfe4efb4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * Sricharan R <r.sricharan@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _CLOCKS_OMAP5_H_ -#define _CLOCKS_OMAP5_H_ -#include <common.h> -#include <asm/omap_common.h> - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* SGX */ -#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) -#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_CLKSEL_ABE_PLL_SYS */ -#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 -#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 -#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 -#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) - -/* CM_L3INIT_SATA_CLKCTRL */ -#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 - -/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ -#define OPTFCLKEN_FUNC48M_CLK (1 << 15) -#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) -#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) -#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) -#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) -#define OPTFCLKEN_UTMI_P3_CLK (1 << 10) -#define OPTFCLKEN_UTMI_P2_CLK (1 << 9) -#define OPTFCLKEN_UTMI_P1_CLK (1 << 8) -#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) -#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) - -/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ -#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) -#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) -#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) - -/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ -#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) - -/* CM_L3INIT_USB_OTG_SS_CLKCTRL */ -#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) -#define OPTFCLKEN_REFCLK960M (1 << 8) - -/* CM_L3INIT_OCP2SCP1_CLKCTRL */ -#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) - -/* CM_WKUPAON_SCRM_CLKCTRL */ -#define OPTFCLKEN_SCRM_PER_SHIFT 9 -#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) -#define OPTFCLKEN_SCRM_CORE_SHIFT 8 -#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) - -/* CM_COREAON_IO_SRCOMP_CLKCTRL */ -#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 -#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) - -/* PRM_RSTTIME */ -#define RSTTIME1_SHIFT 0 -#define RSTTIME1_MASK (0x3ff << 0) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* CTRL_CORE_SRCOMP_NORTH_SIDE */ -#define USB2PHY_DISCHGDET (1 << 29) -#define USB2PHY_AUTORESUME_EN (1 << 30) - -/* SMPS */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -#define SMPS_REG_ADDR_12_MPU 0x23 -#define SMPS_REG_ADDR_45_IVA 0x2B -#define SMPS_REG_ADDR_8_CORE 0x37 - -/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ -/* ES1.0 settings */ -#define VDD_MPU 1040 -#define VDD_MM 1040 -#define VDD_CORE 1040 - -#define VDD_MPU_LOW 890 -#define VDD_MM_LOW 890 -#define VDD_CORE_LOW 890 - -/* ES2.0 settings */ -#define VDD_MPU_ES2 1060 -#define VDD_MM_ES2 1025 -#define VDD_CORE_ES2 1040 - -#define VDD_MPU_ES2_HIGH 1250 -#define VDD_MM_ES2_OD 1120 - -#define VDD_MPU_ES2_LOW 880 -#define VDD_MM_ES2_LOW 880 - -/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ -#define VDD_MPU_DRA752 1090 -#define VDD_EVE_DRA752 1060 -#define VDD_GPU_DRA752 1060 -#define VDD_CORE_DRA752 1030 -#define VDD_IVA_DRA752 1060 - -/* Efuse register offsets for DRA7xx platform */ -#define DRA752_EFUSE_BASE 0x4A002000 -#define DRA752_EFUSE_REGBITS 16 -/* STD_FUSE_OPP_VMIN_IVA_2 */ -#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) -/* STD_FUSE_OPP_VMIN_IVA_3 */ -#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) -/* STD_FUSE_OPP_VMIN_IVA_4 */ -#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) -/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ -#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) -/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ -#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) -/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ -#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) -/* STD_FUSE_OPP_VMIN_CORE_2 */ -#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) -/* STD_FUSE_OPP_VMIN_GPU_2 */ -#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) -/* STD_FUSE_OPP_VMIN_GPU_3 */ -#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) -/* STD_FUSE_OPP_VMIN_GPU_4 */ -#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) -/* STD_FUSE_OPP_VMIN_MPU_2 */ -#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) -/* STD_FUSE_OPP_VMIN_MPU_3 */ -#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) -/* STD_FUSE_OPP_VMIN_MPU_4 */ -#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) - -/* Standard offset is 0.5v expressed in uv */ -#define PALMAS_SMPS_BASE_VOLT_UV 500000 - -/* TPS659038 */ -#define TPS659038_I2C_SLAVE_ADDR 0x58 -#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 -#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B -#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F -#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 -#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -/* Defines for DPLL setup */ -#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 -#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 -#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -/* - * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. - * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles - * into microsec and passing the value. - */ -#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 - -#ifdef CONFIG_DRA7XX -#define V_OSCK 20000000 /* Clock output from T2 */ -#else -#define V_OSCK 19200000 /* Clock output from T2 */ -#endif - -#define V_SCLK V_OSCK - -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - -#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h deleted file mode 100644 index 5f1d7454d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2006-2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res1[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u8 res2[0x10]; - u32 tisr_raw; /* 0x24 r */ - u32 tisr; /* 0x28 rw */ - u32 tier; /* 0x2c rw */ - u32 ticr; /* 0x30 rw */ - u32 twer; /* 0x34 rw */ - u32 tclr; /* 0x38 rw */ - u32 tcrr; /* 0x3c rw */ - u32 tldr; /* 0x40 rw */ - u32 ttgr; /* 0x44 rw */ - u32 twpc; /* 0x48 r */ - u32 tmar; /* 0x4c rw */ - u32 tcar1; /* 0x50 r */ - u32 tcicr; /* 0x54 rw */ - u32 tcar2; /* 0x58 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define BIT(x) (1 << (x)) - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* GPMC BASE */ -#define GPMC_BASE (OMAP54XX_GPMC_BASE) - -/* I2C base */ -#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) -#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) -#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) -#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) -#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) - -/* MUSB base */ -#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) - -/* OMAP4 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x0118 -#define OMAP_GPIO_IRQSTATUS2 0x0128 -#define OMAP_GPIO_IRQENABLE2 0x012c -#define OMAP_GPIO_IRQENABLE1 0x011c -#define OMAP_GPIO_WAKE_EN 0x0120 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 -#define OMAP_GPIO_SETIRQENABLE1 0x0164 -#define OMAP_GPIO_CLEARWKUENA 0x0180 -#define OMAP_GPIO_SETWKUENA 0x0184 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4AE06000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) -#define PRM_RSTST_WARM_RESET_MASK 0x7FEA - -/* DRA7XX CPSW Config space */ -#define CPSW_BASE 0x48484000 -#define CPSW_MDIO_BASE 0x48485000 - -#endif /* _CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h deleted file mode 100644 index 63aaa020d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* - * Author: Govindraj R <govindraj.raja@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EHCI_H -#define _EHCI_H - -#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00) -#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000) -#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000) - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ - OMAP_UHH_SYSCONFIG_NOSTDBY) - -#endif /* _EHCI_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h deleted file mode 100644 index 9dd03c9fa..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0 - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP5_H -#define _GPIO_OMAP5_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 256 - -#define OMAP54XX_GPIO1_BASE 0x4Ae10000 -#define OMAP54XX_GPIO2_BASE 0x48055000 -#define OMAP54XX_GPIO3_BASE 0x48057000 -#define OMAP54XX_GPIO4_BASE 0x48059000 -#define OMAP54XX_GPIO5_BASE 0x4805B000 -#define OMAP54XX_GPIO6_BASE 0x4805D000 -#define OMAP54XX_GPIO7_BASE 0x48051000 -#define OMAP54XX_GPIO8_BASE 0x48053000 - -#endif /* _GPIO_OMAP5_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h deleted file mode 100644 index d875cfe0b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2004-2010 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _OMAP5_I2C_H_ -#define _OMAP5_I2C_H_ - -#define I2C_BUS_MAX 5 -#define I2C_DEFAULT_BASE I2C_BASE1 - -struct i2c { - unsigned short revnb_lo; /* 0x00 */ - unsigned short res1; - unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; - unsigned short irqstatus_raw; /* 0x24 */ - unsigned short res4; - unsigned short stat; /* 0x28 */ - unsigned short res5; - unsigned short ie; /* 0x2C */ - unsigned short res6; - unsigned short irqenable_clr; /* 0x30 */ - unsigned short res7; - unsigned short iv; /* 0x34 */ - unsigned short res8[45]; - unsigned short syss; /* 0x90 */ - unsigned short res9; - unsigned short buf; /* 0x94 */ - unsigned short res10; - unsigned short cnt; /* 0x98 */ - unsigned short res11; - unsigned short data; /* 0x9C */ - unsigned short res13; - unsigned short res14; /* 0xA0 */ - unsigned short res15; - unsigned short con; /* 0xA4 */ - unsigned short res16; - unsigned short oa; /* 0xA8 */ - unsigned short res17; - unsigned short sa; /* 0xAC */ - unsigned short res18; - unsigned short psc; /* 0xB0 */ - unsigned short res19; - unsigned short scll; /* 0xB4 */ - unsigned short res20; - unsigned short sclh; /* 0xB8 */ - unsigned short res21; - unsigned short systest; /* 0xBC */ - unsigned short res22; - unsigned short bufstat; /* 0xC0 */ - unsigned short res23; -}; - -#endif /* _OMAP5_I2C_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h deleted file mode 100644 index 9c8ccb6c8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC1_BASE 0x4809C100 -#define OMAP_HSMMC2_BASE 0x480B4100 -#define OMAP_HSMMC3_BASE 0x480AD100 - -#endif /* MMC_HOST_DEF_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h deleted file mode 100644 index e1553879d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated - * - * Nishant Kamat <nskamat@ti.com> - * Lokesh Vutla <lokeshvutla@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _MUX_DRA7XX_H_ -#define _MUX_DRA7XX_H_ - -#include <asm/types.h> - -#define FSC (1 << 19) -#define SSC (0 << 19) - -#define IEN (1 << 18) -#define IDIS (0 << 18) - -#define PTU (1 << 17) -#define PTD (0 << 17) -#define PEN (1 << 16) -#define PDIS (0 << 16) - -#define WKEN (1 << 24) -#define WKDIS (0 << 24) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 -#define M8 8 -#define M9 9 -#define M10 10 -#define M11 11 -#define M12 12 -#define M13 13 -#define M14 14 -#define M15 15 - -#define SAFE_MODE M15 - -#define GPMC_AD0 0x000 -#define GPMC_AD1 0x004 -#define GPMC_AD2 0x008 -#define GPMC_AD3 0x00C -#define GPMC_AD4 0x010 -#define GPMC_AD5 0x014 -#define GPMC_AD6 0x018 -#define GPMC_AD7 0x01C -#define GPMC_AD8 0x020 -#define GPMC_AD9 0x024 -#define GPMC_AD10 0x028 -#define GPMC_AD11 0x02C -#define GPMC_AD12 0x030 -#define GPMC_AD13 0x034 -#define GPMC_AD14 0x038 -#define GPMC_AD15 0x03C -#define GPMC_A0 0x040 -#define GPMC_A1 0x044 -#define GPMC_A2 0x048 -#define GPMC_A3 0x04C -#define GPMC_A4 0x050 -#define GPMC_A5 0x054 -#define GPMC_A6 0x058 -#define GPMC_A7 0x05C -#define GPMC_A8 0x060 -#define GPMC_A9 0x064 -#define GPMC_A10 0x068 -#define GPMC_A11 0x06C -#define GPMC_A12 0x070 -#define GPMC_A13 0x074 -#define GPMC_A14 0x078 -#define GPMC_A15 0x07C -#define GPMC_A16 0x080 -#define GPMC_A17 0x084 -#define GPMC_A18 0x088 -#define GPMC_A19 0x08C -#define GPMC_A20 0x090 -#define GPMC_A21 0x094 -#define GPMC_A22 0x098 -#define GPMC_A23 0x09C -#define GPMC_A24 0x0A0 -#define GPMC_A25 0x0A4 -#define GPMC_A26 0x0A8 -#define GPMC_A27 0x0AC -#define GPMC_CS1 0x0B0 -#define GPMC_CS0 0x0B4 -#define GPMC_CS2 0x0B8 -#define GPMC_CS3 0x0BC -#define GPMC_CLK 0x0C0 -#define GPMC_ADVN_ALE 0x0C4 -#define GPMC_OEN_REN 0x0C8 -#define GPMC_WEN 0x0CC -#define GPMC_BEN0 0x0D0 -#define GPMC_BEN1 0x0D4 -#define GPMC_WAIT0 0x0D8 -#define VIN1A_CLK0 0x0DC -#define VIN1B_CLK1 0x0E0 -#define VIN1A_DE0 0x0E4 -#define VIN1A_FLD0 0x0E8 -#define VIN1A_HSYNC0 0x0EC -#define VIN1A_VSYNC0 0x0F0 -#define VIN1A_D0 0x0F4 -#define VIN1A_D1 0x0F8 -#define VIN1A_D2 0x0FC -#define VIN1A_D3 0x100 -#define VIN1A_D4 0x104 -#define VIN1A_D5 0x108 -#define VIN1A_D6 0x10C -#define VIN1A_D7 0x110 -#define VIN1A_D8 0x114 -#define VIN1A_D9 0x118 -#define VIN1A_D10 0x11C -#define VIN1A_D11 0x120 -#define VIN1A_D12 0x124 -#define VIN1A_D13 0x128 -#define VIN1A_D14 0x12C -#define VIN1A_D15 0x130 -#define VIN1A_D16 0x134 -#define VIN1A_D17 0x138 -#define VIN1A_D18 0x13C -#define VIN1A_D19 0x140 -#define VIN1A_D20 0x144 -#define VIN1A_D21 0x148 -#define VIN1A_D22 0x14C -#define VIN1A_D23 0x150 -#define VIN2A_CLK0 0x154 -#define VIN2A_DE0 0x158 -#define VIN2A_FLD0 0x15C -#define VIN2A_HSYNC0 0x160 -#define VIN2A_VSYNC0 0x164 -#define VIN2A_D0 0x168 -#define VIN2A_D1 0x16C -#define VIN2A_D2 0x170 -#define VIN2A_D3 0x174 -#define VIN2A_D4 0x178 -#define VIN2A_D5 0x17C -#define VIN2A_D6 0x180 -#define VIN2A_D7 0x184 -#define VIN2A_D8 0x188 -#define VIN2A_D9 0x18C -#define VIN2A_D10 0x190 -#define VIN2A_D11 0x194 -#define VIN2A_D12 0x198 -#define VIN2A_D13 0x19C -#define VIN2A_D14 0x1A0 -#define VIN2A_D15 0x1A4 -#define VIN2A_D16 0x1A8 -#define VIN2A_D17 0x1AC -#define VIN2A_D18 0x1B0 -#define VIN2A_D19 0x1B4 -#define VIN2A_D20 0x1B8 -#define VIN2A_D21 0x1BC -#define VIN2A_D22 0x1C0 -#define VIN2A_D23 0x1C4 -#define VOUT1_CLK 0x1C8 -#define VOUT1_DE 0x1CC -#define VOUT1_FLD 0x1D0 -#define VOUT1_HSYNC 0x1D4 -#define VOUT1_VSYNC 0x1D8 -#define VOUT1_D0 0x1DC -#define VOUT1_D1 0x1E0 -#define VOUT1_D2 0x1E4 -#define VOUT1_D3 0x1E8 -#define VOUT1_D4 0x1EC -#define VOUT1_D5 0x1F0 -#define VOUT1_D6 0x1F4 -#define VOUT1_D7 0x1F8 -#define VOUT1_D8 0x1FC -#define VOUT1_D9 0x200 -#define VOUT1_D10 0x204 -#define VOUT1_D11 0x208 -#define VOUT1_D12 0x20C -#define VOUT1_D13 0x210 -#define VOUT1_D14 0x214 -#define VOUT1_D15 0x218 -#define VOUT1_D16 0x21C -#define VOUT1_D17 0x220 -#define VOUT1_D18 0x224 -#define VOUT1_D19 0x228 -#define VOUT1_D20 0x22C -#define VOUT1_D21 0x230 -#define VOUT1_D22 0x234 -#define VOUT1_D23 0x238 -#define MDIO_MCLK 0x23C -#define MDIO_D 0x240 -#define RMII_MHZ_50_CLK 0x244 -#define UART3_RXD 0x248 -#define UART3_TXD 0x24C -#define RGMII0_TXC 0x250 -#define RGMII0_TXCTL 0x254 -#define RGMII0_TXD3 0x258 -#define RGMII0_TXD2 0x25C -#define RGMII0_TXD1 0x260 -#define RGMII0_TXD0 0x264 -#define RGMII0_RXC 0x268 -#define RGMII0_RXCTL 0x26C -#define RGMII0_RXD3 0x270 -#define RGMII0_RXD2 0x274 -#define RGMII0_RXD1 0x278 -#define RGMII0_RXD0 0x27C -#define USB1_DRVVBUS 0x280 -#define USB2_DRVVBUS 0x284 -#define GPIO6_14 0x288 -#define GPIO6_15 0x28C -#define GPIO6_16 0x290 -#define XREF_CLK0 0x294 -#define XREF_CLK1 0x298 -#define XREF_CLK2 0x29C -#define XREF_CLK3 0x2A0 -#define MCASP1_ACLKX 0x2A4 -#define MCASP1_FSX 0x2A8 -#define MCASP1_ACLKR 0x2AC -#define MCASP1_FSR 0x2B0 -#define MCASP1_AXR0 0x2B4 -#define MCASP1_AXR1 0x2B8 -#define MCASP1_AXR2 0x2BC -#define MCASP1_AXR3 0x2C0 -#define MCASP1_AXR4 0x2C4 -#define MCASP1_AXR5 0x2C8 -#define MCASP1_AXR6 0x2CC -#define MCASP1_AXR7 0x2D0 -#define MCASP1_AXR8 0x2D4 -#define MCASP1_AXR9 0x2D8 -#define MCASP1_AXR10 0x2DC -#define MCASP1_AXR11 0x2E0 -#define MCASP1_AXR12 0x2E4 -#define MCASP1_AXR13 0x2E8 -#define MCASP1_AXR14 0x2EC -#define MCASP1_AXR15 0x2F0 -#define MCASP2_ACLKX 0x2F4 -#define MCASP2_FSX 0x2F8 -#define MCASP2_ACLKR 0x2FC -#define MCASP2_FSR 0x300 -#define MCASP2_AXR0 0x304 -#define MCASP2_AXR1 0x308 -#define MCASP2_AXR2 0x30C -#define MCASP2_AXR3 0x310 -#define MCASP2_AXR4 0x314 -#define MCASP2_AXR5 0x318 -#define MCASP2_AXR6 0x31C -#define MCASP2_AXR7 0x320 -#define MCASP3_ACLKX 0x324 -#define MCASP3_FSX 0x328 -#define MCASP3_AXR0 0x32C -#define MCASP3_AXR1 0x330 -#define MCASP4_ACLKX 0x334 -#define MCASP4_FSX 0x338 -#define MCASP4_AXR0 0x33C -#define MCASP4_AXR1 0x340 -#define MCASP5_ACLKX 0x344 -#define MCASP5_FSX 0x348 -#define MCASP5_AXR0 0x34C -#define MCASP5_AXR1 0x350 -#define MMC1_CLK 0x354 -#define MMC1_CMD 0x358 -#define MMC1_DAT0 0x35C -#define MMC1_DAT1 0x360 -#define MMC1_DAT2 0x364 -#define MMC1_DAT3 0x368 -#define MMC1_SDCD 0x36C -#define MMC1_SDWP 0x370 -#define GPIO6_10 0x374 -#define GPIO6_11 0x378 -#define MMC3_CLK 0x37C -#define MMC3_CMD 0x380 -#define MMC3_DAT0 0x384 -#define MMC3_DAT1 0x388 -#define MMC3_DAT2 0x38C -#define MMC3_DAT3 0x390 -#define MMC3_DAT4 0x394 -#define MMC3_DAT5 0x398 -#define MMC3_DAT6 0x39C -#define MMC3_DAT7 0x3A0 -#define SPI1_SCLK 0x3A4 -#define SPI1_D1 0x3A8 -#define SPI1_D0 0x3AC -#define SPI1_CS0 0x3B0 -#define SPI1_CS1 0x3B4 -#define SPI1_CS2 0x3B8 -#define SPI1_CS3 0x3BC -#define SPI2_SCLK 0x3C0 -#define SPI2_D1 0x3C4 -#define SPI2_D0 0x3C8 -#define SPI2_CS0 0x3CC -#define DCAN1_TX 0x3D0 -#define DCAN1_RX 0x3D4 -#define DCAN2_TX 0x3D8 -#define DCAN2_RX 0x3DC -#define UART1_RXD 0x3E0 -#define UART1_TXD 0x3E4 -#define UART1_CTSN 0x3E8 -#define UART1_RTSN 0x3EC -#define UART2_RXD 0x3F0 -#define UART2_TXD 0x3F4 -#define UART2_CTSN 0x3F8 -#define UART2_RTSN 0x3FC -#define I2C1_SDA 0x400 -#define I2C1_SCL 0x404 -#define I2C2_SDA 0x408 -#define I2C2_SCL 0x40C -#define I2C3_SDA 0x410 -#define I2C3_SCL 0x414 -#define WAKEUP0 0x418 -#define WAKEUP1 0x41C -#define WAKEUP2 0x420 -#define WAKEUP3 0x424 -#define ON_OFF 0x428 -#define RTC_PORZ 0x42C -#define TMS 0x430 -#define TDI 0x434 -#define TDO 0x438 -#define TCLK 0x43C -#define TRSTN 0x440 -#define RTCK 0x444 -#define EMU0 0x448 -#define EMU1 0x44C -#define EMU2 0x450 -#define EMU3 0x454 -#define EMU4 0x458 -#define RESETN 0x45C -#define NMIN 0x460 -#define RSTOUTN 0x464 - -#endif /* _MUX_DRA7XX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h deleted file mode 100644 index 3e93a1512..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _MUX_OMAP5_H_ -#define _MUX_OMAP5_H_ - -#include <asm/types.h> - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define EMMC_CLK 0x0040 -#define EMMC_CMD 0x0042 -#define EMMC_DATA0 0x0044 -#define EMMC_DATA1 0x0046 -#define EMMC_DATA2 0x0048 -#define EMMC_DATA3 0x004a -#define EMMC_DATA4 0x004c -#define EMMC_DATA5 0x004e -#define EMMC_DATA6 0x0050 -#define EMMC_DATA7 0x0052 -#define C2C_CLKOUT0 0x0054 -#define C2C_CLKOUT1 0x0056 -#define C2C_CLKIN0 0x0058 -#define C2C_CLKIN1 0x005a -#define C2C_DATAIN0 0x005c -#define C2C_DATAIN1 0x005e -#define C2C_DATAIN2 0x0060 -#define C2C_DATAIN3 0x0062 -#define C2C_DATAIN4 0x0064 -#define C2C_DATAIN5 0x0066 -#define C2C_DATAIN6 0x0068 -#define C2C_DATAIN7 0x006a -#define C2C_DATAOUT0 0x006c -#define C2C_DATAOUT1 0x006e -#define C2C_DATAOUT2 0x0070 -#define C2C_DATAOUT3 0x0072 -#define C2C_DATAOUT4 0x0074 -#define C2C_DATAOUT5 0x0076 -#define C2C_DATAOUT6 0x0078 -#define C2C_DATAOUT7 0x007a -#define C2C_DATA8 0x007c -#define C2C_DATA9 0x007e -#define C2C_DATA10 0x0080 -#define C2C_DATA11 0x0082 -#define C2C_DATA12 0x0084 -#define C2C_DATA13 0x0086 -#define C2C_DATA14 0x0088 -#define C2C_DATA15 0x008a -#define LLIA_WAKEREQOUT 0x008c -#define LLIB_WAKEREQOUT 0x008e -#define HSI1_ACREADY 0x0090 -#define HSI1_CAREADY 0x0092 -#define HSI1_ACWAKE 0x0094 -#define HSI1_CAWAKE 0x0096 -#define HSI1_ACFLAG 0x0098 -#define HSI1_ACDATA 0x009a -#define HSI1_CAFLAG 0x009c -#define HSI1_CADATA 0x009e -#define UART1_TX 0x00a0 -#define UART1_CTS 0x00a2 -#define UART1_RX 0x00a4 -#define UART1_RTS 0x00a6 -#define HSI2_CAREADY 0x00a8 -#define HSI2_ACREADY 0x00aa -#define HSI2_CAWAKE 0x00ac -#define HSI2_ACWAKE 0x00ae -#define HSI2_CAFLAG 0x00b0 -#define HSI2_CADATA 0x00b2 -#define HSI2_ACFLAG 0x00b4 -#define HSI2_ACDATA 0x00b6 -#define UART2_RTS 0x00b8 -#define UART2_CTS 0x00ba -#define UART2_RX 0x00bc -#define UART2_TX 0x00be -#define USBB1_HSIC_STROBE 0x00c0 -#define USBB1_HSIC_DATA 0x00c2 -#define USBB2_HSIC_STROBE 0x00c4 -#define USBB2_HSIC_DATA 0x00c6 -#define TIMER10_PWM_EVT 0x00c8 -#define DSIPORTA_TE0 0x00ca -#define DSIPORTA_LANE0X 0x00cc -#define DSIPORTA_LANE0Y 0x00ce -#define DSIPORTA_LANE1X 0x00d0 -#define DSIPORTA_LANE1Y 0x00d2 -#define DSIPORTA_LANE2X 0x00d4 -#define DSIPORTA_LANE2Y 0x00d6 -#define DSIPORTA_LANE3X 0x00d8 -#define DSIPORTA_LANE3Y 0x00da -#define DSIPORTA_LANE4X 0x00dc -#define DSIPORTA_LANE4Y 0x00de -#define DSIPORTC_LANE0X 0x00e0 -#define DSIPORTC_LANE0Y 0x00e2 -#define DSIPORTC_LANE1X 0x00e4 -#define DSIPORTC_LANE1Y 0x00e6 -#define DSIPORTC_LANE2X 0x00e8 -#define DSIPORTC_LANE2Y 0x00ea -#define DSIPORTC_LANE3X 0x00ec -#define DSIPORTC_LANE3Y 0x00ee -#define DSIPORTC_LANE4X 0x00f0 -#define DSIPORTC_LANE4Y 0x00f2 -#define DSIPORTC_TE0 0x00f4 -#define TIMER9_PWM_EVT 0x00f6 -#define I2C4_SCL 0x00f8 -#define I2C4_SDA 0x00fa -#define MCSPI2_CLK 0x00fc -#define MCSPI2_SIMO 0x00fe -#define MCSPI2_SOMI 0x0100 -#define MCSPI2_CS0 0x0102 -#define RFBI_DATA15 0x0104 -#define RFBI_DATA14 0x0106 -#define RFBI_DATA13 0x0108 -#define RFBI_DATA12 0x010a -#define RFBI_DATA11 0x010c -#define RFBI_DATA10 0x010e -#define RFBI_DATA9 0x0110 -#define RFBI_DATA8 0x0112 -#define RFBI_DATA7 0x0114 -#define RFBI_DATA6 0x0116 -#define RFBI_DATA5 0x0118 -#define RFBI_DATA4 0x011a -#define RFBI_DATA3 0x011c -#define RFBI_DATA2 0x011e -#define RFBI_DATA1 0x0120 -#define RFBI_DATA0 0x0122 -#define RFBI_WE 0x0124 -#define RFBI_CS0 0x0126 -#define RFBI_A0 0x0128 -#define RFBI_RE 0x012a -#define RFBI_HSYNC0 0x012c -#define RFBI_TE_VSYNC0 0x012e -#define GPIO6_182 0x0130 -#define GPIO6_183 0x0132 -#define GPIO6_184 0x0134 -#define GPIO6_185 0x0136 -#define GPIO6_186 0x0138 -#define GPIO6_187 0x013a -#define HDMI_CEC 0x013c -#define HDMI_HPD 0x013e -#define HDMI_DDC_SCL 0x0140 -#define HDMI_DDC_SDA 0x0142 -#define CSIPORTC_LANE0X 0x0144 -#define CSIPORTC_LANE0Y 0x0146 -#define CSIPORTC_LANE1X 0x0148 -#define CSIPORTC_LANE1Y 0x014a -#define CSIPORTB_LANE0X 0x014c -#define CSIPORTB_LANE0Y 0x014e -#define CSIPORTB_LANE1X 0x0150 -#define CSIPORTB_LANE1Y 0x0152 -#define CSIPORTB_LANE2X 0x0154 -#define CSIPORTB_LANE2Y 0x0156 -#define CSIPORTA_LANE0X 0x0158 -#define CSIPORTA_LANE0Y 0x015a -#define CSIPORTA_LANE1X 0x015c -#define CSIPORTA_LANE1Y 0x015e -#define CSIPORTA_LANE2X 0x0160 -#define CSIPORTA_LANE2Y 0x0162 -#define CSIPORTA_LANE3X 0x0164 -#define CSIPORTA_LANE3Y 0x0166 -#define CSIPORTA_LANE4X 0x0168 -#define CSIPORTA_LANE4Y 0x016a -#define CAM_SHUTTER 0x016c -#define CAM_STROBE 0x016e -#define CAM_GLOBALRESET 0x0170 -#define TIMER11_PWM_EVT 0x0172 -#define TIMER5_PWM_EVT 0x0174 -#define TIMER6_PWM_EVT 0x0176 -#define TIMER8_PWM_EVT 0x0178 -#define I2C3_SCL 0x017a -#define I2C3_SDA 0x017c -#define GPIO8_233 0x017e -#define GPIO8_234 0x0180 -#define ABE_CLKS 0x0182 -#define ABEDMIC_DIN1 0x0184 -#define ABEDMIC_DIN2 0x0186 -#define ABEDMIC_DIN3 0x0188 -#define ABEDMIC_CLK1 0x018a -#define ABEDMIC_CLK2 0x018c -#define ABEDMIC_CLK3 0x018e -#define ABESLIMBUS1_CLOCK 0x0190 -#define ABESLIMBUS1_DATA 0x0192 -#define ABEMCBSP2_DR 0x0194 -#define ABEMCBSP2_DX 0x0196 -#define ABEMCBSP2_FSX 0x0198 -#define ABEMCBSP2_CLKX 0x019a -#define ABEMCPDM_UL_DATA 0x019c -#define ABEMCPDM_DL_DATA 0x019e -#define ABEMCPDM_FRAME 0x01a0 -#define ABEMCPDM_LB_CLK 0x01a2 -#define WLSDIO_CLK 0x01a4 -#define WLSDIO_CMD 0x01a6 -#define WLSDIO_DATA0 0x01a8 -#define WLSDIO_DATA1 0x01aa -#define WLSDIO_DATA2 0x01ac -#define WLSDIO_DATA3 0x01ae -#define UART5_RX 0x01b0 -#define UART5_TX 0x01b2 -#define UART5_CTS 0x01b4 -#define UART5_RTS 0x01b6 -#define I2C2_SCL 0x01b8 -#define I2C2_SDA 0x01ba -#define MCSPI1_CLK 0x01bc -#define MCSPI1_SOMI 0x01be -#define MCSPI1_SIMO 0x01c0 -#define MCSPI1_CS0 0x01c2 -#define MCSPI1_CS1 0x01c4 -#define I2C5_SCL 0x01c6 -#define I2C5_SDA 0x01c8 -#define PERSLIMBUS2_CLOCK 0x01ca -#define PERSLIMBUS2_DATA 0x01cc -#define UART6_TX 0x01ce -#define UART6_RX 0x01d0 -#define UART6_CTS 0x01d2 -#define UART6_RTS 0x01d4 -#define UART3_CTS_RCTX 0x01d6 -#define UART3_RTS_IRSD 0x01d8 -#define UART3_TX_IRTX 0x01da -#define UART3_RX_IRRX 0x01dc -#define USBB3_HSIC_STROBE 0x01de -#define USBB3_HSIC_DATA 0x01e0 -#define SDCARD_CLK 0x01e2 -#define SDCARD_CMD 0x01e4 -#define SDCARD_DATA2 0x01e6 -#define SDCARD_DATA3 0x01e8 -#define SDCARD_DATA0 0x01ea -#define SDCARD_DATA1 0x01ec -#define USBD0_HS_DP 0x01ee -#define USBD0_HS_DM 0x01f0 -#define I2C1_PMIC_SCL 0x01f2 -#define I2C1_PMIC_SDA 0x01f4 -#define USBD0_SS_RX 0x01f6 - -#define LLIA_WAKEREQIN 0x0040 -#define LLIB_WAKEREQIN 0x0042 -#define DRM_EMU0 0x0044 -#define DRM_EMU1 0x0046 -#define JTAG_NTRST 0x0048 -#define JTAG_TCK 0x004a -#define JTAG_RTCK 0x004c -#define JTAG_TMSC 0x004e -#define JTAG_TDI 0x0050 -#define JTAG_TDO 0x0052 -#define SYS_32K 0x0054 -#define FREF_CLK_IOREQ 0x0056 -#define FREF_CLK0_OUT 0x0058 -#define FREF_CLK1_OUT 0x005a -#define FREF_CLK2_OUT 0x005c -#define FREF_CLK2_REQ 0x005e -#define FREF_CLK1_REQ 0x0060 -#define SYS_NRESPWRON 0x0062 -#define SYS_NRESWARM 0x0064 -#define SYS_PWR_REQ 0x0066 -#define SYS_NIRQ1 0x0068 -#define SYS_NIRQ2 0x006a -#define SR_PMIC_SCL 0x006c -#define SR_PMIC_SDA 0x006e -#define SYS_BOOT0 0x0070 -#define SYS_BOOT1 0x0072 -#define SYS_BOOT2 0x0074 -#define SYS_BOOT3 0x0076 -#define SYS_BOOT4 0x0078 -#define SYS_BOOT5 0x007a - -#endif /* _MUX_OMAP5_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h deleted file mode 100644 index 19fdecec0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Authors: - * Aneesh V <aneesh@ti.com> - * Sricharan R <r.sricharan@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _OMAP5_H_ -#define _OMAP5_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP54XX_L4_CORE_BASE 0x4A000000 -#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 -#define OMAP54XX_L4_PER_BASE 0x48000000 - -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF -#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END - -/* CONTROL ID CODE */ -#define CONTROL_CORE_ID_CODE 0x4A002204 -#define CONTROL_WKUP_ID_CODE 0x4AE0C204 - -#ifdef CONFIG_DRA7XX -#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE -#else -#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE -#endif - -/* To be verified */ -#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F -#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F -#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F -#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F -#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F -#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F - -/* UART */ -#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) -#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) -#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) - -/* General Purpose Timers */ -#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) -#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) -#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) - -/* Watchdog Timer2 - MPU watchdog */ -#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) - -/* GPMC */ -#define OMAP54XX_GPMC_BASE 0x50000000 - -/* QSPI */ -#define QSPI_BASE 0x4B300000 - -/* SATA */ -#define DWC_AHSATA_BASE 0x4A140000 - -/* - * Hardware Register Details - */ - -/* Watchdog Timer */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* GP Timer */ -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* Control Module */ -#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) -#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f -#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 -#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 - -/* LPDDR2 IO regs */ -#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C -#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E -#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C -#define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 - -/* CONTROL_EFUSE_2 */ -#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 - -#define SDCARD_BIAS_PWRDNZ (1 << 27) -#define SDCARD_PWRDNZ (1 << 26) -#define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_PBIASLITE_VMODE (1 << 21) - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#define DEVICE_TYPE_SHIFT 0x6 -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#define DEVICE_GP 0x3 - -/* Output impedance control */ -#define ds_120_ohm 0x0 -#define ds_60_ohm 0x1 -#define ds_45_ohm 0x2 -#define ds_30_ohm 0x3 -#define ds_mask 0x3 - -/* Slew rate control */ -#define sc_slow 0x0 -#define sc_medium 0x1 -#define sc_fast 0x2 -#define sc_na 0x3 -#define sc_mask 0x3 - -/* Target capacitance control */ -#define lb_5_12_pf 0x0 -#define lb_12_25_pf 0x1 -#define lb_25_50_pf 0x2 -#define lb_50_80_pf 0x3 -#define lb_mask 0x3 - -#define usb_i_mask 0x7 - -#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 -#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 -#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 -#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 -#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 - -#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 -#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC -#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 - -#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 -#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC -#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 - -#define EFUSE_1 0x45145100 -#define EFUSE_2 0x45145100 -#define EFUSE_3 0x45145100 -#define EFUSE_4 0x45145100 -#endif /* __ASSEMBLY__ */ - -/* - * In all cases, the TRM defines the RAM Memory Map for the processor - * and indicates the area for the downloaded image. We use all of that - * space for download and once up and running may use other parts of the - * map for our needs. We set a scratch space that is at the end of the - * OMAP5 download area, but within the DRA7xx download area (as it is - * much larger) and do not, at this time, make use of the additional - * space. - */ -#ifdef CONFIG_DRA7XX -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ -#else -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ -#endif -#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_ROM_VECT_BASE 0x4031F000 - -/* CONTROL_SRCOMP_XXX_SIDE */ -#define OVERRIDE_XS_SHIFT 30 -#define OVERRIDE_XS_MASK (1 << 30) -#define SRCODE_READ_XS_SHIFT 12 -#define SRCODE_READ_XS_MASK (0xff << 12) -#define PWRDWN_XS_SHIFT 11 -#define PWRDWN_XS_MASK (1 << 11) -#define DIVIDE_FACTOR_XS_SHIFT 4 -#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) -#define MULTIPLY_FACTOR_XS_SHIFT 1 -#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) -#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 -#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 50 -#define OMAP_ABB_CLOCK_CYCLES 16 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) - -/* ABB efuse masks */ -#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) -#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) -#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) -#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) -#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) -#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) - -/* IO Delay module defines */ -#define CFG_IO_DELAY_BASE 0x4844A000 -#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) - -/* CPSW IO Delay registers*/ -#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) -#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) -#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) -#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) -#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) -#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) -#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) -#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) -#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) -#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) - -#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA -#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB -#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 -#define CFG_IO_DELAY_LOCK_MASK 0x400 - -#ifndef __ASSEMBLY__ -struct srcomp_params { - s8 divide_factor; - s8 multiply_factor; -}; - -struct ctrl_ioregs { - u32 ctrl_ddrch; - u32 ctrl_lpddr2ch; - u32 ctrl_ddr3ch; - u32 ctrl_ddrio_0; - u32 ctrl_ddrio_1; - u32 ctrl_ddrio_2; - u32 ctrl_emif_sdram_config_ext; - u32 ctrl_emif_sdram_config_ext_final; - u32 ctrl_ddr_ctrl_ext_0; -}; - -struct io_delay { - u32 addr; - u32 dly; -}; -#endif /* __ASSEMBLY__ */ -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h deleted file mode 100644 index b69165b5e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SATA Wrapper Register map - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TI_SATA_H -#define _TI_SATA_H - -/* SATA Wrapper module */ -#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) -/* SATA PHY Module */ -#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) - -/* SATA Wrapper register offsets */ -#define TI_SATA_SYSCONFIG 0x00 -#define TI_SATA_CDRLOCK 0x04 - -/* Register Set */ -#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) -#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) -#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) - -/* Standby modes */ -#define TI_SATA_STANDBY_FORCE 0x0 -#define TI_SATA_STANDBY_NO (0x1 << 4) -#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) -#define TI_SATA_STANDBY_SMART (0x2 << 4) - -/* Idle modes */ -#define TI_SATA_IDLE_FORCE 0x0 -#define TI_SATA_IDLE_NO (0x1 << 2) -#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) -#define TI_SATA_IDLE_SMART (0x2 << 2) - -#endif /* _TI_SATA_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h deleted file mode 100644 index f70799860..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_SATA 9 -#define BOOT_DEVICE_SPI 10 -#define BOOT_DEVICE_UART 0x43 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h deleted file mode 100644 index bf12c7337..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/arch/omap.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/omap_common.h> -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/clock.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct pad_conf_entry { - u32 offset; - u32 val; -}; - -struct omap_sysinfo { - char *board_string; -}; -extern const struct omap_sysinfo sysinfo; - -void gpmc_init(void); -void watchdog_init(void); -u32 get_device_type(void); -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); -void set_muxconf_regs_essential(void); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void setup_clocks_for_console(void); -void prcm_init(void); -void bypass_dpll(u32 const base); -void freq_update_core(void); -u32 get_sys_clk_freq(void); -u32 omap5_ddr_clk(void); -void cancel_out(u32 *num, u32 *den, u32 den_limit); -void sdram_init(void); -u32 omap_sdram_size(void); -u32 cortex_rev(void); -void save_omap_boot_params(void); -void init_omap_revision(void); -void do_io_settings(void); -void sri2c_init(void); -void gpi2c_init(void); -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); -u32 warm_reset(void); -void force_emif_self_refresh(void); -void get_ioregs(const struct ctrl_ioregs **regs); -void srcomp_enable(void); -void setup_warmreset_time(void); - -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP54XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - -static inline u32 div_round_up(u32 num, u32 den) -{ - return (num + den - 1)/den; -} - -static inline u32 usec_to_32k(u32 usec) -{ - return div_round_up(32768 * usec, 1000000); -} -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/cpu.h deleted file mode 100644 index 08a450f1f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/cpu.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * Based on original Kirorion5x_ood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ORION5X_CPU_H -#define _ORION5X_CPU_H - -#include <asm/system.h> - -#ifndef __ASSEMBLY__ - -#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) - -#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) - -enum memory_bank { - BANK0, - BANK1, - BANK2, - BANK3 -}; - -enum orion5x_cpu_winen { - ORION5X_WIN_DISABLE, - ORION5X_WIN_ENABLE -}; - -enum orion5x_cpu_target { - ORION5X_TARGET_DRAM = 0, - ORION5X_TARGET_DEVICE = 1, - ORION5X_TARGET_PCI = 3, - ORION5X_TARGET_PCIE = 4, - ORION5X_TARGET_SASRAM = 9 -}; - -enum orion5x_cpu_attrib { - ORION5X_ATTR_DRAM_CS0 = 0x0e, - ORION5X_ATTR_DRAM_CS1 = 0x0d, - ORION5X_ATTR_DRAM_CS2 = 0x0b, - ORION5X_ATTR_DRAM_CS3 = 0x07, - ORION5X_ATTR_PCI_MEM = 0x59, - ORION5X_ATTR_PCI_IO = 0x51, - ORION5X_ATTR_PCIE_MEM = 0x59, - ORION5X_ATTR_PCIE_IO = 0x51, - ORION5X_ATTR_SASRAM = 0x00, - ORION5X_ATTR_DEV_CS0 = 0x1e, - ORION5X_ATTR_DEV_CS1 = 0x1d, - ORION5X_ATTR_DEV_CS2 = 0x1b, - ORION5X_ATTR_BOOTROM = 0x0f -}; - -/* - * Device Address MAP BAR values - * - * All addresses and sizes not defined by board code - * will be given default values here. - */ - -#if !defined (ORION5X_ADR_PCIE_MEM) -#define ORION5X_ADR_PCIE_MEM 0x90000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) -#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) -#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 -#endif - -#if !defined (ORION5X_SZ_PCIE_MEM) -#define ORION5X_SZ_PCIE_MEM (128*1024*1024) -#endif - -#if !defined (ORION5X_ADR_PCIE_IO) -#define ORION5X_ADR_PCIE_IO 0xf0000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) -#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000 -#endif - -#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) -#define ORION5X_ADR_PCIE_IO_REMAP_HI 0 -#endif - -#if !defined (ORION5X_SZ_PCIE_IO) -#define ORION5X_SZ_PCIE_IO (64*1024) -#endif - -#if !defined (ORION5X_ADR_PCI_MEM) -#define ORION5X_ADR_PCI_MEM 0x98000000 -#endif - -#if !defined (ORION5X_SZ_PCI_MEM) -#define ORION5X_SZ_PCI_MEM (128*1024*1024) -#endif - -#if !defined (ORION5X_ADR_PCI_IO) -#define ORION5X_ADR_PCI_IO 0xf0100000 -#endif - -#if !defined (ORION5X_SZ_PCI_IO) -#define ORION5X_SZ_PCI_IO (64*1024) -#endif - -#if !defined (ORION5X_ADR_DEV_CS0) -#define ORION5X_ADR_DEV_CS0 0xfa000000 -#endif - -#if !defined (ORION5X_SZ_DEV_CS0) -#define ORION5X_SZ_DEV_CS0 (2*1024*1024) -#endif - -#if !defined (ORION5X_ADR_DEV_CS1) -#define ORION5X_ADR_DEV_CS1 0xf8000000 -#endif - -#if !defined (ORION5X_SZ_DEV_CS1) -#define ORION5X_SZ_DEV_CS1 (32*1024*1024) -#endif - -#if !defined (ORION5X_ADR_DEV_CS2) -#define ORION5X_ADR_DEV_CS2 0xfa800000 -#endif - -#if !defined (ORION5X_SZ_DEV_CS2) -#define ORION5X_SZ_DEV_CS2 (1*1024*1024) -#endif - -#if !defined (ORION5X_ADR_BOOTROM) -#define ORION5X_ADR_BOOTROM 0xFFF80000 -#endif - -#if !defined (ORION5X_SZ_BOOTROM) -#define ORION5X_SZ_BOOTROM (512*1024) -#endif - -/* - * PCIE registers are used for SoC device ID and revision - */ -#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) -#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) - -/* - * The following definitions are intended for identifying - * the real device and revision on which u-boot is running - * even if it was compiled only for a specific one. Thus, - * these constants must not be considered chip-specific. - */ - -/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -#define MV88F5181L_REV_A0 8 -#define MV88F5181L_REV_A1 9 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D0 4 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 -/* Orion-1-90 (88F6183) */ -#define MV88F6183_DEV_ID 0x6183 -#define MV88F6183_REV_B0 3 - -/* - * read feroceon core extra feature register - * using co-proc instruction - */ -static inline unsigned int readfr_extra_feature_reg(void) -{ - unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r" - (val) : : "cc"); - return val; -} - -/* - * write feroceon core extra feature register - * using co-proc instruction - */ -static inline void writefr_extra_feature_reg(unsigned int val) -{ - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r" - (val) : "cc"); - isb(); -} - -/* - * AHB to Mbus Bridge Registers - * Source: 88F5182 User Manual, Appendix A, section A.4 - * Note: only windows 0 and 1 have remap capability. - */ -struct orion5x_win_registers { - u32 ctrl; - u32 base; - u32 remap_lo; - u32 remap_hi; -}; - -/* - * CPU control and status Registers - * Source: 88F5182 User Manual, Appendix A, section A.4 - */ -struct orion5x_cpu_registers { - u32 config; /*0x20100 */ - u32 ctrl_stat; /*0x20104 */ - u32 rstoutn_mask; /* 0x20108 */ - u32 sys_soft_rst; /* 0x2010C */ - u32 ahb_mbus_cause_irq; /* 0x20110 */ - u32 ahb_mbus_mask_irq; /* 0x20114 */ -}; - -/* - * DDR SDRAM Controller Address Decode Registers - * Source: 88F5182 User Manual, Appendix A, section A.5.1 - */ -struct orion5x_ddr_addr_decode_registers { - u32 base; - u32 size; -}; - -/* - * functions - */ -u32 orion5x_device_id(void); -u32 orion5x_device_rev(void); -unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); -void timer_init_r(void); -#endif /* __ASSEMBLY__ */ -#endif /* _ORION5X_CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/mv88f5182.h deleted file mode 100644 index e6c71ae1b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/mv88f5182.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * Based on original Kirkwood 88F6182 support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Header file for Feroceon CPU core 88F5182 SOC. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_88F5182_H -#define _CONFIG_88F5182_H - -/* SOC specific definitions */ -#define F88F5182_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE - -/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -#endif /* _CONFIG_88F5182_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/orion5x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/orion5x.h deleted file mode 100644 index fbb1de8c0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/orion5x.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * Header file for Marvell's Orion SoC with Feroceon CPU core. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_ORION5X_H -#define _ASM_ARCH_ORION5X_H - -#if defined(CONFIG_FEROCEON) - -/* SOC specific definations */ -#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) - -/* Documented registers */ -#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) -#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) -#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) -#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) -#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) -#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) -#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) -#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) -#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) -#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) -#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) -#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) -#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) -#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) -#define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000)) -#define ORION5X_SATA_PORT0_OFFSET 0x2000 -#define ORION5X_SATA_PORT1_OFFSET 0x4000 - -/* Orion5x GbE controller has a single port */ -#define MAX_MVGBE_DEVS 1 -#define MVGBE0_BASE ORION5X_EGIGA_BASE - -/* Orion5x USB Host controller is port 1 */ -#define MVUSB0_BASE ORION5X_USB20_HOST_PORT_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 ORION5X_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 ORION5X_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 ORION5X_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 ORION5X_ATTR_DRAM_CS3 - -/* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA ORION5X_CPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE -#define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE - -#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) - -/* include here SoC variants. 5181, 5281, 6183 should go here when - adding support for them, and this comment should then be updated. */ -#if defined(CONFIG_88F5182) -#include <asm/arch/mv88f5182.h> -#else -#error "SOC Name not defined" -#endif -#endif /* CONFIG_FEROCEON */ -#endif /* _ASM_ARCH_ORION5X_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/config.h deleted file mode 100644 index fdccd222d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/config.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_CONFIG_H -#define _PANTHEON_CONFIG_H - -#include <asm/arch/pantheon.h> - -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ -/* default Dcache Line length for pantheon */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE PANTHEON_MFPR_BASE -#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ -/* - * I2C definition - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_REG 0xd4011000 -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 0 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -/* - * MMC definition - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_CMD_FAT 1 -#define CONFIG_MMC 1 -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_SDHCI 1 -#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1 -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000 -#define CONFIG_MMC_SDMA 1 -#define CONFIG_MV_SDHCI 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -#define CONFIG_SYS_MMC_NUM 2 -#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000} -#endif - -#endif /* _PANTHEON_CONFIG_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/cpu.h deleted file mode 100644 index 3ccdf8a35..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/cpu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_CPU_H -#define _PANTHEON_CPU_H - -#include <asm/io.h> -#include <asm/system.h> - -/* - * Main Power Management (MPMU) Registers - * Refer Register Datasheet 9.1 - */ -struct panthmpmu_registers { - u8 pad0[0x0024]; - u32 ccgr; /*0x0024*/ - u8 pad1[0x0200 - 0x024 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad2[0x1020 - 0x200 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ -}; - -/* - * Application Power Management (APMU) Registers - * Refer Register Datasheet 9.2 - */ -struct panthapmu_registers { - u8 pad0[0x0054]; - u32 sd1; /*0x0054*/ - u8 pad1[0x00e0 - 0x054 - 4]; - u32 sd3; /*0x00e0*/ -}; - -/* - * APB Clock Reset/Control Registers - * Refer Register Datasheet 6.14 - */ -struct panthapb_registers { - u32 uart0; /*0x000*/ - u32 uart1; /*0x004*/ - u32 gpio; /*0x008*/ - u8 pad0[0x02c - 0x08 - 4]; - u32 twsi; /*0x02c*/ - u8 pad1[0x034 - 0x2c - 4]; - u32 timers; /*0x034*/ -}; - -/* - * CPU Interface Registers - * Refer Register Datasheet 4.3 - */ -struct panthcpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 panth_sdram_base(int); -u32 panth_sdram_size(int); -int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); - -#endif /* _PANTHEON_CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/mfp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/mfp.h deleted file mode 100644 index 7909d53d4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/mfp.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Based on arch/arm/include/asm/arch-armada100/mfp.h - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PANTHEON_MFP_H -#define __PANTHEON_MFP_H - -/* - * Frequently used MFP Configuration macros for all PANTHEON family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ -#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM) - -#define MFP_PIN_MAX 117 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/pantheon.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/pantheon.h deleted file mode 100644 index c3a71bfce..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/pantheon.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_H -#define _PANTHEON_H - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Common APMU register bit definitions */ -#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */ -#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/ -#define APMU_PERI_RST (1<<1) /* Peripheral Reset */ -#define APMU_AXI_RST (1<<0) /* AXI Reset */ - -/* Register Base Addresses */ -#define PANTHEON_DRAM_BASE 0xB0000000 -#define PANTHEON_TIMER_BASE 0xD4014000 -#define PANTHEON_WD_TIMER_BASE 0xD4080000 -#define PANTHEON_APBC_BASE 0xD4015000 -#define PANTHEON_UART1_BASE 0xD4017000 -#define PANTHEON_UART2_BASE 0xD4018000 -#define PANTHEON_GPIO_BASE 0xD4019000 -#define PANTHEON_MFPR_BASE 0xD401E000 -#define PANTHEON_MPMU_BASE 0xD4050000 -#define PANTHEON_APMU_BASE 0xD4282800 -#define PANTHEON_CPU_BASE 0xD4282C00 - -#endif /* _PANTHEON_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h deleted file mode 100644 index 104a21c2e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h deleted file mode 100644 index e671c143a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/hardware.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: This file was taken from linux-2.4.19-rmk4-pxa1 - * - * - 2003/01/20 implementation specifics activated - * Robert Schwebel <r.schwebel@pengutronix.de> - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/mach-types.h> - -/* - * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. - * PXA300/310/320 all have distinct register mappings in some cases, that's why - * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common - * drivers and compatibility glue with old source then. - */ -#ifndef CONFIG_CPU_MONAHANS -#if defined(CONFIG_CPU_PXA300) || \ - defined(CONFIG_CPU_PXA310) || \ - defined(CONFIG_CPU_PXA320) -#define CONFIG_CPU_MONAHANS -#endif -#endif - -/* - * These are statically mapped PCMCIA IO space for designs using it as a - * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc. - * The actual PCMCIA code is mapping required IO region at run time. - */ -#define PCMCIA_IO_0_BASE 0xf6000000 -#define PCMCIA_IO_1_BASE 0xf7000000 - - -/* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* - * Workarounds for at least 2 errata so far require this. - * The mapping is set in mach-pxa/generic.c. - */ -#define UNCACHED_PHYS_0 0xff000000 -#define UNCACHED_ADDR UNCACHED_PHYS_0 - -/* - * Intel PXA internal I/O mappings: - * - * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff - * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff - * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff - */ - -#include "pxa-regs.h" - -#ifndef __ASSEMBLY__ - -/* - * GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * This must be called *before* the corresponding IRQ is registered. - * Use this instead of directly setting GRER/GFER. - */ -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 - -#endif - - -/* - * Implementation specifics - */ - -#ifdef CONFIG_ARCH_LUBBOCK -#include "lubbock.h" -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -#include "idp.h" -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -#include "cerf.h" -#endif - -#ifdef CONFIG_ARCH_CSB226 -#include "csb226.h" -#endif - -#ifdef CONFIG_ARCH_INNOKOM -#include "innokom.h" -#endif - -#ifdef CONFIG_ARCH_PLEB -#include "pleb.h" -#endif - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h deleted file mode 100644 index b81b42c07..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ /dev/null @@ -1,2635 +0,0 @@ -/* - * linux/include/asm-arm/arch-pxa/pxa-regs.h - * - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de - * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions. - * Added include for hardware.h (for __REG definition) - */ -#ifndef _PXA_REGS_H_ -#define _PXA_REGS_H_ - -#include "bitfield.h" -#include "hardware.h" - -/* FIXME hack so that SA-1111.h will work [cb] */ - -#ifndef __ASSEMBLY__ -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; -#endif - -/* - * PXA Chip selects - */ -#ifdef CONFIG_CPU_MONAHANS -#define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */ -#define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */ -#define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */ -#define PXA_CS2_PHYS 0x10000000 /* (64MB) */ -#define PXA_CS3_PHYS 0x14000000 /* (64MB) */ -#define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */ -#else -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * Personal Computer Memory Card International Association (PCMCIA) sockets - */ -#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ -#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ - -#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ -#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ -#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ -#endif - -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ -#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ -#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ - -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) - -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ - -#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ -#endif - -/* - * DMA Controller - */ -#define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */ -#define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */ -#define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */ -#define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */ -#define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */ -#define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */ -#define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */ -#define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */ -#define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */ -#define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */ -#define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */ -#define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */ -#define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */ -#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ -#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ -#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ -#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ -#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ -#define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */ -#define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */ -#define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */ -#define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */ -#define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */ -#define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */ -#define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */ -#define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */ -#define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */ -#define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */ -#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ -#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ -#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#define DCSR(x) (0x40000000 | ((x) << 2)) - -#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ -#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ -#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ -#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ -#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ -#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ -#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ -#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ -#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ -#endif - -#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ -#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ -#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ -#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ -#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ - -#define DINT 0x400000f0 /* DMA Interrupt Register */ - -#define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */ -#define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */ -#define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */ -#define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */ -#define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */ -#define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ -#define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */ -#define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */ -#define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */ -#define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */ -#define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */ -#define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */ -#define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */ -#define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */ -#define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */ -#define DRCMR15 0x4000013c /* Reserved */ -#define DRCMR16 0x40000140 /* Reserved */ -#define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */ -#define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */ -#define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */ -#define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */ -#define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */ -#define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */ -#define DRCMR23 0x4000015c /* Reserved */ -#define DRCMR24 0x40000160 /* Reserved */ -#define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */ -#define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */ -#define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */ -#define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */ -#define DRCMR29 0x40000174 /* Reserved */ -#define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */ -#define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */ -#define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */ -#define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */ -#define DRCMR34 0x40000188 /* Reserved */ -#define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */ -#define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */ -#define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */ -#define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */ -#define DRCMR39 0x4000019C /* Reserved */ - -#define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */ -#define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */ -#define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */ - -#define DRCMRRXSADR DRCMR2 -#define DRCMRTXSADR DRCMR3 -#define DRCMRRXBTRBR DRCMR4 -#define DRCMRTXBTTHR DRCMR5 -#define DRCMRRXFFRBR DRCMR6 -#define DRCMRTXFFTHR DRCMR7 -#define DRCMRRXMCDR DRCMR8 -#define DRCMRRXMODR DRCMR9 -#define DRCMRTXMODR DRCMR10 -#define DRCMRRXPCDR DRCMR11 -#define DRCMRTXPCDR DRCMR12 -#define DRCMRRXSSDR DRCMR13 -#define DRCMRTXSSDR DRCMR14 -#define DRCMRRXICDR DRCMR17 -#define DRCMRTXICDR DRCMR18 -#define DRCMRRXSTRBR DRCMR19 -#define DRCMRTXSTTHR DRCMR20 -#define DRCMRRXMMC DRCMR21 -#define DRCMRTXMMC DRCMR22 - -#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ -#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ - -#define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */ -#define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */ -#define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */ -#define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */ -#define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */ -#define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */ -#define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */ -#define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */ -#define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */ -#define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */ -#define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */ -#define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */ -#define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */ -#define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */ -#define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */ -#define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */ -#define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */ -#define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */ -#define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */ -#define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */ -#define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */ -#define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */ -#define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */ -#define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */ -#define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */ -#define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */ -#define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */ -#define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */ -#define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */ -#define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */ -#define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */ -#define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */ -#define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */ -#define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */ -#define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */ -#define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */ -#define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */ -#define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */ -#define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */ -#define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */ -#define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */ -#define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */ -#define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */ -#define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */ -#define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */ -#define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */ -#define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */ -#define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */ -#define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */ -#define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */ -#define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */ -#define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */ -#define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */ -#define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */ -#define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */ -#define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */ -#define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */ -#define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */ -#define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */ -#define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */ -#define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */ -#define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */ -#define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */ -#define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */ - -#define DDADR(x) (0x40000200 | ((x) << 4)) -#define DSADR(x) (0x40000204 | ((x) << 4)) -#define DTADR(x) (0x40000208 | ((x) << 4)) -#define DCMD(x) (0x4000020c | ((x) << 4)) - -#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ -#define DDADR_STOP (1 << 0) /* Stop (read / write) */ - -#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ -#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ -#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ -#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ -#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ -#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ -#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ -#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ -#define DCMD_BURST16 (2 << 16) /* 16 byte burst */ -#define DCMD_BURST32 (3 << 16) /* 32 byte burst */ -#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ -#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ -#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ -#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -/* default combinations */ -#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) -#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) -#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) - -/******************************************************************************/ -/* - * IrSR (Infrared Selection Register) - */ -#define IrSR_OFFSET 0x20 - -#define IrSR_RXPL_NEG_IS_ZERO (1<<4) -#define IrSR_RXPL_POS_IS_ZERO 0x0 -#define IrSR_TXPL_NEG_IS_ZERO (1<<3) -#define IrSR_TXPL_POS_IS_ZERO 0x0 -#define IrSR_XMODE_PULSE_1_6 (1<<2) -#define IrSR_XMODE_PULSE_3_16 0x0 -#define IrSR_RCVEIR_IR_MODE (1<<1) -#define IrSR_RCVEIR_UART_MODE 0x0 -#define IrSR_XMITIR_IR_MODE (1<<0) -#define IrSR_XMITIR_UART_MODE 0x0 - -#define IrSR_IR_RECEIVE_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_IR_MODE | \ - IrSR_XMITIR_UART_MODE) - -#define IrSR_IR_TRANSMIT_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_UART_MODE | \ - IrSR_XMITIR_IR_MODE) - -/* - * Serial Audio Controller - */ -/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these - * short defines because there is too much chance of namespace collision - */ -#define SACR0 0x40400000 /* Global Control Register */ -#define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */ -#define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ -#define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */ -#define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */ -#define SADIV 0x40400060 /* Audio Clock Divider Register. */ -#define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ - -/* - * AC97 Controller registers - */ -#define POCR 0x40500000 /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define PICR 0x40500004 /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define MCCR 0x40500008 /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ - -#define GCR 0x4050000C /* Global Control Register */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR 0x40500010 /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ - -#define PISR 0x40500014 /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ - -#define MCSR 0x40500018 /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ - -#define GSR 0x4050001C /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR 0x40500020 /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR 0x40500040 /* PCM FIFO Data Register */ -#define MCDR 0x40500060 /* Mic-in FIFO Data Register */ - -#define MOCR 0x40500100 /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ - -#define MICR 0x40500108 /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ - -#define MOSR 0x40500110 /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ - -#define MISR 0x40500118 /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ - -#define MODR 0x40500140 /* Modem FIFO Data Register */ - -#define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */ -#define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */ -#define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */ -#define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */ - - -/* - * USB Device Controller - */ -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -#define UDCCR 0x40600000 /* UDC Control Register */ -#define UDCCR_UDE (1 << 0) /* UDC enable */ -#define UDCCR_UDA (1 << 1) /* UDC active */ -#define UDCCR_RSM (1 << 2) /* Device resume */ -#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ -#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */ -#define UDCCR_RESIR (1 << 29) /* Resume interrupt request */ -#define UDCCR_SUSIR (1 << 28) /* Suspend interrupt request */ -#define UDCCR_SM (1 << 28) /* Suspend interrupt mask */ -#define UDCCR_RSTIR (1 << 27) /* Reset interrupt request */ -#define UDCCR_REM (1 << 27) /* Reset interrupt mask */ -#define UDCCR_RM (1 << 29) /* resume interrupt mask */ -#define UDCCR_SRM (UDCCR_SM|UDCCR_RM) -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */ -#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */ -#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */ -#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ -#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ -#define UDCCR_ACN_S 11 -#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ -#define UDCCR_AIN_S 8 -#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */ -#define UDCCR_AAISN_S 5 - -#define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */ -#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ -#define UDCCS0_IPR (1 << 1) /* IN packet ready */ -#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS0_DRWF (1 << 16) /* Device remote wakeup feature */ -#define UDCCS0_SST (1 << 4) /* Sent stall */ -#define UDCCS0_FST (1 << 5) /* Force stall */ -#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ -#define UDCCS0_SA (1 << 7) /* Setup active */ - -/* Bulk IN - Endpoint 1,6,11 */ -#define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */ -#define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */ -#define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */ - -#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_BI_FTF (1 << 8) /* Flush Tx FIFO */ -#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_BI_SST (1 << 4) /* Sent stall */ -#define UDCCS_BI_FST (1 << 5) /* Force stall */ -#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ - -/* Bulk OUT - Endpoint 2,7,12 */ -#define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */ -#define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */ -#define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */ - -#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_BO_DME (1 << 3) /* DMA enable */ -#define UDCCS_BO_SST (1 << 4) /* Sent stall */ -#define UDCCS_BO_FST (1 << 5) /* Force stall */ -#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ - -/* Isochronous IN - Endpoint 3,8,13 */ -#define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */ -#define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */ -#define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */ - -#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ - -/* Isochronous OUT - Endpoint 4,9,14 */ -#define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */ -#define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */ -#define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */ - -#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ -#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ -#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ -#define UDCCS_IO_DME (1 << 3) /* DMA enable */ -#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ -#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ - -/* Interrupt IN - Endpoint 5,10,15 */ -#define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ -#define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ -#define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ - -#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ -#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ -#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ -#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ -#define UDCCS_INT_SST (1 << 4) /* Sent stall */ -#define UDCCS_INT_FST (1 << 5) /* Force stall */ -#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ - -#define UFNRH 0x40600060 /* UDC Frame Number Register High */ -#define UFNRL 0x40600014 /* UDC Frame Number Register Low */ -#define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */ -#define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */ -#define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */ -#define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */ -#define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */ -#define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */ -#define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */ -#define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */ -#define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */ -#define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */ -#define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */ -#define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */ -#define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */ -#define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */ -#define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */ -#define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */ -#define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */ -#define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */ -#define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */ -#define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */ -#define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */ -#define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */ - -#define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */ - -#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ -#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ -#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ -#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ -#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ -#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ -#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ -#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ - -#define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */ - -#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ -#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ -#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ -#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ -#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ -#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ -#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ -#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ - -#define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */ - -#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ -#define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */ -#define USIR0_IR2 (1 << 4) /* Interrup request ep 2 */ -#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ -#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ -#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ -#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ -#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ - -#define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */ - -#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ -#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ -#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ -#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ -#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ -#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ -#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ -#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ - - -#define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */ -#define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */ -#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ -#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ - -#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ - -#define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */ -#define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */ -#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */ -#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */ -#define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */ -#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */ - - -#define UDCFNR 0x40600014 /* UDC Frame Number Register */ -#define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */ -#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */ -#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */ -#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ - -#define UDCCSN(x) (0x40600100 + ((x) << 2)) -#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */ - -#define UDCCSR0_SA (1 << 7) /* Setup Active */ -#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define UDCCSR0_FST (1 << 5) /* Force Stall */ -#define UDCCSR0_SST (1 << 4) /* Sent Stall */ -#define UDCCSR0_DME (1 << 3) /* DMA Enable */ -#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ - -#define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */ - -#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ -#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ -#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ -#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ -#define UDCCSR_FST (1 << 5) /* Force STALL */ -#define UDCCSR_SST (1 << 4) /* Sent STALL */ -#define UDCCSR_DME (1 << 3) /* DMA Enable */ -#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ -#define UDCCSR_PC (1 << 1) /* Packet Complete */ -#define UDCCSR_FS (1 << 0) /* FIFO needs service */ - -#define UDCBCN(x) (0x40600200 + ((x) << 2)) -#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */ -#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */ -#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */ -#define UDCBCRC 0x4060020C /* Byte Count Register - EPC */ -#define UDCBCRD 0x40600210 /* Byte Count Register - EPD */ -#define UDCBCRE 0x40600214 /* Byte Count Register - EPE */ -#define UDCBCRF 0x40600218 /* Byte Count Register - EPF */ -#define UDCBCRG 0x4060021C /* Byte Count Register - EPG */ -#define UDCBCRH 0x40600220 /* Byte Count Register - EPH */ -#define UDCBCRI 0x40600224 /* Byte Count Register - EPI */ -#define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */ -#define UDCBCRK 0x4060022C /* Byte Count Register - EPK */ -#define UDCBCRL 0x40600230 /* Byte Count Register - EPL */ -#define UDCBCRM 0x40600234 /* Byte Count Register - EPM */ -#define UDCBCRN 0x40600238 /* Byte Count Register - EPN */ -#define UDCBCRP 0x4060023C /* Byte Count Register - EPP */ -#define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */ -#define UDCBCRR 0x40600244 /* Byte Count Register - EPR */ -#define UDCBCRS 0x40600248 /* Byte Count Register - EPS */ -#define UDCBCRT 0x4060024C /* Byte Count Register - EPT */ -#define UDCBCRU 0x40600250 /* Byte Count Register - EPU */ -#define UDCBCRV 0x40600254 /* Byte Count Register - EPV */ -#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */ -#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */ - -#define UDCDN(x) (0x40600300 + ((x) << 2)) -#define UDCDR0 0x40600300 /* Data Register - EP0 */ -#define UDCDRA 0x40600304 /* Data Register - EPA */ -#define UDCDRB 0x40600308 /* Data Register - EPB */ -#define UDCDRC 0x4060030C /* Data Register - EPC */ -#define UDCDRD 0x40600310 /* Data Register - EPD */ -#define UDCDRE 0x40600314 /* Data Register - EPE */ -#define UDCDRF 0x40600318 /* Data Register - EPF */ -#define UDCDRG 0x4060031C /* Data Register - EPG */ -#define UDCDRH 0x40600320 /* Data Register - EPH */ -#define UDCDRI 0x40600324 /* Data Register - EPI */ -#define UDCDRJ 0x40600328 /* Data Register - EPJ */ -#define UDCDRK 0x4060032C /* Data Register - EPK */ -#define UDCDRL 0x40600330 /* Data Register - EPL */ -#define UDCDRM 0x40600334 /* Data Register - EPM */ -#define UDCDRN 0x40600338 /* Data Register - EPN */ -#define UDCDRP 0x4060033C /* Data Register - EPP */ -#define UDCDRQ 0x40600340 /* Data Register - EPQ */ -#define UDCDRR 0x40600344 /* Data Register - EPR */ -#define UDCDRS 0x40600348 /* Data Register - EPS */ -#define UDCDRT 0x4060034C /* Data Register - EPT */ -#define UDCDRU 0x40600350 /* Data Register - EPU */ -#define UDCDRV 0x40600354 /* Data Register - EPV */ -#define UDCDRW 0x40600358 /* Data Register - EPW */ -#define UDCDRX 0x4060035C /* Data Register - EPX */ - -#define UDCCN(x) (0x40600400 + ((x) << 2)) -#define UDCCRA 0x40600404 /* Configuration register EPA */ -#define UDCCRB 0x40600408 /* Configuration register EPB */ -#define UDCCRC 0x4060040C /* Configuration register EPC */ -#define UDCCRD 0x40600410 /* Configuration register EPD */ -#define UDCCRE 0x40600414 /* Configuration register EPE */ -#define UDCCRF 0x40600418 /* Configuration register EPF */ -#define UDCCRG 0x4060041C /* Configuration register EPG */ -#define UDCCRH 0x40600420 /* Configuration register EPH */ -#define UDCCRI 0x40600424 /* Configuration register EPI */ -#define UDCCRJ 0x40600428 /* Configuration register EPJ */ -#define UDCCRK 0x4060042C /* Configuration register EPK */ -#define UDCCRL 0x40600430 /* Configuration register EPL */ -#define UDCCRM 0x40600434 /* Configuration register EPM */ -#define UDCCRN 0x40600438 /* Configuration register EPN */ -#define UDCCRP 0x4060043C /* Configuration register EPP */ -#define UDCCRQ 0x40600440 /* Configuration register EPQ */ -#define UDCCRR 0x40600444 /* Configuration register EPR */ -#define UDCCRS 0x40600448 /* Configuration register EPS */ -#define UDCCRT 0x4060044C /* Configuration register EPT */ -#define UDCCRU 0x40600450 /* Configuration register EPU */ -#define UDCCRV 0x40600454 /* Configuration register EPV */ -#define UDCCRW 0x40600458 /* Configuration register EPW */ -#define UDCCRX 0x4060045C /* Configuration register EPX */ - -#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ -#define UDCCONR_CN_S (25) -#define UDCCONR_IN (0x07 << 22) /* Interface Number */ -#define UDCCONR_IN_S (22) -#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ -#define UDCCONR_AISN_S (19) -#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ -#define UDCCONR_EN_S (15) -#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ -#define UDCCONR_ET_S (13) -#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ -#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ -#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ -#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ -#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ -#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ -#define UDCCONR_MPS_S (2) -#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ -#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ - - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) -#define UDC_FNR_MASK (0x7ff) -#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) -#define UDC_BCR_MASK (0x3ff) - -#endif /* CONFIG_CPU_PXA27X */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -/******************************************************************************/ -/* - * USB Host Controller - */ -#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ -#define UHCREV 0x4C000000 -#define UHCHCON 0x4C000004 -#define UHCCOMS 0x4C000008 -#define UHCINTS 0x4C00000C -#define UHCINTE 0x4C000010 -#define UHCINTD 0x4C000014 -#define UHCHCCA 0x4C000018 -#define UHCPCED 0x4C00001C -#define UHCCHED 0x4C000020 -#define UHCCCED 0x4C000024 -#define UHCBHED 0x4C000028 -#define UHCBCED 0x4C00002C -#define UHCDHEAD 0x4C000030 -#define UHCFMI 0x4C000034 -#define UHCFMR 0x4C000038 -#define UHCFMN 0x4C00003C -#define UHCPERS 0x4C000040 -#define UHCLST 0x4C000044 -#define UHCRHDA 0x4C000048 -#define UHCRHDB 0x4C00004C -#define UHCRHS 0x4C000050 -#define UHCRHPS1 0x4C000054 -#define UHCRHPS2 0x4C000058 -#define UHCRHPS3 0x4C00005C -#define UHCSTAT 0x4C000060 -#define UHCHR 0x4C000064 -#define UHCHIE 0x4C000068 -#define UHCHIT 0x4C00006C - -#define UHCCOMS_HCR (1<<0) - -#define UHCHR_FSBIR (1<<0) -#define UHCHR_FHR (1<<1) -#define UHCHR_CGR (1<<2) -#define UHCHR_SSDC (1<<3) -#define UHCHR_UIT (1<<4) -#define UHCHR_SSE (1<<5) -#define UHCHR_PSPL (1<<6) -#define UHCHR_PCPL (1<<7) -#define UHCHR_SSEP0 (1<<9) -#define UHCHR_SSEP1 (1<<10) -#define UHCHR_SSEP2 (1<<11) - -#define UHCHIE_UPRIE (1<<13) -#define UHCHIE_UPS2IE (1<<12) -#define UHCHIE_UPS1IE (1<<11) -#define UHCHIE_TAIE (1<<10) -#define UHCHIE_HBAIE (1<<8) -#define UHCHIE_RWIE (1<<7) - -#define UP2OCR 0x40600020 - -#define UP2OCR_HXOE (1<<17) -#define UP2OCR_HXS (1<<16) -#define UP2OCR_IDON (1<<10) -#define UP2OCR_EXSUS (1<<9) -#define UP2OCR_EXSP (1<<8) -#define UP2OCR_DMSTATE (1<<7) -#define UP2OCR_VPM (1<<6) -#define UP2OCR_DPSTATE (1<<5) -#define UP2OCR_DPPUE (1<<4) -#define UP2OCR_DMPDE (1<<3) -#define UP2OCR_DPPDE (1<<2) -#define UP2OCR_CPVPE (1<<1) -#define UP2OCR_CPVEN (1<<0) - -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * Fast Infrared Communication Port - */ -#define ICCR0 0x40800000 /* ICP Control Register 0 */ -#define ICCR1 0x40800004 /* ICP Control Register 1 */ -#define ICCR2 0x40800008 /* ICP Control Register 2 */ -#define ICDR 0x4080000c /* ICP Data Register */ -#define ICSR0 0x40800014 /* ICP Status Register 0 */ -#define ICSR1 0x40800018 /* ICP Status Register 1 */ - -/* - * Real Time Clock - */ -#define RCNR 0x40900000 /* RTC Count Register */ -#define RTAR 0x40900004 /* RTC Alarm Register */ -#define RTSR 0x40900008 /* RTC Status Register */ -#define RTTR 0x4090000C /* RTC Timer Trim Register */ -#define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */ -#define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */ -#define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */ -#define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */ -#define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */ -#define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */ -#define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */ -#define RDCR 0x40900010 /* RTC Day Count Register. */ -#define RYCR 0x40900014 /* RTC Year Count Register. */ -#define SWCR 0x40900028 /* Stopwatch Count Register */ -#define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */ - -#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ -#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ -#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ -#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ -#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ -#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ -#define RTSR_AL (1 << 0) /* RTC alarm detected */ - -/******************************************************************************/ -/* - * OS Timer & Match Registers - */ -#define OSMR0 0x40A00000 /* OS Timer Match Register 0 */ -#define OSMR1 0x40A00004 /* OS Timer Match Register 1 */ -#define OSMR2 0x40A00008 /* OS Timer Match Register 2 */ -#define OSMR3 0x40A0000C /* OS Timer Match Register 3 */ -#define OSCR 0x40A00010 /* OS Timer Counter Register */ -#define OSSR 0x40A00014 /* OS Timer Status Register */ -#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ -#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ -#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ -#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ -#define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */ -#define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */ -#define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */ -#define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */ -#define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */ - -#define OSMR4 0x40A00080 /* OS Timer Match Register 4 */ -#define OSMR5 0x40A00084 /* OS Timer Match Register 5 */ -#define OSMR6 0x40A00088 /* OS Timer Match Register 6 */ -#define OSMR7 0x40A0008C /* OS Timer Match Register 7 */ -#define OSMR8 0x40A00090 /* OS Timer Match Register 8 */ -#define OSMR9 0x40A00094 /* OS Timer Match Register 9 */ -#define OSMR10 0x40A00098 /* OS Timer Match Register 10 */ -#define OSMR11 0x40A0009C /* OS Timer Match Register 11 */ - -#define OMCR4 0x40A000C0 /* OS Match Control Register 4 */ -#define OMCR5 0x40A000C4 /* OS Match Control Register 5 */ -#define OMCR6 0x40A000C8 /* OS Match Control Register 6 */ -#define OMCR7 0x40A000CC /* OS Match Control Register 7 */ -#define OMCR8 0x40A000D0 /* OS Match Control Register 8 */ -#define OMCR9 0x40A000D4 /* OS Match Control Register 9 */ -#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ -#define OMCR11 0x40A000DC /* OS Match Control Register 11 */ - -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#define OSSR_M4 (1 << 4) /* Match status channel 4 */ -#define OSSR_M3 (1 << 3) /* Match status channel 3 */ -#define OSSR_M2 (1 << 2) /* Match status channel 2 */ -#define OSSR_M1 (1 << 1) /* Match status channel 1 */ -#define OSSR_M0 (1 << 0) /* Match status channel 0 */ - -#define OWER_WME (1 << 0) /* Watchdog Match Enable */ - -#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */ -#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ -#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ -#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ -#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ - -#define OSCR_CLK_FREQ 3250 - -/******************************************************************************/ -/* - * Core Clock - */ - -#if defined(CONFIG_CPU_MONAHANS) -#define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */ -#define ACSR 0x41340004 /* Application Subsystem Clock Status Register */ -#define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA 0x4134000C /* A Clock Enable Register */ -#define CKENB 0x41340010 /* B Clock Enable Register */ -#define AC97_DIV 0x41340014 /* AC97 clock divisor value register */ - -#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ -#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ -#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ -#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ -#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ -#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ - -#else /* if defined CONFIG_CPU_MONAHANS */ - -#define CCCR 0x41300000 /* Core Clock Configuration Register */ -#define CKEN 0x41300004 /* Clock Enable Register */ -#define OSCC 0x41300008 /* Oscillator Configuration Register */ -#define CCSR 0x4130000C /* Core Clock Status Register */ - -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_CPU_PXA27X) -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#endif -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_CPU_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ -#endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#if !defined(CONFIG_CPU_PXA27X) -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) -#endif - -#endif /* CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * Pulse Width Modulator - */ -#define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */ -#define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */ - -#define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */ -#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ -#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ -#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ - -#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ -#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ -#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/* - * Interrupt Controller - */ -#define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */ -#define ICMR 0x40D00004 /* Interrupt Controller Mask Register */ -#define ICLR 0x40D00008 /* Interrupt Controller Level Register */ -#define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */ -#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ -#define ICCR 0x40D00014 /* Interrupt Controller Control Register */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ -#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ -#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ -#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -/******************************************************************************/ -/* - * General Purpose I/O - */ -#define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ -#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */ - -#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */ - -#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */ - -#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */ - -#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */ - -#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */ - -#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ -#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ -#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */ - -#ifdef CONFIG_CPU_MONAHANS -#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) -#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) -#endif - -#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) -#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) -#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) -#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) -#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) -#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) -#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) -#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) -#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) -#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) -#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) -#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) -#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) -#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) -#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) -#else -#define GPLR(x) _GPLR(x) -#define GPDR(x) _GPDR(x) -#define GPSR(x) _GPSR(x) -#define GPCR(x) _GPCR(x) -#define GRER(x) _GRER(x) -#define GFER(x) _GFER(x) -#define GEDR(x) _GEDR(x) -#define GAFR(x) _GAFR(x) -#endif - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -/******************************************************************************/ -/* - * Multi-function Pin Registers: - */ -/* PXA320 */ -#if defined(CONFIG_CPU_PXA320) -#define DF_IO0 0x40e1024c -#define DF_IO1 0x40e10254 -#define DF_IO2 0x40e1025c -#define DF_IO3 0x40e10264 -#define DF_IO4 0x40e1026c -#define DF_IO5 0x40e10274 -#define DF_IO6 0x40e1027c -#define DF_IO7 0x40e10284 -#define DF_IO8 0x40e10250 -#define DF_IO9 0x40e10258 -#define DF_IO10 0x40e10260 -#define DF_IO11 0x40e10268 -#define DF_IO12 0x40e10270 -#define DF_IO13 0x40e10278 -#define DF_IO14 0x40e10280 -#define DF_IO15 0x40e10288 -#define DF_CLE_nOE 0x40e10204 -#define DF_ALE_nWE1 0x40e10208 -#define DF_ALE_nWE2 0x40e1021c -#define DF_SCLK_E 0x40e10210 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define nBE0 0x40e10214 -#define nBE1 0x40e10218 -#define nLUA 0x40e10234 -#define nLLA 0x40e10238 -#define DF_ADDR0 0x40e1023c -#define DF_ADDR1 0x40e10240 -#define DF_ADDR2 0x40e10244 -#define DF_ADDR3 0x40e10248 -#define DF_INT_RnB 0x40e10220 -#define DF_nCS0 0x40e10224 -#define DF_nCS1 0x40e10228 -#define DF_nWE 0x40e1022c -#define DF_nRE 0x40e10230 - -#define nXCVREN 0x40e10138 - -#define GPIO0 0x40e10124 -#define GPIO1 0x40e10128 -#define GPIO2 0x40e1012c -#define GPIO3 0x40e10130 -#define GPIO4 0x40e10134 -#define GPIO5 0x40e1028c -#define GPIO6 0x40e10290 -#define GPIO7 0x40e10294 -#define GPIO8 0x40e10298 -#define GPIO9 0x40e1029c -#define GPIO10 0x40e10458 -#define GPIO11 0x40e102a0 -#define GPIO12 0x40e102a4 -#define GPIO13 0x40e102a8 -#define GPIO14 0x40e102ac -#define GPIO15 0x40e102b0 -#define GPIO16 0x40e102b4 -#define GPIO17 0x40e102b8 -#define GPIO18 0x40e102bc -#define GPIO19 0x40e102c0 -#define GPIO20 0x40e102c4 -#define GPIO21 0x40e102c8 -#define GPIO22 0x40e102cc -#define GPIO23 0x40e102d0 -#define GPIO24 0x40e102d4 -#define GPIO25 0x40e102d8 -#define GPIO26 0x40e102dc - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define GPIO30 0x40e1040c -#define GPIO31 0x40e10410 -#define GPIO32 0x40e10414 -#define GPIO33 0x40e10418 -#define GPIO34 0x40e1041c -#define GPIO35 0x40e10420 -#define GPIO36 0x40e10424 -#define GPIO37 0x40e10428 -#define GPIO38 0x40e1042c -#define GPIO39 0x40e10430 -#define GPIO40 0x40e10434 -#define GPIO41 0x40e10438 -#define GPIO42 0x40e1043c -#define GPIO43 0x40e10440 -#define GPIO44 0x40e10444 -#define GPIO45 0x40e10448 -#define GPIO46 0x40e1044c -#define GPIO47 0x40e10450 -#define GPIO48 0x40e10454 -#define GPIO49 0x40e1045c -#define GPIO50 0x40e10460 -#define GPIO51 0x40e10464 -#define GPIO52 0x40e10468 -#define GPIO53 0x40e1046c -#define GPIO54 0x40e10470 -#define GPIO55 0x40e10474 -#define GPIO56 0x40e10478 -#define GPIO57 0x40e1047c -#define GPIO58 0x40e10480 -#define GPIO59 0x40e10484 -#define GPIO60 0x40e10488 -#define GPIO61 0x40e1048c -#define GPIO62 0x40e10490 - -#define GPIO6_2 0x40e10494 -#define GPIO7_2 0x40e10498 -#define GPIO8_2 0x40e1049c -#define GPIO9_2 0x40e104a0 -#define GPIO10_2 0x40e104a4 -#define GPIO11_2 0x40e104a8 -#define GPIO12_2 0x40e104ac -#define GPIO13_2 0x40e104b0 - -#define GPIO63 0x40e104b4 -#define GPIO64 0x40e104b8 -#define GPIO65 0x40e104bc -#define GPIO66 0x40e104c0 -#define GPIO67 0x40e104c4 -#define GPIO68 0x40e104c8 -#define GPIO69 0x40e104cc -#define GPIO70 0x40e104d0 -#define GPIO71 0x40e104d4 -#define GPIO72 0x40e104d8 -#define GPIO73 0x40e104dc - -#define GPIO14_2 0x40e104e0 -#define GPIO15_2 0x40e104e4 -#define GPIO16_2 0x40e104e8 -#define GPIO17_2 0x40e104ec - -#define GPIO74 0x40e104f0 -#define GPIO75 0x40e104f4 -#define GPIO76 0x40e104f8 -#define GPIO77 0x40e104fc -#define GPIO78 0x40e10500 -#define GPIO79 0x40e10504 -#define GPIO80 0x40e10508 -#define GPIO81 0x40e1050c -#define GPIO82 0x40e10510 -#define GPIO83 0x40e10514 -#define GPIO84 0x40e10518 -#define GPIO85 0x40e1051c -#define GPIO86 0x40e10520 -#define GPIO87 0x40e10524 -#define GPIO88 0x40e10528 -#define GPIO89 0x40e1052c -#define GPIO90 0x40e10530 -#define GPIO91 0x40e10534 -#define GPIO92 0x40e10538 -#define GPIO93 0x40e1053c -#define GPIO94 0x40e10540 -#define GPIO95 0x40e10544 -#define GPIO96 0x40e10548 -#define GPIO97 0x40e1054c -#define GPIO98 0x40e10550 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e1067c -#define GPIO3_2 0x40e10680 -#define GPIO4_2 0x40e10684 -#define GPIO5_2 0x40e10688 - -/* PXA300 and PXA310 */ -#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) -#define DF_IO0 0x40e10220 -#define DF_IO1 0x40e10228 -#define DF_IO2 0x40e10230 -#define DF_IO3 0x40e10238 -#define DF_IO4 0x40e10258 -#define DF_IO5 0x40e10260 -#define DF_IO7 0x40e10270 -#define DF_IO6 0x40e10268 -#define DF_IO8 0x40e10224 -#define DF_IO9 0x40e1022c -#define DF_IO10 0x40e10234 -#define DF_IO11 0x40e1023c -#define DF_IO12 0x40e1025c -#define DF_IO13 0x40e10264 -#define DF_IO14 0x40e1026c -#define DF_IO15 0x40e10274 -#define DF_CLE_NOE 0x40e10240 -#define DF_ALE_nWE 0x40e1020c -#define DF_SCLK_E 0x40e10250 -#define nCS0 0x40e100c4 -#define nCS1 0x40e100c0 -#define nBE0 0x40e10204 -#define nBE1 0x40e10208 -#define nLUA 0x40e10244 -#define nLLA 0x40e10254 -#define DF_ADDR0 0x40e10210 -#define DF_ADDR1 0x40e10214 -#define DF_ADDR2 0x40e10218 -#define DF_ADDR3 0x40e1021c -#define DF_INT_RnB 0x40e100c8 -#define DF_nCS0 0x40e10248 -#define DF_nCS1 0x40e10278 -#define DF_nWE 0x40e100cc -#define DF_nRE 0x40e10200 - -#define GPIO0 0x40e100b4 -#define GPIO1 0x40e100b8 -#define GPIO2 0x40e100bc -#define GPIO3 0x40e1027c -#define GPIO4 0x40e10280 - -#define GPIO5 0x40e10284 -#define GPIO6 0x40e10288 -#define GPIO7 0x40e1028c -#define GPIO8 0x40e10290 -#define GPIO9 0x40e10294 -#define GPIO10 0x40e10298 -#define GPIO11 0x40e1029c -#define GPIO12 0x40e102a0 -#define GPIO13 0x40e102a4 -#define GPIO14 0x40e102a8 -#define GPIO15 0x40e102ac -#define GPIO16 0x40e102b0 -#define GPIO17 0x40e102b4 -#define GPIO18 0x40e102b8 -#define GPIO19 0x40e102bc -#define GPIO20 0x40e102c0 -#define GPIO21 0x40e102c4 -#define GPIO22 0x40e102c8 -#define GPIO23 0x40e102cc -#define GPIO24 0x40e102d0 -#define GPIO25 0x40e102d4 -#define GPIO26 0x40e102d8 - -#define GPIO27 0x40e10400 -#define GPIO28 0x40e10404 -#define GPIO29 0x40e10408 -#define ULPI_STP 0x40e1040c -#define ULPI_NXT 0x40e10410 -#define ULPI_DIR 0x40e10414 -#define GPIO30 0x40e10418 -#define GPIO31 0x40e1041c -#define GPIO32 0x40e10420 -#define GPIO33 0x40e10424 -#define GPIO34 0x40e10428 -#define GPIO35 0x40e1042c -#define GPIO36 0x40e10430 -#define GPIO37 0x40e10434 -#define GPIO38 0x40e10438 -#define GPIO39 0x40e1043c -#define GPIO40 0x40e10440 -#define GPIO41 0x40e10444 -#define GPIO42 0x40e10448 -#define GPIO43 0x40e1044c -#define GPIO44 0x40e10450 -#define GPIO45 0x40e10454 -#define GPIO46 0x40e10458 -#define GPIO47 0x40e1045c -#define GPIO48 0x40e10460 - -#define GPIO49 0x40e10464 -#define GPIO50 0x40e10468 -#define GPIO51 0x40e1046c -#define GPIO52 0x40e10470 -#define GPIO53 0x40e10474 -#define GPIO54 0x40e10478 -#define GPIO55 0x40e1047c -#define GPIO56 0x40e10480 -#define GPIO57 0x40e10484 -#define GPIO58 0x40e10488 -#define GPIO59 0x40e1048c -#define GPIO60 0x40e10490 -#define GPIO61 0x40e10494 -#define GPIO62 0x40e10498 -#define GPIO63 0x40e1049c -#define GPIO64 0x40e104a0 -#define GPIO65 0x40e104a4 -#define GPIO66 0x40e104a8 -#define GPIO67 0x40e104ac -#define GPIO68 0x40e104b0 -#define GPIO69 0x40e104b4 -#define GPIO70 0x40e104b8 -#define GPIO71 0x40e104bc -#define GPIO72 0x40e104c0 -#define GPIO73 0x40e104c4 -#define GPIO74 0x40e104c8 -#define GPIO75 0x40e104cc -#define GPIO76 0x40e104d0 -#define GPIO77 0x40e104d4 -#define GPIO78 0x40e104d8 -#define GPIO79 0x40e104dc -#define GPIO80 0x40e104e0 -#define GPIO81 0x40e104e4 -#define GPIO82 0x40e104e8 -#define GPIO83 0x40e104ec -#define GPIO84 0x40e104f0 -#define GPIO85 0x40e104f4 -#define GPIO86 0x40e104f8 -#define GPIO87 0x40e104fc -#define GPIO88 0x40e10500 -#define GPIO89 0x40e10504 -#define GPIO90 0x40e10508 -#define GPIO91 0x40e1050c -#define GPIO92 0x40e10510 -#define GPIO93 0x40e10514 -#define GPIO94 0x40e10518 -#define GPIO95 0x40e1051c -#define GPIO96 0x40e10520 -#define GPIO97 0x40e10524 -#define GPIO98 0x40e10528 - -#define GPIO99 0x40e10600 -#define GPIO100 0x40e10604 -#define GPIO101 0x40e10608 -#define GPIO102 0x40e1060c -#define GPIO103 0x40e10610 -#define GPIO104 0x40e10614 -#define GPIO105 0x40e10618 -#define GPIO106 0x40e1061c -#define GPIO107 0x40e10620 -#define GPIO108 0x40e10624 -#define GPIO109 0x40e10628 -#define GPIO110 0x40e1062c -#define GPIO111 0x40e10630 -#define GPIO112 0x40e10634 - -#define GPIO113 0x40e10638 -#define GPIO114 0x40e1063c -#define GPIO115 0x40e10640 -#define GPIO116 0x40e10644 -#define GPIO117 0x40e10648 -#define GPIO118 0x40e1064c -#define GPIO119 0x40e10650 -#define GPIO120 0x40e10654 -#define GPIO121 0x40e10658 -#define GPIO122 0x40e1065c -#define GPIO123 0x40e10660 -#define GPIO124 0x40e10664 -#define GPIO125 0x40e10668 -#define GPIO126 0x40e1066c -#define GPIO127 0x40e10670 - -#define GPIO0_2 0x40e10674 -#define GPIO1_2 0x40e10678 -#define GPIO2_2 0x40e102dc -#define GPIO3_2 0x40e102e0 -#define GPIO4_2 0x40e102e4 -#define GPIO5_2 0x40e102e8 -#define GPIO6_2 0x40e102ec - -#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ -#define GPIO7_2 0x40e1052c -#define GPIO8_2 0x40e10530 -#define GPIO9_2 0x40e10534 -#define GPIO10_2 0x40e10538 -#endif -#endif - -#ifdef CONFIG_CPU_MONAHANS -/* MFPR Bit Definitions, see 4-10, Vol. 1 */ -#define PULL_SEL 0x8000 -#define PULLUP_EN 0x4000 -#define PULLDOWN_EN 0x2000 - -#define DRIVE_FAST_1mA 0x0 -#define DRIVE_FAST_2mA 0x400 -#define DRIVE_FAST_3mA 0x800 -#define DRIVE_FAST_4mA 0xC00 -#define DRIVE_SLOW_6mA 0x1000 -#define DRIVE_FAST_6mA 0x1400 -#define DRIVE_SLOW_10mA 0x1800 -#define DRIVE_FAST_10mA 0x1C00 - -#define SLEEP_SEL 0x200 -#define SLEEP_DATA 0x100 -#define SLEEP_OE_N 0x80 -#define EDGE_CLEAR 0x40 -#define EDGE_FALL_EN 0x20 -#define EDGE_RISE_EN 0x10 - -#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ -#define AF_SEL_1 0x1 /* Alternate function 1 */ -#define AF_SEL_2 0x2 /* Alternate function 2 */ -#define AF_SEL_3 0x3 /* Alternate function 3 */ -#define AF_SEL_4 0x4 /* Alternate function 4 */ -#define AF_SEL_5 0x5 /* Alternate function 5 */ -#define AF_SEL_6 0x6 /* Alternate function 6 */ -#define AF_SEL_7 0x7 /* Alternate function 7 */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* GPIO alternate function assignments */ - -#define GPIO1_RST 1 /* reset */ -#define GPIO6_MMCCLK 6 /* MMC Clock */ -#define GPIO8_48MHz 7 /* 48 MHz clock output */ -#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ -#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ -#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ -#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ -#define GPIO12_32KHz 12 /* 32 kHz out */ -#define GPIO13_MBGNT 13 /* memory controller grant */ -#define GPIO14_MBREQ 14 /* alternate bus master request */ -#define GPIO15_nCS_1 15 /* chip select 1 */ -#define GPIO16_PWM0 16 /* PWM0 output */ -#define GPIO17_PWM1 17 /* PWM1 output */ -#define GPIO18_RDY 18 /* Ext. Bus Ready */ -#define GPIO19_DREQ1 19 /* External DMA Request */ -#define GPIO20_DREQ0 20 /* External DMA Request */ -#define GPIO23_SCLK 23 /* SSP clock */ -#define GPIO24_SFRM 24 /* SSP Frame */ -#define GPIO25_STXD 25 /* SSP transmit */ -#define GPIO26_SRXD 26 /* SSP receive */ -#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ -#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ -#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ -#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ -#define GPIO31_SYNC 31 /* AC97/I2S sync */ -#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ -#define GPIO33_nCS_5 33 /* chip select 5 */ -#define GPIO34_FFRXD 34 /* FFUART receive */ -#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ -#define GPIO35_FFCTS 35 /* FFUART Clear to send */ -#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ -#define GPIO37_FFDSR 37 /* FFUART data set ready */ -#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ -#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ -#define GPIO39_FFTXD 39 /* FFUART transmit data */ -#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ -#define GPIO41_FFRTS 41 /* FFUART request to send */ -#define GPIO42_BTRXD 42 /* BTUART receive data */ -#define GPIO43_BTTXD 43 /* BTUART transmit data */ -#define GPIO44_BTCTS 44 /* BTUART clear to send */ -#define GPIO45_BTRTS 45 /* BTUART request to send */ -#define GPIO46_ICPRXD 46 /* ICP receive data */ -#define GPIO46_STRXD 46 /* STD_UART receive data */ -#define GPIO47_ICPTXD 47 /* ICP transmit data */ -#define GPIO47_STTXD 47 /* STD_UART transmit data */ -#define GPIO48_nPOE 48 /* Output Enable for Card Space */ -#define GPIO49_nPWE 49 /* Write Enable for Card Space */ -#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ -#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ -#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ -#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ -#define GPIO53_MMCCLK 53 /* MMC Clock */ -#define GPIO54_MMCCLK 54 /* MMC Clock */ -#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ -#define GPIO55_nPREG 55 /* Card Address bit 26 */ -#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ -#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ -#define GPIO58_LDD_0 58 /* LCD data pin 0 */ -#define GPIO59_LDD_1 59 /* LCD data pin 1 */ -#define GPIO60_LDD_2 60 /* LCD data pin 2 */ -#define GPIO61_LDD_3 61 /* LCD data pin 3 */ -#define GPIO62_LDD_4 62 /* LCD data pin 4 */ -#define GPIO63_LDD_5 63 /* LCD data pin 5 */ -#define GPIO64_LDD_6 64 /* LCD data pin 6 */ -#define GPIO65_LDD_7 65 /* LCD data pin 7 */ -#define GPIO66_LDD_8 66 /* LCD data pin 8 */ -#define GPIO66_MBREQ 66 /* alternate bus master req */ -#define GPIO67_LDD_9 67 /* LCD data pin 9 */ -#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ -#define GPIO68_LDD_10 68 /* LCD data pin 10 */ -#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ -#define GPIO69_LDD_11 69 /* LCD data pin 11 */ -#define GPIO69_MMCCLK 69 /* MMC_CLK */ -#define GPIO70_LDD_12 70 /* LCD data pin 12 */ -#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ -#define GPIO71_LDD_13 71 /* LCD data pin 13 */ -#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ -#define GPIO72_LDD_14 72 /* LCD data pin 14 */ -#define GPIO72_32kHz 72 /* 32 kHz clock */ -#define GPIO73_LDD_15 73 /* LCD data pin 15 */ -#define GPIO73_MBGNT 73 /* Memory controller grant */ -#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ -#define GPIO75_LCD_LCLK 75 /* LCD line clock */ -#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ -#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ -#define GPIO78_nCS_2 78 /* chip select 2 */ -#define GPIO79_nCS_3 79 /* chip select 3 */ -#define GPIO80_nCS_4 80 /* chip select 4 */ - -/* GPIO alternate function mode & direction */ - -#define GPIO_IN 0x000 -#define GPIO_OUT 0x080 -#define GPIO_ALT_FN_1_IN 0x100 -#define GPIO_ALT_FN_1_OUT 0x180 -#define GPIO_ALT_FN_2_IN 0x200 -#define GPIO_ALT_FN_2_OUT 0x280 -#define GPIO_ALT_FN_3_IN 0x300 -#define GPIO_ALT_FN_3_OUT 0x380 -#define GPIO_MD_MASK_NR 0x07f -#define GPIO_MD_MASK_DIR 0x080 -#define GPIO_MD_MASK_FN 0x300 - -#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) -#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) -#define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) -#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) -#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) -#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) -#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) -#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) -#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) -#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) -#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) -#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) -#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) -#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) -#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) -#define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT) -#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) -#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) -#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) -#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) -#define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN) -#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) -#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) -#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) -#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) -#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) -#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) -#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) -#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) -#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) -#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) -#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) -#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) -#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) -#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) -#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) -#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) -#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) -#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) -#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) -#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) -#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) -#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) -#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) -#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) -#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) -#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) -#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) -#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) -#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) -#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) -#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) -#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) -#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) -#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) -#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) -#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) -#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) -#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) -#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) -#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) -#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) -#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) -#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) -#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) -#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) -#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) -#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) -#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) -#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) -#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) -#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) -#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) -#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) -#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) -#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) -#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) -#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) -#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) -#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) -#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) -#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) -#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) -#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) -#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) -#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) -#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) -#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) -#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) -#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) - -#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) -#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) - -/* - * Power Manager - */ -#ifdef CONFIG_CPU_MONAHANS - -#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */ -#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */ -#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */ -#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */ -#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */ - -#define PMCR 0x40F50000 /* Power Manager Control Register */ -#define PSR 0x40F50004 /* Power Manager S2 Status Register */ -#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */ -#define PCFR 0x40F5000C /* Power Manager General Configuration Register */ -#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */ -#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */ -#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */ -#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */ -#define PCMD(x) (0x40F50110 + x*4) -#define PCMD0 (0x40F50110 + 0 * 4) -#define PCMD1 (0x40F50110 + 1 * 4) -#define PCMD2 (0x40F50110 + 2 * 4) -#define PCMD3 (0x40F50110 + 3 * 4) -#define PCMD4 (0x40F50110 + 4 * 4) -#define PCMD5 (0x40F50110 + 5 * 4) -#define PCMD6 (0x40F50110 + 6 * 4) -#define PCMD7 (0x40F50110 + 7 * 4) -#define PCMD8 (0x40F50110 + 8 * 4) -#define PCMD9 (0x40F50110 + 9 * 4) -#define PCMD10 (0x40F50110 + 10 * 4) -#define PCMD11 (0x40F50110 + 11 * 4) -#define PCMD12 (0x40F50110 + 12 * 4) -#define PCMD13 (0x40F50110 + 13 * 4) -#define PCMD14 (0x40F50110 + 14 * 4) -#define PCMD15 (0x40F50110 + 15 * 4) -#define PCMD16 (0x40F50110 + 16 * 4) -#define PCMD17 (0x40F50110 + 17 * 4) -#define PCMD18 (0x40F50110 + 18 * 4) -#define PCMD19 (0x40F50110 + 19 * 4) -#define PCMD20 (0x40F50110 + 20 * 4) -#define PCMD21 (0x40F50110 + 21 * 4) -#define PCMD22 (0x40F50110 + 22 * 4) -#define PCMD23 (0x40F50110 + 23 * 4) -#define PCMD24 (0x40F50110 + 24 * 4) -#define PCMD25 (0x40F50110 + 25 * 4) -#define PCMD26 (0x40F50110 + 26 * 4) -#define PCMD27 (0x40F50110 + 27 * 4) -#define PCMD28 (0x40F50110 + 28 * 4) -#define PCMD29 (0x40F50110 + 29 * 4) -#define PCMD30 (0x40F50110 + 30 * 4) -#define PCMD31 (0x40F50110 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ - -#define PVCR_FVC (0x1 << 28) -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PVCR_ReadPointer 0x01f00000 -#define PVCR_SlaveAddress (0x7f) - -#else /* ifdef CONFIG_CPU_MONAHANS */ - -#define PMCR 0x40F00000 /* Power Manager Control Register */ -#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */ -#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */ -#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */ -#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR 0x40F0001C /* Power Manager General Configuration Register */ -#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR 0x40F00030 /* Reset Controller Status Register */ - -#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */ -#define PSTR 0x40F00038 /* Power Manager Standby Config Register */ -#define PSNR 0x40F0003C /* Power Manager Sense Config Register */ -#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */ -#define PCMD(x) (0x40F00080 + x*4) -#define PCMD0 (0x40F00080 + 0 * 4) -#define PCMD1 (0x40F00080 + 1 * 4) -#define PCMD2 (0x40F00080 + 2 * 4) -#define PCMD3 (0x40F00080 + 3 * 4) -#define PCMD4 (0x40F00080 + 4 * 4) -#define PCMD5 (0x40F00080 + 5 * 4) -#define PCMD6 (0x40F00080 + 6 * 4) -#define PCMD7 (0x40F00080 + 7 * 4) -#define PCMD8 (0x40F00080 + 8 * 4) -#define PCMD9 (0x40F00080 + 9 * 4) -#define PCMD10 (0x40F00080 + 10 * 4) -#define PCMD11 (0x40F00080 + 11 * 4) -#define PCMD12 (0x40F00080 + 12 * 4) -#define PCMD13 (0x40F00080 + 13 * 4) -#define PCMD14 (0x40F00080 + 14 * 4) -#define PCMD15 (0x40F00080 + 15 * 4) -#define PCMD16 (0x40F00080 + 16 * 4) -#define PCMD17 (0x40F00080 + 17 * 4) -#define PCMD18 (0x40F00080 + 18 * 4) -#define PCMD19 (0x40F00080 + 19 * 4) -#define PCMD20 (0x40F00080 + 20 * 4) -#define PCMD21 (0x40F00080 + 21 * 4) -#define PCMD22 (0x40F00080 + 22 * 4) -#define PCMD23 (0x40F00080 + 23 * 4) -#define PCMD24 (0x40F00080 + 24 * 4) -#define PCMD25 (0x40F00080 + 25 * 4) -#define PCMD26 (0x40F00080 + 26 * 4) -#define PCMD27 (0x40F00080 + 27 * 4) -#define PCMD28 (0x40F00080 + 28 * 4) -#define PCMD29 (0x40F00080 + 29 * 4) -#define PCMD30 (0x40F00080 + 30 * 4) -#define PCMD31 (0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ - /* bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -/* define MACRO for Power Manager General Configuration Register (PCFR) */ -#define PCFR_FVC (0x1 << 10) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#endif /* CONFIG_CPU_MONAHANS */ - -/* - * SSP Serial Port Registers - */ -#define SSCR0 0x41000000 /* SSP Control Register 0 */ -#define SSCR1 0x41000004 /* SSP Control Register 1 */ -#define SSSR 0x41000008 /* SSP Status Register */ -#define SSITR 0x4100000C /* SSP Interrupt Test Register */ -#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ - -/* - * MultiMediaCard (MMC) controller - */ -#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */ -#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */ -#define MMC_CLKRT 0x41100008 /* MMC clock rate */ -#define MMC_SPI 0x4110000c /* SPI mode control bits */ -#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */ -#define MMC_RESTO 0x41100014 /* Expected response time out */ -#define MMC_RDTO 0x41100018 /* Expected data read time out */ -#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */ -#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */ -#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK 0x41100028 /* Interrupt Mask */ -#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */ -#define MMC_CMD 0x41100030 /* Index of current command */ -#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */ -#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */ -#define MMC_RES 0x4110003c /* Response FIFO (read only) */ -#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */ -#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */ - - -/* - * LCD - */ -#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ -#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */ -#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */ -#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */ -#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 0x44000038 /* LCD Controller Status Register */ -#define LCSR1 0x44000034 /* LCD Controller Status Register */ -#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */ -#define TMEDCR 0x44000044 /* TMED Control Register */ - -#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */ -#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ -#define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */ -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */ -#define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */ -#define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#if defined(CONFIG_CPU_PXA27X) -#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ -#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ -#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ -#endif - -#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) - -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) - -#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) - -#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) - - -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) - -#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) - -#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) - -#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* pixel clock polarity */ -#define LCCR3_OEP (1 << 23) /* output enable polarity */ -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - - -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) - - -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) - -#define LCCR3_ACB Fld (8, 8) /* AC Bias */ -#define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ - -#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR0_SOF (1 << 1) /* Start of frame */ -#define LCSR0_BER (1 << 2) /* Bus error */ -#define LCSR0_ABC (1 << 3) /* AC Bias count */ -#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR0_OU (1 << 6) /* output FIFO underrun */ -#define LCSR0_QD (1 << 7) /* quick disable */ -#define LCSR0_EOF0 (1 << 8) /* end of frame */ -#define LCSR0_BS (1 << 9) /* branch status */ -#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ - -#define LCSR1_SOF1 (1 << 0) -#define LCSR1_SOF2 (1 << 1) -#define LCSR1_SOF3 (1 << 2) -#define LCSR1_SOF4 (1 << 3) -#define LCSR1_SOF5 (1 << 4) -#define LCSR1_SOF6 (1 << 5) - -#define LCSR1_EOF1 (1 << 8) -#define LCSR1_EOF2 (1 << 9) -#define LCSR1_EOF3 (1 << 10) -#define LCSR1_EOF4 (1 << 11) -#define LCSR1_EOF5 (1 << 12) -#define LCSR1_EOF6 (1 << 13) - -#define LCSR1_BS1 (1 << 16) -#define LCSR1_BS2 (1 << 17) -#define LCSR1_BS3 (1 << 18) -#define LCSR1_BS4 (1 << 19) -#define LCSR1_BS5 (1 << 20) -#define LCSR1_BS6 (1 << 21) - -#define LCSR1_IU2 (1 << 25) -#define LCSR1_IU3 (1 << 26) -#define LCSR1_IU4 (1 << 27) -#define LCSR1_IU5 (1 << 28) -#define LCSR1_IU6 (1 << 29) - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#if defined(CONFIG_CPU_PXA27X) -#define LDCMD_SOFINT (1 << 22) -#define LDCMD_EOFINT (1 << 21) -#endif - -/* - * Memory controller - */ - -#ifdef CONFIG_CPU_MONAHANS - -/* PXA3xx */ - -/* Static Memory Controller Registers */ -#define MSC0 0x4A000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4A00000C /* Static Memory Control Register 1 */ -#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */ -#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */ -#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */ -#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */ -#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */ -#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */ -#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */ -#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */ - -/* Dynamic Memory Controller Registers */ -#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ -#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ -#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */ -#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */ -#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI 0x48100090 /* EMPI Control Register */ -#define RCOMP 0x48100100 -#define PAD_MA 0x48100110 -#define PAD_MDMSB 0x48100114 -#define PAD_MDLSB 0x48100118 -#define PAD_DMEM 0x4810011c -#define PAD_SDCLK 0x48100120 -#define PAD_SDCS 0x48100124 -#define PAD_SMEM 0x48100128 -#define PAD_SCLK 0x4810012C -#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */ - -/* Some frequently used bits */ -#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ -#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ -#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ -#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ - -#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ -#define MDCNFG_DTC_1 0x100 -#define MDCNFG_DTC_2 0x200 -#define MDCNFG_DTC_3 0x300 - -#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ -#define MDCNFG_DRAC_13 0x20 -#define MDCNFG_DRAC_14 0x40 - -#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ -#define MDCNFG_DCAC_10 0x08 -#define MDCNFG_DCAC_11 0x10 - -#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ -#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ -#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ - - -/* Data Flash Controller Registers */ - -#define NDCR 0x43100000 /* Data Flash Control register */ -#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR 0x43100014 /* Data Controller Status Register */ -#define NDPCR 0x43100018 /* Data Controller Page Count Register */ -#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */ -#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */ -#define NDDB 0x43100040 /* Data Controller Data Buffer */ -#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */ -#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */ -#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */ - -#define NDCR_SPARE_EN (0x1<<31) -#define NDCR_ECC_EN (0x1<<30) -#define NDCR_DMA_EN (0x1<<29) -#define NDCR_ND_RUN (0x1<<28) -#define NDCR_DWIDTH_C (0x1<<27) -#define NDCR_DWIDTH_M (0x1<<26) -#define NDCR_PAGE_SZ (0x3<<24) -#define NDCR_NCSX (0x1<<23) -#define NDCR_ND_STOP (0x1<<22) -/* reserved: - * #define NDCR_ND_MODE (0x3<<21) - * #define NDCR_NAND_MODE 0x0 */ -#define NDCR_CLR_PG_CNT (0x1<<20) -#define NDCR_CLR_ECC (0x1<<19) -#define NDCR_RD_ID_CNT (0x7<<16) -#define NDCR_RA_START (0x1<<15) -#define NDCR_PG_PER_BLK (0x1<<14) -#define NDCR_ND_ARB_EN (0x1<<12) -#define NDCR_RDYM (0x1<<11) -#define NDCR_CS0_PAGEDM (0x1<<10) -#define NDCR_CS1_PAGEDM (0x1<<9) -#define NDCR_CS0_CMDDM (0x1<<8) -#define NDCR_CS1_CMDDM (0x1<<7) -#define NDCR_CS0_BBDM (0x1<<6) -#define NDCR_CS1_BBDM (0x1<<5) -#define NDCR_DBERRM (0x1<<4) -#define NDCR_SBERRM (0x1<<3) -#define NDCR_WRDREQM (0x1<<2) -#define NDCR_RDDREQM (0x1<<1) -#define NDCR_WRCMDREQM (0x1) - -#define NDSR_RDY (0x1<<11) -#define NDSR_CS0_PAGED (0x1<<10) -#define NDSR_CS1_PAGED (0x1<<9) -#define NDSR_CS0_CMDD (0x1<<8) -#define NDSR_CS1_CMDD (0x1<<7) -#define NDSR_CS0_BBD (0x1<<6) -#define NDSR_CS1_BBD (0x1<<5) -#define NDSR_DBERR (0x1<<4) -#define NDSR_SBERR (0x1<<3) -#define NDSR_WRDREQ (0x1<<2) -#define NDSR_RDDREQ (0x1<<1) -#define NDSR_WRCMDREQ (0x1) - -#define NDCB0_AUTO_RS (0x1<<25) -#define NDCB0_CSEL (0x1<<24) -#define NDCB0_CMD_TYPE (0x7<<21) -#define NDCB0_NC (0x1<<20) -#define NDCB0_DBC (0x1<<19) -#define NDCB0_ADDR_CYC (0x7<<16) -#define NDCB0_CMD2 (0xff<<8) -#define NDCB0_CMD1 (0xff) -#define MCMEM(s) MCMEM0 -#define MCATT(s) MCATT0 -#define MCIO(s) MCIO0 -#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ - -/* Maximum values for NAND Interface Timing Registers in DFC clock - * periods */ -#define DFC_MAX_tCH 7 -#define DFC_MAX_tCS 7 -#define DFC_MAX_tWH 7 -#define DFC_MAX_tWP 7 -#define DFC_MAX_tRH 7 -#define DFC_MAX_tRP 15 -#define DFC_MAX_tR 65535 -#define DFC_MAX_tWHR 15 -#define DFC_MAX_tAR 15 - -#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ -#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ - -#else /* CONFIG_CPU_MONAHANS */ - -/* PXA2xx */ - -#define MEMC_BASE 0x48000000 /* Base of Memory Controller */ -#define MDCNFG_OFFSET 0x0 -#define MDREFR_OFFSET 0x4 -#define MSC0_OFFSET 0x8 -#define MSC1_OFFSET 0xC -#define MSC2_OFFSET 0x10 -#define MECR_OFFSET 0x14 -#define SXLCR_OFFSET 0x18 -#define SXCNFG_OFFSET 0x1C -#define FLYCNFG_OFFSET 0x20 -#define SXMRS_OFFSET 0x24 -#define MCMEM0_OFFSET 0x28 -#define MCMEM1_OFFSET 0x2C -#define MCATT0_OFFSET 0x30 -#define MCATT1_OFFSET 0x34 -#define MCIO0_OFFSET 0x38 -#define MCIO1_OFFSET 0x3C -#define MDMRS_OFFSET 0x40 - -#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ -#define MDCNFG_DE0 0x00000001 -#define MDCNFG_DE1 0x00000002 -#define MDCNFG_DE2 0x00010000 -#define MDCNFG_DE3 0x00020000 -#define MDCNFG_DWID0 0x00000004 - -#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ -#define MSC0 0x48000008 /* Static Memory Control Register 0 */ -#define MSC1 0x4800000C /* Static Memory Control Register 1 */ -#define MSC2 0x48000010 /* Static Memory Control Register 2 */ -#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */ -#define FLYCNFG 0x48000020 -#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ -#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ -#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -#if defined(CONFIG_CPU_PXA27X) - -#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -#endif /* CONFIG_CPU_PXA27X */ - -/* LCD registers */ -#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ -#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ -#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ -#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ -#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */ -#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */ -#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */ -#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */ -#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */ -#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */ - -#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */ -#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */ -#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */ -#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */ -#define CCR 0x44000090 /* Cursor Control Register */ - -#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ -#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */ - -#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ -#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ - -#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ -#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ - -#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ -#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ -#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ -#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ -#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ -#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ - -#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ -#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ -#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ -#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ -#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ -#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ - -#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ -#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ -#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ -#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ - -#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ -#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ -#define CCR_CEN (1<<31) /* Enable bit for Cursor */ - -/* Keypad controller */ - -#define KPC 0x41500000 /* Keypad Interface Control register */ -#define KPDK 0x41500008 /* Keypad Interface Direct Key register */ -#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */ -#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */ -#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */ - -#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ -#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ -#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ -#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ -#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ -#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ -#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ -#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ -#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ -#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ -#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ -#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ -#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ -#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ -#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ -#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ -#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ -#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ -#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ - -#define KPDK_DKP (0x1 << 31) -#define KPDK_DK7 (0x1 << 7) -#define KPDK_DK6 (0x1 << 6) -#define KPDK_DK5 (0x1 << 5) -#define KPDK_DK4 (0x1 << 4) -#define KPDK_DK3 (0x1 << 3) -#define KPDK_DK2 (0x1 << 2) -#define KPDK_DK1 (0x1 << 1) -#define KPDK_DK0 (0x1 << 0) - -#define KPREC_OF1 (0x1 << 31) -#define kPREC_UF1 (0x1 << 30) -#define KPREC_OF0 (0x1 << 15) -#define KPREC_UF0 (0x1 << 14) - -#define KPMK_MKP (0x1 << 31) -#define KPAS_SO (0x1 << 31) -#define KPASMKPx_SO (0x1 << 31) - -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR 0x40F00034 -#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ -#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ -#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */ -#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 0x40A00080 /* */ -#define OSCR4 0x40A00040 /* OS Timer Counter Register */ -#define OMCR4 0x40A000C0 /* */ - -#endif /* CONFIG_CPU_PXA27X */ - -#endif /* _PXA_REGS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h deleted file mode 100644 index d759aea60..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * PXA common functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PXA_H__ -#define __PXA_H__ - -#define PXA255_A0 0x00000106 -#define PXA250_C0 0x00000105 -#define PXA250_B2 0x00000104 -#define PXA250_B1 0x00000103 -#define PXA250_B0 0x00000102 -#define PXA250_A1 0x00000101 -#define PXA250_A0 0x00000100 -#define PXA210_C0 0x00000125 -#define PXA210_B2 0x00000124 -#define PXA210_B1 0x00000123 -#define PXA210_B0 0x00000122 - -int cpu_is_pxa25x(void); -int cpu_is_pxa27x(void); -uint32_t pxa_get_cpu_revision(void); -void pxa2xx_dram_init(void); - -#endif /* __PXA_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h deleted file mode 100644 index 1b18eea0c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REGS_MMC_H__ -#define __REGS_MMC_H__ - -#define MMC0_BASE 0x41100000 -#define MMC1_BASE 0x42000000 - -int pxa_mmc_register(int card_index); - -struct pxa_mmc_regs { - uint32_t strpcl; - uint32_t stat; - uint32_t clkrt; - uint32_t spi; - uint32_t cmdat; - uint32_t resto; - uint32_t rdto; - uint32_t blklen; - uint32_t nob; - uint32_t prtbuf; - uint32_t i_mask; - uint32_t i_reg; - uint32_t cmd; - uint32_t argh; - uint32_t argl; - uint32_t res; - uint32_t rxfifo; - uint32_t txfifo; -}; - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (1 << 0) -#define MMC_STRPCL_START_CLK (1 << 1) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (1 << 13) -#define MMC_STAT_PRG_DONE (1 << 12) -#define MMC_STAT_DATA_TRAN_DONE (1 << 11) -#define MMC_STAT_CLK_EN (1 << 8) -#define MMC_STAT_RECV_FIFO_FULL (1 << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) -#define MMC_STAT_RES_CRC_ERROR (1 << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) -#define MMC_STAT_CRC_READ_ERROR (1 << 3) -#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) -#define MMC_STAT_READ_TIME_OUT (1 << 0) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ 0 -#define MMC_CLKRT_10MHZ 1 -#define MMC_CLKRT_5MHZ 2 -#define MMC_CLKRT_2_5MHZ 3 -#define MMC_CLKRT_1_25MHZ 4 -#define MMC_CLKRT_0_625MHZ 5 -#define MMC_CLKRT_0_3125MHZ 6 - -/* MMC_SPI */ -#define MMC_SPI_EN (1 << 0) -#define MMC_SPI_CS_EN (1 << 2) -#define MMC_SPI_CS_ADDRESS (1 << 3) -#define MMC_SPI_CRC_ON (1 << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (1 << 8) -#define MMC_CMDAT_MMC_DMA_EN (1 << 7) -#define MMC_CMDAT_INIT (1 << 6) -#define MMC_CMDAT_BUSY (1 << 5) -#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) -#define MMC_CMDAT_STREAM (1 << 4) -#define MMC_CMDAT_WRITE (1 << 3) -#define MMC_CMDAT_DATA_EN (1 << 2) -#define MMC_CMDAT_R0 0 -#define MMC_CMDAT_R1 1 -#define MMC_CMDAT_R2 2 -#define MMC_CMDAT_R3 3 - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX_MASK 0x7f - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX_MASK 0xffff - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX_MASK 0x3ff - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_MASK_CLK_IS_OFF (1 << 4) -#define MMC_I_MASK_STOP_CMD (1 << 3) -#define MMC_I_MASK_END_CMD_RES (1 << 2) -#define MMC_I_MASK_PRG_DONE (1 << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) -#define MMC_I_MASK_ALL 0x7f - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) -#define MMC_I_REG_CLK_IS_OFF (1 << 4) -#define MMC_I_REG_STOP_CMD (1 << 3) -#define MMC_I_REG_END_CMD_RES (1 << 2) -#define MMC_I_REG_PRG_DONE (1 << 1) -#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX 0x6f - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __REGS_MMC_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h deleted file mode 100644 index 313a6919c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REGS_UART_H__ -#define __REGS_UART_H__ - -#define FFUART_BASE 0x40100000 -#define BTUART_BASE 0x40200000 -#define STUART_BASE 0x40700000 -#define HWUART_BASE 0x41600000 - -struct pxa_uart_regs { - union { - uint32_t thr; - uint32_t rbr; - uint32_t dll; - }; - union { - uint32_t ier; - uint32_t dlh; - }; - union { - uint32_t fcr; - uint32_t iir; - }; - uint32_t lcr; - uint32_t mcr; - uint32_t lsr; - uint32_t msr; - uint32_t spr; - uint32_t isr; -}; - -#define IER_DMAE (1 << 7) -#define IER_UUE (1 << 6) -#define IER_NRZE (1 << 5) -#define IER_RTIOE (1 << 4) -#define IER_MIE (1 << 3) -#define IER_RLSE (1 << 2) -#define IER_TIE (1 << 1) -#define IER_RAVIE (1 << 0) - -#define IIR_FIFOES1 (1 << 7) -#define IIR_FIFOES0 (1 << 6) -#define IIR_TOD (1 << 3) -#define IIR_IID2 (1 << 2) -#define IIR_IID1 (1 << 1) -#define IIR_IP (1 << 0) - -#define FCR_ITL2 (1 << 7) -#define FCR_ITL1 (1 << 6) -#define FCR_RESETTF (1 << 2) -#define FCR_RESETRF (1 << 1) -#define FCR_TRFIFOE (1 << 0) -#define FCR_ITL_1 0 -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) -#define LCR_SB (1 << 6) -#define LCR_STKYP (1 << 5) -#define LCR_EPS (1 << 4) -#define LCR_PEN (1 << 3) -#define LCR_STB (1 << 2) -#define LCR_WLS1 (1 << 1) -#define LCR_WLS0 (1 << 0) - -#define LSR_FIFOE (1 << 7) -#define LSR_TEMT (1 << 6) -#define LSR_TDRQ (1 << 5) -#define LSR_BI (1 << 4) -#define LSR_FE (1 << 3) -#define LSR_PE (1 << 2) -#define LSR_OE (1 << 1) -#define LSR_DR (1 << 0) - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) -#define MCR_OUT1 (1 << 2) -#define MCR_RTS (1 << 1) -#define MCR_DTR (1 << 0) - -#define MSR_DCD (1 << 7) -#define MSR_RI (1 << 6) -#define MSR_DSR (1 << 5) -#define MSR_CTS (1 << 4) -#define MSR_DDCD (1 << 3) -#define MSR_TERI (1 << 2) -#define MSR_DDSR (1 << 1) -#define MSR_DCTS (1 << 0) - -#endif /* __REGS_UART_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h deleted file mode 100644 index 90ffbf470..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * PXA25x UDC definitions - * - * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct pxa25x_udc_regs { - /* UDC Control Register */ - uint32_t udccr; /* 0x000 */ - uint32_t reserved1; - - /* UDC Control Function Register */ - uint32_t udccfr; /* 0x008 */ - uint32_t reserved2; - - /* UDC Endpoint Control/Status Registers */ - uint32_t udccs[16]; /* 0x010 - 0x04c */ - - /* UDC Interrupt Control/Status Registers */ - uint32_t uicr0; /* 0x050 */ - uint32_t uicr1; /* 0x054 */ - uint32_t usir0; /* 0x058 */ - uint32_t usir1; /* 0x05c */ - - /* UDC Frame Number/Byte Count Registers */ - uint32_t ufnrh; /* 0x060 */ - uint32_t ufnrl; /* 0x064 */ - uint32_t ubcr2; /* 0x068 */ - uint32_t ubcr4; /* 0x06c */ - uint32_t ubcr7; /* 0x070 */ - uint32_t ubcr9; /* 0x074 */ - uint32_t ubcr12; /* 0x078 */ - uint32_t ubcr14; /* 0x07c */ - - /* UDC Endpoint Data Registers */ - uint32_t uddr0; /* 0x080 */ - uint32_t reserved3[7]; - uint32_t uddr5; /* 0x0a0 */ - uint32_t reserved4[7]; - uint32_t uddr10; /* 0x0c0 */ - uint32_t reserved5[7]; - uint32_t uddr15; /* 0x0e0 */ - uint32_t reserved6[7]; - uint32_t uddr1; /* 0x100 */ - uint32_t reserved7[31]; - uint32_t uddr2; /* 0x180 */ - uint32_t reserved8[31]; - uint32_t uddr3; /* 0x200 */ - uint32_t reserved9[127]; - uint32_t uddr4; /* 0x400 */ - uint32_t reserved10[127]; - uint32_t uddr6; /* 0x600 */ - uint32_t reserved11[31]; - uint32_t uddr7; /* 0x680 */ - uint32_t reserved12[31]; - uint32_t uddr8; /* 0x700 */ - uint32_t reserved13[127]; - uint32_t uddr9; /* 0x900 */ - uint32_t reserved14[127]; - uint32_t uddr11; /* 0xb00 */ - uint32_t reserved15[31]; - uint32_t uddr12; /* 0xb80 */ - uint32_t reserved16[31]; - uint32_t uddr13; /* 0xc00 */ - uint32_t reserved17[127]; - uint32_t uddr14; /* 0xe00 */ - -}; - -#define PXA25X_UDC_BASE 0x40600000 - -#define UDCCR_UDE (1 << 0) -#define UDCCR_UDA (1 << 1) -#define UDCCR_RSM (1 << 2) -#define UDCCR_RESIR (1 << 3) -#define UDCCR_SUSIR (1 << 4) -#define UDCCR_SRM (1 << 5) -#define UDCCR_RSTIR (1 << 6) -#define UDCCR_REM (1 << 7) - -/* Bulk IN endpoint 1/6/11 */ -#define UDCCS_BI_TSP (1 << 7) -#define UDCCS_BI_FST (1 << 5) -#define UDCCS_BI_SST (1 << 4) -#define UDCCS_BI_TUR (1 << 3) -#define UDCCS_BI_FTF (1 << 2) -#define UDCCS_BI_TPC (1 << 1) -#define UDCCS_BI_TFS (1 << 0) - -/* Bulk OUT endpoint 2/7/12 */ -#define UDCCS_BO_RSP (1 << 7) -#define UDCCS_BO_RNE (1 << 6) -#define UDCCS_BO_FST (1 << 5) -#define UDCCS_BO_SST (1 << 4) -#define UDCCS_BO_DME (1 << 3) -#define UDCCS_BO_RPC (1 << 1) -#define UDCCS_BO_RFS (1 << 0) - -/* Isochronous OUT endpoint 4/9/14 */ -#define UDCCS_IO_RSP (1 << 7) -#define UDCCS_IO_RNE (1 << 6) -#define UDCCS_IO_DME (1 << 3) -#define UDCCS_IO_ROF (1 << 2) -#define UDCCS_IO_RPC (1 << 1) -#define UDCCS_IO_RFS (1 << 0) - -/* Control endpoint 0 */ -#define UDCCS0_OPR (1 << 0) -#define UDCCS0_IPR (1 << 1) -#define UDCCS0_FTF (1 << 2) -#define UDCCS0_DRWF (1 << 3) -#define UDCCS0_SST (1 << 4) -#define UDCCS0_FST (1 << 5) -#define UDCCS0_RNE (1 << 6) -#define UDCCS0_SA (1 << 7) - -#define UICR0_IM0 (1 << 0) - -#define USIR0_IR0 (1 << 0) -#define USIR0_IR1 (1 << 1) -#define USIR0_IR2 (1 << 2) -#define USIR0_IR3 (1 << 3) -#define USIR0_IR4 (1 << 4) -#define USIR0_IR5 (1 << 5) -#define USIR0_IR6 (1 << 6) -#define USIR0_IR7 (1 << 7) - -#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ -#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ -/* - * Intel(R) PXA255 Processor Specification, September 2003 (page 31) - * define new "must be one" bits in UDCCFR (see Table 12-13.) - */ -#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) - -#define UFNRH_SIR (1 << 7) /* SOF interrupt request */ -#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ -#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ -#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ -#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ - -#endif /* __REGS_USB_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h deleted file mode 100644 index 463654efd..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2013,2014 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __EHCI_RMOBILE_H__ -#define __EHCI_RMOBILE_H__ - -/* Register offset */ -#define OHCI_OFFSET 0x00 -#define OHCI_SIZE 0x1000 -#define EHCI_OFFSET 0x1000 -#define EHCI_SIZE 0x1000 - -#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) - -/* USBCTR */ -#define DIRPD (1 << 8) -#define PLL_RST (1 << 2) -#define PCICLK_MASK (1 << 1) -#define USBH_RST (1 << 0) - -/* CMND_STS */ -#define SERREN (1 << 8) -#define PERREN (1 << 6) -#define MASTEREN (1 << 2) -#define MEMEN (1 << 1) - -/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ -#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) - -/* AHBPCI_WIN1_CTR */ -#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) -#define AHB_CFG_AHBPCI 0x40000000 -#define AHB_CFG_HOST 0x80000000 - -/* AHBPCI_WIN2_CTR */ -#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) - -/* PCI_INT_ENABLE */ -#define USBH_PMEEN (1 << 19) -#define USBH_INTBEN (1 << 17) -#define USBH_INTAEN (1 << 16) - -/* AHB_BUS_CTR */ -#define SMODE_READY_CTR (1 << 17) -#define SMODE_READ_BURST (1 << 16) -#define MMODE_HBUSREQ (1 << 7) -#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) -#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) -#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) -#define MMODE_WR_INCR (1 << 2) -#define MMODE_BYTE_BURST (1 << 1) -#define MMODE_HTRANS (1 << 0) - -/* PCI_ARBITER_CTR */ -#define PCIBUS_PARK_TIMER 0x00FF0000 -#define PCIBUS_PARK_TIMER_SET 0x00070000 -#define PCIBP_MODE (1 << 12) -#define PCIREQ7 (1 << 7) -#define PCIREQ6 (1 << 6) -#define PCIREQ5 (1 << 5) -#define PCIREQ4 (1 << 4) -#define PCIREQ3 (1 << 3) -#define PCIREQ2 (1 << 2) -#define PCIREQ1 (1 << 1) -#define PCIREQ0 (1 << 0) - -#define SMSTPCR7 0xE615014C -#define SMSTPCR703 (1 << 3) - -/* Init AHB master and slave functions of the host logic */ -#define AHB_BUS_CTR_INIT \ - (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ - MMODE_BYTE_BURST | MMODE_HTRANS) - -#define USBCTR_WIN_SIZE_1GB 0x800 - -/* PCI Configuration Registers */ -#define PCI_CONF_OHCI_OFFSET 0x10000 -#define PCI_CONF_EHCI_OFFSET 0x10100 -struct ahb_pciconf { - u32 vid_did; - u32 cmnd_sts; - u32 rev; - u32 cache_line; - u32 basead; -}; - -/* PCI Configuration Registers for AHB-PCI Bridge Registers */ -#define PCI_CONF_AHBPCI_OFFSET 0x10000 -struct ahbconf_pci_bridge { - u32 vid_did; /* 0x00 */ - u32 cmnd_sts; - u32 revid_cc; - u32 cls_lt_ht_bist; - u32 basead; /* 0x10 */ - u32 win1_basead; - u32 win2_basead; - u32 dummy0[5]; - u32 ssvdi_ssid; /* 0x2C */ - u32 dummy1[4]; - u32 intr_line_pin; -}; - -/* AHB-PCI Bridge PCI Communication Registers */ -#define AHBPCI_OFFSET 0x10800 -struct ahbcom_pci_bridge { - u32 pciahb_win1_ctr; /* 0x00 */ - u32 pciahb_win2_ctr; - u32 pciahb_dct_ctr; - u32 dummy0; - u32 ahbpci_win1_ctr; /* 0x10 */ - u32 ahbpci_win2_ctr; - u32 dummy1; - u32 ahbpci_dct_ctr; - u32 pci_int_enable; /* 0x20 */ - u32 pci_int_status; - u32 dummy2[2]; - u32 ahb_bus_ctr; /* 0x30 */ - u32 usbctr; - u32 dummy3[2]; - u32 pci_arbiter_ctr; /* 0x40 */ - u32 dummy4; - u32 pci_unit_rev; /* 0x48 */ -}; - -struct rmobile_ehci_reg { - u32 hciversion; /* hciversion/caplength */ - u32 hcsparams; /* hcsparams */ - u32 hccparams; /* hccparams */ - u32 hcsp_portroute; /* hcsp_portroute */ - u32 usbcmd; /* usbcmd */ - u32 usbsts; /* usbsts */ - u32 usbintr; /* usbintr */ - u32 frindex; /* frindex */ - u32 ctrldssegment; /* ctrldssegment */ - u32 periodiclistbase; /* periodiclistbase */ - u32 asynclistaddr; /* asynclistaddr */ - u32 dummy[9]; - u32 configflag; /* configflag */ - u32 portsc; /* portsc */ -}; - -#endif /* __EHCI_RMOBILE_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/gpio.h deleted file mode 100644 index 560e9f42d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#if defined(CONFIG_SH73A0) -#include "sh73a0-gpio.h" -void sh73a0_pinmux_init(void); -#elif defined(CONFIG_R8A7740) -#include "r8a7740-gpio.h" -void r8a7740_pinmux_init(void); -#elif defined(CONFIG_R8A7790) -#include "r8a7790-gpio.h" -void r8a7790_pinmux_init(void); -#elif defined(CONFIG_R8A7791) -#include "r8a7791-gpio.h" -void r8a7791_pinmux_init(void); -#endif - -#endif /* __ASM_ARCH_GPIO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/irqs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/irqs.h deleted file mode 100644 index dcb714f4d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/irqs.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_MACH_IRQS_H -#define __ASM_MACH_IRQS_H - -#define NR_IRQS 1024 - -/* GIC */ -#define gic_spi(nr) ((nr) + 32) - -/* INTCA */ -#define evt2irq(evt) (((evt) >> 5) - 16) -#define irq2evt(irq) (((irq) + 16) << 5) - -/* INTCS */ -#define INTCS_VECT_BASE 0x2200 -#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) -#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) - -#endif /* __ASM_MACH_IRQS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h deleted file mode 100644 index 9d447abb9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __ASM_R8A7740_H__ -#define __ASM_R8A7740_H__ - -/* - * MD_CKx pin - */ -#define MD_CK2 (1 << 2) -#define MD_CK1 (1 << 1) -#define MD_CK0 (1 << 0) - -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, - - GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, - GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, - - GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, - - /* IRQ */ - GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, - GPIO_FN_IRQ1, - GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, - GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, - GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, - GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, - GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, - GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, - GPIO_FN_IRQ8, - GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, - GPIO_FN_IRQ10, - GPIO_FN_IRQ11, - GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, - GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, - GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, - GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, - GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, - GPIO_FN_IRQ17, - GPIO_FN_IRQ18, - GPIO_FN_IRQ19, - GPIO_FN_IRQ20, - GPIO_FN_IRQ21, - GPIO_FN_IRQ22, - GPIO_FN_IRQ23, - GPIO_FN_IRQ24, - GPIO_FN_IRQ25, - GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, - GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, - GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, - GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, - GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, - GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, - - /* Function */ - - /* DBGT */ - GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, - GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, - GPIO_FN_DBGMD21, - - /* FSI */ - GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ - GPIO_FN_FSIAISLD_PORT5, - GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ - GPIO_FN_FSIASPDIF_PORT18, - GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, - GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, - GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, - GPIO_FN_FSIACK, GPIO_FN_FSIAILR, - GPIO_FN_FSIAIBT, - - /* FMSI */ - GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ - GPIO_FN_FMSISLD_PORT6, - GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, - GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, - GPIO_FN_FMSICK, GPIO_FN_FMSOILR, - GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, - GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, - GPIO_FN_FMSOCK, - - /* SCIFA0 */ - GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, - GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_TXD, - - /* SCIFA1 */ - GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, - GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, - GPIO_FN_SCIFA1_RTS, - - /* SCIFA2 */ - GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ - GPIO_FN_SCIFA2_SCK_PORT199, - GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, - GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, - - /* SCIFA3 */ - GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ - GPIO_FN_SCIFA3_SCK_PORT116, - GPIO_FN_SCIFA3_CTS_PORT117, - GPIO_FN_SCIFA3_RXD_PORT174, - GPIO_FN_SCIFA3_TXD_PORT175, - - GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ - GPIO_FN_SCIFA3_SCK_PORT158, - GPIO_FN_SCIFA3_CTS_PORT162, - GPIO_FN_SCIFA3_RXD_PORT159, - GPIO_FN_SCIFA3_TXD_PORT160, - - /* SCIFA4 */ - GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ - GPIO_FN_SCIFA4_TXD_PORT13, - - GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ - GPIO_FN_SCIFA4_TXD_PORT203, - - GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ - GPIO_FN_SCIFA4_TXD_PORT93, - - GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ - GPIO_FN_SCIFA4_SCK_PORT205, - - /* SCIFA5 */ - GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ - GPIO_FN_SCIFA5_RXD_PORT10, - - GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ - GPIO_FN_SCIFA5_TXD_PORT208, - - GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ - GPIO_FN_SCIFA5_RXD_PORT92, - - GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ - GPIO_FN_SCIFA5_SCK_PORT206, - - /* SCIFA6 */ - GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, - - /* SCIFA7 */ - GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, - - /* SCIFAB */ - GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ - GPIO_FN_SCIFB_RXD_PORT191, - GPIO_FN_SCIFB_TXD_PORT192, - GPIO_FN_SCIFB_RTS_PORT186, - GPIO_FN_SCIFB_CTS_PORT187, - - GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ - GPIO_FN_SCIFB_RXD_PORT3, - GPIO_FN_SCIFB_TXD_PORT4, - GPIO_FN_SCIFB_RTS_PORT172, - GPIO_FN_SCIFB_CTS_PORT173, - - /* LCD0 */ - GPIO_FN_LCDC0_SELECT, - GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, - GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, - GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, - GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, - GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, - GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, - GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, - - GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ - GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ - - GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ - GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ - - GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, - GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, - GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, - GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ - - GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, - GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, - GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, - GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ - - /* LCD1 */ - GPIO_FN_LCDC1_SELECT, - GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, - GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, - GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, - GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, - GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, - GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, - GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, - GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, - GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, - GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, - - GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ - GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ - - GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ - GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ - - /* RSPI */ - GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, - GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, - GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, - GPIO_FN_RSPI_CK_A, - - /* VIO CKO */ - GPIO_FN_VIO_CKO1, - GPIO_FN_VIO_CKO2, - GPIO_FN_VIO_CKO_1, - GPIO_FN_VIO_CKO, - - /* VIO0 */ - GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, - GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, - GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, - GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, - GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, - GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, - - GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ - GPIO_FN_VIO0_D14_PORT25, - GPIO_FN_VIO0_D15_PORT24, - - GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ - GPIO_FN_VIO0_D14_PORT95, - GPIO_FN_VIO0_D15_PORT96, - - /* VIO1 */ - GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, - GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, - GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, - GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, - - /* TPU0 */ - GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, - GPIO_FN_TPU0TO3, - GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ - GPIO_FN_TPU0TO2_PORT202, - - /* SSP1 0 */ - GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, - GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, - GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, - GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, - - /* SSP1 1 */ - GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, - GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, - GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, - - GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ - GPIO_FN_STP1_IPEN_PORT187, - - GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ - GPIO_FN_STP1_IPEN_PORT193, - - /* SIM */ - GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, - GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ - GPIO_FN_SIM_D_PORT199, - - /* SDHI0 */ - GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, - GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, - GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, - - /* SDHI1 */ - GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, - GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, - GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, - - /* SDHI2 */ - GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, - GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, - - GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ - GPIO_FN_SDHI2_WP_PORT25, - - GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ - GPIO_FN_SDHI2_CD_PORT202, - - /* MSIOF2 */ - GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, - GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_MSIOF2_RSCK, - - /* KEYSC */ - GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, - GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, - GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, - GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, - GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, - - GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ - GPIO_FN_KEYIN1_PORT44, - GPIO_FN_KEYIN2_PORT45, - GPIO_FN_KEYIN3_PORT46, - - GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ - GPIO_FN_KEYIN1_PORT57, - GPIO_FN_KEYIN2_PORT56, - GPIO_FN_KEYIN3_PORT55, - - /* VOU */ - GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, - GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, - GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, - GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, - GPIO_FN_DV_CLK, - GPIO_FN_DV_VSYNC, - GPIO_FN_DV_HSYNC, - - /* MEMC */ - GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, - GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, - GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, - GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, - GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, - GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, - GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, - - GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ - GPIO_FN_MEMC_ADV, - GPIO_FN_MEMC_WAIT, - GPIO_FN_MEMC_BUSCLK, - - GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ - GPIO_FN_MEMC_DREQ0, - GPIO_FN_MEMC_DREQ1, - GPIO_FN_MEMC_A0, - - /* MMC */ - GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, - GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, - GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, - GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, - GPIO_FN_MMC0_CLK_PORT66, - GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ - - GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, - GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, - GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, - GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, - GPIO_FN_MMC1_CLK_PORT103, - GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ - - /* MSIOF0 */ - GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, - GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, - GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, - - /* MSIOF1 */ - GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, - - GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, - GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, - GPIO_FN_MSIOF1_TSYNC_PORT120, - GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ - - GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, - GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, - GPIO_FN_MSIOF1_RXD_PORT75, - GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN_GPO0, GPIO_FN_GPI0, - GPIO_FN_GPO1, GPIO_FN_GPI1, - - /* USB0 */ - GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, - - /* USB1 */ - GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, - - /* BBIF1 */ - GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, - GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, - - /* BBIF2 */ - GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ - GPIO_FN_BBIF2_RXD2_PORT60, - GPIO_FN_BBIF2_TSYNC2_PORT6, - GPIO_FN_BBIF2_TSCK2_PORT59, - - GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ - GPIO_FN_BBIF2_TXD2_PORT183, - GPIO_FN_BBIF2_TSCK2_PORT89, - GPIO_FN_BBIF2_TSYNC2_PORT184, - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, - GPIO_FN_CS5B, GPIO_FN_CS6A, - GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ - GPIO_FN_CS5A_PORT19, - GPIO_FN_IOIS16, /* ? */ - - GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, - GPIO_FN_A4_FOE, /* share with FLCTL */ - GPIO_FN_A5_FCDE, /* share with FLCTL */ - GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, - GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, - GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, - GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, - GPIO_FN_A26, - - GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ - GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ - GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ - GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ - GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ - GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ - GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ - GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ - - GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, - GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, - GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, - GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, - - GPIO_FN_WE0_FWE, /* share with FLCTL */ - GPIO_FN_WE1, - GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ - GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ - GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, - GPIO_FN_RD_FSC, /* share with FLCTL */ - GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ - GPIO_FN_WAIT_PORT90, - - GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ - - /* IRDA */ - GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, - - /* ATAPI */ - GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, - GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, - GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, - GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, - GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, - GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, - GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, - GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, - GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, - GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, - - /* RMII */ - GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, - GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, - GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, - GPIO_FN_RMII_REF50CK, /* for RMII */ - GPIO_FN_RMII_REF125CK, /* for GMII */ - - /* GEther */ - GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, - GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, - GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ - GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ - GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, - GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, - GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, - GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, - GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ - GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ - GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, - GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, - GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, - GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, - - /* DMA0 */ - GPIO_FN_DREQ0, GPIO_FN_DACK0, - - /* DMA1 */ - GPIO_FN_DREQ1, GPIO_FN_DACK1, - - /* SYSC */ - GPIO_FN_RESETOUTS, - GPIO_FN_RESETP_PULLUP, - GPIO_FN_RESETP_PLAIN, - - /* SDENC */ - GPIO_FN_SDENC_CPG, - GPIO_FN_SDENC_DV_CLKI, - - /* IRREM */ - GPIO_FN_IROUT, - - /* DEBUG */ - GPIO_FN_EDEBGREQ_PULLDOWN, - GPIO_FN_EDEBGREQ_PULLUP, - - GPIO_FN_TRACEAUD_FROM_VIO, - GPIO_FN_TRACEAUD_FROM_LCDC0, - GPIO_FN_TRACEAUD_FROM_MEMC, -}; - -#endif /* __ASM_R8A7740_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740.h deleted file mode 100644 index 8f179505d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740.h +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_R8A7740_H -#define __ASM_ARCH_R8A7740_H - -/* - * R8A7740 I/O Addresses - */ - -#define MERAM_BASE 0xE5580000 -#define DDRP_BASE 0xC12A0000 -#define HPB_BASE 0xE6000000 -#define RWDT0_BASE 0xE6020000 -#define RWDT1_BASE 0xE6030000 -#define GPIO_BASE 0xE6050000 -#define CMT1_BASE 0xE6138000 -#define CPG_BASE 0xE6150000 -#define SYSC_BASE 0xE6180000 -#define SDHI0_BASE 0xE6850000 -#define SDHI1_BASE 0xE6860000 -#define MMCIF_BASE 0xE6BD0000 -#define SCIF5_BASE 0xE6CB0000 -#define SCIF6_BASE 0xE6CC0000 -#define DBSC_BASE 0xFE400000 -#define BSC_BASE 0xFEC10000 -#define I2C0_BASE 0xFFF20000 -#define I2C1_BASE 0xE6C20000 -#define TMU_BASE 0xFFF80000 - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7740_rwdt { - u16 rwtcnt0; /* 0x00 */ - u16 dummy0; /* 0x02 */ - u16 rwtcsra0; /* 0x04 */ - u16 dummy1; /* 0x06 */ - u16 rwtcsrb0; /* 0x08 */ - u16 dummy2; /* 0x0A */ -}; - -/* HPB Semaphore Control Registers */ -struct r8a7740_hpb { - u32 hpbctrl0; - u32 hpbctrl1; - u32 hpbctrl2; - u32 cccr; - u32 dummy0; /* 0x20 */ - u32 hpbctrl4; - u32 hpbctrl5; -}; - -/* CPG */ -struct r8a7740_cpg { - u32 frqcra; - u32 frqcrb; - u32 vclkcr1; - u32 vclkcr2; - u32 fmsickcr; - u32 fmsockcr; - u32 fsiackcr; - u32 dummy0; /* 0x1c */ - u32 rtstbcr; - u32 systbcr; - u32 pllc01cr; - u32 pllc2cr; - u32 mstpsr0; - u32 dummy1; /* 0x34 */ - u32 mstpsr1; - u32 mstpsr5; - u32 mstpsr2; - u32 dummy2; /* 0x44 */ - u32 mstpsr3; - u32 mstpsr4; - u32 dummy3; /* 0x50 */ - u32 astat; - u32 dummy4[4]; /* 0x58 .. 0x64 */ - u32 ztrckcr; - u32 dummy5[5]; /* 0x6c .. 0x7c */ - u32 subckcr; - u32 spuckcr; - u32 vouckcr; - u32 usbckcr; - u32 dummy6[3]; /* 0x90 .. 0x98 */ - u32 stprckcr; - u32 srcr0; - u32 dummy7; /* 0xa4 */ - u32 srcr1; - u32 dummy8; /* 0xac */ - u32 srcr2; - u32 dummy9; /* 0xb4 */ - u32 srcr3; - u32 srcr4; - u32 dummy10; /* 0xc0 */ - u32 srcr5; - u32 pllc01stpcr; - u32 dummy11[5]; /* 0xcc .. 0xdc */ - u32 frqcrc; - u32 frqcrd; - u32 dummy12[10]; /* 0xe8 .. 0x10c */ - u32 rmstpcr0; - u32 rmstpcr1; - u32 rmstpcr2; - u32 rmstpcr3; - u32 rmstpcr4; - u32 rmstpcr5; - u32 dummy13[2]; /* 0x128 .. 0x12c */ - u32 smstpcr0; - u32 smstpcr1; - u32 smstpcr2; - u32 smstpcr3; - u32 smstpcr4; - u32 smstpcr5; -}; - -/* BSC */ -struct r8a7740_bsc { - u32 cmncr; - u32 cs0bcr; - u32 cs2bcr; - u32 dummy0; /* 0x0c */ - u32 cs4bcr; - u32 cs5abcr; - u32 cs5bbcr; - u32 cs6abcr; - u32 dummy1; /* 0x20 */ - u32 cs0wcr; - u32 cs2wcr; - u32 dummy2; /* 0x2c */ - u32 cs4wcr; - u32 cs5awcr; - u32 cs5bwcr; - u32 cs6awcr; - u32 dummy3[5]; /* 0x40 .. 0x50 */ - u32 rbwtcnt; - u32 busycr; - u32 dummy4[5]; /* 0x5c .. 0x6c */ - u32 bromtimcr; - u32 dummy5[7]; /* 0x74 .. 0x8c */ - u32 bptcr00; - u32 bptcr01; - u32 bptcr02; - u32 bptcr03; - u32 bptcr04; - u32 bptcr05; - u32 bptcr06; - u32 bptcr07; - u32 bptcr08; - u32 bptcr09; - u32 bptcr10; - u32 bptcr11; - u32 bptcr12; - u32 bptcr13; - u32 bptcr14; - u32 bptcr15; - u32 bptcr16; - u32 bptcr17; - u32 bptcr18; - u32 bptcr19; - u32 bptcr20; - u32 bptcr21; - u32 bptcr22; - u32 bptcr23; - u32 bptcr24; - u32 bptcr25; - u32 bptcr26; - u32 bptcr27; - u32 bptcr28; - u32 bptcr29; - u32 bptcr30; - u32 bptcr31; - u32 bswcr; - u32 dummy6[68]; /* 0x114 .. 0x220 */ - u32 cs0wcr2; - u32 cs2wcr2; - u32 dummy7; /* 0x22c */ - u32 cs4wcr2; -}; - -#define CS0WCR2 0xFEC10224 -#define CS2WCR2 0xFEC10228 -#define CS4WCR2 0xFEC10230 - -/* DDRP */ -struct r8a7740_ddrp { - u32 funcctrl; - u32 dllctrl; - u32 zqcalctrl; - u32 zqodtctrl; - u32 rdctrl; - u32 rdtmg; - u32 fifoinit; - u32 outctrl; - u32 dummy0[50]; /* 0x20 .. 0xe4 */ - u32 dqcalofs1; - u32 dqcalofs2; - u32 dummy1[2]; /* 0xf0 .. 0xf4 */ - u32 dqcalexp; -}; - -#define DDRPNCNT 0xE605803C -#define DDRVREFCNT 0xE61500EC - -/* DBSC */ -struct r8a7740_dbsc { - u32 dummy0; - u32 dbsvcr; - u32 dbstate0; - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2c */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3c */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4c */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xac */ - u32 dbbl; - u32 dummy5[3]; /* 0xb4 .. 0xbc */ - u32 dbadj0; - u32 dbadj1; - u32 dbadj2; - u32 dummy6[5]; /* 0xcc .. 0xdc */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dbrfcnf3; - u32 dummy7; /* 0xf0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy8; /* 0xfc */; - u32 dbrnk0; - u32 dummy9[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy10[7]; /* 0x184 .. 0x19C */ - u32 dbmrrdr; - u32 dummy11[39]; /* 0x1A4 .. 0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[46]; /* 0x248 .. 0x2FC */ - u32 dbbs0cnt0; - u32 dbbs0cnt1; -}; - -#endif - -#endif /* __ASM_ARCH_R8A7740_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h deleted file mode 100644 index 444e361c0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h +++ /dev/null @@ -1,387 +0,0 @@ -#ifndef __ASM_R8A7790_H__ -#define __ASM_R8A7790_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, - GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, - GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, - GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, GPIO_GP_1_29, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, - GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, - GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, - GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, - GPIO_GP_2_28, GPIO_GP_2_29, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, - GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, - GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, - GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, - GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, - GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, - GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, - GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, - - GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS, - GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2, - GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2, - - /* IPSR0 */ - GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5, - GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2, - GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4, - GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4, - GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5, - GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5, - GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6, - GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B, - GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C, - GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C, - GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0, - GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0, - - /* IPSR1 */ - GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1, - GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10, - GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2, - GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11, - GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3, - GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3, - GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4, - GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4, - GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N, - GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14, - GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B, - GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6, - GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B, - GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7, - GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4, - - /* IPSR2 */ - GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3, - GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1, - GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7, - GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3, - GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4, - GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B, - GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5, - GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B, - GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6, - GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B, - - /* IPSR3 */ - GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0, - GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B, - GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1, - GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B, - GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2, - GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2, - GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B, - GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15, - GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16, - GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N, - GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19, - GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20, - GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4, - - /* IPSR4 */ - GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B, - GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5, - GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2, - GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24, - GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB, - GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6, - GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N, - GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B, - GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B, - GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B, - GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B, - GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK, - GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B, - GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B, - GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2, - - /* IPSR5 */ - GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1, - GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N, - GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N, - GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B, - GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX, - GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2, - GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N, - GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B, - GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N, - GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3, - GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B, - GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK, - GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B, - GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4, - GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B, - GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N, - GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B, - GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N, - GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C, - GPIO_FN_SSI_WS78_B, - - /* IPSR6 */ - GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B, - GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C, - GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B, - GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1, - GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C, - GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B, - GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N, - GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B, - GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B, - GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E, - GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER, - GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C, - GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0, - GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C, - GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1, - GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B, - GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G, - GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E, - GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E, - GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E, - GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F, - - /* IPSR7 */ - GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E, - GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1, - GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F, - GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C, - GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC, - GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0, - GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C, - GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B, - GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0, - GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C, - GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C, - GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C, - GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C, - GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN, - GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK, - GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1, - GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2, - GPIO_FN_MII_RXD2, - - /* IPSR8 */ - GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3, - GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N, - GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N, - GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N, - GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1, - GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER, - GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK, - GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV, - GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D, - GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1, - GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC, - GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO, - GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D, - GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D, - GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5, - GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK, - GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD, - GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B, - - /* IPSR9 */ - GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B, - GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B, - GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B, - GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B, - GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP, - GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B, - GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP, - GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN, - GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B, - GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK, - GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD, - GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B, - GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK, - GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK, - GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2, - GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B, - GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0, - GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6, - GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B, - GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B, - GPIO_FN_VI3_CLK_B, - - /* IPSR10 */ - GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN, - GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D, - GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK, - GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B, - GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D, - GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D, - GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B, - GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B, - GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D, - GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B, - GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA, - GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D, - GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B, - GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK, - GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B, - GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3, - GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B, - GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B, - GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4, - GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0, - GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B, - GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B, - - /* IPSR11 */ - GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN, - GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D, - GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B, - GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD, - GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N, - GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2, - GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3, - GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1, - GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP, - GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C, - GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F, - GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B, - GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B, - GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN, - GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C, - GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B, - GPIO_FN_MOUT0, - - /* IPSR12 */ - GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1, - GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2, - GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5, - GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6, - GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK, - GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34, - GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC, - GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0, - GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK, - GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N, - GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0, - GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N, - GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1, - GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD, - GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK, - GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS, - GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD, - GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE, - GPIO_FN_CAN_DEBUGOUT4, - - /* IPSR13 */ - GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2, - GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6, - GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C, - GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6, - GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6, - GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4, - GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6, - GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5, - GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1, - GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6, - GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1, - GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7, - GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7, - GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N, - GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11, - GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B, - GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8, - GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C, - GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9, - GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1, - GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA, - GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14, - - /* IPSR14 */ - GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D, - GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15, - GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0, - GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C, - GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0, - GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1, - GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N, - GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3, - GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C, - GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS, - GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B, - GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1, - GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, - GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1, - GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK, - GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK, - GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS, - GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE, - GPIO_FN_HRTS0_N_C, - - /* IPSR15 */ - GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7, - GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN, - GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS, - GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17, - GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0, - GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0, - GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3, - GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4, - GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5, - GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK, - GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0, - GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23, - GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0, - GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1, - GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14, - - /* IPSR16 */ - GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2, - GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B, - GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2, - GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C, - GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC, - GPIO_FN_TCLK1_B, -}; - -#endif /* __ASM_R8A7790_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h deleted file mode 100644 index d9ea71fa1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h +++ /dev/null @@ -1,615 +0,0 @@ -/* - * arch/arm/include/asm/arch-rmobile/r8a7790.h - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __ASM_ARCH_R8A7790_H -#define __ASM_ARCH_R8A7790_H - -/* - * R8A7790 I/O Addresses - */ -#define RWDT_BASE 0xE6020000 -#define SWDT_BASE 0xE6030000 -#define LBSC_BASE 0xFEC00200 -#define DBSC3_0_BASE 0xE6790000 -#define DBSC3_1_BASE 0xE67A0000 -#define TMU_BASE 0xE61E0000 -#define GPIO5_BASE 0xE6055000 -#define SH_QSPI_BASE 0xE6B10000 - -#define S3C_BASE 0xE6784000 -#define S3C_INT_BASE 0xE6784A00 -#define S3C_MEDIA_BASE 0xE6784B00 - -#define S3C_QOS_DCACHE_BASE 0xE6784BDC -#define S3C_QOS_CCI0_BASE 0xE6784C00 -#define S3C_QOS_CCI1_BASE 0xE6784C24 -#define S3C_QOS_MXI_BASE 0xE6784C48 -#define S3C_QOS_AXI_BASE 0xE6784C6C - -#define DBSC3_0_QOS_R0_BASE 0xE6791000 -#define DBSC3_0_QOS_R1_BASE 0xE6791100 -#define DBSC3_0_QOS_R2_BASE 0xE6791200 -#define DBSC3_0_QOS_R3_BASE 0xE6791300 -#define DBSC3_0_QOS_R4_BASE 0xE6791400 -#define DBSC3_0_QOS_R5_BASE 0xE6791500 -#define DBSC3_0_QOS_R6_BASE 0xE6791600 -#define DBSC3_0_QOS_R7_BASE 0xE6791700 -#define DBSC3_0_QOS_R8_BASE 0xE6791800 -#define DBSC3_0_QOS_R9_BASE 0xE6791900 -#define DBSC3_0_QOS_R10_BASE 0xE6791A00 -#define DBSC3_0_QOS_R11_BASE 0xE6791B00 -#define DBSC3_0_QOS_R12_BASE 0xE6791C00 -#define DBSC3_0_QOS_R13_BASE 0xE6791D00 -#define DBSC3_0_QOS_R14_BASE 0xE6791E00 -#define DBSC3_0_QOS_R15_BASE 0xE6791F00 -#define DBSC3_0_QOS_W0_BASE 0xE6792000 -#define DBSC3_0_QOS_W1_BASE 0xE6792100 -#define DBSC3_0_QOS_W2_BASE 0xE6792200 -#define DBSC3_0_QOS_W3_BASE 0xE6792300 -#define DBSC3_0_QOS_W4_BASE 0xE6792400 -#define DBSC3_0_QOS_W5_BASE 0xE6792500 -#define DBSC3_0_QOS_W6_BASE 0xE6792600 -#define DBSC3_0_QOS_W7_BASE 0xE6792700 -#define DBSC3_0_QOS_W8_BASE 0xE6792800 -#define DBSC3_0_QOS_W9_BASE 0xE6792900 -#define DBSC3_0_QOS_W10_BASE 0xE6792A00 -#define DBSC3_0_QOS_W11_BASE 0xE6792B00 -#define DBSC3_0_QOS_W12_BASE 0xE6792C00 -#define DBSC3_0_QOS_W13_BASE 0xE6792D00 -#define DBSC3_0_QOS_W14_BASE 0xE6792E00 -#define DBSC3_0_QOS_W15_BASE 0xE6792F00 - -#define DBSC3_0_DBADJ2 0xE67900C8 - -#define CCI_400_MAXOT_1 0xF0091110 -#define CCI_400_MAXOT_2 0xF0092110 -#define CCI_400_QOSCNTL_1 0xF009110C -#define CCI_400_QOSCNTL_2 0xF009210C - -#define MXI_BASE 0xFE960000 -#define MXI_QOS_BASE 0xFE960300 - -#define SYS_AXI_SYX64TO128_BASE 0xFF800300 -#define SYS_AXI_AVB_BASE 0xFF800340 -#define SYS_AXI_G2D_BASE 0xFF800540 -#define SYS_AXI_IMP0_BASE 0xFF800580 -#define SYS_AXI_IMP1_BASE 0xFF8005C0 -#define SYS_AXI_IMUX0_BASE 0xFF800600 -#define SYS_AXI_IMUX1_BASE 0xFF800640 -#define SYS_AXI_IMUX2_BASE 0xFF800680 -#define SYS_AXI_LBS_BASE 0xFF8006C0 -#define SYS_AXI_MMUDS_BASE 0xFF800700 -#define SYS_AXI_MMUM_BASE 0xFF800740 -#define SYS_AXI_MMUR_BASE 0xFF800780 -#define SYS_AXI_MMUS0_BASE 0xFF8007C0 -#define SYS_AXI_MMUS1_BASE 0xFF800800 -#define SYS_AXI_MTSB0_BASE 0xFF800880 -#define SYS_AXI_MTSB1_BASE 0xFF8008C0 -#define SYS_AXI_PCI_BASE 0xFF800900 -#define SYS_AXI_RTX_BASE 0xFF800940 -#define SYS_AXI_SDS0_BASE 0xFF800A80 -#define SYS_AXI_SDS1_BASE 0xFF800AC0 -#define SYS_AXI_USB20_BASE 0xFF800C00 -#define SYS_AXI_USB21_BASE 0xFF800C40 -#define SYS_AXI_USB22_BASE 0xFF800C80 -#define SYS_AXI_USB30_BASE 0xFF800CC0 - -#define RT_AXI_SHX_BASE 0xFF810100 -#define RT_AXI_RDS_BASE 0xFF8101C0 -#define RT_AXI_RTX64TO128_BASE 0xFF810200 -#define RT_AXI_STPRO_BASE 0xFF810240 - -#define MP_AXI_ADSP_BASE 0xFF820100 -#define MP_AXI_ASDS0_BASE 0xFF8201C0 -#define MP_AXI_ASDS1_BASE 0xFF820200 -#define MP_AXI_MLP_BASE 0xFF820240 -#define MP_AXI_MMUMP_BASE 0xFF820280 -#define MP_AXI_SPU_BASE 0xFF8202C0 -#define MP_AXI_SPUC_BASE 0xFF820300 - -#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 -#define SYS_AXI256_SYX_BASE 0xFF860140 -#define SYS_AXI256_MPX_BASE 0xFF860180 -#define SYS_AXI256_MXI_BASE 0xFF8601C0 - -#define CCI_AXI_MMUS0_BASE 0xFF880100 -#define CCI_AXI_SYX2_BASE 0xFF880140 -#define CCI_AXI_MMUR_BASE 0xFF880180 -#define CCI_AXI_MMUDS_BASE 0xFF8801C0 -#define CCI_AXI_MMUM_BASE 0xFF880200 -#define CCI_AXI_MXI_BASE 0xFF880240 -#define CCI_AXI_MMUS1_BASE 0xFF880280 -#define CCI_AXI_MMUMP_BASE 0xFF8802C0 - -#define MEDIA_AXI_JPR_BASE 0xFE964100 -#define MEDIA_AXI_JPW_BASE 0xFE966100 -#define MEDIA_AXI_GCU0R_BASE 0xFE964140 -#define MEDIA_AXI_GCU0W_BASE 0xFE966140 -#define MEDIA_AXI_GCU1R_BASE 0xFE964180 -#define MEDIA_AXI_GCU1W_BASE 0xFE966180 -#define MEDIA_AXI_TDMR_BASE 0xFE964500 -#define MEDIA_AXI_TDMW_BASE 0xFE966500 -#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 -#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 -#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 -#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 -#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 -#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 -#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 -#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 -#define MEDIA_AXI_VIN0W_BASE 0xFE966900 -#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 -#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 -#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 -#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 -#define MEDIA_AXI_IMSR_BASE 0xFE964D80 -#define MEDIA_AXI_IMSW_BASE 0xFE966D80 -#define MEDIA_AXI_VSP1R_BASE 0xFE965100 -#define MEDIA_AXI_VSP1W_BASE 0xFE967100 -#define MEDIA_AXI_FDP1R_BASE 0xFE965140 -#define MEDIA_AXI_FDP1W_BASE 0xFE967140 -#define MEDIA_AXI_IMRR_BASE 0xFE965180 -#define MEDIA_AXI_IMRW_BASE 0xFE967180 -#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 -#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 -#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 -#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 -#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 -#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 -#define MEDIA_AXI_DU0R_BASE 0xFE965580 -#define MEDIA_AXI_DU0W_BASE 0xFE967580 -#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 -#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 -#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 -#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 -#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 -#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 -#define MEDIA_AXI_VPC0R_BASE 0xFE965980 -#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 -#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 -#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 -#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 -#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 - -#define SYS_AXI_AVBDMSCR 0xFF802000 -#define SYS_AXI_SYX2DMSCR 0xFF802004 -#define SYS_AXI_CC50DMSCR 0xFF802008 -#define SYS_AXI_CC51DMSCR 0xFF80200C -#define SYS_AXI_CCIDMSCR 0xFF802010 -#define SYS_AXI_CSDMSCR 0xFF802014 -#define SYS_AXI_DDMDMSCR 0xFF802018 -#define SYS_AXI_ETHDMSCR 0xFF80201C -#define SYS_AXI_G2DDMSCR 0xFF802020 -#define SYS_AXI_IMP0DMSCR 0xFF802024 -#define SYS_AXI_IMP1DMSCR 0xFF802028 -#define SYS_AXI_LBSDMSCR 0xFF80202C -#define SYS_AXI_MMUDSDMSCR 0xFF802030 -#define SYS_AXI_MMUMXDMSCR 0xFF802034 -#define SYS_AXI_MMURDDMSCR 0xFF802038 -#define SYS_AXI_MMUS0DMSCR 0xFF80203C -#define SYS_AXI_MMUS1DMSCR 0xFF802040 -#define SYS_AXI_MPXDMSCR 0xFF802044 -#define SYS_AXI_MTSB0DMSCR 0xFF802048 -#define SYS_AXI_MTSB1DMSCR 0xFF80204C -#define SYS_AXI_PCIDMSCR 0xFF802050 -#define SYS_AXI_RTXDMSCR 0xFF802054 -#define SYS_AXI_SAT0DMSCR 0xFF802058 -#define SYS_AXI_SAT1DMSCR 0xFF80205C -#define SYS_AXI_SDM0DMSCR 0xFF802060 -#define SYS_AXI_SDM1DMSCR 0xFF802064 -#define SYS_AXI_SDS0DMSCR 0xFF802068 -#define SYS_AXI_SDS1DMSCR 0xFF80206C -#define SYS_AXI_ETRABDMSCR 0xFF802070 -#define SYS_AXI_ETRKFDMSCR 0xFF802074 -#define SYS_AXI_UDM0DMSCR 0xFF802078 -#define SYS_AXI_UDM1DMSCR 0xFF80207C -#define SYS_AXI_USB20DMSCR 0xFF802080 -#define SYS_AXI_USB21DMSCR 0xFF802084 -#define SYS_AXI_USB22DMSCR 0xFF802088 -#define SYS_AXI_USB30DMSCR 0xFF80208C -#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 -#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 -#define SYS_AXI_AVBSLVDMSCR 0xFF802108 -#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C -#define SYS_AXI_ETHSLVDMSCR 0xFF802110 -#define SYS_AXI_GICSLVDMSCR 0xFF802114 -#define SYS_AXI_IMPSLVDMSCR 0xFF802118 -#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C -#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 -#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 -#define SYS_AXI_LBSSLVDMSCR 0xFF802128 -#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C -#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 -#define SYS_AXI_MPXSLVDMSCR 0xFF802134 -#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 -#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C -#define SYS_AXI_MXTSLVDMSCR 0xFF802140 -#define SYS_AXI_PCISLVDMSCR 0xFF802144 -#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 -#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C -#define SYS_AXI_RTXSLVDMSCR 0xFF802150 -#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 -#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C -#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 -#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 -#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 -#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C -#define SYS_AXI_SGXSLVDMSCR 0xFF802180 -#define SYS_AXI_STBSLVDMSCR 0xFF802188 -#define SYS_AXI_STMSLVDMSCR 0xFF80218C -#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 -#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 -#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C -#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 -#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 -#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 -#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC - -#define RT_AXI_CBMDMSCR 0xFF812000 -#define RT_AXI_DBDMSCR 0xFF812004 -#define RT_AXI_RDMDMSCR 0xFF812008 -#define RT_AXI_RDSDMSCR 0xFF81200C -#define RT_AXI_STRDMSCR 0xFF812010 -#define RT_AXI_SY2RTDMSCR 0xFF812014 -#define RT_AXI_CBSSLVDMSCR 0xFF812100 -#define RT_AXI_DBSSLVDMSCR 0xFF812104 -#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 -#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C -#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 -#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 -#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 -#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C -#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 -#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 - -#define MP_AXI_ADSPDMSCR 0xFF822000 -#define MP_AXI_ASDM0DMSCR 0xFF822004 -#define MP_AXI_ASDM1DMSCR 0xFF822008 -#define MP_AXI_ASDS0DMSCR 0xFF82200C -#define MP_AXI_ASDS1DMSCR 0xFF822010 -#define MP_AXI_MLPDMSCR 0xFF822014 -#define MP_AXI_MMUMPDMSCR 0xFF822018 -#define MP_AXI_SPUDMSCR 0xFF82201C -#define MP_AXI_SPUCDMSCR 0xFF822020 -#define MP_AXI_SY2MPDMSCR 0xFF822024 -#define MP_AXI_ADSPSLVDMSCR 0xFF822100 -#define MP_AXI_MLMSLVDMSCR 0xFF822104 -#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 -#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C -#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 -#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 -#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 -#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C -#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 -#define MP_AXI_SPUSLVDMSCR 0xFF822128 -#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C - -#define ADM_AXI_ASDM0DMSCR 0xFF842000 -#define ADM_AXI_ASDM1DMSCR 0xFF842004 -#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 -#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 -#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C - -#define DM_AXI_RDMDMSCR 0xFF852000 -#define DM_AXI_SDM0DMSCR 0xFF852004 -#define DM_AXI_SDM1DMSCR 0xFF852008 -#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 -#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 -#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 -#define DM_AXI_RAP4SLVDMSCR 0xFF85210C -#define DM_AXI_RAP5SLVDMSCR 0xFF852110 -#define DM_AXI_SAP4SLVDMSCR 0xFF852114 -#define DM_AXI_SAP5SLVDMSCR 0xFF852118 -#define DM_AXI_SAP6SLVDMSCR 0xFF85211C -#define DM_AXI_SAP65SLVDMSCR 0xFF852120 -#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 -#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 -#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C -#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 - -#define SYS_AXI256_SYXDMSCR 0xFF862000 -#define SYS_AXI256_MPXDMSCR 0xFF862004 -#define SYS_AXI256_MXIDMSCR 0xFF862008 -#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 -#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 -#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 -#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C -#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 - -#define MXT_SYXDMSCR 0xFF872000 -#define MXT_CMM0SLVDMSCR 0xFF872100 -#define MXT_CMM1SLVDMSCR 0xFF872104 -#define MXT_CMM2SLVDMSCR 0xFF872108 -#define MXT_FDPSLVDMSCR 0xFF87210C -#define MXT_IMRSLVDMSCR 0xFF872110 -#define MXT_VINSLVDMSCR 0xFF872114 -#define MXT_VPC0SLVDMSCR 0xFF872118 -#define MXT_VPC1SLVDMSCR 0xFF87211C -#define MXT_VSP0SLVDMSCR 0xFF872120 -#define MXT_VSP1SLVDMSCR 0xFF872124 -#define MXT_VSPD0SLVDMSCR 0xFF872128 -#define MXT_VSPD1SLVDMSCR 0xFF87212C -#define MXT_MAP1SLVDMSCR 0xFF872130 -#define MXT_MAP2SLVDMSCR 0xFF872134 - -#define CCI_AXI_MMUS0DMSCR 0xFF882000 -#define CCI_AXI_SYX2DMSCR 0xFF882004 -#define CCI_AXI_MMURDMSCR 0xFF882008 -#define CCI_AXI_MMUDSDMSCR 0xFF88200C -#define CCI_AXI_MMUMDMSCR 0xFF882010 -#define CCI_AXI_MXIDMSCR 0xFF882014 -#define CCI_AXI_MMUS1DMSCR 0xFF882018 -#define CCI_AXI_MMUMPDMSCR 0xFF88201C -#define CCI_AXI_DVMDMSCR 0xFF882020 -#define CCI_AXI_CCISLVDMSCR 0xFF882100 - -#define CCI_AXI_IPMMUIDVMCR 0xFF880400 -#define CCI_AXI_IPMMURDVMCR 0xFF880404 -#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 -#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C -#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 -#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 -#define CCI_AXI_AX2ADDRMASK 0xFF88041C - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7790_rwdt { - u32 rwtcnt; /* 0x00 */ - u32 rwtcsra; /* 0x04 */ - u16 rwtcsrb; /* 0x08 */ -}; - -/* SWDT */ -struct r8a7790_swdt { - u32 swtcnt; /* 0x00 */ - u32 swtcsra; /* 0x04 */ - u16 swtcsrb; /* 0x08 */ -}; - -/* LBSC */ -struct r8a7790_lbsc { - u32 cs0ctrl; - u32 cs1ctrl; - u32 ecs0ctrl; - u32 ecs1ctrl; - u32 ecs2ctrl; - u32 ecs3ctrl; - u32 ecs4ctrl; - u32 ecs5ctrl; - u32 dummy0[4]; /* 0x20 .. 0x2C */ - u32 cswcr0; - u32 cswcr1; - u32 ecswcr0; - u32 ecswcr1; - u32 ecswcr2; - u32 ecswcr3; - u32 ecswcr4; - u32 ecswcr5; - u32 exdmawcr0; - u32 exdmawcr1; - u32 exdmawcr2; - u32 dummy1[9]; /* 0x5C .. 0x7C */ - u32 cspwcr0; - u32 cspwcr1; - u32 ecspwcr0; - u32 ecspwcr1; - u32 ecspwcr2; - u32 ecspwcr3; - u32 ecspwcr4; - u32 ecspwcr5; - u32 exwtsync; - u32 dummy2[3]; /* 0xA4 .. 0xAC */ - u32 cs0bstctl; - u32 cs0btph; - u32 dummy3[2]; /* 0xB8 .. 0xBC */ - u32 cs1gdst; - u32 ecs0gdst; - u32 ecs1gdst; - u32 ecs2gdst; - u32 ecs3gdst; - u32 ecs4gdst; - u32 ecs5gdst; - u32 dummy4[5]; /* 0xDC .. 0xEC */ - u32 exdmaset0; - u32 exdmaset1; - u32 exdmaset2; - u32 dummy5[5]; /* 0xFC .. 0x10C */ - u32 exdmcr0; - u32 exdmcr1; - u32 exdmcr2; - u32 dummy6[5]; /* 0x11C .. 0x12C */ - u32 bcintsr; - u32 bcintcr; - u32 bcintmr; - u32 dummy7; /* 0x13C */ - u32 exbatlv; - u32 exwtsts; - u32 dummy8[14]; /* 0x148 .. 0x17C */ - u32 atacsctrl; - u32 dummy9[15]; /* 0x184 .. 0x1BC */ - u32 exbct; - u32 extct; -}; - -/* DBSC3 */ -struct r8a7790_dbsc3 { - u32 dummy0[3]; /* 0x00 .. 0x08 */ - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2C */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3C */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4C */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xAC */ - u32 dbbl; - u32 dummy5[3]; /* 0xB4 .. 0xBC */ - u32 dbadj0; - u32 dummy6; /* 0xC4 */ - u32 dbadj2; - u32 dummy7[5]; /* 0xCC .. 0xDC */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dummy8[2]; /* 0xEC .. 0xF0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy9; /* 0xFC */ - u32 dbrnk0; - u32 dummy10[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy11[47]; /* 0x184 ..0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[14]; /* 0x248 .. 0x27C */ - u32 dbpdlck; - u32 dummy13[3]; /* 0x284 .. 0x28C */ - u32 dbpdrga; - u32 dummy14[3]; /* 0x294 .. 0x29C */ - u32 dbpdrgd; - u32 dummy15[24]; /* 0x2A4 .. 0x300 */ - u32 dbbs0cnt1; - u32 dummy16[30]; /* 0x308 .. 0x37C */ - u32 dbwt0cnf0; - u32 dbwt0cnf1; - u32 dbwt0cnf2; - u32 dbwt0cnf3; - u32 dbwt0cnf4; -}; - -/* GPIO */ -struct r8a7790_gpio { - u32 iointsel; - u32 inoutsel; - u32 outdt; - u32 indt; - u32 intdt; - u32 intclr; - u32 intmsk; - u32 posneg; - u32 edglevel; - u32 filonoff; - u32 intmsks; - u32 mskclrs; - u32 outdtsel; - u32 outdth; - u32 outdtl; - u32 bothedge; -}; - -/* S3C(QoS) */ -struct r8a7790_s3c { - u32 s3cexcladdmsk; - u32 s3cexclidmsk; - u32 s3cadsplcr; - u32 s3cmaar; - u32 s3carcr11; - u32 s3crorr; - u32 s3cworr; - u32 s3carcr22; - u32 dummy1[2]; /* 0x20 .. 0x24 */ - u32 s3cmctr; - u32 dummy2; /* 0x2C */ - u32 cconf0; - u32 cconf1; - u32 cconf2; - u32 cconf3; -}; - -struct r8a7790_s3c_qos { - u32 s3cqos0; - u32 s3cqos1; - u32 s3cqos2; - u32 s3cqos3; - u32 s3cqos4; - u32 s3cqos5; - u32 s3cqos6; - u32 s3cqos7; - u32 s3cqos8; -}; - -/* DBSC(QoS) */ -struct r8a7790_dbsc3_qos { - u32 dblgcnt; - u32 dbtmval0; - u32 dbtmval1; - u32 dbtmval2; - u32 dbtmval3; - u32 dbrqctr; - u32 dbthres0; - u32 dbthres1; - u32 dbthres2; - u32 dummy0; /* 0x24 */ - u32 dblgqon; -}; - -/* MXI(QoS) */ -struct r8a7790_mxi { - u32 mxsaar0; - u32 mxsaar1; - u32 dummy0[7]; /* 0x08 .. 0x20 */ - u32 mxaxiracr; - u32 mxs3cracr; - u32 dummy1[2]; /* 0x2C .. 0x30 */ - u32 mxaxiwacr; - u32 mxs3cwacr; - u32 dummy2; /* 0x3C */ - u32 mxrtcr; - u32 mxwtcr; -}; - -struct r8a7790_mxi_qos { - u32 vspdu0; - u32 vspdu1; - u32 du0; - u32 du1; -}; - -/* AXI(QoS) */ -struct r8a7790_axi_qos { - u32 qosconf; - u32 qosctset0; - u32 qosctset1; - u32 qosctset2; - u32 qosctset3; - u32 qosreqctr; - u32 qosthres0; - u32 qosthres1; - u32 qosthres2; - u32 qosqon; -}; - -#endif - -#endif /* __ASM_ARCH_R8A7790_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h deleted file mode 100644 index d3cf0c10a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h +++ /dev/null @@ -1,438 +0,0 @@ -#ifndef __ASM_R8A7791_H__ -#define __ASM_R8A7791_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, - GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, - GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, - GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, - GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, - GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, - GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, - GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, - GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, - GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, - GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, - GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, - GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, - GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, - GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7, - GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11, - GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15, - GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19, - GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23, - GPIO_GP_7_24, GPIO_GP_7_25, - - GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA, - GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0, - GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2, - GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5, - GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7, - GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, - - /* IPSR0 */ - GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5, - GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, - GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, - GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B, - GPIO_FN_SCL0_C, GPIO_FN_PWM2_B, - GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B, - GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B, - GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK, - - /* IPSR1 */ - GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8, - GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0, - GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0, - GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN, - GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_A15, GPIO_FN_BPFCLK_C, - GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B, - GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C, - GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C, - - /* IPSR2 */ - GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C, - GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B, - GPIO_FN_A20, GPIO_FN_SPCLK, - GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0, - GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B, - GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD, - GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B, - GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD, - GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3, - GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD, - GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C, - GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD, - GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1, - GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1, - GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK, - GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC, - GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD, - GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1, - - /* IPSR3 */ - GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N, - GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2, - GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1, - GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B, - GPIO_FN_PWM1, GPIO_FN_TPU_TO1, - GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2, - GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B, - GPIO_FN_PWM2, GPIO_FN_TPU_TO2, - GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B, - GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D, - GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B, - GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B, - GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B, - GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B, - GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3, - GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON, - GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C, - GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B, - GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D, - GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C, - GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C, - GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C, - GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C, - - /* IPSR4 */ - GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B, - GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B, - GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D, - GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B, - GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D, - GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B, - GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B, - GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E, - GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B, - GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E, - GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B, - GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E, - GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3, - GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D, - GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D, - GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0, - GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B, - - /* IPSR5 */ - GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0, - GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B, - GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0, - GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B, - GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0, - GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B, - GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK, - GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B, - GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B, - GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B, - GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS, - GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON, - GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B, - GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B, - GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D, - GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D, - GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D, - - /* IPSR6 */ - GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E, - GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E, - GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD, - GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N, - GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N, - GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N, - GPIO_FN_IRQ3, GPIO_FN_SCL4_C, - GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N, - GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C, - GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N, - GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E, - GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E, - GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, - GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D, - - /* IPSR7 */ - GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D, - GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D, - GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B, - GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B, - GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B, - GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B, - GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B, - GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B, - GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B, - GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B, - GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B, - GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B, - GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B, - GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B, - - /* IPSR8 */ - GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11, - GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B, - GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B, - GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B, - GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B, - GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B, - GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B, - GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B, - GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B, - GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B, - GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B, - GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B, - GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B, - GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B, - GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B, - GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20, - GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX, - GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3, - GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX, - - /* IPSR9 */ - GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C, - GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD, - GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C, - GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK, - GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS, - GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK, - GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX, - GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4, - GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS, - GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE, - GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, - GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B, - GPIO_FN_DU1_DISP, GPIO_FN_QPOLA, - GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B, - GPIO_FN_VI0_CLKENB, GPIO_FN_TX4, - GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D, - GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D, - GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5, - GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D, - GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5, - GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B, - GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4, - GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N, - - /* IPSR10 */ - GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4, - GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N, - GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C, - GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N, - GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C, - GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N, - GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D, - GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C, - GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E, - GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D, - GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D, - GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D, - GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B, - GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N, - GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B, - GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N, - GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3, - GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C, - GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4, - GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B, - GPIO_FN_TX0_C, GPIO_FN_SCL1_D, - - /* IPSR11 */ - GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B, - GPIO_FN_RX0_C, GPIO_FN_SDA1_D, - GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B, - GPIO_FN_TX1_C, GPIO_FN_SCL4_B, - GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E, - GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D, - GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B, - GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B, - GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B, - GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B, - GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B, - GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5, - GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6, - GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7, - GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER, - GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO, - GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV, - GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC, - GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC, - GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C, - GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C, - - /* IPSR12 */ - GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7, - GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7, - GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C, - GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C, - GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B, - GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B, - GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3, - GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B, - GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C, - GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C, - GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C, - GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D, - GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C, - GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D, - GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C, - - /* IPSR13 */ - GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C, - GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C, - GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK, - GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C, - GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL, - GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C, - GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B, - GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C, - GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B, - GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B, - GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B, - GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B, - GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B, - GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F, - GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C, - GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F, - GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C, - GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B, - GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B, - GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B, - GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B, - GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C, - - /* IPSR14 */ - GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C, - GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD, - GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1, - GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3, - GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C, - GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C, - GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C, - GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C, - GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA, - GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B, - GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP, - GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B, - GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK, - GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B, - GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0, - GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B, - GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E, - GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B, - GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E, - GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B, - - /* IPSR15 */ - GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D, - GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C, - GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D, - GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B, - GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C, - GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5, - GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C, - GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6, - GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C, - GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C, - GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C, - GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N, - GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C, - GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK, - GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C, - GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C, - GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C, - GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C, - GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C, - - /* IPSR16 */ - GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B, - GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C, - GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B, - GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C, - GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C, - GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N, - GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B, - GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N, - GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, -}; - -#endif /* __ASM_R8A7791_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h deleted file mode 100644 index ff3018059..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ /dev/null @@ -1,665 +0,0 @@ -/* - * arch/arm/include/asm/arch-rmobile/r8a7791.h - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __ASM_ARCH_R8A7791_H -#define __ASM_ARCH_R8A7791_H - -/* - * R8A7791 I/O Addresses - */ -#define RWDT_BASE 0xE6020000 -#define SWDT_BASE 0xE6030000 -#define LBSC_BASE 0xFEC00200 -#define DBSC3_0_BASE 0xE6790000 -#define DBSC3_1_BASE 0xE67A0000 -#define TMU_BASE 0xE61E0000 -#define GPIO5_BASE 0xE6055000 -#define SH_QSPI_BASE 0xE6B10000 - -#define S3C_BASE 0xE6784000 -#define S3C_INT_BASE 0xE6784A00 -#define S3C_MEDIA_BASE 0xE6784B00 - -#define S3C_QOS_DCACHE_BASE 0xE6784BDC -#define S3C_QOS_CCI0_BASE 0xE6784C00 -#define S3C_QOS_CCI1_BASE 0xE6784C24 -#define S3C_QOS_MXI_BASE 0xE6784C48 -#define S3C_QOS_AXI_BASE 0xE6784C6C - -#define DBSC3_0_QOS_R0_BASE 0xE6791000 -#define DBSC3_0_QOS_R1_BASE 0xE6791100 -#define DBSC3_0_QOS_R2_BASE 0xE6791200 -#define DBSC3_0_QOS_R3_BASE 0xE6791300 -#define DBSC3_0_QOS_R4_BASE 0xE6791400 -#define DBSC3_0_QOS_R5_BASE 0xE6791500 -#define DBSC3_0_QOS_R6_BASE 0xE6791600 -#define DBSC3_0_QOS_R7_BASE 0xE6791700 -#define DBSC3_0_QOS_R8_BASE 0xE6791800 -#define DBSC3_0_QOS_R9_BASE 0xE6791900 -#define DBSC3_0_QOS_R10_BASE 0xE6791A00 -#define DBSC3_0_QOS_R11_BASE 0xE6791B00 -#define DBSC3_0_QOS_R12_BASE 0xE6791C00 -#define DBSC3_0_QOS_R13_BASE 0xE6791D00 -#define DBSC3_0_QOS_R14_BASE 0xE6791E00 -#define DBSC3_0_QOS_R15_BASE 0xE6791F00 -#define DBSC3_0_QOS_W0_BASE 0xE6792000 -#define DBSC3_0_QOS_W1_BASE 0xE6792100 -#define DBSC3_0_QOS_W2_BASE 0xE6792200 -#define DBSC3_0_QOS_W3_BASE 0xE6792300 -#define DBSC3_0_QOS_W4_BASE 0xE6792400 -#define DBSC3_0_QOS_W5_BASE 0xE6792500 -#define DBSC3_0_QOS_W6_BASE 0xE6792600 -#define DBSC3_0_QOS_W7_BASE 0xE6792700 -#define DBSC3_0_QOS_W8_BASE 0xE6792800 -#define DBSC3_0_QOS_W9_BASE 0xE6792900 -#define DBSC3_0_QOS_W10_BASE 0xE6792A00 -#define DBSC3_0_QOS_W11_BASE 0xE6792B00 -#define DBSC3_0_QOS_W12_BASE 0xE6792C00 -#define DBSC3_0_QOS_W13_BASE 0xE6792D00 -#define DBSC3_0_QOS_W14_BASE 0xE6792E00 -#define DBSC3_0_QOS_W15_BASE 0xE6792F00 - -#define DBSC3_1_QOS_R0_BASE 0xE67A1000 -#define DBSC3_1_QOS_R1_BASE 0xE67A1100 -#define DBSC3_1_QOS_R2_BASE 0xE67A1200 -#define DBSC3_1_QOS_R3_BASE 0xE67A1300 -#define DBSC3_1_QOS_R4_BASE 0xE67A1400 -#define DBSC3_1_QOS_R5_BASE 0xE67A1500 -#define DBSC3_1_QOS_R6_BASE 0xE67A1600 -#define DBSC3_1_QOS_R7_BASE 0xE67A1700 -#define DBSC3_1_QOS_R8_BASE 0xE67A1800 -#define DBSC3_1_QOS_R9_BASE 0xE67A1900 -#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 -#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 -#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 -#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 -#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 -#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 -#define DBSC3_1_QOS_W0_BASE 0xE67A2000 -#define DBSC3_1_QOS_W1_BASE 0xE67A2100 -#define DBSC3_1_QOS_W2_BASE 0xE67A2200 -#define DBSC3_1_QOS_W3_BASE 0xE67A2300 -#define DBSC3_1_QOS_W4_BASE 0xE67A2400 -#define DBSC3_1_QOS_W5_BASE 0xE67A2500 -#define DBSC3_1_QOS_W6_BASE 0xE67A2600 -#define DBSC3_1_QOS_W7_BASE 0xE67A2700 -#define DBSC3_1_QOS_W8_BASE 0xE67A2800 -#define DBSC3_1_QOS_W9_BASE 0xE67A2900 -#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 -#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 -#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 -#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 -#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 -#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 - -#define DBSC3_0_DBADJ2 0xE67900C8 - -#define CCI_400_MAXOT_1 0xF0091110 -#define CCI_400_MAXOT_2 0xF0092110 -#define CCI_400_QOSCNTL_1 0xF009110C -#define CCI_400_QOSCNTL_2 0xF009210C - -#define MXI_BASE 0xFE960000 -#define MXI_QOS_BASE 0xFE960300 - -#define SYS_AXI_SYX64TO128_BASE 0xFF800300 -#define SYS_AXI_AVB_BASE 0xFF800340 -#define SYS_AXI_G2D_BASE 0xFF800540 -#define SYS_AXI_IMP0_BASE 0xFF800580 -#define SYS_AXI_IMP1_BASE 0xFF8005C0 -#define SYS_AXI_IMUX0_BASE 0xFF800600 -#define SYS_AXI_IMUX1_BASE 0xFF800640 -#define SYS_AXI_IMUX2_BASE 0xFF800680 -#define SYS_AXI_LBS_BASE 0xFF8006C0 -#define SYS_AXI_MMUDS_BASE 0xFF800700 -#define SYS_AXI_MMUM_BASE 0xFF800740 -#define SYS_AXI_MMUR_BASE 0xFF800780 -#define SYS_AXI_MMUS0_BASE 0xFF8007C0 -#define SYS_AXI_MMUS1_BASE 0xFF800800 -#define SYS_AXI_MTSB0_BASE 0xFF800880 -#define SYS_AXI_MTSB1_BASE 0xFF8008C0 -#define SYS_AXI_PCI_BASE 0xFF800900 -#define SYS_AXI_RTX_BASE 0xFF800940 -#define SYS_AXI_SDS0_BASE 0xFF800A80 -#define SYS_AXI_SDS1_BASE 0xFF800AC0 -#define SYS_AXI_USB20_BASE 0xFF800C00 -#define SYS_AXI_USB21_BASE 0xFF800C40 -#define SYS_AXI_USB22_BASE 0xFF800C80 -#define SYS_AXI_USB30_BASE 0xFF800CC0 -#define SYS_AXI_AX2M_BASE 0xFF800380 -#define SYS_AXI_CC50_BASE 0xFF8003C0 -#define SYS_AXI_CCI_BASE 0xFF800440 -#define SYS_AXI_CS_BASE 0xFF800480 -#define SYS_AXI_DDM_BASE 0xFF8004C0 -#define SYS_AXI_ETH_BASE 0xFF800500 -#define SYS_AXI_MPXM_BASE 0xFF800840 -#define SYS_AXI_SAT0_BASE 0xFF800980 -#define SYS_AXI_SAT1_BASE 0xFF8009C0 -#define SYS_AXI_SDM0_BASE 0xFF800A00 -#define SYS_AXI_SDM1_BASE 0xFF800A40 -#define SYS_AXI_TRAB_BASE 0xFF800B00 -#define SYS_AXI_UDM0_BASE 0xFF800B80 -#define SYS_AXI_UDM1_BASE 0xFF800BC0 - -#define RT_AXI_SHX_BASE 0xFF810100 -#define RT_AXI_DBG_BASE 0xFF810140 -#define RT_AXI_RDM_BASE 0xFF810180 -#define RT_AXI_RDS_BASE 0xFF8101C0 -#define RT_AXI_RTX64TO128_BASE 0xFF810200 -#define RT_AXI_STPRO_BASE 0xFF810240 -#define RT_AXI_SY2RT_BASE 0xFF810280 - -#define MP_AXI_ADSP_BASE 0xFF820100 -#define MP_AXI_ASDS0_BASE 0xFF8201C0 -#define MP_AXI_ASDS1_BASE 0xFF820200 -#define MP_AXI_MLP_BASE 0xFF820240 -#define MP_AXI_MMUMP_BASE 0xFF820280 -#define MP_AXI_SPU_BASE 0xFF8202C0 -#define MP_AXI_SPUC_BASE 0xFF820300 - -#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 -#define SYS_AXI256_SYX_BASE 0xFF860140 -#define SYS_AXI256_MPX_BASE 0xFF860180 -#define SYS_AXI256_MXI_BASE 0xFF8601C0 - -#define CCI_AXI_MMUS0_BASE 0xFF880100 -#define CCI_AXI_SYX2_BASE 0xFF880140 -#define CCI_AXI_MMUR_BASE 0xFF880180 -#define CCI_AXI_MMUDS_BASE 0xFF8801C0 -#define CCI_AXI_MMUM_BASE 0xFF880200 -#define CCI_AXI_MXI_BASE 0xFF880240 -#define CCI_AXI_MMUS1_BASE 0xFF880280 -#define CCI_AXI_MMUMP_BASE 0xFF8802C0 - -#define MEDIA_AXI_MXR_BASE 0xFE960080 -#define MEDIA_AXI_MXW_BASE 0xFE9600C0 -#define MEDIA_AXI_JPR_BASE 0xFE964100 -#define MEDIA_AXI_JPW_BASE 0xFE966100 -#define MEDIA_AXI_GCU0R_BASE 0xFE964140 -#define MEDIA_AXI_GCU0W_BASE 0xFE966140 -#define MEDIA_AXI_GCU1R_BASE 0xFE964180 -#define MEDIA_AXI_GCU1W_BASE 0xFE966180 -#define MEDIA_AXI_TDMR_BASE 0xFE964500 -#define MEDIA_AXI_TDMW_BASE 0xFE966500 -#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 -#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 -#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 -#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 -#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 -#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 -#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 -#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 -#define MEDIA_AXI_VIN0W_BASE 0xFE966900 -#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 -#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 -#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 -#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 -#define MEDIA_AXI_IMSR_BASE 0xFE964D80 -#define MEDIA_AXI_IMSW_BASE 0xFE966D80 -#define MEDIA_AXI_VSP1R_BASE 0xFE965100 -#define MEDIA_AXI_VSP1W_BASE 0xFE967100 -#define MEDIA_AXI_FDP1R_BASE 0xFE965140 -#define MEDIA_AXI_FDP1W_BASE 0xFE967140 -#define MEDIA_AXI_IMRR_BASE 0xFE965180 -#define MEDIA_AXI_IMRW_BASE 0xFE967180 -#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 -#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 -#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 -#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 -#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 -#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 -#define MEDIA_AXI_DU0R_BASE 0xFE965580 -#define MEDIA_AXI_DU0W_BASE 0xFE967580 -#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 -#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 -#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 -#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 -#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 -#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 -#define MEDIA_AXI_VPC0R_BASE 0xFE965980 -#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 -#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 -#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 -#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 -#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 - -#define SYS_AXI_AVBDMSCR 0xFF802000 -#define SYS_AXI_SYX2DMSCR 0xFF802004 -#define SYS_AXI_CC50DMSCR 0xFF802008 -#define SYS_AXI_CC51DMSCR 0xFF80200C -#define SYS_AXI_CCIDMSCR 0xFF802010 -#define SYS_AXI_CSDMSCR 0xFF802014 -#define SYS_AXI_DDMDMSCR 0xFF802018 -#define SYS_AXI_ETHDMSCR 0xFF80201C -#define SYS_AXI_G2DDMSCR 0xFF802020 -#define SYS_AXI_IMP0DMSCR 0xFF802024 -#define SYS_AXI_IMP1DMSCR 0xFF802028 -#define SYS_AXI_LBSDMSCR 0xFF80202C -#define SYS_AXI_MMUDSDMSCR 0xFF802030 -#define SYS_AXI_MMUMXDMSCR 0xFF802034 -#define SYS_AXI_MMURDDMSCR 0xFF802038 -#define SYS_AXI_MMUS0DMSCR 0xFF80203C -#define SYS_AXI_MMUS1DMSCR 0xFF802040 -#define SYS_AXI_MPXDMSCR 0xFF802044 -#define SYS_AXI_MTSB0DMSCR 0xFF802048 -#define SYS_AXI_MTSB1DMSCR 0xFF80204C -#define SYS_AXI_PCIDMSCR 0xFF802050 -#define SYS_AXI_RTXDMSCR 0xFF802054 -#define SYS_AXI_SAT0DMSCR 0xFF802058 -#define SYS_AXI_SAT1DMSCR 0xFF80205C -#define SYS_AXI_SDM0DMSCR 0xFF802060 -#define SYS_AXI_SDM1DMSCR 0xFF802064 -#define SYS_AXI_SDS0DMSCR 0xFF802068 -#define SYS_AXI_SDS1DMSCR 0xFF80206C -#define SYS_AXI_ETRABDMSCR 0xFF802070 -#define SYS_AXI_ETRKFDMSCR 0xFF802074 -#define SYS_AXI_UDM0DMSCR 0xFF802078 -#define SYS_AXI_UDM1DMSCR 0xFF80207C -#define SYS_AXI_USB20DMSCR 0xFF802080 -#define SYS_AXI_USB21DMSCR 0xFF802084 -#define SYS_AXI_USB22DMSCR 0xFF802088 -#define SYS_AXI_USB30DMSCR 0xFF80208C -#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 -#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 -#define SYS_AXI_AVBSLVDMSCR 0xFF802108 -#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C -#define SYS_AXI_ETHSLVDMSCR 0xFF802110 -#define SYS_AXI_GICSLVDMSCR 0xFF802114 -#define SYS_AXI_IMPSLVDMSCR 0xFF802118 -#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C -#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 -#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 -#define SYS_AXI_LBSSLVDMSCR 0xFF802128 -#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C -#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 -#define SYS_AXI_MPXSLVDMSCR 0xFF802134 -#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 -#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C -#define SYS_AXI_MXTSLVDMSCR 0xFF802140 -#define SYS_AXI_PCISLVDMSCR 0xFF802144 -#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 -#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C -#define SYS_AXI_RTXSLVDMSCR 0xFF802150 -#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 -#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C -#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 -#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 -#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 -#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C -#define SYS_AXI_SGXSLVDMSCR 0xFF802180 -#define SYS_AXI_STBSLVDMSCR 0xFF802188 -#define SYS_AXI_STMSLVDMSCR 0xFF80218C -#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 -#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 -#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C -#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 -#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 -#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 -#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC - -#define RT_AXI_CBMDMSCR 0xFF812000 -#define RT_AXI_DBDMSCR 0xFF812004 -#define RT_AXI_RDMDMSCR 0xFF812008 -#define RT_AXI_RDSDMSCR 0xFF81200C -#define RT_AXI_STRDMSCR 0xFF812010 -#define RT_AXI_SY2RTDMSCR 0xFF812014 -#define RT_AXI_CBSSLVDMSCR 0xFF812100 -#define RT_AXI_DBSSLVDMSCR 0xFF812104 -#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 -#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C -#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 -#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 -#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 -#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C -#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 -#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 - -#define MP_AXI_ADSPDMSCR 0xFF822000 -#define MP_AXI_ASDM0DMSCR 0xFF822004 -#define MP_AXI_ASDM1DMSCR 0xFF822008 -#define MP_AXI_ASDS0DMSCR 0xFF82200C -#define MP_AXI_ASDS1DMSCR 0xFF822010 -#define MP_AXI_MLPDMSCR 0xFF822014 -#define MP_AXI_MMUMPDMSCR 0xFF822018 -#define MP_AXI_SPUDMSCR 0xFF82201C -#define MP_AXI_SPUCDMSCR 0xFF822020 -#define MP_AXI_SY2MPDMSCR 0xFF822024 -#define MP_AXI_ADSPSLVDMSCR 0xFF822100 -#define MP_AXI_MLMSLVDMSCR 0xFF822104 -#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 -#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C -#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 -#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 -#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 -#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C -#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 -#define MP_AXI_SPUSLVDMSCR 0xFF822128 -#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C - -#define ADM_AXI_ASDM0DMSCR 0xFF842000 -#define ADM_AXI_ASDM1DMSCR 0xFF842004 -#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 -#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 -#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C - -#define DM_AXI_RDMDMSCR 0xFF852000 -#define DM_AXI_SDM0DMSCR 0xFF852004 -#define DM_AXI_SDM1DMSCR 0xFF852008 -#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 -#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 -#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 -#define DM_AXI_RAP4SLVDMSCR 0xFF85210C -#define DM_AXI_RAP5SLVDMSCR 0xFF852110 -#define DM_AXI_SAP4SLVDMSCR 0xFF852114 -#define DM_AXI_SAP5SLVDMSCR 0xFF852118 -#define DM_AXI_SAP6SLVDMSCR 0xFF85211C -#define DM_AXI_SAP65SLVDMSCR 0xFF852120 -#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 -#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 -#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C -#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 - -#define SYS_AXI256_SYXDMSCR 0xFF862000 -#define SYS_AXI256_MPXDMSCR 0xFF862004 -#define SYS_AXI256_MXIDMSCR 0xFF862008 -#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 -#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 -#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 -#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C -#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 - -#define MXT_SYXDMSCR 0xFF872000 -#define MXT_CMM0SLVDMSCR 0xFF872100 -#define MXT_CMM1SLVDMSCR 0xFF872104 -#define MXT_CMM2SLVDMSCR 0xFF872108 -#define MXT_FDPSLVDMSCR 0xFF87210C -#define MXT_IMRSLVDMSCR 0xFF872110 -#define MXT_VINSLVDMSCR 0xFF872114 -#define MXT_VPC0SLVDMSCR 0xFF872118 -#define MXT_VPC1SLVDMSCR 0xFF87211C -#define MXT_VSP0SLVDMSCR 0xFF872120 -#define MXT_VSP1SLVDMSCR 0xFF872124 -#define MXT_VSPD0SLVDMSCR 0xFF872128 -#define MXT_VSPD1SLVDMSCR 0xFF87212C -#define MXT_MAP1SLVDMSCR 0xFF872130 -#define MXT_MAP2SLVDMSCR 0xFF872134 - -#define CCI_AXI_MMUS0DMSCR 0xFF882000 -#define CCI_AXI_SYX2DMSCR 0xFF882004 -#define CCI_AXI_MMURDMSCR 0xFF882008 -#define CCI_AXI_MMUDSDMSCR 0xFF88200C -#define CCI_AXI_MMUMDMSCR 0xFF882010 -#define CCI_AXI_MXIDMSCR 0xFF882014 -#define CCI_AXI_MMUS1DMSCR 0xFF882018 -#define CCI_AXI_MMUMPDMSCR 0xFF88201C -#define CCI_AXI_DVMDMSCR 0xFF882020 -#define CCI_AXI_CCISLVDMSCR 0xFF882100 - -#define CCI_AXI_IPMMUIDVMCR 0xFF880400 -#define CCI_AXI_IPMMURDVMCR 0xFF880404 -#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 -#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C -#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 -#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 -#define CCI_AXI_AX2ADDRMASK 0xFF88041C - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7791_rwdt { - u32 rwtcnt; /* 0x00 */ - u32 rwtcsra; /* 0x04 */ - u16 rwtcsrb; /* 0x08 */ -}; - -/* SWDT */ -struct r8a7791_swdt { - u32 swtcnt; /* 0x00 */ - u32 swtcsra; /* 0x04 */ - u16 swtcsrb; /* 0x08 */ -}; - -/* LBSC */ -struct r8a7791_lbsc { - u32 cs0ctrl; - u32 cs1ctrl; - u32 ecs0ctrl; - u32 ecs1ctrl; - u32 ecs2ctrl; - u32 ecs3ctrl; - u32 ecs4ctrl; - u32 ecs5ctrl; - u32 dummy0[4]; /* 0x20 .. 0x2C */ - u32 cswcr0; - u32 cswcr1; - u32 ecswcr0; - u32 ecswcr1; - u32 ecswcr2; - u32 ecswcr3; - u32 ecswcr4; - u32 ecswcr5; - u32 exdmawcr0; - u32 exdmawcr1; - u32 exdmawcr2; - u32 dummy1[9]; /* 0x5C .. 0x7C */ - u32 cspwcr0; - u32 cspwcr1; - u32 ecspwcr0; - u32 ecspwcr1; - u32 ecspwcr2; - u32 ecspwcr3; - u32 ecspwcr4; - u32 ecspwcr5; - u32 exwtsync; - u32 dummy2[3]; /* 0xA4 .. 0xAC */ - u32 cs0bstctl; - u32 cs0btph; - u32 dummy3[2]; /* 0xB8 .. 0xBC */ - u32 cs1gdst; - u32 ecs0gdst; - u32 ecs1gdst; - u32 ecs2gdst; - u32 ecs3gdst; - u32 ecs4gdst; - u32 ecs5gdst; - u32 dummy4[5]; /* 0xDC .. 0xEC */ - u32 exdmaset0; - u32 exdmaset1; - u32 exdmaset2; - u32 dummy5[5]; /* 0xFC .. 0x10C */ - u32 exdmcr0; - u32 exdmcr1; - u32 exdmcr2; - u32 dummy6[5]; /* 0x11C .. 0x12C */ - u32 bcintsr; - u32 bcintcr; - u32 bcintmr; - u32 dummy7; /* 0x13C */ - u32 exbatlv; - u32 exwtsts; - u32 dummy8[14]; /* 0x148 .. 0x17C */ - u32 atacsctrl; - u32 dummy9[15]; /* 0x184 .. 0x1BC */ - u32 exbct; - u32 extct; -}; - -/* DBSC3 */ -struct r8a7791_dbsc3 { - u32 dummy0[3]; /* 0x00 .. 0x08 */ - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2C */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3C */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4C */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xAC */ - u32 dbbl; - u32 dummy5[3]; /* 0xB4 .. 0xBC */ - u32 dbadj0; - u32 dummy6; /* 0xC4 */ - u32 dbadj2; - u32 dummy7[5]; /* 0xCC .. 0xDC */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dummy8[2]; /* 0xEC .. 0xF0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy9; /* 0xFC */ - u32 dbrnk0; - u32 dummy10[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy11[47]; /* 0x184 ..0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[14]; /* 0x248 .. 0x27C */ - u32 dbpdlck; - u32 dummy13[3]; /* 0x284 .. 0x28C */ - u32 dbpdrga; - u32 dummy14[3]; /* 0x294 .. 0x29C */ - u32 dbpdrgd; - u32 dummy15[24]; /* 0x2A4 .. 0x300 */ - u32 dbbs0cnt1; - u32 dummy16[30]; /* 0x308 .. 0x37C */ - u32 dbwt0cnf0; - u32 dbwt0cnf1; - u32 dbwt0cnf2; - u32 dbwt0cnf3; - u32 dbwt0cnf4; -}; - -/* GPIO */ -struct r8a7791_gpio { - u32 iointsel; - u32 inoutsel; - u32 outdt; - u32 indt; - u32 intdt; - u32 intclr; - u32 intmsk; - u32 posneg; - u32 edglevel; - u32 filonoff; - u32 intmsks; - u32 mskclrs; - u32 outdtsel; - u32 outdth; - u32 outdtl; - u32 bothedge; -}; - -/* S3C(QoS) */ -struct r8a7791_s3c { - u32 s3cexcladdmsk; - u32 s3cexclidmsk; - u32 s3cadsplcr; - u32 s3cmaar; - u32 dummy0; /* 0x10 */ - u32 s3crorr; - u32 s3cworr; - u32 s3carcr22; - u32 dummy1[2]; /* 0x20 .. 0x24 */ - u32 s3cmctr; - u32 dummy2; /* 0x2C */ - u32 cconf0; - u32 cconf1; - u32 cconf2; - u32 cconf3; -}; - -struct r8a7791_s3c_qos { - u32 s3cqos0; - u32 s3cqos1; - u32 s3cqos2; - u32 s3cqos3; - u32 s3cqos4; - u32 s3cqos5; - u32 s3cqos6; - u32 s3cqos7; - u32 s3cqos8; -}; - -/* DBSC(QoS) */ -struct r8a7791_dbsc3_qos { - u32 dblgcnt; - u32 dbtmval0; - u32 dbtmval1; - u32 dbtmval2; - u32 dbtmval3; - u32 dbrqctr; - u32 dbthres0; - u32 dbthres1; - u32 dbthres2; - u32 dummy0; /* 0x24 */ - u32 dblgqon; -}; - -/* MXI(QoS) */ -struct r8a7791_mxi { - u32 mxsaar0; - u32 mxsaar1; - u32 dummy0[8]; /* 0x08 .. 0x24 */ - u32 mxs3cracr; - u32 dummy1[3]; /* 0x2C .. 0x34 */ - u32 mxs3cwacr; - u32 dummy2; /* 0x3C */ - u32 mxrtcr; - u32 mxwtcr; -}; - -struct r8a7791_mxi_qos { - u32 vspdu0; - u32 vspdu1; - u32 du0; - u32 du1; -}; - -/* AXI(QoS) */ -struct r8a7791_axi_qos { - u32 qosconf; - u32 qosctset0; - u32 qosctset1; - u32 qosctset2; - u32 qosctset3; - u32 qosreqctr; - u32 qosthres0; - u32 qosthres1; - u32 qosthres2; - u32 qosqon; -}; - -#endif - -#endif /* __ASM_ARCH_R8A7791_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/rmobile.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/rmobile.h deleted file mode 100644 index 238256502..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/rmobile.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_ARCH_RMOBILE_H -#define __ASM_ARCH_RMOBILE_H - -#if defined(CONFIG_RMOBILE) -#if defined(CONFIG_SH73A0) -#include <asm/arch/sh73a0.h> -#elif defined(CONFIG_R8A7740) -#include <asm/arch/r8a7740.h> -#elif defined(CONFIG_R8A7790) -#include <asm/arch/r8a7790.h> -#elif defined(CONFIG_R8A7791) -#include <asm/arch/r8a7791.h> -#else -#error "SOC Name not defined" -#endif -#endif /* CONFIG_RMOBILE */ - -#endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h deleted file mode 100644 index 398e2c109..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h +++ /dev/null @@ -1,553 +0,0 @@ -#ifndef __ASM_SH73A0_H__ -#define __ASM_SH73A0_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function and MSEL switch - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* Hardware manual Table 25-1 (GPIO) */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, - - GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - - GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, - GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, - - GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, - GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, - - GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, - GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, - - GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, - GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, - - GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, - GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, - - GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, - GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, - - GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, - GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, - - GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, - - GPIO_PORT288, GPIO_PORT289, - - GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, - GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, - - GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, - GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, - - /* Table 25-1 (Function 0-7) */ - GPIO_FN_VBUS_0, - GPIO_FN_GPI0, - GPIO_FN_GPI1, - GPIO_FN_GPI2, - GPIO_FN_GPI3, - GPIO_FN_GPI4, - GPIO_FN_GPI5, - GPIO_FN_GPI6, - GPIO_FN_GPI7, - GPIO_FN_SCIFA7_RXD, - GPIO_FN_SCIFA7_CTS_, - GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, - GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, - GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ - GPIO_FN_PORT16_VIO_CKOR, - GPIO_FN_SCIFA0_TXD, - GPIO_FN_SCIFA7_TXD, - GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, - GPIO_FN_GPO0, - GPIO_FN_GPO1, - GPIO_FN_GPO2, GPIO_FN_STATUS0, - GPIO_FN_GPO3, GPIO_FN_STATUS1, - GPIO_FN_GPO4, GPIO_FN_STATUS2, - GPIO_FN_VINT, - GPIO_FN_TCKON, - GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ - GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, - GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ - GPIO_FN_PORT28_TPU1TO1, - GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, - GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, - GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, - GPIO_FN_SCIFA4_TXD, - GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, - GPIO_FN_SCIFA4_RTS_, - GPIO_FN_SCIFA4_CTS_, - GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, - GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, - GPIO_FN_FSIBOSLD, - GPIO_FN_FSIBISLD, - GPIO_FN_VACK, - GPIO_FN_XTAL1L, - GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, - GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, - GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, - GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, - GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, - GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, - GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ - GPIO_FN_FSIAOMC, - GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, - - GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, - GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, - GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ - GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, - GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ - GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, - GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, - GPIO_FN_A0, GPIO_FN_BS_, - GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, - GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, - GPIO_FN_A14, GPIO_FN_KEYOUT5, - GPIO_FN_A15, GPIO_FN_KEYOUT4, - GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, - GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, - GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, - GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, - GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, - GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, - GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, - GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, - GPIO_FN_A26, GPIO_FN_KEYIN6, - GPIO_FN_KEYIN7, - GPIO_FN_D0_NAF0, - GPIO_FN_D1_NAF1, - GPIO_FN_D2_NAF2, - GPIO_FN_D3_NAF3, - GPIO_FN_D4_NAF4, - GPIO_FN_D5_NAF5, - GPIO_FN_D6_NAF6, - GPIO_FN_D7_NAF7, - GPIO_FN_D8_NAF8, - GPIO_FN_D9_NAF9, - GPIO_FN_D10_NAF10, - GPIO_FN_D11_NAF11, - GPIO_FN_D12_NAF12, - GPIO_FN_D13_NAF13, - GPIO_FN_D14_NAF14, - GPIO_FN_D15_NAF15, - GPIO_FN_CS4_, - GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, - GPIO_FN_CS5B_, GPIO_FN_FCE1_, - GPIO_FN_CS6B_, GPIO_FN_DACK0, - GPIO_FN_FCE0_, GPIO_FN_CS6A_, - GPIO_FN_WAIT_, GPIO_FN_DREQ0, - GPIO_FN_RD__FSC, - GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, - GPIO_FN_WE1_, - GPIO_FN_FRB, - GPIO_FN_CKO, - GPIO_FN_NBRSTOUT_, - GPIO_FN_NBRST_, - GPIO_FN_BBIF2_TXD, - GPIO_FN_BBIF2_RXD, - GPIO_FN_BBIF2_SYNC, - GPIO_FN_BBIF2_SCK, - GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, - GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, - GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, - GPIO_FN_SCIFA3_TXD, - GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, - GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, - GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, - GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ - GPIO_FN_PORT115_I2C_SCL3, - GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ - GPIO_FN_PORT116_I2C_SDA3, - GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, - GPIO_FN_HSI_TX_FLAG, - GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ - GPIO_FN_LCD2D0, - - GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ - GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, - GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, - GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ - GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, - GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ - GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, - GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, - GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, - GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, - GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, - GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, - GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ - GPIO_FN_LCD2D6, - GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ - GPIO_FN_LCD2D7, - GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, - GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, - GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ - GPIO_FN_LCD2D2, - GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ - GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, - GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ - GPIO_FN_LCD2D4, - GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ - GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, - GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ - GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, - GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, - GPIO_FN_VIO_CKO, - GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ - GPIO_FN_PORT149_KEYOUT9, - GPIO_FN_MFG0_IN2, - GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, - GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, - GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, - GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, - GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, - GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, - GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, - GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, - GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, - GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, - GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, - GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ - GPIO_FN_TPU3TO0, - GPIO_FN_LCDD0, - GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, - GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, - GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, - GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ - GPIO_FN_TPU2TO1, - GPIO_FN_LCDD6, - GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, - GPIO_FN_LCDD8, GPIO_FN_D16, - GPIO_FN_LCDD9, GPIO_FN_D17, - GPIO_FN_LCDD10, GPIO_FN_D18, - GPIO_FN_LCDD11, GPIO_FN_D19, - GPIO_FN_LCDD12, GPIO_FN_D20, - GPIO_FN_LCDD13, GPIO_FN_D21, - GPIO_FN_LCDD14, GPIO_FN_D22, - GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, - GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, - GPIO_FN_LCDD17, GPIO_FN_D25, - GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, - GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, - GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, - GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, - GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, - GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, - GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, - GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ - GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, - GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ - GPIO_FN_PORT218_VIO_CKOR, - GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ - GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ - GPIO_FN_LCD2DCK_2, - GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, - GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ - GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ - GPIO_FN_PORT221_LCD2HSYN, - GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ - GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, - - GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, - GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, - GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, - GPIO_FN_SCIFA1_RXD, - GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, - GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, - GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, - GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, - GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, - GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ - GPIO_FN_LCD2D20, - GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ - GPIO_FN_LCD2D21, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, - GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, - GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, - GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, - GPIO_FN_SCIFA6_TXD, - GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ - GPIO_FN_TPU4TO0, - GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, - GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, - GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ - GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, - GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ - GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, - GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ - GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, - GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ - GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, - GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ - GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ - GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, - GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ - GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, - GPIO_FN_SDHICLK0, - GPIO_FN_SDHICD0, - GPIO_FN_SDHID0_0, - GPIO_FN_SDHID0_1, - GPIO_FN_SDHID0_2, - GPIO_FN_SDHID0_3, - GPIO_FN_SDHICMD0, - GPIO_FN_SDHIWP0, - GPIO_FN_SDHICLK1, - GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, - GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, - GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, - GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, - GPIO_FN_SDHICMD1, - GPIO_FN_SDHICLK2, - GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, - GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, - GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, - GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, - GPIO_FN_SDHICMD2, - GPIO_FN_MMCCLK0, - GPIO_FN_MMCD0_0, - GPIO_FN_MMCD0_1, - GPIO_FN_MMCD0_2, - GPIO_FN_MMCD0_3, - GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, - GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, - GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, - GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, - GPIO_FN_MMCCMD0, - GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, - GPIO_FN_MCP_WAIT__MCP_FRB, - GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, - GPIO_FN_MCP_D15_MCP_NAF15, - GPIO_FN_MCP_D14_MCP_NAF14, - GPIO_FN_MCP_D13_MCP_NAF13, - GPIO_FN_MCP_D12_MCP_NAF12, - GPIO_FN_MCP_D11_MCP_NAF11, - GPIO_FN_MCP_D10_MCP_NAF10, - GPIO_FN_MCP_D9_MCP_NAF9, - GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, - GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, - - GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, - GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, - GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, - GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, - GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, - GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, - GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, - GPIO_FN_MCP_NBRSTOUT_, - GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, - - /* MSEL2 special case */ - GPIO_FN_TSIF2_TS_XX1, - GPIO_FN_TSIF2_TS_XX2, - GPIO_FN_TSIF2_TS_XX3, - GPIO_FN_TSIF2_TS_XX4, - GPIO_FN_TSIF2_TS_XX5, - GPIO_FN_TSIF1_TS_XX1, - GPIO_FN_TSIF1_TS_XX2, - GPIO_FN_TSIF1_TS_XX3, - GPIO_FN_TSIF1_TS_XX4, - GPIO_FN_TSIF1_TS_XX5, - GPIO_FN_TSIF0_TS_XX1, - GPIO_FN_TSIF0_TS_XX2, - GPIO_FN_TSIF0_TS_XX3, - GPIO_FN_TSIF0_TS_XX4, - GPIO_FN_TSIF0_TS_XX5, - GPIO_FN_MST1_TS_XX1, - GPIO_FN_MST1_TS_XX2, - GPIO_FN_MST1_TS_XX3, - GPIO_FN_MST1_TS_XX4, - GPIO_FN_MST1_TS_XX5, - GPIO_FN_MST0_TS_XX1, - GPIO_FN_MST0_TS_XX2, - GPIO_FN_MST0_TS_XX3, - GPIO_FN_MST0_TS_XX4, - GPIO_FN_MST0_TS_XX5, - - /* MSEL3 special cases */ - GPIO_FN_SDHI0_VCCQ_MC0_ON, - GPIO_FN_SDHI0_VCCQ_MC0_OFF, - GPIO_FN_DEBUG_MON_VIO, - GPIO_FN_DEBUG_MON_LCDD, - GPIO_FN_LCDC_LCDC0, - GPIO_FN_LCDC_LCDC1, - - /* MSEL4 special cases */ - GPIO_FN_IRQ9_MEM_INT, - GPIO_FN_IRQ9_MCP_INT, - GPIO_FN_A11, - GPIO_FN_KEYOUT8, - GPIO_FN_TPU4TO3, - GPIO_FN_RESETA_N_PU_ON, - GPIO_FN_RESETA_N_PU_OFF, - GPIO_FN_EDBGREQ_PD, - GPIO_FN_EDBGREQ_PU, - - /* Functions with pull-ups */ - GPIO_FN_KEYIN0_PU, - GPIO_FN_KEYIN1_PU, - GPIO_FN_KEYIN2_PU, - GPIO_FN_KEYIN3_PU, - GPIO_FN_KEYIN4_PU, - GPIO_FN_KEYIN5_PU, - GPIO_FN_KEYIN6_PU, - GPIO_FN_KEYIN7_PU, - GPIO_FN_SDHICD0_PU, - GPIO_FN_SDHID0_0_PU, - GPIO_FN_SDHID0_1_PU, - GPIO_FN_SDHID0_2_PU, - GPIO_FN_SDHID0_3_PU, - GPIO_FN_SDHICMD0_PU, - GPIO_FN_SDHIWP0_PU, - GPIO_FN_SDHID1_0_PU, - GPIO_FN_SDHID1_1_PU, - GPIO_FN_SDHID1_2_PU, - GPIO_FN_SDHID1_3_PU, - GPIO_FN_SDHICMD1_PU, - GPIO_FN_SDHID2_0_PU, - GPIO_FN_SDHID2_1_PU, - GPIO_FN_SDHID2_2_PU, - GPIO_FN_SDHID2_3_PU, - GPIO_FN_SDHICMD2_PU, - GPIO_FN_MMCCMD0_PU, - GPIO_FN_MMCCMD1_PU, - GPIO_FN_MMCD0_0_PU, - GPIO_FN_MMCD0_1_PU, - GPIO_FN_MMCD0_2_PU, - GPIO_FN_MMCD0_3_PU, - GPIO_FN_MMCD0_4_PU, - GPIO_FN_MMCD0_5_PU, - GPIO_FN_MMCD0_6_PU, - GPIO_FN_MMCD0_7_PU, - GPIO_FN_FSIACK_PU, - GPIO_FN_FSIAILR_PU, - GPIO_FN_FSIAIBT_PU, - GPIO_FN_FSIAISLD_PU, - - /* end of GPIO */ - GPIO_NR, -}; - -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_SCIF0_TX, - SHDMA_SLAVE_SCIF0_RX, - SHDMA_SLAVE_SCIF1_TX, - SHDMA_SLAVE_SCIF1_RX, - SHDMA_SLAVE_SCIF2_TX, - SHDMA_SLAVE_SCIF2_RX, - SHDMA_SLAVE_SCIF3_TX, - SHDMA_SLAVE_SCIF3_RX, - SHDMA_SLAVE_SCIF4_TX, - SHDMA_SLAVE_SCIF4_RX, - SHDMA_SLAVE_SCIF5_TX, - SHDMA_SLAVE_SCIF5_RX, - SHDMA_SLAVE_SCIF6_TX, - SHDMA_SLAVE_SCIF6_RX, - SHDMA_SLAVE_SCIF7_TX, - SHDMA_SLAVE_SCIF7_RX, - SHDMA_SLAVE_SCIF8_TX, - SHDMA_SLAVE_SCIF8_RX, - SHDMA_SLAVE_SDHI0_TX, - SHDMA_SLAVE_SDHI0_RX, - SHDMA_SLAVE_SDHI1_TX, - SHDMA_SLAVE_SDHI1_RX, - SHDMA_SLAVE_SDHI2_TX, - SHDMA_SLAVE_SDHI2_RX, - SHDMA_SLAVE_MMCIF_TX, - SHDMA_SLAVE_MMCIF_RX, -}; - -/* - * SH73A0 IRQ LOCATION TABLE - * - * 416 ----------------------------------------- - * IRQ0-IRQ15 - * 431 ----------------------------------------- - * ... - * 448 ----------------------------------------- - * sh73a0-intcs - * sh73a0-intca-irq-pins - * 680 ----------------------------------------- - * ... - * 700 ----------------------------------------- - * sh73a0-pint0 - * 731 ----------------------------------------- - * 732 ----------------------------------------- - * sh73a0-pint1 - * 739 ----------------------------------------- - * ... - * 800 ----------------------------------------- - * IRQ16-IRQ31 - * 815 ----------------------------------------- - * ... - * 928 ----------------------------------------- - * sh73a0-intca-irq-pins - * 943 ----------------------------------------- - */ - -/* PINT interrupts are located at Linux IRQ 700 and up */ -#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) -#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) - -#endif /* __ASM_SH73A0_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0.h deleted file mode 100644 index bdbb40864..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0.h +++ /dev/null @@ -1,289 +0,0 @@ -#ifndef __ASM_ARCH_RMOBILE_SH73A0_H -#define __ASM_ARCH_RMOBILE_SH73A0_H - -/* Global Timer */ -#define GLOBAL_TIMER_BASE_ADDR (0xF0000200) -#define MERAM_BASE (0xE5580000) - -/* GIC */ -#define GIC_BASE (0xF0000100) -#define ICCICR GIC_BASE - -/* Secure control register */ -#define LIFEC_SEC_SRC (0xE6110008) - -/* RWDT */ -#define RWDT_BASE (0xE6020000) - -/* HPB Semaphore Control Registers */ -#define HPB_BASE (0xE6001010) - -/* Bus Semaphore Control Registers */ -#define HPBSCR_BASE (0xE6001600) - -/* SBSC1 */ -#define SBSC1_BASE (0xFE400000) -#define SDMRA1A (SBSC1_BASE + 0x100000) -#define SDMRA2A (SBSC1_BASE + 0x1C0000) -#define SDMRA3A (SBSC1_BASE + 0x104000) - -/* SBSC2 */ -#define SBSC2_BASE (0xFB400000) -#define SDMRA1B (SBSC2_BASE + 0x100000) -#define SDMRA2B (SBSC2_BASE + 0x1C0000) -#define SDMRA3B (SBSC2_BASE + 0x104000) - -/* CPG */ -#define CPG_BASE (0xE6150000) -#define CPG_SRCR_BASE (CPG_BASE + 0x80A0) -#define WUPCR (CPG_BASE + 0x1010) -#define SRESCR (CPG_BASE + 0x1018) -#define PCLKCR (CPG_BASE + 0x1020) - -/* SYSC */ -#define SYSC_BASE (0xE6180000) -#define RESCNT2 (SYSC_BASE + 0x8020) - -/* BSC */ -#define BSC_BASE (0xFEC10000) - -/* SCIF */ -#define SCIF0_BASE (0xE6C40000) -#define SCIF1_BASE (0xE6C50000) -#define SCIF2_BASE (0xE6C60000) -#define SCIF3_BASE (0xE6C70000) -#define SCIF4_BASE (0xE6C80000) -#define SCIF5_BASE (0xE6CB0000) -#define SCIF6_BASE (0xE6CC0000) -#define SCIF7_BASE (0xE6CD0000) - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct sh73a0_rwdt { - u16 rwtcnt0; /* 0x00 */ - u16 dummy0; /* 0x02 */ - u16 rwtcsra0; /* 0x04 */ - u16 dummy1; /* 0x06 */ - u16 rwtcsrb0; /* 0x08 */ -}; - -/* HPB Semaphore Control Registers */ -struct sh73a0_hpb { - u32 hpbctrl0; - u32 hpbctrl1; - u32 hpbctrl2; - u32 cccr; - u32 dummy0; /* 0x20 */ - u32 hpbctrl4; - u32 hpbctrl5; - u32 dummy1; /* 0x2C */ - u32 hpbctrl6; -}; - -/* Bus Semaphore Control Registers */ -struct sh73a0_hpb_bscr { - u32 mpsrc; /* 0x00 */ - u32 mpacctl; /* 0x04 */ - u32 dummy0[6]; - u32 smgpiosrc; /* 0x20 */ - u32 smgpioerr; - u32 smgpiotime; - u32 smgpiocnt; - u32 dummy1[4]; /* 0x30 .. 0x3C */ - u32 smcmt2src; - u32 smcmt2err; - u32 smcmt2time; - u32 smcmt2cnt; - u32 smcpgsrc; - u32 smcpgerr; - u32 smcpgtime; - u32 smcpgcnt; - u32 dummy2[4]; /* 0x60 - 0x6C */ - u32 smsyscsrc; - u32 smsyscerr; - u32 smsysctime; - u32 smsysccnt; -}; - -/* SBSC */ -struct sh73a0_sbsc { - u32 dummy0[2]; /* 0x00, 0x04 */ - u32 sdcr0; - u32 sdcr1; - u32 sdpcr; - u32 dummy1; /* 0x14 */ - u32 sdcr0s; - u32 sdcr1s; - u32 rtcsr; - u32 dummy2; /* 0x24 */ - u32 rtcor; - u32 rtcorh; - u32 rtcors; - u32 rtcorsh; - u32 dummy3[2]; /* 0x38, 0x3C */ - u32 sdwcrc0; - u32 sdwcrc1; - u32 sdwcr00; - u32 sdwcr01; - u32 sdwcr10; - u32 sdwcr11; - u32 sdpdcr0; - u32 dummy4; /* 0x5C */ - u32 sdwcr2; - u32 sdwcrc2; - u32 zqccr; - u32 dummy5[6]; /* 0x6C .. 0x80 */ - u32 sdmracr0; - u32 dummy6; /* 0x88 */ - u32 sdmrtmpcr; - u32 dummy7; /* 0x90 */ - u32 sdmrtmpmsk; - u32 dummy8; /* 0x98 */ - u32 sdgencnt; - u32 dphycnt0; - u32 dphycnt1; - u32 dphycnt2; - u32 dummy9[2]; /* 0xAC .. 0xB0 */ - u32 sddrvcr0; - u32 dummy10[14]; /* 0xB8 .. 0xEC */ - u32 dptdivcr0; - u32 dptdivcr1; - u32 dptdivcr2; - u32 dummy11; /* 0xFC */ - u32 sdptcr0; - u32 sdptcr1; - u32 sdptcr2; - u32 sdptcr3; /* 0x10C */ - u32 dummy12[145]; /* 0x110 .. 0x350 */ - u32 dllcnt0; /* 0x354 */ - u32 sbscmon0; -}; - -/* CPG */ -struct sh73a0_sbsc_cpg { - u32 frqcra; /* 0x00 */ - u32 frqcrb; - u32 vclkcr1; - u32 vclkcr2; - u32 zbckcr; - u32 flckcr; - u32 fsiackcr; - u32 vclkcr3; - u32 rtstbcr; - u32 systbcr; - u32 pll1cr; - u32 pll2cr; - u32 mstpsr0; - u32 dummy0; /* 0x34 */ - u32 mstpsr1; - u32 mstpsr5; - u32 mstpsr2; - u32 dummy1; /* 0x44 */ - u32 mstpsr3; - u32 mstpsr4; - u32 dummy2; /* 0x50 */ - u32 astat; - u32 dvfscr0; - u32 dvfscr1; - u32 dsitckcr; - u32 dsi0pckcr; - u32 dsi1pckcr; - u32 dsi0phycr; - u32 dsi1phycr; - u32 sd0ckcr; - u32 sd1ckcr; - u32 sd2ckcr; - u32 subckcr; - u32 spuackcr; - u32 msuckcr; - u32 hsickcr; - u32 fsibckcr; - u32 spuvckcr; - u32 mfck1cr; - u32 mfck2cr; - u32 dummy3[8]; /* 0xA0 .. 0xBC */ - u32 ckscr; - u32 dummy4; /* 0xC4 */ - u32 pll1stpcr; - u32 mpmode; - u32 pllecr; - u32 dummy5; /* 0xD4 */ - u32 pll0cr; - u32 pll3cr; - u32 dummy6; /* 0xE0 */ - u32 frqcrd; - u32 dummyi7; /* 0xE8 */ - u32 vrefcr; - u32 pll0stpcr; - u32 dummy8; /* 0xF4 */ - u32 pll2stpcr; - u32 pll3stpcr; - u32 dummy9[4]; /* 0x100 .. 0x10c */ - u32 rmstpcr0; - u32 rmstpcr1; - u32 rmstpcr2; - u32 rmstpcr3; - u32 rmstpcr4; - u32 rmstpcr5; - u32 dummy10[2]; /* 0x128 .. 0x12c */ - u32 smstpcr0; - u32 smstpcr1; - u32 smstpcr2; - u32 smstpcr3; - u32 smstpcr4; - u32 smstpcr5; - u32 dummy11[2]; /* 0x148 .. 0x14c */ - u32 cpgxxcs4; - u32 dummy12[7]; /* 0x154 .. 0x16c */ - u32 dvfscr2; - u32 dvfscr3; - u32 dvfscr4; - u32 dvfscr5; /* 0x17C */ -}; - -/* CPG SRCR part OK */ -struct sh73a0_sbsc_cpg_srcr { - u32 srcr0; - u32 dummy0; /* 0xA4 */ - u32 srcr1; - u32 dummy1; /* 0xAC */ - u32 srcr2; - u32 dummy2; /* 0xB4 */ - u32 srcr3; - u32 srcr4; - u32 dummy3; /* 0xC0 */ - u32 srcr5; -}; - -/* BSC */ -struct sh73a0_bsc { - u32 cmncr; - u32 cs0bcr; - u32 cs2bcr; - u32 dummy0; /* 0x0C */ - u32 cs4bcr; - u32 cs5abcr; - u32 cs5bbcr; - u32 cs6abcr; - u32 cs6bbcr; - u32 cs0wcr; - u32 cs2wcr; - u32 dummy1; /* 0x2C */ - u32 cs4wcr; - u32 cs5awcr; - u32 cs5bwcr; - u32 cs6awcr; - u32 cs6bwcr; - u32 rbwtcnt; - u32 busycr; - u32 dummy2; /* 0x5c */ - u32 cs7abcr; - u32 cs7awcr; - u32 dummy3[2]; /* 0x68, 0x6C */ - u32 bromtimcr; -}; -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sys_proto.h deleted file mode 100644 index 326f6b148..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sys_proto.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -struct rmobile_sysinfo { - char *board_string; -}; -extern const struct rmobile_sysinfo sysinfo; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h deleted file mode 100644 index a749b6491..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2012. - * - * Gabriel Huau <contact@huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S3C24X0_GPIO_H_ -#define _S3C24X0_GPIO_H_ - -enum s3c2440_gpio { - GPA0, - GPA1, - GPA2, - GPA3, - GPA4, - GPA5, - GPA6, - GPA7, - GPA8, - GPA9, - GPA10, - GPA11, - GPA12, - GPA13, - GPA14, - GPA15, - GPA16, - GPA17, - GPA18, - GPA19, - GPA20, - GPA21, - GPA22, - GPA23, - GPA24, - - GPB0 = 32, - GPB1, - GPB2, - GPB3, - GPB4, - GPB5, - GPB6, - GPB7, - GPB8, - GPB9, - GPB10, - - GPC0 = 64, - GPC1, - GPC2, - GPC3, - GPC4, - GPC5, - GPC6, - GPC7, - GPC8, - GPC9, - GPC10, - GPC11, - GPC12, - GPC13, - GPC14, - GPC15, - - GPD0 = 96, - GPD1, - GPD2, - GPD3, - GPD4, - GPD5, - GPD6, - GPD7, - GPD8, - GPD9, - GPD10, - GPD11, - GPD12, - GPD13, - GPD14, - GPD15, - - GPE0 = 128, - GPE1, - GPE2, - GPE3, - GPE4, - GPE5, - GPE6, - GPE7, - GPE8, - GPE9, - GPE10, - GPE11, - GPE12, - GPE13, - GPE14, - GPE15, - - GPF0 = 160, - GPF1, - GPF2, - GPF3, - GPF4, - GPF5, - GPF6, - GPF7, - - GPG0 = 192, - GPG1, - GPG2, - GPG3, - GPG4, - GPG5, - GPG6, - GPG7, - GPG8, - GPG9, - GPG10, - GPG11, - GPG12, - GPG13, - GPG14, - GPG15, - - GPH0 = 224, - GPH1, - GPH2, - GPH3, - GPH4, - GPH5, - GPH6, - GPH7, - GPH8, - GPH9, - GPH10, - - GPJ0 = 256, - GPJ1, - GPJ2, - GPJ3, - GPJ4, - GPJ5, - GPJ6, - GPJ7, - GPJ8, - GPJ9, - GPJ10, - GPJ11, - GPJ12, -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h deleted file mode 100644 index 981164434..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2012 - * - * Gabriel Huau <contact@huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S3C24X0_IOMUX_H_ -#define _S3C24X0_IOMUX_H_ - -enum s3c2440_iomux_func { - /* PORT A */ - IOMUXA_ADDR0 = 1, - IOMUXA_ADDR16 = (1 << 1), - IOMUXA_ADDR17 = (1 << 2), - IOMUXA_ADDR18 = (1 << 3), - IOMUXA_ADDR19 = (1 << 4), - IOMUXA_ADDR20 = (1 << 5), - IOMUXA_ADDR21 = (1 << 6), - IOMUXA_ADDR22 = (1 << 7), - IOMUXA_ADDR23 = (1 << 8), - IOMUXA_ADDR24 = (1 << 9), - IOMUXA_ADDR25 = (1 << 10), - IOMUXA_ADDR26 = (1 << 11), - IOMUXA_nGCS1 = (1 << 12), - IOMUXA_nGCS2 = (1 << 13), - IOMUXA_nGCS3 = (1 << 14), - IOMUXA_nGCS4 = (1 << 15), - IOMUXA_nGCS5 = (1 << 16), - IOMUXA_CLE = (1 << 17), - IOMUXA_ALE = (1 << 18), - IOMUXA_nFWE = (1 << 19), - IOMUXA_nFRE = (1 << 20), - IOMUXA_nRSTOUT = (1 << 21), - IOMUXA_nFCE = (1 << 22), - - /* PORT B */ - IOMUXB_nXDREQ0 = (2 << 20), - IOMUXB_nXDACK0 = (2 << 18), - IOMUXB_nXDREQ1 = (2 << 16), - IOMUXB_nXDACK1 = (2 << 14), - IOMUXB_nXBREQ = (2 << 12), - IOMUXB_nXBACK = (2 << 10), - IOMUXB_TCLK0 = (2 << 8), - IOMUXB_TOUT3 = (2 << 6), - IOMUXB_TOUT2 = (2 << 4), - IOMUXB_TOUT1 = (2 << 2), - IOMUXB_TOUT0 = 2, - - /* PORT C */ - IOMUXC_VS7 = (2 << 30), - IOMUXC_VS6 = (2 << 28), - IOMUXC_VS5 = (2 << 26), - IOMUXC_VS4 = (2 << 24), - IOMUXC_VS3 = (2 << 22), - IOMUXC_VS2 = (2 << 20), - IOMUXC_VS1 = (2 << 18), - IOMUXC_VS0 = (2 << 16), - IOMUXC_LCD_LPCREVB = (2 << 14), - IOMUXC_LCD_LPCREV = (2 << 12), - IOMUXC_LCD_LPCOE = (2 << 10), - IOMUXC_VM = (2 << 8), - IOMUXC_VFRAME = (2 << 6), - IOMUXC_VLINE = (2 << 4), - IOMUXC_VCLK = (2 << 2), - IOMUXC_LEND = 2, - IOMUXC_I2SSDI = (3 << 8), - - /* PORT D */ - IOMUXD_VS23 = (2 << 30), - IOMUXD_VS22 = (2 << 28), - IOMUXD_VS21 = (2 << 26), - IOMUXD_VS20 = (2 << 24), - IOMUXD_VS19 = (2 << 22), - IOMUXD_VS18 = (2 << 20), - IOMUXD_VS17 = (2 << 18), - IOMUXD_VS16 = (2 << 16), - IOMUXD_VS15 = (2 << 14), - IOMUXD_VS14 = (2 << 12), - IOMUXD_VS13 = (2 << 10), - IOMUXD_VS12 = (2 << 8), - IOMUXD_VS11 = (2 << 6), - IOMUXD_VS10 = (2 << 4), - IOMUXD_VS9 = (2 << 2), - IOMUXD_VS8 = 2, - IOMUXD_nSS0 = (3 << 30), - IOMUXD_nSS1 = (3 << 28), - IOMUXD_SPICLK1 = (3 << 20), - IOMUXD_SPIMOSI1 = (3 << 18), - IOMUXD_SPIMISO1 = (3 << 16), - - /* PORT E */ - IOMUXE_IICSDA = (2 << 30), - IOMUXE_IICSCL = (2 << 28), - IOMUXE_SPICLK0 = (2 << 26), - IOMUXE_SPIMOSI0 = (2 << 24), - IOMUXE_SPIMISO0 = (2 << 22), - IOMUXE_SDDAT3 = (2 << 20), - IOMUXE_SDDAT2 = (2 << 18), - IOMUXE_SDDAT1 = (2 << 16), - IOMUXE_SDDAT0 = (2 << 14), - IOMUXE_SDCMD = (2 << 12), - IOMUXE_SDCLK = (2 << 10), - IOMUXE_I2SDO = (2 << 8), - IOMUXE_I2SDI = (2 << 6), - IOMUXE_CDCLK = (2 << 4), - IOMUXE_I2SSCLK = (2 << 2), - IOMUXE_I2SLRCK = 2, - IOMUXE_AC_SDATA_OUT = (3 << 8), - IOMUXE_AC_SDATA_IN = (3 << 6), - IOMUXE_AC_nRESET = (3 << 4), - IOMUXE_AC_BIT_CLK = (3 << 2), - IOMUXE_AC_SYNC = 3, - - /* PORT F */ - IOMUXF_EINT7 = (2 << 14), - IOMUXF_EINT6 = (2 << 12), - IOMUXF_EINT5 = (2 << 10), - IOMUXF_EINT4 = (2 << 8), - IOMUXF_EINT3 = (2 << 6), - IOMUXF_EINT2 = (2 << 4), - IOMUXF_EINT1 = (2 << 2), - IOMUXF_EINT0 = 2, - - /* PORT G */ - IOMUXG_EINT23 = (2 << 30), - IOMUXG_EINT22 = (2 << 28), - IOMUXG_EINT21 = (2 << 26), - IOMUXG_EINT20 = (2 << 24), - IOMUXG_EINT19 = (2 << 22), - IOMUXG_EINT18 = (2 << 20), - IOMUXG_EINT17 = (2 << 18), - IOMUXG_EINT16 = (2 << 16), - IOMUXG_EINT15 = (2 << 14), - IOMUXG_EINT14 = (2 << 12), - IOMUXG_EINT13 = (2 << 10), - IOMUXG_EINT12 = (2 << 8), - IOMUXG_EINT11 = (2 << 6), - IOMUXG_EINT10 = (2 << 4), - IOMUXG_EINT9 = (2 << 2), - IOMUXG_EINT8 = 2, - IOMUXG_TCLK1 = (3 << 22), - IOMUXG_nCTS1 = (3 << 20), - IOMUXG_nRTS1 = (3 << 18), - IOMUXG_SPICLK1 = (3 << 14), - IOMUXG_SPIMOSI1 = (3 << 12), - IOMUXG_SPIMISO1 = (3 << 10), - IOMUXG_LCD_PWRDN = (3 << 8), - IOMUXG_nSS1 = (3 << 6), - IOMUXG_nSS0 = (3 << 4), - - /* PORT H */ - IOMUXH_CLKOUT1 = (2 << 20), - IOMUXH_CLKOUT0 = (2 << 18), - IOMUXH_UEXTCLK = (2 << 16), - IOMUXH_RXD2 = (2 << 14), - IOMUXH_TXD2 = (2 << 12), - IOMUXH_RXD1 = (2 << 10), - IOMUXH_TXD1 = (2 << 8), - IOMUXH_RXD0 = (2 << 6), - IOMUXH_TXD0 = (2 << 4), - IOMUXH_nRTS0 = (2 << 2), - IOMUXH_nCTS0 = 2, - IOMUXH_nCTS1 = (3 << 14), - IOMUXH_nRTS1 = (3 << 12), - - /* PORT J */ - IOMUXJ_CAMRESET = (2 << 24), - IOMUXJ_CAMCLKOUT = (2 << 22), - IOMUXJ_CAMHREF = (2 << 20), - IOMUXJ_CAMVSYNC = (2 << 18), - IOMUXJ_CAMPCLK = (2 << 16), - IOMUXJ_CAMDATA7 = (2 << 14), - IOMUXJ_CAMDATA6 = (2 << 12), - IOMUXJ_CAMDATA5 = (2 << 10), - IOMUXJ_CAMDATA4 = (2 << 8), - IOMUXJ_CAMDATA3 = (2 << 6), - IOMUXJ_CAMDATA2 = (2 << 4), - IOMUXJ_CAMDATA1 = (2 << 2), - IOMUXJ_CAMDATA0 = 2 -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h deleted file mode 100644 index d6a787b66..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de - * based on - * linux/include/asm-arm/arch-sa1100/memory.h - * - * Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com> - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - - -/* - * Task size: 3GB - */ -#define TASK_SIZE (0xc0000000UL) -#define TASK_SIZE_26 (0x04000000UL) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -/* - * Page offset: 3GB - */ -#define PAGE_OFFSET (0xc0000000UL) - -/* - * Physical DRAM offset is 0x0c000000 on the S3C2400 - */ -#define PHYS_OFFSET (0x0c000000UL) - -/* Modified for S3C2400, by chc, 20010509 */ -#define RAM_IN_BANK_0 32*1024*1024 -#define RAM_IN_BANK_1 0 -#define RAM_IN_BANK_2 0 -#define RAM_IN_BANK_3 0 - -#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3) - - -/* translation macros */ -#define __virt_to_phys__is_a_macro -#define __phys_to_virt__is_a_macro - -#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 ) -#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET ) - -#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \ - (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -/* Two identical banks */ -#define __virt_to_phys(x) \ - ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \ - ((x) - PAGE_OFFSET + _DRAMBnk0) : \ - ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) ) -#define __phys_to_virt(x) \ - ( ((x)&0x07ffffff) + \ - (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) ) -#else - -/* It's more efficient for all other cases to use the function call */ -#undef __virt_to_phys__is_a_macro -#undef __phys_to_virt__is_a_macro -extern unsigned long __virt_to_phys(unsigned long vpage); -extern unsigned long __phys_to_virt(unsigned long ppage); - -#endif - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * On the SA1100, bus addresses are equivalent to physical addresses. - */ -#define __virt_to_bus__is_a_macro -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt__is_a_macro -#define __bus_to_virt(x) __phys_to_virt(x) - - -#ifdef CONFIG_DISCONTIGMEM -#error "CONFIG_DISCONTIGMEM will not work on S3C2400" -/* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much more convenient to use Linux's NUMA support to implement - * our memory map representation. Assuming all memory nodes have equal access - * characteristics, we then have generic discontiguous memory support. - * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. - * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff - */ - -#define NR_NODES 4 - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - 0xc0000000) >> 27) - -/* - * Given a physical address, convert it to a node id. - */ -#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(kvaddr) \ - (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) - -/* - * Given a kaddr, virt_to_page returns a pointer to the corresponding - * mem_map entry. - */ -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -/* - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they refer to. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ( (node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ -}) - -#else - -#define PHYS_TO_NID(addr) (0) - -#endif -#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h deleted file mode 100644 index 2389118e7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2400.h - * Version : 31.3.2003 - * - * Based on S3C2400X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2400_H__ -#define __S3C2400_H__ - -#define S3C24X0_UART_CHANNELS 2 -#define S3C24X0_SPI_CHANNELS 1 -#define PALETTE (0x14A00400) /* SJS */ - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, -}; - -/*S3C2400 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x14000000 -#define S3C24X0_USB_HOST_BASE 0x14200000 -#define S3C24X0_INTERRUPT_BASE 0x14400000 -#define S3C24X0_DMA_BASE 0x14600000 -#define S3C24X0_CLOCK_POWER_BASE 0x14800000 -#define S3C24X0_LCD_BASE 0x14A00000 -#define S3C24X0_UART_BASE 0x15000000 -#define S3C24X0_TIMER_BASE 0x15100000 -#define S3C24X0_USB_DEVICE_BASE 0x15200140 -#define S3C24X0_WATCHDOG_BASE 0x15300000 -#define S3C24X0_I2C_BASE 0x15400000 -#define S3C24X0_I2S_BASE 0x15508000 -#define S3C24X0_GPIO_BASE 0x15600000 -#define S3C24X0_RTC_BASE 0x15700000 -#define S3C24X0_ADC_BASE 0x15800000 -#define S3C24X0_SPI_BASE 0x15900000 -#define S3C2400_MMC_BASE 0x15A00000 - -/* include common stuff */ -#include <asm/arch/s3c24x0.h> - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2400_adc *s3c2400_get_base_adc(void) -{ - return (struct s3c2400_adc *)S3C24X0_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) -{ - return (struct s3c2400_mmc *)S3C2400_MMC_BASE; -} - -#endif /*__S3C2400_H__*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h deleted file mode 100644 index 01fe0f27e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2410.h - * Version : 31.3.2003 - * - * Based on S3C2410X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2410_H__ -#define __S3C2410_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2410 only supports 512 Byte HW ECC */ -#define S3C2410_ECCSIZE 512 -#define S3C2410_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2410 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2410_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - - -/* include common stuff */ -#include <asm/arch/s3c24x0.h> - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c2410_nand *s3c2410_get_base_nand(void) -{ - return (struct s3c2410_nand *)S3C2410_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2410_adc *s3c2410_get_base_adc(void) -{ - return (struct s3c2410_adc *)S3C2410_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) -{ - return (struct s3c2410_sdi *)S3C2410_SDI_BASE; -} - -#endif /*__S3C2410_H__*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h deleted file mode 100644 index 15a7cb43d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2003 - * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2440.h - * Version : 31.3.2003 - * - * Based on S3C2440 User's manual Rev x.x - ************************************************/ - -#ifndef __S3C2440_H__ -#define __S3C2440_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2440 only supports 512 Byte HW ECC */ -#define S3C2440_ECCSIZE 512 -#define S3C2440_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2440 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2440_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2440_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2440_SDI_BASE 0x5A000000 - -/* include common stuff */ -#include <asm/arch/s3c24x0.h> - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c2440_nand *s3c2440_get_base_nand(void) -{ - return (struct s3c2440_nand *)S3C2440_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2440_adc *s3c2440_get_base_adc(void) -{ - return (struct s3c2440_adc *)S3C2440_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) -{ - return (struct s3c2440_sdi *)S3C2440_SDI_BASE; -} - -#endif /*__S3C2440_H__*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h deleted file mode 100644 index 86d720c06..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ /dev/null @@ -1,704 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c24x0.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C24X0 SoC - ************************************************/ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -/* Memory controller (see manual chapter 5) */ -struct s3c24x0_memctl { - u32 bwscon; - u32 bankcon[8]; - u32 refresh; - u32 banksize; - u32 mrsrb6; - u32 mrsrb7; -}; - - -/* USB HOST (see manual chapter 12) */ -struct s3c24x0_usb_host { - u32 HcRevision; - u32 HcControl; - u32 HcCommonStatus; - u32 HcInterruptStatus; - u32 HcInterruptEnable; - u32 HcInterruptDisable; - u32 HcHCCA; - u32 HcPeriodCuttendED; - u32 HcControlHeadED; - u32 HcControlCurrentED; - u32 HcBulkHeadED; - u32 HcBuldCurrentED; - u32 HcDoneHead; - u32 HcRmInterval; - u32 HcFmRemaining; - u32 HcFmNumber; - u32 HcPeriodicStart; - u32 HcLSThreshold; - u32 HcRhDescriptorA; - u32 HcRhDescriptorB; - u32 HcRhStatus; - u32 HcRhPortStatus1; - u32 HcRhPortStatus2; -}; - - -/* INTERRUPT (see manual chapter 14) */ -struct s3c24x0_interrupt { - u32 srcpnd; - u32 intmod; - u32 intmsk; - u32 priority; - u32 intpnd; - u32 intoffset; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 subsrcpnd; - u32 intsubmsk; -#endif -}; - - -/* DMAS (see manual chapter 8) */ -struct s3c24x0_dma { - u32 disrc; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 disrcc; -#endif - u32 didst; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 didstc; -#endif - u32 dcon; - u32 dstat; - u32 dcsrc; - u32 dcdst; - u32 dmasktrig; -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \ - || defined(CONFIG_S3C2440) - u32 res[1]; -#endif -}; - -struct s3c24x0_dmas { - struct s3c24x0_dma dma[4]; -}; - - -/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ -/* (see S3C2410 manual chapter 7) */ -struct s3c24x0_clock_power { - u32 locktime; - u32 mpllcon; - u32 upllcon; - u32 clkcon; - u32 clkslow; - u32 clkdivn; -#if defined(CONFIG_S3C2440) - u32 camdivn; -#endif -}; - - -/* LCD CONTROLLER (see manual chapter 15) */ -struct s3c24x0_lcd { - u32 lcdcon1; - u32 lcdcon2; - u32 lcdcon3; - u32 lcdcon4; - u32 lcdcon5; - u32 lcdsaddr1; - u32 lcdsaddr2; - u32 lcdsaddr3; - u32 redlut; - u32 greenlut; - u32 bluelut; - u32 res[8]; - u32 dithmode; - u32 tpal; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 lcdintpnd; - u32 lcdsrcpnd; - u32 lcdintmsk; - u32 lpcsel; -#endif -}; - - -#ifdef CONFIG_S3C2410 -/* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { - u32 nfconf; - u32 nfcmd; - u32 nfaddr; - u32 nfdata; - u32 nfstat; - u32 nfecc; -}; -#endif -#ifdef CONFIG_S3C2440 -/* NAND FLASH (see S3C2440 manual chapter 6) */ -struct s3c2440_nand { - u32 nfconf; - u32 nfcont; - u32 nfcmd; - u32 nfaddr; - u32 nfdata; - u32 nfeccd0; - u32 nfeccd1; - u32 nfeccd; - u32 nfstat; - u32 nfstat0; - u32 nfstat1; -}; -#endif - - -/* UART (see manual chapter 11) */ -struct s3c24x0_uart { - u32 ulcon; - u32 ucon; - u32 ufcon; - u32 umcon; - u32 utrstat; - u32 uerstat; - u32 ufstat; - u32 umstat; -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 utxh; - u8 res2[3]; - u8 urxh; -#else /* Little Endian */ - u8 utxh; - u8 res1[3]; - u8 urxh; - u8 res2[3]; -#endif - u32 ubrdiv; -}; - - -/* PWM TIMER (see manual chapter 10) */ -struct s3c24x0_timer { - u32 tcntb; - u32 tcmpb; - u32 tcnto; -}; - -struct s3c24x0_timers { - u32 tcfg0; - u32 tcfg1; - u32 tcon; - struct s3c24x0_timer ch[4]; - u32 tcntb4; - u32 tcnto4; -}; - - -/* USB DEVICE (see manual chapter 13) */ -struct s3c24x0_usb_dev_fifos { -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 ep_fifo_reg; -#else /* little endian */ - u8 ep_fifo_reg; - u8 res[3]; -#endif -}; - -struct s3c24x0_usb_dev_dmas { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 ep_dma_con; - u8 res2[3]; - u8 ep_dma_unit; - u8 res3[3]; - u8 ep_dma_fifo; - u8 res4[3]; - u8 ep_dma_ttc_l; - u8 res5[3]; - u8 ep_dma_ttc_m; - u8 res6[3]; - u8 ep_dma_ttc_h; -#else /* little endian */ - u8 ep_dma_con; - u8 res1[3]; - u8 ep_dma_unit; - u8 res2[3]; - u8 ep_dma_fifo; - u8 res3[3]; - u8 ep_dma_ttc_l; - u8 res4[3]; - u8 ep_dma_ttc_m; - u8 res5[3]; - u8 ep_dma_ttc_h; - u8 res6[3]; -#endif -}; - -struct s3c24x0_usb_device { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 func_addr_reg; - u8 res2[3]; - u8 pwr_reg; - u8 res3[3]; - u8 ep_int_reg; - u8 res4[15]; - u8 usb_int_reg; - u8 res5[3]; - u8 ep_int_en_reg; - u8 res6[15]; - u8 usb_int_en_reg; - u8 res7[3]; - u8 frame_num1_reg; - u8 res8[3]; - u8 frame_num2_reg; - u8 res9[3]; - u8 index_reg; - u8 res10[7]; - u8 maxp_reg; - u8 res11[3]; - u8 ep0_csr_in_csr1_reg; - u8 res12[3]; - u8 in_csr2_reg; - u8 res13[7]; - u8 out_csr1_reg; - u8 res14[3]; - u8 out_csr2_reg; - u8 res15[3]; - u8 out_fifo_cnt1_reg; - u8 res16[3]; - u8 out_fifo_cnt2_reg; -#else /* little endian */ - u8 func_addr_reg; - u8 res1[3]; - u8 pwr_reg; - u8 res2[3]; - u8 ep_int_reg; - u8 res3[15]; - u8 usb_int_reg; - u8 res4[3]; - u8 ep_int_en_reg; - u8 res5[15]; - u8 usb_int_en_reg; - u8 res6[3]; - u8 frame_num1_reg; - u8 res7[3]; - u8 frame_num2_reg; - u8 res8[3]; - u8 index_reg; - u8 res9[7]; - u8 maxp_reg; - u8 res10[7]; - u8 ep0_csr_in_csr1_reg; - u8 res11[3]; - u8 in_csr2_reg; - u8 res12[3]; - u8 out_csr1_reg; - u8 res13[7]; - u8 out_csr2_reg; - u8 res14[3]; - u8 out_fifo_cnt1_reg; - u8 res15[3]; - u8 out_fifo_cnt2_reg; - u8 res16[3]; -#endif /* __BIG_ENDIAN */ - struct s3c24x0_usb_dev_fifos fifo[5]; - struct s3c24x0_usb_dev_dmas dma[5]; -}; - - -/* WATCH DOG TIMER (see manual chapter 18) */ -struct s3c24x0_watchdog { - u32 wtcon; - u32 wtdat; - u32 wtcnt; -}; - -/* IIS (see manual chapter 21) */ -struct s3c24x0_i2s { -#ifdef __BIG_ENDIAN - u16 res1; - u16 iiscon; - u16 res2; - u16 iismod; - u16 res3; - u16 iispsr; - u16 res4; - u16 iisfcon; - u16 res5; - u16 iisfifo; -#else /* little endian */ - u16 iiscon; - u16 res1; - u16 iismod; - u16 res2; - u16 iispsr; - u16 res3; - u16 iisfcon; - u16 res4; - u16 iisfifo; - u16 res5; -#endif -}; - - -/* I/O PORT (see manual chapter 9) */ -struct s3c24x0_gpio { -#ifdef CONFIG_S3C2400 - u32 pacon; - u32 padat; - - u32 pbcon; - u32 pbdat; - u32 pbup; - - u32 pccon; - u32 pcdat; - u32 pcup; - - u32 pdcon; - u32 pddat; - u32 pdup; - - u32 pecon; - u32 pedat; - u32 peup; - - u32 pfcon; - u32 pfdat; - u32 pfup; - - u32 pgcon; - u32 pgdat; - u32 pgup; - - u32 opencr; - - u32 misccr; - u32 extint; -#endif -#ifdef CONFIG_S3C2410 - u32 gpacon; - u32 gpadat; - u32 res1[2]; - u32 gpbcon; - u32 gpbdat; - u32 gpbup; - u32 res2; - u32 gpccon; - u32 gpcdat; - u32 gpcup; - u32 res3; - u32 gpdcon; - u32 gpddat; - u32 gpdup; - u32 res4; - u32 gpecon; - u32 gpedat; - u32 gpeup; - u32 res5; - u32 gpfcon; - u32 gpfdat; - u32 gpfup; - u32 res6; - u32 gpgcon; - u32 gpgdat; - u32 gpgup; - u32 res7; - u32 gphcon; - u32 gphdat; - u32 gphup; - u32 res8; - - u32 misccr; - u32 dclkcon; - u32 extint0; - u32 extint1; - u32 extint2; - u32 eintflt0; - u32 eintflt1; - u32 eintflt2; - u32 eintflt3; - u32 eintmask; - u32 eintpend; - u32 gstatus0; - u32 gstatus1; - u32 gstatus2; - u32 gstatus3; - u32 gstatus4; -#endif -#if defined(CONFIG_S3C2440) - u32 gpacon; - u32 gpadat; - u32 res1[2]; - u32 gpbcon; - u32 gpbdat; - u32 gpbup; - u32 res2; - u32 gpccon; - u32 gpcdat; - u32 gpcup; - u32 res3; - u32 gpdcon; - u32 gpddat; - u32 gpdup; - u32 res4; - u32 gpecon; - u32 gpedat; - u32 gpeup; - u32 res5; - u32 gpfcon; - u32 gpfdat; - u32 gpfup; - u32 res6; - u32 gpgcon; - u32 gpgdat; - u32 gpgup; - u32 res7; - u32 gphcon; - u32 gphdat; - u32 gphup; - u32 res8; - - u32 misccr; - u32 dclkcon; - u32 extint0; - u32 extint1; - u32 extint2; - u32 eintflt0; - u32 eintflt1; - u32 eintflt2; - u32 eintflt3; - u32 eintmask; - u32 eintpend; - u32 gstatus0; - u32 gstatus1; - u32 gstatus2; - u32 gstatus3; - u32 gstatus4; - - u32 res9; - u32 dsc0; - u32 dsc1; - u32 mslcon; - u32 gpjcon; - u32 gpjdat; - u32 gpjup; - u32 res10; -#endif -}; - - -/* RTC (see manual chapter 17) */ -struct s3c24x0_rtc { -#ifdef __BIG_ENDIAN - u8 res1[67]; - u8 rtccon; - u8 res2[3]; - u8 ticnt; - u8 res3[11]; - u8 rtcalm; - u8 res4[3]; - u8 almsec; - u8 res5[3]; - u8 almmin; - u8 res6[3]; - u8 almhour; - u8 res7[3]; - u8 almdate; - u8 res8[3]; - u8 almmon; - u8 res9[3]; - u8 almyear; - u8 res10[3]; - u8 rtcrst; - u8 res11[3]; - u8 bcdsec; - u8 res12[3]; - u8 bcdmin; - u8 res13[3]; - u8 bcdhour; - u8 res14[3]; - u8 bcddate; - u8 res15[3]; - u8 bcdday; - u8 res16[3]; - u8 bcdmon; - u8 res17[3]; - u8 bcdyear; -#else /* little endian */ - u8 res0[64]; - u8 rtccon; - u8 res1[3]; - u8 ticnt; - u8 res2[11]; - u8 rtcalm; - u8 res3[3]; - u8 almsec; - u8 res4[3]; - u8 almmin; - u8 res5[3]; - u8 almhour; - u8 res6[3]; - u8 almdate; - u8 res7[3]; - u8 almmon; - u8 res8[3]; - u8 almyear; - u8 res9[3]; - u8 rtcrst; - u8 res10[3]; - u8 bcdsec; - u8 res11[3]; - u8 bcdmin; - u8 res12[3]; - u8 bcdhour; - u8 res13[3]; - u8 bcddate; - u8 res14[3]; - u8 bcdday; - u8 res15[3]; - u8 bcdmon; - u8 res16[3]; - u8 bcdyear; - u8 res17[3]; -#endif -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2400_adc { - u32 adccon; - u32 adcdat; -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2410_adc { - u32 adccon; - u32 adctsc; - u32 adcdly; - u32 adcdat0; - u32 adcdat1; -}; - - -/* SPI (see manual chapter 22) */ -struct s3c24x0_spi_channel { - u8 spcon; - u8 res1[3]; - u8 spsta; - u8 res2[3]; - u8 sppin; - u8 res3[3]; - u8 sppre; - u8 res4[3]; - u8 sptdat; - u8 res5[3]; - u8 sprdat; - u8 res6[3]; - u8 res7[16]; -}; - -struct s3c24x0_spi { - struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; -}; - - -/* MMC INTERFACE (see S3C2400 manual chapter 19) */ -struct s3c2400_mmc { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 mmcon; - u8 res2[3]; - u8 mmcrr; - u8 res3[3]; - u8 mmfcon; - u8 res4[3]; - u8 mmsta; - u16 res5; - u16 mmfsta; - u8 res6[3]; - u8 mmpre; - u16 res7; - u16 mmlen; - u8 res8[3]; - u8 mmcr7; - u32 mmrsp[4]; - u8 res9[3]; - u8 mmcmd0; - u32 mmcmd1; - u16 res10; - u16 mmcr16; - u8 res11[3]; - u8 mmdat; -#else - u8 mmcon; - u8 res1[3]; - u8 mmcrr; - u8 res2[3]; - u8 mmfcon; - u8 res3[3]; - u8 mmsta; - u8 res4[3]; - u16 mmfsta; - u16 res5; - u8 mmpre; - u8 res6[3]; - u16 mmlen; - u16 res7; - u8 mmcr7; - u8 res8[3]; - u32 mmrsp[4]; - u8 mmcmd0; - u8 res9[3]; - u32 mmcmd1; - u16 mmcr16; - u16 res10; - u8 mmdat; - u8 res11[3]; -#endif -}; - - -/* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c2410_sdi { - u32 sdicon; - u32 sdipre; - u32 sdicarg; - u32 sdiccon; - u32 sdicsta; - u32 sdirsp0; - u32 sdirsp1; - u32 sdirsp2; - u32 sdirsp3; - u32 sdidtimer; - u32 sdibsize; - u32 sdidcon; - u32 sdidcnt; - u32 sdidsta; - u32 sdifsta; -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 sdidat; -#else - u8 sdidat; - u8 res[3]; -#endif - u32 sdiimsk; -}; - -#endif /*__S3C24X0_H__*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h deleted file mode 100644 index 393cc9d9f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2009 - * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef CONFIG_S3C2400 - #include <asm/arch/s3c2400.h> -#elif defined CONFIG_S3C2410 - #include <asm/arch/s3c2410.h> -#elif defined CONFIG_S3C2440 - #include <asm/arch/s3c2440.h> -#else - #error Please define the s3c24x0 cpu type -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clk.h deleted file mode 100644 index 6457ac738..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_CLK_H_ -#define __ASM_ARM_ARCH_CLK_H_ - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 - -unsigned long get_pll_clk(int pllreg); -unsigned long get_arm_clk(void); -unsigned long get_pwm_clk(void); -unsigned long get_uart_clk(int dev_index); -void set_mmc_clk(int dev_index, unsigned int div); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clock.h deleted file mode 100644 index 858496af5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clock.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_CLOCK_H_ -#define __ASM_ARM_ARCH_CLOCK_H_ - -#ifndef __ASSEMBLY__ -struct s5pc100_clock { - unsigned int apll_lock; - unsigned int mpll_lock; - unsigned int epll_lock; - unsigned int hpll_lock; - unsigned char res1[0xf0]; - unsigned int apll_con; - unsigned int mpll_con; - unsigned int epll_con; - unsigned int hpll_con; - unsigned char res2[0xf0]; - unsigned int src0; - unsigned int src1; - unsigned int src2; - unsigned int src3; - unsigned char res3[0xf0]; - unsigned int div0; - unsigned int div1; - unsigned int div2; - unsigned int div3; - unsigned int div4; - unsigned char res4[0x1ec]; - unsigned int gate_d00; - unsigned int gate_d01; - unsigned int gate_d02; - unsigned char res5[0x54]; - unsigned int gate_sclk0; - unsigned int gate_sclk1; -}; - -struct s5pc110_clock { - unsigned int apll_lock; - unsigned char res1[0x4]; - unsigned int mpll_lock; - unsigned char res2[0x4]; - unsigned int epll_lock; - unsigned char res3[0xc]; - unsigned int vpll_lock; - unsigned char res4[0xdc]; - unsigned int apll_con; - unsigned char res5[0x4]; - unsigned int mpll_con; - unsigned char res6[0x4]; - unsigned int epll_con; - unsigned char res7[0xc]; - unsigned int vpll_con; - unsigned char res8[0xdc]; - unsigned int src0; - unsigned int src1; - unsigned int src2; - unsigned int src3; - unsigned char res9[0xf0]; - unsigned int div0; - unsigned int div1; - unsigned int div2; - unsigned int div3; - unsigned int div4; - unsigned char res10[0x1ec]; - unsigned int gate_d00; - unsigned int gate_d01; - unsigned int gate_d02; - unsigned char res11[0x54]; - unsigned int gate_sclk0; - unsigned int gate_sclk1; -}; -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/cpu.h deleted file mode 100644 index 5ae5c8716..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S5PC1XX_CPU_H -#define _S5PC1XX_CPU_H - -#define S5P_CPU_NAME "S5P" -#define S5PC1XX_ADDR_BASE 0xE0000000 - -/* S5PC100 */ -#define S5PC100_PRO_ID 0xE0000000 -#define S5PC100_CLOCK_BASE 0xE0100000 -#define S5PC100_GPIO_BASE 0xE0300000 -#define S5PC100_VIC0_BASE 0xE4000000 -#define S5PC100_VIC1_BASE 0xE4100000 -#define S5PC100_VIC2_BASE 0xE4200000 -#define S5PC100_DMC_BASE 0xE6000000 -#define S5PC100_SROMC_BASE 0xE7000000 -#define S5PC100_ONENAND_BASE 0xE7100000 -#define S5PC100_PWMTIMER_BASE 0xEA000000 -#define S5PC100_WATCHDOG_BASE 0xEA200000 -#define S5PC100_UART_BASE 0xEC000000 -#define S5PC100_MMC_BASE 0xED800000 - -/* S5PC110 */ -#define S5PC110_PRO_ID 0xE0000000 -#define S5PC110_CLOCK_BASE 0xE0100000 -#define S5PC110_GPIO_BASE 0xE0200000 -#define S5PC110_PWMTIMER_BASE 0xE2500000 -#define S5PC110_WATCHDOG_BASE 0xE2700000 -#define S5PC110_UART_BASE 0xE2900000 -#define S5PC110_SROMC_BASE 0xE8000000 -#define S5PC110_MMC_BASE 0xEB000000 -#define S5PC110_DMC0_BASE 0xF0000000 -#define S5PC110_DMC1_BASE 0xF1400000 -#define S5PC110_VIC0_BASE 0xF2000000 -#define S5PC110_VIC1_BASE 0xF2100000 -#define S5PC110_VIC2_BASE 0xF2200000 -#define S5PC110_VIC3_BASE 0xF2300000 -#define S5PC110_OTG_BASE 0xEC000000 -#define S5PC110_PHY_BASE 0xEC100000 -#define S5PC110_USB_PHY_CONTROL 0xE010E80C - - -#ifndef __ASSEMBLY__ -#include <asm/io.h> -/* CPU detection macros */ -extern unsigned int s5p_cpu_id; -extern unsigned int s5p_cpu_rev; - -static inline int s5p_get_cpu_rev(void) -{ - return s5p_cpu_rev; -} - -static inline void s5p_set_cpu_id(void) -{ - s5p_cpu_id = readl(S5PC100_PRO_ID); - s5p_cpu_rev = s5p_cpu_id & 0x000000FF; - s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); -} - -static inline char *s5p_get_cpu_name(void) -{ - return S5P_CPU_NAME; -} - -#define IS_SAMSUNG_TYPE(type, id) \ -static inline int cpu_is_##type(void) \ -{ \ - return s5p_cpu_id == id ? 1 : 0; \ -} - -IS_SAMSUNG_TYPE(s5pc100, 0xc100) -IS_SAMSUNG_TYPE(s5pc110, 0xc110) - -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - if (cpu_is_s5pc100()) \ - return S5PC100_##base; \ - else if (cpu_is_s5pc110()) \ - return S5PC110_##base; \ - else \ - return 0; \ -} - -SAMSUNG_BASE(clock, CLOCK_BASE) -SAMSUNG_BASE(gpio, GPIO_BASE) -SAMSUNG_BASE(pro_id, PRO_ID) -SAMSUNG_BASE(mmc, MMC_BASE) -SAMSUNG_BASE(sromc, SROMC_BASE) -SAMSUNG_BASE(timer, PWMTIMER_BASE) -SAMSUNG_BASE(uart, UART_BASE) -SAMSUNG_BASE(watchdog, WATCHDOG_BASE) -#endif - -#endif /* _S5PC1XX_CPU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/gpio.h deleted file mode 100644 index da8df74a1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ -struct s5p_gpio_bank { - unsigned int con; - unsigned int dat; - unsigned int pull; - unsigned int drv; - unsigned int pdn_con; - unsigned int pdn_pull; - unsigned char res1[8]; -}; - -struct s5pc100_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c; - struct s5p_gpio_bank d; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank l3; - struct s5p_gpio_bank l4; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; -}; - -struct s5pc110_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank mp0_1; - struct s5p_gpio_bank mp0_2; - struct s5p_gpio_bank mp0_3; - struct s5p_gpio_bank mp0_4; - struct s5p_gpio_bank mp0_5; - struct s5p_gpio_bank mp0_6; - struct s5p_gpio_bank mp0_7; - struct s5p_gpio_bank mp1_0; - struct s5p_gpio_bank mp1_1; - struct s5p_gpio_bank mp1_2; - struct s5p_gpio_bank mp1_3; - struct s5p_gpio_bank mp1_4; - struct s5p_gpio_bank mp1_5; - struct s5p_gpio_bank mp1_6; - struct s5p_gpio_bank mp1_7; - struct s5p_gpio_bank mp1_8; - struct s5p_gpio_bank mp2_0; - struct s5p_gpio_bank mp2_1; - struct s5p_gpio_bank mp2_2; - struct s5p_gpio_bank mp2_3; - struct s5p_gpio_bank mp2_4; - struct s5p_gpio_bank mp2_5; - struct s5p_gpio_bank mp2_6; - struct s5p_gpio_bank mp2_7; - struct s5p_gpio_bank mp2_8; - struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; -}; - -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 - -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) - -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) - -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) - -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) - -#define S5PC100_SET_BANK(bank) \ - (((unsigned)&(((struct s5pc100_gpio *) \ - S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define S5PC110_SET_BANK(bank) \ - ((((unsigned)&(((struct s5pc110_gpio *) \ - S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define s5pc100_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC100_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define s5pc110_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC110_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) - -static inline unsigned int s5p_gpio_base(int nr) -{ - return samsung_get_base_gpio(); -} -#endif - -/* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) - -/* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 - -/* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/mmc.h deleted file mode 100644 index dd473c8ec..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MMC_H_ -#define __ASM_ARCH_MMC_H_ - -#define S5P_MMC_DEV_OFFSET 0x100000 - -#define SDHCI_CONTROL2 0x80 -#define SDHCI_CONTROL3 0x84 -#define SDHCI_CONTROL4 0x8C - -#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) -#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) -#define SDHCI_CTRL2_CDINVRXD3 (1 << 29) -#define SDHCI_CTRL2_SLCARDOUT (1 << 28) - -#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) -#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) -#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) - -#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) -#define SDHCI_CTRL2_LVLDAT_SHIFT (16) -#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) - -#define SDHCI_CTRL2_ENFBCLKTX (1 << 15) -#define SDHCI_CTRL2_ENFBCLKRX (1 << 14) -#define SDHCI_CTRL2_SDCDSEL (1 << 13) -#define SDHCI_CTRL2_SDSIGPC (1 << 12) -#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) - -#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9) -#define SDHCI_CTRL2_DFCNT_SHIFT (9) - -#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) -#define SDHCI_CTRL2_RWAITMODE (1 << 7) -#define SDHCI_CTRL2_DISBUFRD (1 << 6) -#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4) -#define SDHCI_CTRL2_SELBASECLK_SHIFT (4) -#define SDHCI_CTRL2_PWRSYNC (1 << 3) -#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) -#define SDHCI_CTRL2_HWINITFIN (1 << 0) - -#define SDHCI_CTRL3_FCSEL3 (1 << 31) -#define SDHCI_CTRL3_FCSEL2 (1 << 23) -#define SDHCI_CTRL3_FCSEL1 (1 << 15) -#define SDHCI_CTRL3_FCSEL0 (1 << 7) - -#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) -#define SDHCI_CTRL4_DRIVE_SHIFT (16) - -int s5p_sdhci_init(u32 regbase, int index, int bus_width); - -static inline int s5p_mmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + - (S5P_MMC_DEV_OFFSET * index); - - return s5p_sdhci_init(base, index, bus_width); -} -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/power.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/power.h deleted file mode 100644 index 8400cda1e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/power.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_POWER_H_ -#define __ASM_ARM_ARCH_POWER_H_ - -/* - * Power control - */ -#define S5PC100_OTHERS 0xE0108200 -#define S5PC100_RST_STAT 0xE0108300 -#define S5PC100_SLEEP_WAKEUP (1 << 3) -#define S5PC100_WAKEUP_STAT 0xE0108304 -#define S5PC100_INFORM0 0xE0108400 - -#define S5PC110_RST_STAT 0xE010A000 -#define S5PC110_SLEEP_WAKEUP (1 << 3) -#define S5PC110_WAKEUP_STAT 0xE010C200 -#define S5PC110_OTHERS 0xE010E000 -#define S5PC110_USB_PHY_CON 0xE010E80C -#define S5PC110_INFORM0 0xE010F000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/pwm.h deleted file mode 100644 index 7a33ed895..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_PWM_H_ -#define __ASM_ARM_ARCH_PWM_H_ - -#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ -#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ - -/* Divider MUX */ -#define MUX_DIV_1 0 /* 1/1 period */ -#define MUX_DIV_2 1 /* 1/2 period */ -#define MUX_DIV_4 2 /* 1/4 period */ -#define MUX_DIV_8 3 /* 1/8 period */ -#define MUX_DIV_16 4 /* 1/16 period */ - -#define MUX_DIV_SHIFT(x) (x * 4) - -#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) - -#define TCON_START(x) (1 << TCON_OFFSET(x)) -#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) -#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) -#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) -#define TCON4_AUTO_RELOAD (1 << 22) - -#ifndef __ASSEMBLY__ -struct s5p_timer { - unsigned int tcfg0; - unsigned int tcfg1; - unsigned int tcon; - unsigned int tcntb0; - unsigned int tcmpb0; - unsigned int tcnto0; - unsigned int tcntb1; - unsigned int tcmpb1; - unsigned int tcnto1; - unsigned int tcntb2; - unsigned int tcmpb2; - unsigned int tcnto2; - unsigned int tcntb3; - unsigned int res1; - unsigned int tcnto3; - unsigned int tcntb4; - unsigned int tcnto4; - unsigned int tintcstat; -}; -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sromc.h deleted file mode 100644 index df1bf51bf..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sromc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2010 Samsung Electronics - * Naveen Krishna Ch <ch.naveen@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Note: This file contains the register description for Memory subsystem - * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. - * - * Only SROMC is defined as of now - */ - -#ifndef __ASM_ARCH_SROMC_H_ -#define __ASM_ARCH_SROMC_H_ - -#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) -#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ - /* 1-> Byte base address*/ -#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) -#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) - -#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ -#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ -#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ -#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ -#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ -#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ -#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ - -#ifndef __ASSEMBLY__ -struct s5p_sromc { - unsigned int bw; - unsigned int bc[6]; -}; -#endif /* __ASSEMBLY__ */ - -/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); - -#endif /* __ASM_ARCH_SMC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h deleted file mode 100644 index 647d6c438..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electrnoics - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_device_type(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/uart.h deleted file mode 100644 index 26db09884..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_UART_H_ -#define __ASM_ARCH_UART_H_ - -#ifndef __ASSEMBLY__ -/* baudrate rest value */ -union br_rest { - unsigned short slot; /* udivslot */ - unsigned char value; /* ufracval */ -}; - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - union br_rest rest; - unsigned char res3[0x3d0]; -}; - -static inline int s5p_uart_divslot(void) -{ - return 1; -} - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/watchdog.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/watchdog.h deleted file mode 100644 index 2f9746c2f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/watchdog.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim <riverful.kim@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_ARCH_WATCHDOG_H_ -#define __ASM_ARM_ARCH_WATCHDOG_H_ - -#define WTCON_RESET_OFFSET 0 -#define WTCON_INTEN_OFFSET 2 -#define WTCON_CLKSEL_OFFSET 3 -#define WTCON_EN_OFFSET 5 -#define WTCON_PRE_OFFSET 8 - -#define WTCON_CLK_16 0x0 -#define WTCON_CLK_32 0x1 -#define WTCON_CLK_64 0x2 -#define WTCON_CLK_128 0x3 - -#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) -#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) -#define WTCON_EN (0x1 << WTCON_EN_OFFSET) -#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) -#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) - -#ifndef __ASSEMBLY__ -struct s5p_watchdog { - unsigned int wtcon; - unsigned int wtdat; - unsigned int wtcnt; - unsigned int wtclrint; -}; - -/* functions */ -void wdt_stop(void); -void wdt_start(unsigned int timeout); -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h deleted file mode 100644 index 104a21c2e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FILE bitfield.h - * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) - * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. - */ - - -#ifndef __BITFIELD_H -#define __BITFIELD_H - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) -#else -#define UData(Data) (Data) -#endif - - -/* - * MACRO: Fld - * - * Purpose - * The macro "Fld" encodes a bit field, given its size and its shift value - * with respect to bit 0. - * - * Note - * A more intuitive way to encode bit fields would have been to use their - * mask. However, extracting size and shift value information from a bit - * field's mask is cumbersome and might break the assembler (255-character - * line-size limit). - * - * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. - * - * Output - * Fld Encoded bit field. - */ - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - - -/* - * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit - * - * Purpose - * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return - * the size, shift value, mask, aligned mask, and first bit of a - * bit field. - * - * Input - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. - */ - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - - -/* - * MACRO: FInsrt - * - * Purpose - * The macro "FInsrt" inserts a value into a bit field by shifting the - * former appropriately. - * - * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FInsrt Bit-field value positioned appropriately. - */ - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - - -/* - * MACRO: FExtr - * - * Purpose - * The macro "FExtr" extracts the value of a bit field by masking and - * shifting it appropriately. - * - * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). - * - * Output - * FExtr Bit-field value. - */ - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - - -#endif /* __BITFIELD_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h deleted file mode 100644 index 966add3e9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CLOCK_MANAGER_H_ -#define _CLOCK_MANAGER_H_ - -typedef struct { - /* main group */ - uint32_t main_vco_base; - uint32_t mpuclk; - uint32_t mainclk; - uint32_t dbgatclk; - uint32_t mainqspiclk; - uint32_t mainnandsdmmcclk; - uint32_t cfg2fuser0clk; - uint32_t maindiv; - uint32_t dbgdiv; - uint32_t tracediv; - uint32_t l4src; - - /* peripheral group */ - uint32_t peri_vco_base; - uint32_t emac0clk; - uint32_t emac1clk; - uint32_t perqspiclk; - uint32_t pernandsdmmcclk; - uint32_t perbaseclk; - uint32_t s2fuser1clk; - uint32_t perdiv; - uint32_t gpiodiv; - uint32_t persrc; - - /* sdram pll group */ - uint32_t sdram_vco_base; - uint32_t ddrdqsclk; - uint32_t ddr2xdqsclk; - uint32_t ddrdqclk; - uint32_t s2fuser2clk; -} cm_config_t; - -extern void cm_basic_init(const cm_config_t *cfg); - -struct socfpga_clock_manager { - u32 ctrl; - u32 bypass; - u32 inter; - u32 intren; - u32 dbctrl; - u32 stat; - u32 _pad_0x18_0x3f[10]; - u32 mainpllgrp; - u32 perpllgrp; - u32 sdrpllgrp; - u32 _pad_0xe0_0x200[72]; - - u32 main_pll_vco; - u32 main_pll_misc; - u32 main_pll_mpuclk; - u32 main_pll_mainclk; - u32 main_pll_dbgatclk; - u32 main_pll_mainqspiclk; - u32 main_pll_mainnandsdmmcclk; - u32 main_pll_cfgs2fuser0clk; - u32 main_pll_en; - u32 main_pll_maindiv; - u32 main_pll_dbgdiv; - u32 main_pll_tracediv; - u32 main_pll_l4src; - u32 main_pll_stat; - u32 main_pll__pad_0x38_0x40[2]; - - u32 per_pll_vco; - u32 per_pll_misc; - u32 per_pll_emac0clk; - u32 per_pll_emac1clk; - u32 per_pll_perqspiclk; - u32 per_pll_pernandsdmmcclk; - u32 per_pll_perbaseclk; - u32 per_pll_s2fuser1clk; - u32 per_pll_en; - u32 per_pll_div; - u32 per_pll_gpiodiv; - u32 per_pll_src; - u32 per_pll_stat; - u32 per_pll__pad_0x34_0x40[3]; - - u32 sdr_pll_vco; - u32 sdr_pll_ctrl; - u32 sdr_pll_ddrdqsclk; - u32 sdr_pll_ddr2xdqsclk; - u32 sdr_pll_ddrdqclk; - u32 sdr_pll_s2fuser2clk; - u32 sdr_pll_en; - u32 sdr_pll_stat; -}; - -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 -#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 -#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 -#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) -#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) -#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \ - (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \ - (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) -#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) -#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) -#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 -#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) -#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) -#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) -#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff - -#define MAIN_VCO_BASE \ - (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ - CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)) - -#define PERI_VCO_BASE \ - (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \ - CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \ - CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)) - -#define SDR_VCO_BASE \ - (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \ - CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \ - CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)) - -#endif /* _CLOCK_MANAGER_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/dwmmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/dwmmc.h deleted file mode 100644 index 945eb646c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/dwmmc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_DWMMC_H_ -#define _SOCFPGA_DWMMC_H_ - -extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); - -#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h deleted file mode 100644 index 120f20e03..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FREEZE_CONTROLLER_H_ -#define _FREEZE_CONTROLLER_H_ - -struct socfpga_freeze_controller { - u32 vioctrl; - u32 padding[3]; - u32 hioctrl; - u32 src; - u32 hwctrl; -}; - -#define FREEZE_CHANNEL_NUM (4) - -typedef enum { - FREEZE_CTRL_FROZEN = 0, - FREEZE_CTRL_THAWED = 1 -} FREEZE_CTRL_CHAN_STATE; - -#define SYSMGR_FRZCTRL_ADDRESS 0x40 -#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 -#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 -#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 -#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 -#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 -#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 -#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 -#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 -#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 -#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 -#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 -#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 -#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 -#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 -#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 -#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 -#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 -#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 -#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 -#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 - -void sys_mgr_frzctrl_freeze_req(void); -void sys_mgr_frzctrl_thaw_req(void); - -#endif /* _FREEZE_CONTROLLER_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/reset_manager.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/reset_manager.h deleted file mode 100644 index 3e9547682..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _RESET_MANAGER_H_ -#define _RESET_MANAGER_H_ - -void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void); - -struct socfpga_reset_manager { - u32 status; - u32 ctrl; - u32 counts; - u32 padding1; - u32 mpu_mod_reset; - u32 per_mod_reset; - u32 per2_mod_reset; - u32 brg_mod_reset; -}; - -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 -#else -#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 -#endif - -#endif /* _RESET_MANAGER_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h deleted file mode 100644 index f564046bc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_BASE_ADDRS_H_ -#define _SOCFPGA_BASE_ADDRS_H_ - -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 - -#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/spl.h deleted file mode 100644 index 7e310d5a0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/spl.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2012 Pavel Machek <pavel@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_SPL_H_ -#define _SOCFPGA_SPL_H_ - -/* Symbols from linker script */ -extern char __malloc_start, __malloc_end, __stack_start; - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/system_manager.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/system_manager.h deleted file mode 100644 index 838d21053..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/system_manager.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYSTEM_MANAGER_H_ -#define _SYSTEM_MANAGER_H_ - -#ifndef __ASSEMBLY__ - -void sysmgr_pinmux_init(void); - -/* declaration for handoff table type */ -extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; - -#endif - - -#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) - -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) - -struct socfpga_system_manager { - u32 siliconid1; - u32 siliconid2; - u32 _pad_0x8_0xf[2]; - u32 wddbg; - u32 bootinfo; - u32 hpsinfo; - u32 parityinj; - u32 fpgaintfgrp_gbl; - u32 fpgaintfgrp_indiv; - u32 fpgaintfgrp_module; - u32 _pad_0x2c_0x2f; - u32 scanmgrgrp_ctrl; - u32 _pad_0x34_0x3f[3]; - u32 frzctrl_vioctrl; - u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; - u32 frzctrl_src; - u32 frzctrl_hwctrl; - u32 _pad_0x5c_0x5f; - u32 emacgrp_ctrl; - u32 emacgrp_l3master; - u32 _pad_0x68_0x6f[2]; - u32 dmagrp_ctrl; - u32 dmagrp_persecurity; - u32 _pad_0x78_0x7f[2]; - u32 iswgrp_handoff[8]; - u32 _pad_0xa0_0xbf[8]; - u32 romcodegrp_ctrl; - u32 romcodegrp_cpu1startaddr; - u32 romcodegrp_initswstate; - u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; - u32 __pad_0xd4_0xdf[3]; - u32 romcodegrp_warmramgrp_enable; - u32 romcodegrp_warmramgrp_datastart; - u32 romcodegrp_warmramgrp_length; - u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; - u32 __pad_0xf4_0xff[3]; - u32 romhwgrp_ctrl; - u32 _pad_0x104_0x107; - u32 sdmmcgrp_ctrl; - u32 sdmmcgrp_l3master; - u32 nandgrp_bootstrap; - u32 nandgrp_l3master; - u32 usbgrp_l3master; - u32 _pad_0x11c_0x13f[9]; - u32 eccgrp_l2; - u32 eccgrp_ocram; - u32 eccgrp_usb0; - u32 eccgrp_usb1; - u32 eccgrp_emac0; - u32 eccgrp_emac1; - u32 eccgrp_dma; - u32 eccgrp_can0; - u32 eccgrp_can1; - u32 eccgrp_nand; - u32 eccgrp_qspi; - u32 eccgrp_sdmmc; -}; - -#endif /* _SYSTEM_MANAGER_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/timer.h deleted file mode 100644 index ee6969bac..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/timer.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_TIMER_H_ -#define _SOCFPGA_TIMER_H_ - -struct socfpga_timer { - u32 load_val; - u32 curr_val; - u32 ctrl; - u32 eoi; - u32 int_stat; -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h deleted file mode 100644 index a07d0d5f9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * (C) Copyright 2010 - * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return 83000000; -} diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h deleted file mode 100644 index 54e6b5bfd..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2012 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_SPEAR_GPIO_H -#define __ASM_ARCH_SPEAR_GPIO_H - -enum gpio_direction { - GPIO_DIRECTION_IN, - GPIO_DIRECTION_OUT, -}; - -struct gpio_regs { - u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ - u32 gpiodir; /* 0x400 */ -}; - -#define SPEAR_GPIO_COUNT 8 -#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) - -#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h deleted file mode 100644 index c6da405cc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#define CONFIG_SYS_USBD_BASE 0xE1100000 -#define CONFIG_SYS_PLUG_BASE 0xE1200000 -#define CONFIG_SYS_FIFO_BASE 0xE1000800 -#define CONFIG_SYS_SMI_BASE 0xFC000000 -#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 -#define CONFIG_SPEAR_TIMERBASE 0xFC800000 -#define CONFIG_SPEAR_MISCBASE 0xFCA80000 -#define CONFIG_SPEAR_ETHBASE 0xE0800000 -#define CONFIG_SPEAR_MPMCBASE 0xFC600000 -#define CONFIG_SSP1_BASE 0xD0100000 -#define CONFIG_SSP2_BASE 0xD0180000 -#define CONFIG_SSP3_BASE 0xD8180000 -#define CONFIG_GPIO_BASE 0xD8100000 - -#define CONFIG_SYS_NAND_CLE (1 << 16) -#define CONFIG_SYS_NAND_ALE (1 << 17) - -#if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_FSMC_BASE 0xD1800000 -#define CONFIG_FSMC_NAND_BASE 0xD2000000 - -#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 -#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 -#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB -#define CONFIG_SPEAR_ONLYSNORBOOT 0xA -#define CONFIG_SPEAR_NORNANDBOOT 0xB -#define CONFIG_SPEAR_NORNAND8BOOT 0x8 -#define CONFIG_SPEAR_NORNAND16BOOT 0x9 -#define CONFIG_SPEAR_USBBOOT 0x8 - -#define CONFIG_SPEAR_MPMCREGS 100 - -#elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_FSMC_BASE 0x94000000 - -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_FSMC_BASE 0x44000000 - -#undef CONFIG_SYS_NAND_CLE -#undef CONFIG_SYS_NAND_ALE -#define CONFIG_SYS_NAND_CLE (1 << 17) -#define CONFIG_SYS_NAND_ALE (1 << 16) - -#define CONFIG_SPEAR_EMIBASE 0x4F000000 -#define CONFIG_SPEAR_RASBASE 0xB4000000 - -#define CONFIG_SYS_MACB0_BASE 0xB0000000 -#define CONFIG_SYS_MACB1_BASE 0xB0800000 -#define CONFIG_SYS_MACB2_BASE 0xB1000000 -#define CONFIG_SYS_MACB3_BASE 0xB1800000 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_FSMC_BASE 0x4C000000 - -#define CONFIG_SPEAR_EMIBASE 0x40000000 -#define CONFIG_SPEAR_RASBASE 0xB3000000 - -#define CONFIG_SYS_MACB0_BASE 0xAA000000 - -#endif -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h deleted file mode 100644 index 7e77a3033..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SPR_DEFS_H__ -#define __SPR_DEFS_H__ - -extern int spear_board_init(ulong); -extern void setfreq(unsigned int, unsigned int); -extern unsigned int setfreq_sz; - -void plat_ddr_init(void); -void soc_init(void); -void spear_late_init(void); -void plat_late_init(void); - -int snor_boot_selected(void); -int nand_boot_selected(void); -int pnor_boot_selected(void); -int usb_boot_selected(void); -int uart_boot_selected(void); -int tftp_boot_selected(void); -int i2c_boot_selected(void); -int spi_boot_selected(void); -int mmc_boot_selected(void); - -extern u32 mpmc_conf_vals[]; - -struct chip_data { - int cpufreq; - int dramfreq; - int dramtype; - uchar version[32]; -}; - -/* HW mac id in i2c memory definitions */ -#define MAGIC_OFF 0x0 -#define MAGIC_LEN 0x2 -#define MAGIC_BYTE0 0x55 -#define MAGIC_BYTE1 0xAA -#define MAC_OFF 0x2 -#define MAC_LEN 0x6 - -#define PNOR_WIDTH_8 0 -#define PNOR_WIDTH_16 1 -#define PNOR_WIDTH_32 2 -#define PNOR_WIDTH_NUM 3 -#define PNOR_WIDTH_SEARCH 0xff - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h deleted file mode 100644 index 3a6acb58c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 - * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SPEAR_EMI_H__ -#define __SPEAR_EMI_H__ - -#ifdef CONFIG_SPEAR_EMI - -struct emi_bank_regs { - u32 tap; - u32 tsdp; - u32 tdpw; - u32 tdpr; - u32 tdcs; - u32 control; -}; - -struct emi_regs { - struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS]; - u32 tout; - u32 ack; - u32 irq; -}; - -#define EMI_ACKMSK 0x40 - -/* control register definitions */ -#define EMI_CNTL_ENBBYTEW (1 << 2) -#define EMI_CNTL_ENBBYTER (1 << 3) -#define EMI_CNTL_ENBBYTERW (EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW) - -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h deleted file mode 100644 index 687e08017..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SPR_GPT_H -#define _SPR_GPT_H - -struct gpt_regs { - u8 reserved[0x80]; - u32 control; - u32 status; - u32 compare; - u32 count; - u32 capture_re; - u32 capture_fe; -}; - -/* - * TIMER_CONTROL register settings - */ - -#define GPT_PRESCALER_MASK 0x000F -#define GPT_PRESCALER_1 0x0000 -#define GPT_PRESCALER_2 0x0001 -#define GPT_PRESCALER_4 0x0002 -#define GPT_PRESCALER_8 0x0003 -#define GPT_PRESCALER_16 0x0004 -#define GPT_PRESCALER_32 0x0005 -#define GPT_PRESCALER_64 0x0006 -#define GPT_PRESCALER_128 0x0007 -#define GPT_PRESCALER_256 0x0008 - -#define GPT_MODE_SINGLE_SHOT 0x0010 -#define GPT_MODE_AUTO_RELOAD 0x0000 - -#define GPT_ENABLE 0x0020 - -#define GPT_CAPT_MODE_MASK 0x00C0 -#define GPT_CAPT_MODE_NONE 0x0000 -#define GPT_CAPT_MODE_RE 0x0040 -#define GPT_CAPT_MODE_FE 0x0080 -#define GPT_CAPT_MODE_BOTH 0x00C0 - -#define GPT_INT_MATCH 0x0100 -#define GPT_INT_FE 0x0200 -#define GPT_INT_RE 0x0400 - -/* - * TIMER_STATUS register settings - */ - -#define GPT_STS_MATCH 0x0001 -#define GPT_STS_FE 0x0002 -#define GPT_STS_RE 0x0004 - -/* - * TIMER_COMPARE register settings - */ - -#define GPT_FREE_RUNNING 0xFFFF - -/* Timer, HZ specific defines */ -#define CONFIG_SPEAR_HZ 1000 -#define CONFIG_SPEAR_HZ_CLOCK 8300000 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h deleted file mode 100644 index b55026ecd..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SPR_MISC_H -#define _SPR_MISC_H - -struct misc_regs { - u32 auto_cfg_reg; /* 0x0 */ - u32 armdbg_ctr_reg; /* 0x4 */ - u32 pll1_cntl; /* 0x8 */ - u32 pll1_frq; /* 0xc */ - u32 pll1_mod; /* 0x10 */ - u32 pll2_cntl; /* 0x14 */ - u32 pll2_frq; /* 0x18 */ - u32 pll2_mod; /* 0x1C */ - u32 pll_ctr_reg; /* 0x20 */ - u32 amba_clk_cfg; /* 0x24 */ - u32 periph_clk_cfg; /* 0x28 */ - u32 periph1_clken; /* 0x2C */ - u32 soc_core_id; /* 0x30 */ - u32 ras_clken; /* 0x34 */ - u32 periph1_rst; /* 0x38 */ - u32 periph2_rst; /* 0x3C */ - u32 ras_rst; /* 0x40 */ - u32 prsc1_clk_cfg; /* 0x44 */ - u32 prsc2_clk_cfg; /* 0x48 */ - u32 prsc3_clk_cfg; /* 0x4C */ - u32 amem_cfg_ctrl; /* 0x50 */ - u32 expi_clk_cfg; /* 0x54 */ - u32 reserved_1; /* 0x58 */ - u32 clcd_synth_clk; /* 0x5C */ - u32 irda_synth_clk; /* 0x60 */ - u32 uart_synth_clk; /* 0x64 */ - u32 gmac_synth_clk; /* 0x68 */ - u32 ras_synth1_clk; /* 0x6C */ - u32 ras_synth2_clk; /* 0x70 */ - u32 ras_synth3_clk; /* 0x74 */ - u32 ras_synth4_clk; /* 0x78 */ - u32 arb_icm_ml1; /* 0x7C */ - u32 arb_icm_ml2; /* 0x80 */ - u32 arb_icm_ml3; /* 0x84 */ - u32 arb_icm_ml4; /* 0x88 */ - u32 arb_icm_ml5; /* 0x8C */ - u32 arb_icm_ml6; /* 0x90 */ - u32 arb_icm_ml7; /* 0x94 */ - u32 arb_icm_ml8; /* 0x98 */ - u32 arb_icm_ml9; /* 0x9C */ - u32 dma_src_sel; /* 0xA0 */ - u32 uphy_ctr_reg; /* 0xA4 */ - u32 gmac_ctr_reg; /* 0xA8 */ - u32 port_bridge_ctrl; /* 0xAC */ - u32 reserved_2[4]; /* 0xB0--0xBC */ - u32 prc1_ilck_ctrl_reg; /* 0xC0 */ - u32 prc2_ilck_ctrl_reg; /* 0xC4 */ - u32 prc3_ilck_ctrl_reg; /* 0xC8 */ - u32 prc4_ilck_ctrl_reg; /* 0xCC */ - u32 prc1_intr_ctrl_reg; /* 0xD0 */ - u32 prc2_intr_ctrl_reg; /* 0xD4 */ - u32 prc3_intr_ctrl_reg; /* 0xD8 */ - u32 prc4_intr_ctrl_reg; /* 0xDC */ - u32 powerdown_cfg_reg; /* 0xE0 */ - u32 ddr_1v8_compensation; /* 0xE4 */ - u32 ddr_2v5_compensation; /* 0xE8 */ - u32 core_3v3_compensation; /* 0xEC */ - u32 ddr_pad; /* 0xF0 */ - u32 bist1_ctr_reg; /* 0xF4 */ - u32 bist2_ctr_reg; /* 0xF8 */ - u32 bist3_ctr_reg; /* 0xFC */ - u32 bist4_ctr_reg; /* 0x100 */ - u32 bist5_ctr_reg; /* 0x104 */ - u32 bist1_rslt_reg; /* 0x108 */ - u32 bist2_rslt_reg; /* 0x10C */ - u32 bist3_rslt_reg; /* 0x110 */ - u32 bist4_rslt_reg; /* 0x114 */ - u32 bist5_rslt_reg; /* 0x118 */ - u32 syst_error_reg; /* 0x11C */ - u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */ - u32 ras_gpp1_in; /* 0x8000 */ - u32 ras_gpp2_in; /* 0x8004 */ - u32 ras_gpp1_out; /* 0x8008 */ - u32 ras_gpp2_out; /* 0x800C */ -}; - -/* SYNTH_CLK value*/ -#define SYNTH23 0x00020003 - -/* PLLx_FRQ value */ -#if defined(CONFIG_SPEAR3XX) -#define FREQ_332 0xA600010C -#define FREQ_266 0x8500010C -#elif defined(CONFIG_SPEAR600) -#define FREQ_332 0xA600010F -#define FREQ_266 0x8500010F -#endif - -/* PLL_CTR_REG */ -#define MEM_CLK_SEL_MSK 0x70000000 -#define MEM_CLK_HCLK 0x00000000 -#define MEM_CLK_2HCLK 0x10000000 -#define MEM_CLK_PLL2 0x30000000 - -#define EXPI_CLK_CFG_LOW_COMPR 0x2000 -#define EXPI_CLK_CFG_CLK_EN 0x0400 -#define EXPI_CLK_CFG_RST 0x0200 -#define EXPI_CLK_SYNT_EN 0x0010 -#define EXPI_CLK_CFG_SEL_PLL2 0x0004 -#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 - -#define PLL2_CNTL_6UA 0x1c00 -#define PLL2_CNTL_SAMPLE 0x0008 -#define PLL2_CNTL_ENABLE 0x0004 -#define PLL2_CNTL_RESETN 0x0002 -#define PLL2_CNTL_LOCK 0x0001 - -/* AUTO_CFG_REG value */ -#define MISC_SOCCFGMSK 0x0000003F -#define MISC_SOCCFG30 0x0000000C -#define MISC_SOCCFG31 0x0000000D -#define MISC_NANDDIS 0x00020000 - -/* PERIPH_CLK_CFG value */ -#define MISC_GPT3SYNTH 0x00000400 -#define MISC_GPT4SYNTH 0x00000800 -#define CONFIG_SPEAR_UART48M 0 -#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4) - -/* PRSC_CLK_CFG value */ -/* - * Fout = Fin / (2^(N+1) * (M + 1)) - */ -#define MISC_PRSC_N_1 0x00001000 -#define MISC_PRSC_M_9 0x00000009 -#define MISC_PRSC_N_4 0x00004000 -#define MISC_PRSC_M_399 0x0000018F -#define MISC_PRSC_N_6 0x00006000 -#define MISC_PRSC_M_2593 0x00000A21 -#define MISC_PRSC_M_124 0x0000007C -#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9) - -/* PERIPH1_CLKEN, PERIPH1_RST value */ -#define MISC_USBDENB 0x01000000 -#define MISC_ETHENB 0x00800000 -#define MISC_SMIENB 0x00200000 -#define MISC_GPT3ENB 0x00010000 -#define MISC_GPIO4ENB 0x00002000 -#define MISC_GPT2ENB 0x00000800 -#define MISC_FSMCENB 0x00000200 -#define MISC_I2CENB 0x00000080 -#define MISC_SSP2ENB 0x00000070 -#define MISC_UART0ENB 0x00000008 - -/* PERIPH_CLK_CFG */ -#define XTALTIMEEN 0x00000001 -#define PLLTIMEEN 0x00000002 -#define CLCDCLK_SYNTH 0x00000000 -#define CLCDCLK_48MHZ 0x00000004 -#define CLCDCLK_EXT 0x00000008 -#define UARTCLK_MASK (0x1 << 4) -#define UARTCLK_48MHZ 0x00000000 -#define UARTCLK_SYNTH 0x00000010 -#define IRDACLK_48MHZ 0x00000000 -#define IRDACLK_SYNTH 0x00000020 -#define IRDACLK_EXT 0x00000040 -#define RTC_DISABLE 0x00000080 -#define GPT1CLK_48MHZ 0x00000000 -#define GPT1CLK_SYNTH 0x00000100 -#define GPT2CLK_48MHZ 0x00000000 -#define GPT2CLK_SYNTH 0x00000200 -#define GPT3CLK_48MHZ 0x00000000 -#define GPT3CLK_SYNTH 0x00000400 -#define GPT4CLK_48MHZ 0x00000000 -#define GPT4CLK_SYNTH 0x00000800 -#define GPT5CLK_48MHZ 0x00000000 -#define GPT5CLK_SYNTH 0x00001000 -#define GPT1_FREEZE 0x00002000 -#define GPT2_FREEZE 0x00004000 -#define GPT3_FREEZE 0x00008000 -#define GPT4_FREEZE 0x00010000 -#define GPT5_FREEZE 0x00020000 - -/* PERIPH1_CLKEN bits */ -#define PERIPH_ARM1_WE 0x00000001 -#define PERIPH_ARM1 0x00000002 -#define PERIPH_ARM2 0x00000004 -#define PERIPH_UART1 0x00000008 -#define PERIPH_UART2 0x00000010 -#define PERIPH_SSP1 0x00000020 -#define PERIPH_SSP2 0x00000040 -#define PERIPH_I2C 0x00000080 -#define PERIPH_JPEG 0x00000100 -#define PERIPH_FSMC 0x00000200 -#define PERIPH_FIRDA 0x00000400 -#define PERIPH_GPT4 0x00000800 -#define PERIPH_GPT5 0x00001000 -#define PERIPH_GPIO4 0x00002000 -#define PERIPH_SSP3 0x00004000 -#define PERIPH_ADC 0x00008000 -#define PERIPH_GPT3 0x00010000 -#define PERIPH_RTC 0x00020000 -#define PERIPH_GPIO3 0x00040000 -#define PERIPH_DMA 0x00080000 -#define PERIPH_ROM 0x00100000 -#define PERIPH_SMI 0x00200000 -#define PERIPH_CLCD 0x00400000 -#define PERIPH_GMAC 0x00800000 -#define PERIPH_USBD 0x01000000 -#define PERIPH_USBH1 0x02000000 -#define PERIPH_USBH2 0x04000000 -#define PERIPH_MPMC 0x08000000 -#define PERIPH_RAMW 0x10000000 -#define PERIPH_MPMC_EN 0x20000000 -#define PERIPH_MPMC_WE 0x40000000 -#define PERIPH_MPMCMSK 0x60000000 - -#define PERIPH_CLK_ALL 0x0FFFFFF8 -#define PERIPH_RST_ALL 0x00000004 - -/* DDR_PAD values */ -#define DDR_PAD_CNF_MSK 0x0000ffff -#define DDR_PAD_SW_CONF 0x00060000 -#define DDR_PAD_SSTL_SEL 0x00000001 -#define DDR_PAD_DRAM_TYPE 0x00008000 - -/* DDR_COMP values */ -#define DDR_COMP_ACCURATE 0x00000010 - -/* SoC revision stuff */ -#define SOC_PRI_SHFT 16 -#define SOC_SEC_SHFT 8 - -/* Revision definitions */ -#define SOC_SPEAR_NA 0 - -/* - * The definitons have started from - * 101 for SPEAr6xx - * 201 for SPEAr3xx - * 301 for SPEAr13xx - */ -#define SOC_SPEAR600_AA 101 -#define SOC_SPEAR600_AB 102 -#define SOC_SPEAR600_BA 103 -#define SOC_SPEAR600_BB 104 -#define SOC_SPEAR600_BC 105 -#define SOC_SPEAR600_BD 106 - -#define SOC_SPEAR300 201 -#define SOC_SPEAR310 202 -#define SOC_SPEAR320 203 - -extern int get_socrev(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h deleted file mode 100644 index b13db573f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SPR_SSP_H -#define _SPR_SSP_H - -struct ssp_regs { - u32 sspcr0; - u32 sspcr1; - u32 sspdr; - u32 sspsr; - u32 sspcpsr; - u32 sspimsc; - u32 sspicr; - u32 sspdmacr; -}; - -#define SSPCR0_FRF_MOT_SPI 0x0000 -#define SSPCR0_DSS_16BITS 0x000f - -#define SSPCR1_SSE 0x0002 - -#define SSPSR_TNF 0x2 -#define SSPSR_TFE 0x1 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h deleted file mode 100644 index 95bd443da..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2009 - * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SYSCTRL_H -#define __SYSCTRL_H - -struct syscntl_regs { - u32 scctrl; - u32 scsysstat; - u32 scimctrl; - u32 scimsysstat; - u32 scxtalctrl; - u32 scpllctrl; - u32 scpllfctrl; - u32 scperctrl0; - u32 scperctrl1; - u32 scperen; - u32 scperdis; - const u32 scperclken; - const u32 scperstat; -}; - -#define MODE_SHIFT 0x00000003 - -#define NORMAL 0x00000004 -#define SLOW 0x00000002 -#define DOZE 0x00000001 -#define SLEEP 0x00000000 - -#define PLL_TIM 0x01FFFFFF - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h deleted file mode 100644 index bc5851c1d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2010-2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <asm/types.h> - -/* Stabilization delays, in usec */ -#define PLL_STABILIZATION_DELAY (300) -#define IO_STABILIZATION_DELAY (1000) - -#define PLLX_ENABLED (1 << 30) -#define CCLK_BURST_POLICY 0x20008888 -#define SUPER_CCLK_DIVIDER 0x80000000 - -/* Calculate clock fractional divider value from ref and target frequencies */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) - -/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - -#define CORESIGHT_UNLOCK 0xC5ACCE55; - -/* AP base physical address of internal SRAM */ -#define NV_PA_BASE_SRAM 0x40000000 - -#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) -#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) -#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) - -#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) -#define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) - -/* This is the main entry into U-Boot, used by the Cortex-A9 */ -extern void _start(void); - -/** - * Works out the SOC/SKU type used for clocks settings - * - * @return SOC type - see TEGRA_SOC... - */ -int tegra_get_chip_sku(void); - -/** - * Returns the pure SOC (chip ID) from the HIDREV register - * - * @return SOC ID - see CHIPID_TEGRAxx... - */ -int tegra_get_chip(void); - -/** - * Returns the SKU ID from the sku_info register - * - * @return SKU ID - see SKU_ID_Txx... - */ -int tegra_get_sku_info(void); - -/* Do any chip-specific cache config */ -void config_cache(void); diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h deleted file mode 100644 index a5bc092ff..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ - -/* APB_MISC_PP registers */ -struct apb_misc_pp_ctlr { - u32 reserved0[2]; - u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ - u32 reserved1[6]; /* 0x0c .. 0x20 */ - u32 cfg_ctl; /* 0x24 */ -}; - -/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ -#define RAM_CODE_SHIFT 4 -#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h deleted file mode 100644 index ff773646c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_BOARD_H_ -#define _TEGRA_BOARD_H_ - -/* Set up pinmux to make UART usable */ -void gpio_early_init_uart(void); - -/* Set up early UART output */ -void board_init_uart_f(void); - -/* Set up any early GPIOs the board might need for proper operation */ -void gpio_early_init(void); /* overrideable GPIO config */ - -/* - * Hooks to allow boards to set up the pinmux for a specific function. - * Has to be implemented in the board files as we don't yet support pinmux - * setup from FTD. If a board file does not implement one of those functions - * an empty stub function will be called. - */ - -void pinmux_init(void); /* overrideable general pinmux setup */ -void pin_mux_usb(void); /* overrideable USB pinmux setup */ -void pin_mux_spi(void); /* overrideable SPI pinmux setup */ -void pin_mux_nand(void); /* overrideable NAND pinmux setup */ -void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h deleted file mode 100644 index 7d28e16f1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2010-2014 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_CLK_RST_H_ -#define _TEGRA_CLK_RST_H_ - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll { - uint pll_base; /* the control register */ - /* pll_out[0] is output A control, pll_out[1] is output B control */ - uint pll_out[2]; - uint pll_misc; /* other misc things */ -}; - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll_simple { - uint pll_base; /* the control register */ - uint pll_misc; /* other misc things */ -}; - -struct clk_pllm { - uint pllm_base; /* the control register */ - uint pllm_out; /* output control */ - uint pllm_misc1; /* misc1 */ - uint pllm_misc2; /* misc2 */ -}; - -/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ -struct clk_set_clr { - uint set; - uint clr; -}; - -/* - * Most PLLs use the clk_pll structure, but some have a simpler two-member - * structure for which we use clk_pll_simple. The reason for this non- - * othogonal setup is not stated. - */ -enum { - TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ - TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ - TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ - TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ - TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ - TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ -}; - -/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct clk_rst_ctlr { - uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ - uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ - uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ - uint crc_reserved0; /* reserved_0, 0x1C */ - uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ - uint crc_reserved1; /* reserved_1, 0x3C */ - uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - - struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - - /* PLLs from 0xe0 to 0xf4 */ - struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - - uint crc_reserved10; /* _reserved_10, 0xF8 */ - uint crc_reserved11; /* _reserved_11, 0xFC */ - - uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - - uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */ - - uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ - - uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ - struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; - - uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ - - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ - struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; - - uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */ - - uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - - /* Additional (T30) registers */ - uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ - - uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ - uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ - uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ - struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - /* Additional (T114) registers */ - uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ - uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ - uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ - uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */ - uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - uint crc_reserved40[1]; /* _reserved_40, 0x474 */ - uint crc_intstatus; /* __INTSTATUS_0, 0x478 */ - uint crc_intmask; /* __INTMASK_0, 0x47C */ - uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ - uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - - uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ - uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ - uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ - uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ - uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - uint crc_reserved51[1]; /* _reserved_51, 0x538 */ - uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ - uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ - uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - uint crc_reserved52[1]; /* _reserved_52, 0x554 */ - uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - - /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */ - uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ - uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ -}; - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ -#define CPU3_CLK_STP_SHIFT 11 -#define CPU2_CLK_STP_SHIFT 10 -#define CPU1_CLK_STP_SHIFT 9 -#define CPU0_CLK_STP_SHIFT 8 -#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ -#define PLL_BYPASS_SHIFT 31 -#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) - -#define PLL_ENABLE_SHIFT 30 -#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) - -#define PLL_BASE_OVRRIDE_MASK (1U << 28) - -#define PLL_LOCK_SHIFT 27 -#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) - -#define PLL_DIVP_SHIFT 20 -#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) - -#define PLL_DIVN_SHIFT 8 -#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) - -#define PLL_DIVM_SHIFT 0 -#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ -#define PLL_OUT_RSTN (1 << 0) -#define PLL_OUT_CLKEN (1 << 1) -#define PLL_OUT_OVRRIDE (1 << 2) - -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ -#define PLL_DCCON_SHIFT 20 -#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) - -#define PLL_LOCK_ENABLE_SHIFT 18 -#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT) - -#define PLL_CPCON_SHIFT 8 -#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) - -#define PLL_LFCON_SHIFT 4 -#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) - -#define PLLU_VCO_FREQ_SHIFT 20 -#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) - -#define PLLP_OUT1_OVR (1 << 2) -#define PLLP_OUT2_OVR (1 << 18) -#define PLLP_OUT3_OVR (1 << 2) -#define PLLP_OUT4_OVR (1 << 18) -#define PLLP_OUT1_RATIO 8 -#define PLLP_OUT2_RATIO 24 -#define PLLP_OUT3_RATIO 8 -#define PLLP_OUT4_RATIO 24 - -enum { - IN_408_OUT_204_DIVISOR = 2, - IN_408_OUT_102_DIVISOR = 6, - IN_408_OUT_48_DIVISOR = 15, - IN_408_OUT_9_6_DIVISOR = 83, -}; - -#define PLLP_OUT1_RSTN_DIS (1 << 0) -#define PLLP_OUT1_RSTN_EN (0 << 0) -#define PLLP_OUT1_CLKEN (1 << 1) -#define PLLP_OUT2_RSTN_DIS (1 << 16) -#define PLLP_OUT2_RSTN_EN (0 << 16) -#define PLLP_OUT2_CLKEN (1 << 17) - -#define PLLP_OUT3_RSTN_DIS (1 << 0) -#define PLLP_OUT3_RSTN_EN (0 << 0) -#define PLLP_OUT3_CLKEN (1 << 1) -#define PLLP_OUT4_RSTN_DIS (1 << 16) -#define PLLP_OUT4_RSTN_EN (0 << 16) -#define PLLP_OUT4_CLKEN (1 << 17) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ -#define PLLU_POWERDOWN (1 << 16) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLL_ACTIVE_POWERDOWN (1 << 12) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ -#define OSC_XOE_SHIFT 0 -#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) -#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) -#define OSC_XOBP_SHIFT 1 -#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) -#define OSC_XOFS_SHIFT 4 -#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) -#define OSC_DRIVE_STRENGTH 7 - -/* - * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits - * but can be 16. We could use knowledge we have to restrict the mask in - * the 8-bit cases (the divider_bits value returned by - * get_periph_clock_source()) but it does not seem worth it since the code - * already checks the ranges of values it is writing, in clk_get_divider(). - */ -#define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) - -#define OUT_CLK_SOURCE_31_30_SHIFT 30 -#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT) - -#define OUT_CLK_SOURCE_31_29_SHIFT 29 -#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) - -/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ -#define OUT_CLK_SOURCE_31_28_SHIFT 28 -#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT) - -/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ -#define SCLK_SYS_STATE_SHIFT 28U -#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) -enum { - SCLK_SYS_STATE_STDBY, - SCLK_SYS_STATE_IDLE, - SCLK_SYS_STATE_RUN, - SCLK_SYS_STATE_IRQ = 4U, - SCLK_SYS_STATE_FIQ = 8U, -}; -#define SCLK_COP_FIQ_MASK (1 << 27) -#define SCLK_CPU_FIQ_MASK (1 << 26) -#define SCLK_COP_IRQ_MASK (1 << 25) -#define SCLK_CPU_IRQ_MASK (1 << 24) - -#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 -#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8 -#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4 -#define SCLK_SWAKEUP_RUN_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0 - -#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -enum { - SCLK_SOURCE_CLKM, - SCLK_SOURCE_PLLC_OUT1, - SCLK_SOURCE_PLLP_OUT4, - SCLK_SOURCE_PLLP_OUT3, - SCLK_SOURCE_PLLP_OUT2, - SCLK_SOURCE_CLKD, - SCLK_SOURCE_CLKS, - SCLK_SOURCE_PLLM_OUT1, -}; -#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) -#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) -#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) -#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) - -/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */ -#define SUPER_SCLK_ENB_SHIFT 31U -#define SUPER_SCLK_ENB_MASK (1U << 31) -#define SUPER_SCLK_DIVIDEND_SHIFT 8 -#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT) -#define SUPER_SCLK_DIVISOR_SHIFT 0 -#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) - -/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ -#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 -#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) -#define CLK_SYS_RATE_AHB_RATE_SHIFT 4 -#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3 -#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) -#define CLK_SYS_RATE_APB_RATE_SHIFT 0 -#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) - -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_L2RESET (1 << 24) -#define CLR_NONCPURESET (1 << 29) -#define CLR_PRESETDBG (1 << 30) - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ -#define CLR_CPU0_CLK_STP (1 << 8) -#define CLR_CPU1_CLK_STP (1 << 9) -#define CLR_CPU2_CLK_STP (1 << 10) -#define CLR_CPU3_CLK_STP (1 << 11) - -/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ -#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) - -/* CRC_CLK_ENB_V_SET_0 0x440 */ -#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) -#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) -#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ -#define PLL_ACTIVE_POWERDOWN (1 << 12) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLLU_POWERDOWN (1 << 16) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) - -/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ -#define PLLX_IDDQ_SHIFT 3 -#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) - -#endif /* _TEGRA_CLK_RST_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h deleted file mode 100644 index 9d8114c4e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra clock control functions */ - -#ifndef _TEGRA_CLOCK_H_ -#define _TEGRA_CLOCK_H_ - -/* Set of oscillator frequencies supported in the internal API. */ -enum clock_osc_freq { - /* All in MHz, so 13_0 is 13.0MHz */ - CLOCK_OSC_FREQ_13_0, - CLOCK_OSC_FREQ_19_2, - CLOCK_OSC_FREQ_12_0, - CLOCK_OSC_FREQ_26_0, - - CLOCK_OSC_FREQ_COUNT, -}; - -/* - * Note that no Tegra clock register actually uses all of bits 31:28 as - * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in - * those cases, nothing is stored in the bits about the mux field, so it's - * safe to pretend that the mux field extends all the way to the end of the - * register. As such, the U-Boot clock driver is currently a bit lazy, and - * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps - * them all together and pretends they're all 31:28. - */ -enum { - MASK_BITS_31_30, - MASK_BITS_31_29, - MASK_BITS_31_28, -}; - -#include <asm/arch/clock-tables.h> -/* PLL stabilization delay in usec */ -#define CLOCK_PLL_STABLE_DELAY_US 300 - -/* return the current oscillator clock frequency */ -enum clock_osc_freq clock_get_osc_freq(void); - -/** - * Start PLL using the provided configuration parameters. - * - * @param id clock id - * @param divm input divider - * @param divn feedback divider - * @param divp post divider 2^n - * @param cpcon charge pump setup control - * @param lfcon loop filter setup control - * - * @returns monotonic time in us that the PLL will be stable - */ -unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, - u32 divp, u32 cpcon, u32 lfcon); - -/** - * Set PLL output frequency - * - * @param clkid clock id - * @param pllout pll output id - * @param rate desired output rate - * - * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) - */ -int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, - unsigned rate); - -/** - * Read low-level parameters of a PLL. - * - * @param id clock id to read (note: USB is not supported) - * @param divm returns input divider - * @param divn returns feedback divider - * @param divp returns post divider 2^n - * @param cpcon returns charge pump setup control - * @param lfcon returns loop filter setup control - * - * @returns 0 if ok, -1 on error (invalid clock id) - */ -int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, - u32 *divp, u32 *cpcon, u32 *lfcon); - -/* - * Enable a clock - * - * @param id clock id - */ -void clock_enable(enum periph_id clkid); - -/* - * Disable a clock - * - * @param id clock id - */ -void clock_disable(enum periph_id clkid); - -/* - * Set whether a clock is enabled or disabled. - * - * @param id clock id - * @param enable 1 to enable, 0 to disable - */ -void clock_set_enable(enum periph_id clkid, int enable); - -/** - * Reset a peripheral. This puts it in reset, waits for a delay, then takes - * it out of reset and waits for th delay again. - * - * @param periph_id peripheral to reset - * @param us_delay time to delay in microseconds - */ -void reset_periph(enum periph_id periph_id, int us_delay); - -/** - * Put a peripheral into or out of reset. - * - * @param periph_id peripheral to reset - * @param enable 1 to put into reset, 0 to take out of reset - */ -void reset_set_enable(enum periph_id periph_id, int enable); - - -/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ -enum crc_reset_id { - /* Things we can hold in reset for each CPU */ - crc_rst_cpu = 1, - crc_rst_de = 1 << 4, /* What is de? */ - crc_rst_watchdog = 1 << 8, - crc_rst_debug = 1 << 12, -}; - -/** - * Put parts of the CPU complex into or out of reset.\ - * - * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) - * @param which which parts of the complex to affect (OR of crc_reset_id) - * @param reset 1 to assert reset, 0 to de-assert - */ -void reset_cmplx_set_enable(int cpu, int which, int reset); - -/** - * Set the source for a peripheral clock. This plus the divisor sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - */ -void clock_ll_set_source(enum periph_id periph_id, unsigned source); - -/** - * Set the source and divisor for a peripheral clock. This sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - * @param divisor divisor value to use - */ -void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, - unsigned divisor); - -/** - * Start a peripheral PLL clock at the given rate. This also resets the - * peripheral. - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_start_periph_pll(enum periph_id periph_id, - enum clock_id parent, unsigned rate); - -/** - * Returns the rate of a peripheral clock in Hz. Since the caller almost - * certainly knows the parent clock (having just set it) we require that - * this be passed in so we don't need to work it out. - * - * @param periph_id peripheral to start - * @param parent PLL id of parent clock (used to calculate rate, you - * must know this!) - * @return clock rate of peripheral in Hz - */ -unsigned long clock_get_periph_rate(enum periph_id periph_id, - enum clock_id parent); - -/** - * Adjust peripheral PLL clock to the given rate. This does not reset the - * peripheral. If a second stage divisor is not available, pass NULL for - * extra_div. If it is available, then this parameter will return the - * divisor selected (which will be a power of 2 from 1 to 256). - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @param extra_div value for the second-stage divisor (NULL if one is - not available) - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, - enum clock_id parent, unsigned rate, int *extra_div); - -/** - * Returns the clock rate of a specified clock, in Hz. - * - * @param parent PLL id of clock to check - * @return rate of clock in Hz - */ -unsigned clock_get_rate(enum clock_id clkid); - -/** - * Start up a UART using low-level calls - * - * Prior to relocation clock_start_periph_pll() cannot be called. This - * function provides a way to set up a UART using low-level calls which - * do not require BSS. - * - * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) - */ -void clock_ll_start_uart(enum periph_id periph_id); - -/** - * Decode a peripheral ID from a device tree node. - * - * This works by looking up the peripheral's 'clocks' node and reading out - * the second cell, which is the clock number / peripheral ID. - * - * @param blob FDT blob to use - * @param node Node to look at - * @return peripheral ID, or PERIPH_ID_NONE if none - */ -enum periph_id clock_decode_periph_id(const void *blob, int node); - -/** - * Checks if the oscillator bypass is enabled (XOBP bit) - * - * @return 1 if bypass is enabled, 0 if not - */ -int clock_get_osc_bypass(void); - -/* - * Checks that clocks are valid and prints a warning if not - * - * @return 0 if ok, -1 on error - */ -int clock_verify(void); - -/* Initialize the clocks */ -void clock_init(void); - -/* Initialize the PLLs */ -void clock_early_init(void); - -/* Returns a pointer to the clock source register for a peripheral */ -u32 *get_periph_source_reg(enum periph_id periph_id); - -/** - * Given a peripheral ID and the required source clock, this returns which - * value should be programmed into the source mux for that peripheral. - * - * There is special code here to handle the one source type with 5 sources. - * - * @param periph_id peripheral to start - * @param source PLL id of required parent clock - * @param mux_bits Set to number of bits in mux register: 2 or 4 - * @param divider_bits Set to number of divider bits (8 or 16) - * @return mux value (0-4, or -1 if not found) - */ -int get_periph_clock_source(enum periph_id periph_id, - enum clock_id parent, int *mux_bits, int *divider_bits); - -/* - * Convert a device tree clock ID to our peripheral ID. They are mostly - * the same but we are very cautious so we check that a valid clock ID is - * provided. - * - * @param clk_id Clock ID according to tegra30 device tree binding - * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid - */ -enum periph_id clk_id_to_periph_id(int clk_id); - -/** - * Set the output frequency you want for each PLL clock. - * PLL output frequencies are programmed by setting their N, M and P values. - * The governing equations are: - * VCO = (Fi / m) * n, Fo = VCO / (2^p) - * where Fo is the output frequency from the PLL. - * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) - * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 - * Please see Tegra TRM section 5.3 to get the detail for PLL Programming - * - * @param n PLL feedback divider(DIVN) - * @param m PLL input divider(DIVN) - * @param p post divider(DIVP) - * @param cpcon base PLL charge pump(CPCON) - * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot - * be overriden), 1 if PLL is already correct - */ -int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); - -/* return 1 if a peripheral ID is in range */ -#define clock_type_id_isvalid(id) ((id) >= 0 && \ - (id) < CLOCK_TYPE_COUNT) - -/* return 1 if a periphc_internal_id is in range */ -#define periphc_internal_id_isvalid(id) ((id) >= 0 && \ - (id) < PERIPHC_COUNT) - -/* SoC-specific TSC init */ -void arch_timer_init(void); - -void tegra30_set_up_pllp(void); - -#endif /* _TEGRA_CLOCK_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h deleted file mode 100644 index f101e5ef6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra high-level function multiplexing */ - -#ifndef _TEGRA_FUNCMUX_H_ -#define _TEGRA_FUNCMUX_H_ - -/** - * Select a config for a particular peripheral. - * - * Each peripheral can operate through a number of configurations, - * which are sets of pins that it uses to bring out its signals. - * The basic config is 0, and higher numbers indicate different - * pinmux settings to bring the peripheral out on other pins, - * - * This function also disables tristate for the function's pins, - * so that they operate in normal mode. - * - * @param id Peripheral id - * @param config Configuration to use (FUNCMUX_...), 0 for default - * @return 0 if ok, -1 on error (e.g. incorrect id or config) - */ -int funcmux_select(enum periph_id id, int config); - -#endif /* _TEGRA_FUNCMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h deleted file mode 100644 index 39b578c00..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FUSE_H_ -#define _FUSE_H_ - -/* FUSE registers */ -struct fuse_regs { - u32 reserved0[64]; /* 0x00 - 0xFC: */ - u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ - u32 reserved1[3]; /* 0x104 - 0x10c: */ - u32 sku_info; /* 0x110 */ - u32 reserved2[13]; /* 0x114 - 0x144: */ - u32 fa; /* 0x148: FUSE_FA */ - u32 reserved3[21]; /* 0x14C - 0x19C: */ - u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ -}; - -#endif /* ifndef _FUSE_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h deleted file mode 100644 index 7a86acb1b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_GP_PADCTRL_H_ -#define _TEGRA_GP_PADCTRL_H_ - -#define GP_HIDREV 0x804 - -/* bit fields definitions for APB_MISC_GP_HIDREV register */ -#define HIDREV_CHIPID_SHIFT 8 -#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) -#define HIDREV_MAJORPREV_SHIFT 4 -#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) - -/* CHIPID field returned from APB_MISC_GP_HIDREV register */ -#define CHIPID_TEGRA20 0x20 -#define CHIPID_TEGRA30 0x30 -#define CHIPID_TEGRA114 0x35 -#define CHIPID_TEGRA124 0x40 - -#endif /* _TEGRA_GP_PADCTRL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h deleted file mode 100644 index d97190dd7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_GPIO_H_ -#define _TEGRA_GPIO_H_ - -#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) -#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ - -#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_FULLPORT(x) ((x) >> 3) -#define GPIO_BIT(x) ((x) & 0x7) - -/* - * Tegra-specific GPIO API - */ - -void gpio_info(void); - -#define gpio_status() gpio_info() -#endif /* TEGRA_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/mmc.h deleted file mode 100644 index c2d52b297..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/mmc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_MMC_H_ -#define _TEGRA_MMC_H_ - -void tegra_mmc_init(void); - -#endif /* _TEGRA_MMC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h deleted file mode 100644 index 035159d66..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * (C) Copyright 2010-2014 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_PINMUX_H_ -#define _TEGRA_PINMUX_H_ - -#include <asm/arch/tegra.h> - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; - -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, - PMUX_PIN_NONE, -}; - -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; - -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; - -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; - -#ifdef TEGRA_PMX_HAS_RCV_SEL -enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, - PMUX_PIN_RCV_SEL_HIGH, -}; -#endif /* TEGRA_PMX_HAS_RCV_SEL */ -#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pmux_pingrp_config { - u32 pingrp:16; /* pin group PMUX_PINGRP_... */ - u32 func:8; /* function to assign PMUX_FUNC_... */ - u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ - u32 tristate:2; /* tristate or normal PMUX_TRI_... */ -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC - u32 io:2; /* input or output PMUX_PIN_... */ - u32 lock:2; /* lock enable/disable PMUX_PIN... */ - u32 od:2; /* open-drain or push-pull driver */ - u32 ioreset:2; /* input/output reset PMUX_PIN... */ -#ifdef TEGRA_PMX_HAS_RCV_SEL - u32 rcv_sel:2; /* select between High and Normal */ - /* VIL/VIH receivers */ -#endif -#endif -}; - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); -#endif - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, - int len); - -#ifdef TEGRA_PMX_HAS_DRVGRPS - -#define PMUX_SLWF_MIN 0 -#define PMUX_SLWF_MAX 3 -#define PMUX_SLWF_NONE -1 - -#define PMUX_SLWR_MIN 0 -#define PMUX_SLWR_MAX 3 -#define PMUX_SLWR_NONE -1 - -#define PMUX_DRVUP_MIN 0 -#define PMUX_DRVUP_MAX 127 -#define PMUX_DRVUP_NONE -1 - -#define PMUX_DRVDN_MIN 0 -#define PMUX_DRVDN_MAX 127 -#define PMUX_DRVDN_NONE -1 - -/* Defines a pin group cfg's low-power mode select */ -enum pmux_lpmd { - PMUX_LPMD_X8 = 0, - PMUX_LPMD_X4, - PMUX_LPMD_X2, - PMUX_LPMD_X, - PMUX_LPMD_NONE = -1, -}; - -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pmux_schmt { - PMUX_SCHMT_DISABLE = 0, - PMUX_SCHMT_ENABLE = 1, - PMUX_SCHMT_NONE = -1, -}; - -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pmux_hsm { - PMUX_HSM_DISABLE = 0, - PMUX_HSM_ENABLE = 1, - PMUX_HSM_NONE = -1, -}; - -/* - * This defines the configuration for a pin group's pad control config - */ -struct pmux_drvgrp_config { - u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ - u32 slwf:3; /* falling edge slew */ - u32 slwr:3; /* rising edge slew */ - u32 drvup:8; /* pull-up drive strength */ - u32 drvdn:8; /* pull-down drive strength */ - u32 lpmd:3; /* low-power mode selection */ - u32 schmt:2; /* schmidt enable */ - u32 hsm:2; /* high-speed mode enable */ -}; - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, - int len); - -#endif /* TEGRA_PMX_HAS_DRVGRPS */ - -struct pmux_pingrp_desc { - u8 funcs[4]; -#if defined(CONFIG_TEGRA20) - u8 ctl_id; - u8 pull_id; -#endif /* CONFIG_TEGRA20 */ -}; - -extern const struct pmux_pingrp_desc *tegra_soc_pingroups; - -#endif /* _TEGRA_PINMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h deleted file mode 100644 index 1dd3154fb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * (C) Copyright 2010,2011,2014 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PMC_H_ -#define _PMC_H_ - -/* Power Management Controller (APBDEV_PMC_) registers */ -struct pmc_ctlr { - uint pmc_cntrl; /* _CNTRL_0, offset 00 */ - uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ - uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ - uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ - uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ - uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ - uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ - uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ - uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ - uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ - uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) - uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ -#else - uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */ -#endif - uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ - uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ - uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ - uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ - uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ - uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ - uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ - uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ - - uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ - uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ - uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ - uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ - uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ - uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ - uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ - uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ - uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ - uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ - uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ - uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ - uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ - uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ - uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ - uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ - uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ - uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ - uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ - uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ - uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ - uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ - uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ - uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ - - uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ - uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ - uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ - uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ - uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ - uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ - - uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ - uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ - uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ - uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ - uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ - uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ - uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ - uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ - uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ - uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ - uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ - uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ - uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ - - uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ - uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ - uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ - uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ - uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ - uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ - uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ - uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ - uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ - uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ - uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ - uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ - uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ - uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ - uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ - uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ - uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ - uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ - uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ - - uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ - uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ - uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ - uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ - uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ - uint pmc_gate; /* _GATE_0, offset 15C */ - /* The following fields are in Tegra124 and later only */ - uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ - uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ - uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ - uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ - uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ - uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ - uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ - uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ - uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ - uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ - uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ - uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ - uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ - uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ - uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ - uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ - uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ - uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ - uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ - uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ - uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ - uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ - uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ - uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ - uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ - uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ - uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ - uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ - - uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ - uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ - uint pmc_reserved0; /* _RESERVED, offset 1D8 */ - uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ - uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ - uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ - uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ - uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ - uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ - uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ - uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ - uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ - - uint pmc_todo_0[9]; /* offset 200-220 */ - uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ - uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ - uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ - uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ - uint pmc_scratch45; - uint pmc_scratch46; - uint pmc_scratch47; - uint pmc_scratch48; - uint pmc_scratch49; - uint pmc_scratch50; - uint pmc_scratch51; - uint pmc_scratch52; - uint pmc_scratch53; - uint pmc_scratch54; - uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ - uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ - uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ - uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ - uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ - uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ - uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ - uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ - uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ - uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ - uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ - uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ - uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ - uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ - uint pmc_secure_scratch9; - uint pmc_secure_scratch10; - uint pmc_secure_scratch11; - uint pmc_secure_scratch12; - uint pmc_secure_scratch13; - uint pmc_secure_scratch14; - uint pmc_secure_scratch15; - uint pmc_secure_scratch16; - uint pmc_secure_scratch17; - uint pmc_secure_scratch18; - uint pmc_secure_scratch19; - uint pmc_secure_scratch20; - uint pmc_secure_scratch21; - uint pmc_secure_scratch22; - uint pmc_secure_scratch23; - uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ - uint pmc_secure_scratch25; - uint pmc_secure_scratch26; - uint pmc_secure_scratch27; - uint pmc_secure_scratch28; - uint pmc_secure_scratch29; - uint pmc_secure_scratch30; - uint pmc_secure_scratch31; - uint pmc_secure_scratch32; - uint pmc_secure_scratch33; - uint pmc_secure_scratch34; - uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ - - uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ - uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */ - uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ - uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ - uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ - uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ - uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ - - uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */ - uint pmc_scratch57; - uint pmc_scratch58; - uint pmc_scratch59; - uint pmc_scratch60; - uint pmc_scratch61; - uint pmc_scratch62; - uint pmc_scratch63; - uint pmc_scratch64; - uint pmc_scratch65; - uint pmc_scratch66; - uint pmc_scratch67; - uint pmc_scratch68; - uint pmc_scratch69; - uint pmc_scratch70; - uint pmc_scratch71; - uint pmc_scratch72; - uint pmc_scratch73; - uint pmc_scratch74; - uint pmc_scratch75; - uint pmc_scratch76; - uint pmc_scratch77; - uint pmc_scratch78; - uint pmc_scratch79; - uint pmc_scratch80; - uint pmc_scratch81; - uint pmc_scratch82; - uint pmc_scratch83; - uint pmc_scratch84; - uint pmc_scratch85; - uint pmc_scratch86; - uint pmc_scratch87; - uint pmc_scratch88; - uint pmc_scratch89; - uint pmc_scratch90; - uint pmc_scratch91; - uint pmc_scratch92; - uint pmc_scratch93; - uint pmc_scratch94; - uint pmc_scratch95; - uint pmc_scratch96; - uint pmc_scratch97; - uint pmc_scratch98; - uint pmc_scratch99; - uint pmc_scratch100; - uint pmc_scratch101; - uint pmc_scratch102; - uint pmc_scratch103; - uint pmc_scratch104; - uint pmc_scratch105; - uint pmc_scratch106; - uint pmc_scratch107; - uint pmc_scratch108; - uint pmc_scratch109; - uint pmc_scratch110; - uint pmc_scratch111; - uint pmc_scratch112; - uint pmc_scratch113; - uint pmc_scratch114; - uint pmc_scratch115; - uint pmc_scratch116; - uint pmc_scratch117; - uint pmc_scratch118; - uint pmc_scratch119; - uint pmc_scratch1_eco; /* offset 700 */ -}; - -#define CPU_PWRED 1 -#define CPU_CLMP 1 - -#define PARTID_CP 0xFFFFFFF8 -#define START_CP (1 << 8) - -#define CPUPWRREQ_OE (1 << 16) -#define CPUPWRREQ_POL (1 << 15) - -#define CRAIL 0 -#define CE0 14 -#define C0NC 15 - -#define PMC_XOFS_SHIFT 1 -#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) - -#if defined(CONFIG_TEGRA114) -#define TIMER_MULT_SHIFT 0 -#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) -#define TIMER_MULT_CPU_SHIFT 2 -#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) -#elif defined(CONFIG_TEGRA124) -#define TIMER_MULT_SHIFT 0 -#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT) -#define TIMER_MULT_CPU_SHIFT 3 -#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT) -#endif - -#define MULT_1 0 -#define MULT_2 1 -#define MULT_4 2 -#define MULT_8 3 -#if defined(CONFIG_TEGRA124) -#define MULT_16 4 -#endif - -#define AMAP_WRITE_SHIFT 20 -#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) - -/* SEC_DISABLE_0, 0x04 */ -#define SEC_DISABLE_WRITE0_ON (1 << 4) -#define SEC_DISABLE_READ0_ON (1 << 5) -#define SEC_DISABLE_WRITE1_ON (1 << 6) -#define SEC_DISABLE_READ1_ON (1 << 7) -#define SEC_DISABLE_WRITE2_ON (1 << 8) -#define SEC_DISABLE_READ2_ON (1 << 9) -#define SEC_DISABLE_WRITE3_ON (1 << 10) -#define SEC_DISABLE_READ3_ON (1 << 11) -#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) - -/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ -#define PWRGATE_TOGGLE_PARTID_CRAIL 0 -#define PWRGATE_TOGGLE_PARTID_TD 1 -#define PWRGATE_TOGGLE_PARTID_VE 2 -#define PWRGATE_TOGGLE_PARTID_PCX 3 -#define PWRGATE_TOGGLE_PARTID_VDE 4 -#define PWRGATE_TOGGLE_PARTID_L2C 5 -#define PWRGATE_TOGGLE_PARTID_MPE 6 -#define PWRGATE_TOGGLE_PARTID_HEG 7 -#define PWRGATE_TOGGLE_PARTID_SAX 8 -#define PWRGATE_TOGGLE_PARTID_CE1 9 -#define PWRGATE_TOGGLE_PARTID_CE2 10 -#define PWRGATE_TOGGLE_PARTID_CE3 11 -#define PWRGATE_TOGGLE_PARTID_CELP 12 -#define PWRGATE_TOGGLE_PARTID_CE0 14 -#define PWRGATE_TOGGLE_PARTID_C0NC 15 -#define PWRGATE_TOGGLE_PARTID_C1NC 16 -#define PWRGATE_TOGGLE_PARTID_SOR 17 -#define PWRGATE_TOGGLE_PARTID_DIS 18 -#define PWRGATE_TOGGLE_PARTID_DISB 19 -#define PWRGATE_TOGGLE_PARTID_XUSBA 20 -#define PWRGATE_TOGGLE_PARTID_XUSBB 21 -#define PWRGATE_TOGGLE_PARTID_XUSBC 22 -#define PWRGATE_TOGGLE_PARTID_VIC 23 -#define PWRGATE_TOGGLE_PARTID_IRAM 24 -#define PWRGATE_TOGGLE_START (1 << 8) - -/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ -#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) -#define PWRGATE_STATUS_TD_ENABLE (1 << 1) -#define PWRGATE_STATUS_VE_ENABLE (1 << 2) -#define PWRGATE_STATUS_PCX_ENABLE (1 << 3) -#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) -#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) -#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) -#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) -#define PWRGATE_STATUS_SAX_ENABLE (1 << 8) -#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) -#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) -#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) -#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) -#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) -#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) -#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) -#define PWRGATE_STATUS_SOR_ENABLE (1 << 17) -#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) -#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) -#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) -#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) -#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) -#define PWRGATE_STATUS_VIC_ENABLE (1 << 23) -#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24) - -/* APBDEV_PMC_CNTRL2_0 0x440 */ -#define HOLD_CKE_LOW_EN (1 << 12) - -#endif /* PMC_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h deleted file mode 100644 index 987c16ff4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SCU_H_ -#define _SCU_H_ - -/* ARM Snoop Control Unit (SCU) registers */ -struct scu_ctlr { - uint scu_ctrl; /* SCU Control Register, offset 00 */ - uint scu_cfg; /* SCU Config Register, offset 04 */ - uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ - uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ - uint scu_reserved0[12]; /* reserved, offset 10-3C */ - uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ - uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ - uint scu_reserved1[2]; /* reserved, offset 48-4C */ - uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ - uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ -}; - -#define SCU_CTRL_ENABLE (1 << 0) - -#endif /* SCU_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h deleted file mode 100644 index 8b3fbe12f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -struct tegra_sysinfo { - char *board_string; -}; - -void invalidate_dcache(void); - -extern const struct tegra_sysinfo sysinfo; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h deleted file mode 100644 index d63af0e5f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_H_ -#define _TEGRA_H_ - -#define NV_PA_ARM_PERIPHBASE 0x50040000 -#define NV_PA_PG_UP_BASE 0x60000000 -#define NV_PA_TMRUS_BASE 0x60005010 -#define NV_PA_CLK_RST_BASE 0x60006000 -#define NV_PA_FLOW_BASE 0x60007000 -#define NV_PA_GPIO_BASE 0x6000D000 -#define NV_PA_EVP_BASE 0x6000F000 -#define NV_PA_APB_MISC_BASE 0x70000000 -#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) -#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) -#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) -#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) -#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) -#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) -#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) -#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) -#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) -#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) -#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) -#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) -#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) -#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) -#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ - defined(CONFIG_TEGRA114) -#define NV_PA_CSITE_BASE 0x70040000 -#else -#define NV_PA_CSITE_BASE 0x70800000 -#endif -#define TEGRA_USB_ADDR_MASK 0xFFFFC000 - -#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE -#define LOW_LEVEL_SRAM_STACK 0x4000FFFC -#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) -#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) -#define PG_UP_TAG_AVP 0xAAAAAAAA - -#ifndef __ASSEMBLY__ -struct timerus { - unsigned int cntr_1us; -}; - -/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ -#define NV_WB_RUN_ADDRESS 0x40020000 - -#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ - -/* These are the available SKUs (product types) for Tegra */ -enum { - SKU_ID_T20_7 = 0x7, - SKU_ID_T20 = 0x8, - SKU_ID_T25SE = 0x14, - SKU_ID_AP25 = 0x17, - SKU_ID_T25 = 0x18, - SKU_ID_AP25E = 0x1b, - SKU_ID_T25E = 0x1c, - SKU_ID_T33 = 0x80, - SKU_ID_T30 = 0x81, /* Cardhu value */ - SKU_ID_TM30MQS_P_A3 = 0xb1, - SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ - SKU_ID_T114_1 = 0x01, - SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */ -}; - -/* - * These are used to distinguish SOC types for setting up clocks. Mostly - * we can tell the clocking required by looking at the SOC sku_id, but - * for T30 it is a user option as to whether to run PLLP in fast or slow - * mode, so we have two options there. - */ -enum { - TEGRA_SOC_T20, - TEGRA_SOC_T25, - TEGRA_SOC_T30, - TEGRA_SOC_T114, - TEGRA_SOC_T124, - - TEGRA_SOC_CNT, - TEGRA_SOC_UNKNOWN = -1, -}; - -#else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL NV_PA_PMC_BASE -#endif - -#endif /* TEGRA_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h deleted file mode 100644 index 853e59bb6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * NVIDIA Tegra I2C controller - * - * Copyright 2010-2011 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_I2C_H_ -#define _TEGRA_I2C_H_ - -#include <asm/types.h> - -enum { - I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ - I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ -}; - -enum i2c_transaction_flags { - I2C_IS_WRITE = 0x1, /* for I2C write operation */ - I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ - I2C_USE_REPEATED_START = 0x4, /* for repeat start */ - I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ - I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ - I2C_NO_STOP = 0x20, -}; - -/* Contians the I2C transaction details */ -struct i2c_trans_info { - /* flags to indicate the transaction details */ - enum i2c_transaction_flags flags; - u32 address; /* I2C slave device address */ - u32 num_bytes; /* number of bytes to be transferred */ - /* - * Send/receive buffer. For the I2C send operation this buffer should - * be filled with the data to be sent to the slave device. For the I2C - * receive operation this buffer is filled with the data received from - * the slave device. - */ - u8 *buf; - int is_10bit_address; -}; - -struct i2c_control { - u32 tx_fifo; - u32 rx_fifo; - u32 packet_status; - u32 fifo_control; - u32 fifo_status; - u32 int_mask; - u32 int_status; -}; - -struct dvc_ctlr { - u32 ctrl1; /* 00: DVC_CTRL_REG1 */ - u32 ctrl2; /* 04: DVC_CTRL_REG2 */ - u32 ctrl3; /* 08: DVC_CTRL_REG3 */ - u32 status; /* 0C: DVC_STATUS_REG */ - u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ - u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ - u32 reserved_0[2]; /* 18: */ - u32 req; /* 20: DVC_REQ_REGISTER */ - u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ - u32 reserved_1[6]; /* 28: */ - u32 cnfg; /* 40: DVC_I2C_CNFG */ - u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ - u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ - u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ - u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ - u32 reserved_2[2]; /* 54: */ - u32 i2c_status; /* 5C: DVC_I2C_STATUS */ - struct i2c_control control; /* 60 ~ 78 */ -}; - -struct i2c_ctlr { - u32 cnfg; /* 00: I2C_I2C_CNFG */ - u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ - u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ - u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ - u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ - u32 reserved_0[2]; /* 14: */ - u32 status; /* 1C: I2C_I2C_STATUS */ - u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ - u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ - u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ - u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ - u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ - u32 reserved_1[2]; /* 34: */ - u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ - u32 reserved_2[4]; /* 40: */ - struct i2c_control control; /* 50 ~ 68 */ - u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */ -}; - -/* bit fields definitions for IO Packet Header 1 format */ -#define PKT_HDR1_PROTOCOL_SHIFT 4 -#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) -#define PKT_HDR1_CTLR_ID_SHIFT 12 -#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) -#define PKT_HDR1_PKT_ID_SHIFT 16 -#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) -#define PROTOCOL_TYPE_I2C 1 - -/* bit fields definitions for IO Packet Header 2 format */ -#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 -#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) - -/* bit fields definitions for IO Packet Header 3 format */ -#define PKT_HDR3_READ_MODE_SHIFT 19 -#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) -#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 -#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) - -#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 -#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ - (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) - -/* I2C_CNFG */ -#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 -#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) -#define I2C_CNFG_PACKET_MODE_SHIFT 10 -#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) - -/* I2C_SL_CNFG */ -#define I2C_SL_CNFG_NEWSL_SHIFT 2 -#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) - -/* I2C_FIFO_STATUS */ -#define TX_FIFO_FULL_CNT_SHIFT 0 -#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) -#define TX_FIFO_EMPTY_CNT_SHIFT 4 -#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) - -/* I2C_INTERRUPT_STATUS */ -#define I2C_INT_XFER_COMPLETE_SHIFT 7 -#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) -#define I2C_INT_NO_ACK_SHIFT 3 -#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) -#define I2C_INT_ARBITRATION_LOST_SHIFT 2 -#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) - -/* I2C_CLK_DIVISOR_REGISTER */ -#define CLK_DIV_STD_FAST_MODE 0x19 -#define CLK_DIV_HS_MODE 1 -#define CLK_MULT_STD_FAST_MODE 8 - -/** - * Returns the bus number of the DVC controller - * - * @return number of bus, or -1 if there is no DVC active - */ -int tegra_i2c_get_dvc_bus_num(void); - -#endif /* _TEGRA_I2C_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h deleted file mode 100644 index 310bbd7df..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang@samsung.com> - * Portions Copyright (C) 2011-2012 NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __TEGRA_MMC_H_ -#define __TEGRA_MMC_H_ - -#include <fdtdec.h> - -/* for mmc_config definition */ -#include <mmc.h> - -#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ - -#ifndef __ASSEMBLY__ -struct tegra_mmc { - unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ - unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ - unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ - unsigned int argument; /* _ARGUMENT_0 */ - unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ - unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ - unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ - unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ - unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ - unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ - unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ - unsigned int prnsts; /* _PRESENT_STATE_0 */ - unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ - unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ - unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ - unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ - unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ - unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ - unsigned char swrst; /* _SW_RESET_ 31:24 */ - unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ - unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ - unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ - unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ - unsigned char res1[2]; /* _RESERVED 31:16 */ - unsigned int capareg; /* _CAPABILITIES_0 */ - unsigned char res2[4]; /* RESERVED, offset 44h-47h */ - unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ - unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ - unsigned short setacmd12err; /* offset 50h */ - unsigned short setinterr; /* offset 52h */ - unsigned char admaerr; /* offset 54h */ - unsigned char res4[3]; /* RESERVED, offset 55h-57h */ - unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ - unsigned short slotintstatus; /* offset FCh */ - unsigned short hcver; /* HOST Version */ - unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ - unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ - unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ - unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ - unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ - unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ - unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ - unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ - unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ - unsigned int res6[47]; /* 0x124 ~ 0x1DC */ - unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ - unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ - unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ - unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ -}; - -#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) -#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) -#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) -#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) - -#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) -#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) - -#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) -#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) -#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) -#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) - -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) -#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) - -#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) -#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) -#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) - -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) -#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) - -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) -#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) -#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) - -#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 -#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) - -#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) -#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) - -#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) -#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) - -#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) -#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) -#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) -#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) - -#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) - -/* SDMMC1/3 settings from section 24.6 of T30 TRM */ -#define MEMCOMP_PADCTRL_VREF 7 -#define AUTO_CAL_ENABLED (1 << 29) -#define AUTO_CAL_PD_OFFSET (0x70 << 8) -#define AUTO_CAL_PU_OFFSET (0x62 << 0) - -struct mmc_host { - struct tegra_mmc *reg; - int id; /* device id/number, 0-3 */ - int enabled; /* 1 to enable, 0 to disable */ - int width; /* Bus Width, 1, 4 or 8 */ - enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ - struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */ - struct fdt_gpio_state pwr_gpio; /* Power GPIO */ - struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */ - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ - struct mmc_config cfg; /* mmc configuration */ -}; - -void pad_init_mmc(struct mmc_host *host); - -#endif /* __ASSEMBLY__ */ -#endif /* __TEGRA_MMC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h deleted file mode 100644 index 5d5664115..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 timer functions */ - -#ifndef _TEGRA_TIMER_H -#define _TEGRA_TIMER_H - -/* returns the current monotonic timer value in microseconds */ -unsigned long timer_get_us(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h deleted file mode 100644 index fef7f8db3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _UART_H_ -#define _UART_H_ - -/* UART registers */ -struct uart_ctlr { - uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ - uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ - uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ - uint uart_lcr; /* UART_LCR_0, offset 0C */ - uint uart_mcr; /* UART_MCR_0, offset 10 */ - uint uart_lsr; /* UART_LSR_0, offset 14 */ - uint uart_msr; /* UART_MSR_0, offset 18 */ - uint uart_spr; /* UART_SPR_0, offset 1C */ - uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ - uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ - uint uart_asr; /* UART_ASR_0, offset 3C */ -}; - -#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 -#define NV_DEFAULT_DEBUG_BAUD 115200 - -#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ - -#endif /* UART_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h deleted file mode 100644 index ceb7bcd9c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA_USB_H_ -#define _TEGRA_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - -#ifdef CONFIG_TEGRA20 - /* 0x130 */ - uint reserved4_2[4]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; -#else - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; -#endif - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - -#ifdef CONFIG_TEGRA20 - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[4]; - - /* 0x424 */ - uint ulpi_timing_ctrl_0; - uint ulpi_timing_ctrl_1; - uint reserved13[53]; -#else - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; -#endif - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB1_LEGACY_CTRL */ -#define USB1_NO_LEGACY_MODE 1 - -#define VBUS_SENSE_CTL_SHIFT 1 -#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) -#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 -#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 -#define VBUS_SENSE_CTL_AB_SESS_VLD 2 -#define VBUS_SENSE_CTL_A_SESS_VLD 3 - -/* USBx_IF_USB_SUSP_CTRL_0 */ -#define UTMIP_PHY_ENB (1 << 12) -#define UTMIP_RESET (1 << 11) -#define USB_PHY_CLK_VALID (1 << 7) -#define USB_SUSP_CLR (1 << 5) - -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) -/* USB2_IF_USB_SUSP_CTRL_0 */ -#define ULPI_PHY_ENB (1 << 13) - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) -#endif - -/* USBx_UTMIP_MISC_CFG0 */ -#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) - -/* USBx_UTMIP_MISC_CFG1 */ -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) - -/* - * Tegra 3 and later: Moved to Clock and Reset register space, see - * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 - */ -#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 -#define UTMIP_PLLU_STABLE_COUNT_MASK \ - (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) -/* - * Tegra 3 and later: Moved to Clock and Reset register space, see - * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 - */ -#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 -#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) - -/* USBx_UTMIP_PLL_CFG1_0 */ -/* Tegra 3 and later: Moved to Clock and Reset register space */ -#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 -#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) -#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 -#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff - -/* USBx_UTMIP_BIAS_CFG0_0 */ -#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) -#define UTMIP_OTGPD (1 << 11) -#define UTMIP_BIASPD (1 << 10) -#define UTMIP_HSDISCON_LEVEL_SHIFT 2 -#define UTMIP_HSDISCON_LEVEL_MASK \ - (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) -#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 -#define UTMIP_HSSQUELCH_LEVEL_MASK \ - (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) - -/* USBx_UTMIP_BIAS_CFG1_0 */ -#define UTMIP_FORCE_PDTRK_POWERDOWN 1 -#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 -#define UTMIP_BIAS_PDTRK_COUNT_MASK \ - (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) - -/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ -#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 -#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff - -/* USBx_UTMIP_TX_CFG0_0 */ -#define UTMIP_FS_PREAMBLE_J (1 << 19) - -/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ -#define UTMIP_PD_CHRG 1 - -/* USBx_UTMIP_SPARE_CFG0_0 */ -#define FUSE_SETUP_SEL (1 << 3) - -/* USBx_UTMIP_HSRX_CFG0_0 */ -#define UTMIP_IDLE_WAIT_SHIFT 15 -#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) -#define UTMIP_ELASTIC_LIMIT_SHIFT 10 -#define UTMIP_ELASTIC_LIMIT_MASK \ - (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) - -/* USBx_UTMIP_HSRX_CFG1_0 */ -#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 -#define UTMIP_HS_SYNC_START_DLY_MASK \ - (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) - -/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ -#define IC_ENB1 (1 << 3) - -#ifdef CONFIG_TEGRA20 -/* PORTSC1, USB1 */ -#define PTS1_SHIFT 31 -#define PTS1_MASK (1 << PTS1_SHIFT) -#define STS1 (1 << 30) - -/* PORTSC, USB2, USB3 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) -#define STS (1 << 29) -#else -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) -#define STS (1 << 28) -#endif - -#define PTS_UTMI 0 -#define PTS_RESERVED 1 -#define PTS_ULPI 2 -#define PTS_ICUSB_SER 3 -#define PTS_HSIC 4 - -/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define WKOC (1 << 22) -#define WKDS (1 << 21) -#define WKCN (1 << 20) - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) -#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 -#define UTMIP_XCVR_HSSLEW_MSB_MASK \ - (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) - -/* USBx_UTMIP_XCVR_CFG1_0 */ -#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 -#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ - (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) - -/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ -#define VBUS_VLD_STS (1 << 26) - -/* Setup USB on the board */ -int usb_process_devicetree(const void *blob); - -#endif /* _TEGRA_USB_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h deleted file mode 100644 index 2e66e0f23..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _WARM_BOOT_H_ -#define _WARM_BOOT_H_ - -#define STRAP_OPT_A_RAM_CODE_SHIFT 4 -#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) - -/* Defines the supported operating modes */ -enum fuse_operating_mode { - MODE_PRODUCTION = 3, - MODE_UNDEFINED, -}; - -/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ -enum { - HASH_LENGTH = 4 -}; - -/* Defines the storage for a hash value (128 bits) */ -struct hash { - u32 hash[HASH_LENGTH]; -}; - -/* - * Defines the code header information for the boot rom. - * - * The code immediately follows the code header. - * - * Note that the code header needs to be 16 bytes aligned to preserve - * the alignment of relevant data for hash and decryption computations without - * requiring extra copies to temporary memory areas. - */ -struct wb_header { - u32 length_insecure; /* length of the code header */ - u32 reserved[3]; - struct hash hash; /* hash of header+code, starts next field*/ - struct hash random_aes_block; /* a data block to aid security. */ - u32 length_secure; /* length of the code header */ - u32 destination; /* destination address to put the wb code */ - u32 entry_point; /* execution address of the wb code */ - u32 code_length; /* length of the code */ -}; - -/* - * The warm boot code needs direct access to these registers since it runs in - * SRAM and cannot call other U-Boot code. - */ -union osc_ctrl_reg { - struct { - u32 xoe:1; - u32 xobp:1; - u32 reserved0:2; - u32 xofs:6; - u32 reserved1:2; - u32 xods:5; - u32 reserved2:3; - u32 oscfi_spare:8; - u32 pll_ref_div:2; - u32 osc_freq:2; - }; - u32 word; -}; - -union pllx_base_reg { - struct { - u32 divm:5; - u32 reserved0:3; - u32 divn:10; - u32 reserved1:2; - u32 divp:3; - u32 reserved2:4; - u32 lock:1; - u32 reserved3:1; - u32 ref_dis:1; - u32 enable:1; - u32 bypass:1; - }; - u32 word; -}; - -union pllx_misc_reg { - struct { - u32 vcocon:4; - u32 lfcon:4; - u32 cpcon:4; - u32 lock_sel:6; - u32 reserved0:1; - u32 lock_enable:1; - u32 reserved1:1; - u32 dccon:1; - u32 pts:2; - u32 reserved2:6; - u32 out1_div_byp:1; - u32 out1_inv_clk:1; - }; - u32 word; -}; - -/* - * TODO: This register is not documented in the TRM yet. We could move this - * into the EMC and give it a proper interface, but not while it is - * undocumented. - */ -union scratch3_reg { - struct { - u32 pllx_base_divm:5; - u32 pllx_base_divn:10; - u32 pllx_base_divp:3; - u32 pllx_misc_lfcon:4; - u32 pllx_misc_cpcon:4; - }; - u32 word; -}; - - -/** - * Save warmboot memory settings for a later resume - * - * @return 0 if ok, -1 on error - */ -int warmboot_save_sdram_params(void); - -int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); -void wb_start(void); /* Start of WB assembly code */ -void wb_end(void); /* End of WB assembly code */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h deleted file mode 100644 index d8fa0e1d2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ /dev/null @@ -1,402 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra114 clock PLL tables */ - -#ifndef _TEGRA114_CLOCK_TABLES_H_ -#define _TEGRA114_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - - CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 (DEVICES_L) */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_RESERVED3, - PERIPH_ID_RTC, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_RESERVED16, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_RESERVED24, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S0, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 (DEVICES_H) */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_RESERVED45, - PERIPH_ID_SBC3, - PERIPH_ID_I2C5, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_NANDSPEED, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_3D2, - PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, - PERIPH_ID_I2S3, - PERIPH_ID_I2S4, - PERIPH_ID_I2C4, - - /* 104 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AUDIO, - PERIPH_ID_APBIF, - PERIPH_ID_DAM0, - PERIPH_ID_DAM1, - PERIPH_ID_DAM2, - PERIPH_ID_HDA2CODEC2X, - - /* 112 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, - PERIPH_ID_ACTMON, - - /* 120 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_RESERVED1_SATACOLD, - PERIPH_ID_RESERVED2_PCIERX0, - PERIPH_ID_RESERVED3_PCIERX1, - PERIPH_ID_RESERVED4_PCIERX2, - PERIPH_ID_RESERVED5_PCIERX3, - PERIPH_ID_RESERVED6_PCIERX4, - PERIPH_ID_RESERVED7_PCIERX5, - - /* 136 */ - PERIPH_ID_CEC, - PERIPH_ID_PCIE2_IOBIST, - PERIPH_ID_EMC_IOBIST, - PERIPH_ID_HDMI_IOBIST, - PERIPH_ID_SATA_IOBIST, - PERIPH_ID_MIPI_IOBIST, - PERIPH_ID_EMC1_IOBIST, - PERIPH_ID_XUSB, - - /* 144 */ - PERIPH_ID_CILAB, - PERIPH_ID_CILCD, - PERIPH_ID_CILE, - PERIPH_ID_DSIA_LP, - PERIPH_ID_DSIB_LP, - PERIPH_ID_RESERVED21_ENTROPY, - PERIPH_ID_RESERVED22_W, - PERIPH_ID_RESERVED23_W, - - /* 152 */ - PERIPH_ID_RESERVED24_W, - PERIPH_ID_AMX0, - PERIPH_ID_ADX0, - PERIPH_ID_DVFS, - PERIPH_ID_XUSB_SS, - PERIPH_ID_EMC_DLL, - PERIPH_ID_MC1, - PERIPH_ID_EMC1, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S1, - PERIPHC_I2S2, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_I2C5, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_CVE, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_NDFLASH, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_EPP, - PERIPHC_MPE, - PERIPHC_MIPI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_TVO, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_TVDAC, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S0, - PERIPHC_37h, - - PERIPHC_VW_FIRST, - /* 0x38 */ - PERIPHC_G3D2 = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S3, - PERIPHC_I2S4, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x40 */ - PERIPHC_AUDIO, - PERIPHC_41h, - PERIPHC_DAM0, - PERIPHC_DAM1, - PERIPHC_DAM2, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x48 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_NANDSPEED, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, - - PERIPHC_COUNT, - - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA114_CLOCK_TABLES_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h deleted file mode 100644 index abbefcd0e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra114 clock control functions */ - -#ifndef _TEGRA114_CLOCK_H_ -#define _TEGRA114_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -#endif /* _TEGRA114_CLOCK_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h deleted file mode 100644 index c7eb051c7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_FLOW_H_ -#define _TEGRA114_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 xrq_events; - u32 halt_cpu1_events; - u32 cpu1_csr; - u32 halt_cpu2_events; - u32 cpu2_csr; - u32 halt_cpu3_events; - u32 cpu3_csr; - u32 cluster_control; -}; - -#endif /* _TEGRA114_FLOW_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h deleted file mode 100644 index 7f48f2510..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra114 high-level function multiplexing */ - -#ifndef _TEGRA114_FUNCMUX_H_ -#define _TEGRA114_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART4_GMI = 0, -}; -#endif /* _TEGRA114_FUNCMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h deleted file mode 100644 index 41ce67780..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_GP_PADCTRL_H_ -#define _TEGRA114_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - -#endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h deleted file mode 100644 index 21853b6eb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_GPIO_H_ -#define _TEGRA114_GPIO_H_ - -/* - * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> -#include <asm/arch-tegra30/gpio.h> - -#endif /* _TEGRA114_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/hardware.h deleted file mode 100644 index c21fbb625..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_HARDWARE_H_ -#define _TEGRA114_HARDWARE_H_ - -/* include tegra specific hardware definitions */ - -#endif /* _TEGRA114_HARDWARE_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h deleted file mode 100644 index c1cb3ef16..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA114_PINMUX_H_ -#define _TEGRA114_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_PINGRP_ULPI_DATA4_PO5, - PMUX_PINGRP_ULPI_DATA5_PO6, - PMUX_PINGRP_ULPI_DATA6_PO7, - PMUX_PINGRP_ULPI_DATA7_PO0, - PMUX_PINGRP_ULPI_CLK_PY0, - PMUX_PINGRP_ULPI_DIR_PY1, - PMUX_PINGRP_ULPI_NXT_PY2, - PMUX_PINGRP_ULPI_STP_PY3, - PMUX_PINGRP_DAP3_FS_PP0, - PMUX_PINGRP_DAP3_DIN_PP1, - PMUX_PINGRP_DAP3_DOUT_PP2, - PMUX_PINGRP_DAP3_SCLK_PP3, - PMUX_PINGRP_PV0, - PMUX_PINGRP_PV1, - PMUX_PINGRP_SDMMC1_CLK_PZ0, - PMUX_PINGRP_SDMMC1_CMD_PZ1, - PMUX_PINGRP_SDMMC1_DAT3_PY4, - PMUX_PINGRP_SDMMC1_DAT2_PY5, - PMUX_PINGRP_SDMMC1_DAT1_PY6, - PMUX_PINGRP_SDMMC1_DAT0_PY7, - PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), - PMUX_PINGRP_CLK2_REQ_PCC5, - PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), - PMUX_PINGRP_DDC_SCL_PV4, - PMUX_PINGRP_DDC_SDA_PV5, - PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), - PMUX_PINGRP_UART2_TXD_PC2, - PMUX_PINGRP_UART2_RTS_N_PJ6, - PMUX_PINGRP_UART2_CTS_N_PJ5, - PMUX_PINGRP_UART3_TXD_PW6, - PMUX_PINGRP_UART3_RXD_PW7, - PMUX_PINGRP_UART3_CTS_N_PA1, - PMUX_PINGRP_UART3_RTS_N_PC0, - PMUX_PINGRP_PU0, - PMUX_PINGRP_PU1, - PMUX_PINGRP_PU2, - PMUX_PINGRP_PU3, - PMUX_PINGRP_PU4, - PMUX_PINGRP_PU5, - PMUX_PINGRP_PU6, - PMUX_PINGRP_GEN1_I2C_SDA_PC5, - PMUX_PINGRP_GEN1_I2C_SCL_PC4, - PMUX_PINGRP_DAP4_FS_PP4, - PMUX_PINGRP_DAP4_DIN_PP5, - PMUX_PINGRP_DAP4_DOUT_PP6, - PMUX_PINGRP_DAP4_SCLK_PP7, - PMUX_PINGRP_CLK3_OUT_PEE0, - PMUX_PINGRP_CLK3_REQ_PEE1, - PMUX_PINGRP_GMI_WP_N_PC7, - PMUX_PINGRP_GMI_IORDY_PI5, - PMUX_PINGRP_GMI_WAIT_PI7, - PMUX_PINGRP_GMI_ADV_N_PK0, - PMUX_PINGRP_GMI_CLK_PK1, - PMUX_PINGRP_GMI_CS0_N_PJ0, - PMUX_PINGRP_GMI_CS1_N_PJ2, - PMUX_PINGRP_GMI_CS2_N_PK3, - PMUX_PINGRP_GMI_CS3_N_PK4, - PMUX_PINGRP_GMI_CS4_N_PK2, - PMUX_PINGRP_GMI_CS6_N_PI3, - PMUX_PINGRP_GMI_CS7_N_PI6, - PMUX_PINGRP_GMI_AD0_PG0, - PMUX_PINGRP_GMI_AD1_PG1, - PMUX_PINGRP_GMI_AD2_PG2, - PMUX_PINGRP_GMI_AD3_PG3, - PMUX_PINGRP_GMI_AD4_PG4, - PMUX_PINGRP_GMI_AD5_PG5, - PMUX_PINGRP_GMI_AD6_PG6, - PMUX_PINGRP_GMI_AD7_PG7, - PMUX_PINGRP_GMI_AD8_PH0, - PMUX_PINGRP_GMI_AD9_PH1, - PMUX_PINGRP_GMI_AD10_PH2, - PMUX_PINGRP_GMI_AD11_PH3, - PMUX_PINGRP_GMI_AD12_PH4, - PMUX_PINGRP_GMI_AD13_PH5, - PMUX_PINGRP_GMI_AD14_PH6, - PMUX_PINGRP_GMI_AD15_PH7, - PMUX_PINGRP_GMI_A16_PJ7, - PMUX_PINGRP_GMI_A17_PB0, - PMUX_PINGRP_GMI_A18_PB1, - PMUX_PINGRP_GMI_A19_PK7, - PMUX_PINGRP_GMI_WR_N_PI0, - PMUX_PINGRP_GMI_OE_N_PI1, - PMUX_PINGRP_GMI_DQS_P_PJ3, - PMUX_PINGRP_GMI_RST_N_PI4, - PMUX_PINGRP_GEN2_I2C_SCL_PT5, - PMUX_PINGRP_GEN2_I2C_SDA_PT6, - PMUX_PINGRP_SDMMC4_CLK_PCC4, - PMUX_PINGRP_SDMMC4_CMD_PT7, - PMUX_PINGRP_SDMMC4_DAT0_PAA0, - PMUX_PINGRP_SDMMC4_DAT1_PAA1, - PMUX_PINGRP_SDMMC4_DAT2_PAA2, - PMUX_PINGRP_SDMMC4_DAT3_PAA3, - PMUX_PINGRP_SDMMC4_DAT4_PAA4, - PMUX_PINGRP_SDMMC4_DAT5_PAA5, - PMUX_PINGRP_SDMMC4_DAT6_PAA6, - PMUX_PINGRP_SDMMC4_DAT7_PAA7, - PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), - PMUX_PINGRP_PCC1, - PMUX_PINGRP_PBB0, - PMUX_PINGRP_CAM_I2C_SCL_PBB1, - PMUX_PINGRP_CAM_I2C_SDA_PBB2, - PMUX_PINGRP_PBB3, - PMUX_PINGRP_PBB4, - PMUX_PINGRP_PBB5, - PMUX_PINGRP_PBB6, - PMUX_PINGRP_PBB7, - PMUX_PINGRP_PCC2, - PMUX_PINGRP_JTAG_RTCK, - PMUX_PINGRP_PWR_I2C_SCL_PZ6, - PMUX_PINGRP_PWR_I2C_SDA_PZ7, - PMUX_PINGRP_KB_ROW0_PR0, - PMUX_PINGRP_KB_ROW1_PR1, - PMUX_PINGRP_KB_ROW2_PR2, - PMUX_PINGRP_KB_ROW3_PR3, - PMUX_PINGRP_KB_ROW4_PR4, - PMUX_PINGRP_KB_ROW5_PR5, - PMUX_PINGRP_KB_ROW6_PR6, - PMUX_PINGRP_KB_ROW7_PR7, - PMUX_PINGRP_KB_ROW8_PS0, - PMUX_PINGRP_KB_ROW9_PS1, - PMUX_PINGRP_KB_ROW10_PS2, - PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4), - PMUX_PINGRP_KB_COL1_PQ1, - PMUX_PINGRP_KB_COL2_PQ2, - PMUX_PINGRP_KB_COL3_PQ3, - PMUX_PINGRP_KB_COL4_PQ4, - PMUX_PINGRP_KB_COL5_PQ5, - PMUX_PINGRP_KB_COL6_PQ6, - PMUX_PINGRP_KB_COL7_PQ7, - PMUX_PINGRP_CLK_32K_OUT_PA0, - PMUX_PINGRP_SYS_CLK_REQ_PZ5, - PMUX_PINGRP_CORE_PWR_REQ, - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_OWR, - PMUX_PINGRP_DAP1_FS_PN0, - PMUX_PINGRP_DAP1_DIN_PN1, - PMUX_PINGRP_DAP1_DOUT_PN2, - PMUX_PINGRP_DAP1_SCLK_PN3, - PMUX_PINGRP_CLK1_REQ_PEE2, - PMUX_PINGRP_CLK1_OUT_PW4, - PMUX_PINGRP_SPDIF_IN_PK6, - PMUX_PINGRP_SPDIF_OUT_PK5, - PMUX_PINGRP_DAP2_FS_PA2, - PMUX_PINGRP_DAP2_DIN_PA4, - PMUX_PINGRP_DAP2_DOUT_PA5, - PMUX_PINGRP_DAP2_SCLK_PA3, - PMUX_PINGRP_DVFS_PWM_PX0, - PMUX_PINGRP_GPIO_X1_AUD_PX1, - PMUX_PINGRP_GPIO_X3_AUD_PX3, - PMUX_PINGRP_DVFS_CLK_PX2, - PMUX_PINGRP_GPIO_X4_AUD_PX4, - PMUX_PINGRP_GPIO_X5_AUD_PX5, - PMUX_PINGRP_GPIO_X6_AUD_PX6, - PMUX_PINGRP_GPIO_X7_AUD_PX7, - PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), - PMUX_PINGRP_SDMMC3_CMD_PA7, - PMUX_PINGRP_SDMMC3_DAT0_PB7, - PMUX_PINGRP_SDMMC3_DAT1_PB6, - PMUX_PINGRP_SDMMC3_DAT2_PB5, - PMUX_PINGRP_SDMMC3_DAT3_PB4, - PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), - PMUX_PINGRP_SDMMC1_WP_N_PV3, - PMUX_PINGRP_SDMMC3_CD_N_PV2, - PMUX_PINGRP_GPIO_W2_AUD_PW2, - PMUX_PINGRP_GPIO_W3_AUD_PW3, - PMUX_PINGRP_USB_VBUS_EN0_PN4, - PMUX_PINGRP_USB_VBUS_EN1_PN5, - PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, - PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, - PMUX_PINGRP_GMI_CLK_LB, - PMUX_PINGRP_RESET_OUT_N, - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_AO1, - PMUX_DRVGRP_AO2, - PMUX_DRVGRP_AT1, - PMUX_DRVGRP_AT2, - PMUX_DRVGRP_AT3, - PMUX_DRVGRP_AT4, - PMUX_DRVGRP_AT5, - PMUX_DRVGRP_CDEV1, - PMUX_DRVGRP_CDEV2, - PMUX_DRVGRP_DAP1 = (0x28 / 4), - PMUX_DRVGRP_DAP2, - PMUX_DRVGRP_DAP3, - PMUX_DRVGRP_DAP4, - PMUX_DRVGRP_DBG, - PMUX_DRVGRP_SDIO3 = (0x48 / 4), - PMUX_DRVGRP_SPI, - PMUX_DRVGRP_UAA, - PMUX_DRVGRP_UAB, - PMUX_DRVGRP_UART2, - PMUX_DRVGRP_UART3, - PMUX_DRVGRP_SDIO1 = (0x84 / 4), - PMUX_DRVGRP_DDC = (0x94 / 4), - PMUX_DRVGRP_GMA, - PMUX_DRVGRP_GME = (0xa8 / 4), - PMUX_DRVGRP_GMF, - PMUX_DRVGRP_GMG, - PMUX_DRVGRP_GMH, - PMUX_DRVGRP_OWR, - PMUX_DRVGRP_UDA, - PMUX_DRVGRP_DEV3 = (0xc4 / 4), - PMUX_DRVGRP_CEC = (0xd0 / 4), - PMUX_DRVGRP_AT6 = (0x12c / 4), - PMUX_DRVGRP_DAP5, - PMUX_DRVGRP_USB_VBUS_EN, - PMUX_DRVGRP_AO3, - PMUX_DRVGRP_HV0, - PMUX_DRVGRP_SDIO4, - PMUX_DRVGRP_AO0, - PMUX_DRVGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_BLINK, - PMUX_FUNC_CEC, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_CLK, - PMUX_FUNC_CLK12, - PMUX_FUNC_CPU, - PMUX_FUNC_DAP, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DEV3, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYA_ALT, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DTV, - PMUX_FUNC_EMC_DLL, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_IRDA, - PMUX_FUNC_KBC, - PMUX_FUNC_NAND, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_OWR, - PMUX_FUNC_PMI, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_PWRON, - PMUX_FUNC_RESET_OUT_N, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SOC, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, - PMUX_FUNC_TRACE, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_ULPI, - PMUX_FUNC_USB, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VI, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_RCV_SEL -#define TEGRA_PMX_HAS_DRVGRPS -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pmu.h deleted file mode 100644 index c6e238101..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pmu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_PMU_H_ -#define _TEGRA114_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA114_PMU_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/spl.h deleted file mode 100644 index ebb16fe1d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h deleted file mode 100644 index c05e2c328..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_SYSCTR_H_ -#define _TEGRA114_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h deleted file mode 100644 index 705ca5758..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA114_H_ -#define _TEGRA114_H_ - -#define CONFIG_TEGRA114 - -#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 - -#endif /* TEGRA114_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra114_spi.h deleted file mode 100644 index 48197bc27..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra114_spi.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA114_SPI_H_ -#define _TEGRA114_SPI_H_ - -#include <asm/types.h> - -int tegra114_spi_init(int *node_list, int count); -int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra114_spi_free_slave(struct spi_slave *slave); -int tegra114_spi_claim_bus(struct spi_slave *slave); -void tegra114_spi_cs_activate(struct spi_slave *slave); -void tegra114_spi_cs_deactivate(struct spi_slave *slave); -int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA114_SPI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h deleted file mode 100644 index 4e48c43bb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_AHB_H_ -#define _TEGRA124_AHB_H_ - -struct ahb_ctlr { - u32 reserved0; /* 00h */ - u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ - u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ - u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ - u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ - u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ - u32 reserved6[2]; /* 18h, 1ch */ - u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ - u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ - u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ - u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ - u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ - u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ - u32 reserved13[2]; /* 38h, 3ch */ - u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ - u32 reserved15; /* 44h */ - u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ - u32 reserved17; /* 4ch */ - u32 gizmo_se; /* _GIZMO_SE_0, 50h */ - u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ - u32 reserved20[3]; /* 58h, 5ch, 60h */ - u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ - u32 reserved22[3]; /* 68h, 6ch, 70h */ - u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ - u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ - u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ - u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ - u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ - u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ - u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ - u32 reserved30[13]; /* 90h ~ c0h */ - u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ - u32 reserved32[5]; /* c8h ~ d8h */ - u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ - u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ - u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ - u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ - u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ - u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ - u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ - u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ - /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ - u32 arbitration_ahb_mem_wrque_mst_id; - u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ - u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ - u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ - u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ - u32 reserved46[4]; /* 110h ~ 11ch */ - u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ - u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ - u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ - u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ - u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ - u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ - /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ - u32 axicif_fastsync0_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ - u32 axicif_fastsync1_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ - u32 axicif_fastsync2_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ - u32 axicif_fastsync0_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ - u32 axicif_fastsync1_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ - u32 axicif_fastsync2_mcclk_to_cpuclk; -}; - -#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - -#endif /* _TEGRA124_AHB_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h deleted file mode 100644 index daf9a2b35..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra124 clock PLL tables */ - -#ifndef _TEGRA124_CLOCK_TABLES_H_ -#define _TEGRA124_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SoC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - - CLOCK_ID_COUNT, /* number of PLLs */ - - /* - * These are clock IDs that are used in table clock_source[][] - * but will not be assigned as a clock source for any peripheral. - */ - CLOCK_ID_DISPLAY2, - CLOCK_ID_CGENERAL2, - CLOCK_ID_CGENERAL3, - CLOCK_ID_MEMORY2, - CLOCK_ID_SRC2, - - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 (DEVICES_L) */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_ISPB, - PERIPH_ID_RESERVED4, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_RESERVED13, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TCW, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_RESERVED19, - PERIPH_ID_VI, - PERIPH_ID_RESERVED21, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_RESERVED24, - PERIPH_ID_RESERVED25, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S0, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 (DEVICES_H) */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_RESERVED36, - PERIPH_ID_STAT_MON, - PERIPH_ID_RESERVED38, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_I2C5, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_RESERVED49, - PERIPH_ID_HSI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_RESERVED53, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_MIPI_CAL, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_RESERVED60, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_RESERVED64, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_LA, - PERIPH_ID_TRACECLKIN, - PERIPH_ID_SOC_THERM, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_TSEC, - PERIPH_ID_RESERVED84, - PERIPH_ID_RESERVED85, - PERIPH_ID_RESERVED86, - PERIPH_ID_EMUCIF, - - /* 88 */ - PERIPH_ID_RESERVED88, - PERIPH_ID_XUSB_HOST, - PERIPH_ID_RESERVED90, - PERIPH_ID_MSENC, - PERIPH_ID_RESERVED92, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_XUSB_DEV, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_V_RESERVED2, - PERIPH_ID_MSELECT, - PERIPH_ID_V_RESERVED4, - PERIPH_ID_I2S3, - PERIPH_ID_I2S4, - PERIPH_ID_I2C4, - - /* 104 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AUDIO, - PERIPH_ID_APBIF, - PERIPH_ID_DAM0, - PERIPH_ID_DAM1, - PERIPH_ID_DAM2, - PERIPH_ID_HDA2CODEC2X, - - /* 112 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_V_RESERVED17, - PERIPH_ID_V_RESERVED18, - PERIPH_ID_V_RESERVED19, - PERIPH_ID_V_RESERVED20, - PERIPH_ID_V_RESERVED21, - PERIPH_ID_V_RESERVED22, - PERIPH_ID_ACTMON, - - /* 120 */ - PERIPH_ID_EXTPERIPH1, - PERIPH_ID_EXTPERIPH2, - PERIPH_ID_EXTPERIPH3, - PERIPH_ID_OOB, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_V_RESERVED30, - PERIPH_ID_V_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_SATACOLD, - PERIPH_ID_W_RESERVED2, - PERIPH_ID_W_RESERVED3, - PERIPH_ID_W_RESERVED4, - PERIPH_ID_W_RESERVED5, - PERIPH_ID_W_RESERVED6, - PERIPH_ID_W_RESERVED7, - - /* 136 */ - PERIPH_ID_CEC, - PERIPH_ID_W_RESERVED9, - PERIPH_ID_W_RESERVED10, - PERIPH_ID_W_RESERVED11, - PERIPH_ID_W_RESERVED12, - PERIPH_ID_W_RESERVED13, - PERIPH_ID_XUSB_PADCTL, - PERIPH_ID_W_RESERVED15, - - /* 144 */ - PERIPH_ID_W_RESERVED16, - PERIPH_ID_W_RESERVED17, - PERIPH_ID_W_RESERVED18, - PERIPH_ID_W_RESERVED19, - PERIPH_ID_W_RESERVED20, - PERIPH_ID_ENTROPY, - PERIPH_ID_DDS, - PERIPH_ID_W_RESERVED23, - - /* 152 */ - PERIPH_ID_DP2, - PERIPH_ID_AMX0, - PERIPH_ID_ADX0, - PERIPH_ID_DVFS, - PERIPH_ID_XUSB_SS, - PERIPH_ID_W_RESERVED29, - PERIPH_ID_W_RESERVED30, - PERIPH_ID_W_RESERVED31, - - PERIPH_ID_X_FIRST, - /* X word: 31:0 */ - PERIPH_ID_SPARE = PERIPH_ID_X_FIRST, - PERIPH_ID_X_RESERVED1, - PERIPH_ID_X_RESERVED2, - PERIPH_ID_X_RESERVED3, - PERIPH_ID_CAM_MCLK, - PERIPH_ID_CAM_MCLK2, - PERIPH_ID_I2C6, - PERIPH_ID_X_RESERVED7, - - /* 168 */ - PERIPH_ID_X_RESERVED8, - PERIPH_ID_X_RESERVED9, - PERIPH_ID_X_RESERVED10, - PERIPH_ID_VIM2_CLK, - PERIPH_ID_X_RESERVED12, - PERIPH_ID_X_RESERVED13, - PERIPH_ID_EMC_DLL, - PERIPH_ID_X_RESERVED15, - - /* 176 */ - PERIPH_ID_HDMI_AUDIO, - PERIPH_ID_CLK72MHZ, - PERIPH_ID_VIC, - PERIPH_ID_X_RESERVED19, - PERIPH_ID_ADX1, - PERIPH_ID_DPAUX, - PERIPH_ID_SOR0, - PERIPH_ID_X_RESERVED23, - - /* 184 */ - PERIPH_ID_GPU, - PERIPH_ID_AMX1, - PERIPH_ID_X_RESERVED26, - PERIPH_ID_X_RESERVED27, - PERIPH_ID_X_RESERVED28, - PERIPH_ID_X_RESERVED29, - PERIPH_ID_X_RESERVED30, - PERIPH_ID_X_RESERVED31, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S1, - PERIPHC_I2S2, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_I2C5, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_10h, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_18h, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_1Bh, - PERIPHC_1Ch, - PERIPHC_HSI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_22h, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_25h, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S0, - PERIPHC_DTV, - - /* 0x38 */ - PERIPHC_38h, - PERIPHC_39h, - PERIPHC_3ah, - PERIPHC_3bh, - PERIPHC_MSENC, - PERIPHC_TSEC, - PERIPHC_3eh, - PERIPHC_OSC, - - PERIPHC_VW_FIRST, - /* 0x40 */ - PERIPHC_40h = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S3, - PERIPHC_I2S4, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x48 */ - PERIPHC_AUDIO, - PERIPHC_49h, - PERIPHC_DAM0, - PERIPHC_DAM1, - PERIPHC_DAM2, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x50 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_52h, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_55h, - PERIPHC_56h, - PERIPHC_57h, - - /* 0x58 */ - PERIPHC_58h, - PERIPHC_59h, - PERIPHC_5ah, - PERIPHC_5bh, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, /* 0x428 */ - PERIPHC_5fh, - - PERIPHC_X_FIRST, - /* 0x60 */ - PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */ - PERIPHC_XUSB_FALCON, - PERIPHC_XUSB_FS, - PERIPHC_XUSB_CORE_DEV, - PERIPHC_XUSB_SS, - PERIPHC_CILAB, - PERIPHC_CILCD, - PERIPHC_CILE, - - /* 0x68 */ - PERIPHC_DSIA_LP, - PERIPHC_DSIB_LP, - PERIPHC_ENTROPY, - PERIPHC_DVFS_REF, - PERIPHC_DVFS_SOC, - PERIPHC_TRACECLKIN, - PERIPHC_ADX0, - PERIPHC_AMX0, - - /* 0x70 */ - PERIPHC_EMC_LATENCY, - PERIPHC_SOC_THERM, - PERIPHC_72h, - PERIPHC_73h, - PERIPHC_74h, - PERIPHC_75h, - PERIPHC_VI_SENSOR2, - PERIPHC_I2C6, - - /* 0x78 */ - PERIPHC_78h, - PERIPHC_EMC_DLL, - PERIPHC_HDMI_AUDIO, - PERIPHC_CLK72MHZ, - PERIPHC_ADX1, - PERIPHC_AMX1, - PERIPHC_VIC, - PERIPHC_7fh, - - PERIPHC_COUNT, - - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA124_CLOCK_TABLES_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h deleted file mode 100644 index 8e39d21a7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra124 clock control definitions */ - -#ifndef _TEGRA124_CLOCK_H_ -#define _TEGRA124_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -#endif /* _TEGRA124_CLOCK_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h deleted file mode 100644 index 0db1881bc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_FLOW_H_ -#define _TEGRA124_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; /* offset 0x00 */ - u32 halt_cop_events; /* offset 0x04 */ - u32 cpu_csr; /* offset 0x08 */ - u32 cop_csr; /* offset 0x0c */ - u32 xrq_events; /* offset 0x10 */ - u32 halt_cpu1_events; /* offset 0x14 */ - u32 cpu1_csr; /* offset 0x18 */ - u32 halt_cpu2_events; /* offset 0x1c */ - u32 cpu2_csr; /* offset 0x20 */ - u32 halt_cpu3_events; /* offset 0x24 */ - u32 cpu3_csr; /* offset 0x28 */ - u32 cluster_control; /* offset 0x2c */ - u32 halt_cop1_events; /* offset 0x30 */ - u32 halt_cop1_csr; /* offset 0x34 */ - u32 cpu_pwr_csr; /* offset 0x38 */ - u32 mpid; /* offset 0x3c */ - u32 ram_repair; /* offset 0x40 */ -}; - -/* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) -#define EVENT_MODE_STOP (2 << 29) - -/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - -#endif /* _TEGRA124_FLOW_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h deleted file mode 100644 index df94d135f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra124 high-level function multiplexing */ - -#ifndef _TEGRA124_FUNCMUX_H_ -#define _TEGRA124_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_KBC = 0, - FUNCMUX_UART4_GPIO = 0, -}; -#endif /* _TEGRA124_FUNCMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h deleted file mode 100644 index 440cbbfa3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_GP_PADCTRL_H_ -#define _TEGRA124_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 - -#endif /* _TEGRA124_GP_PADCTRL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h deleted file mode 100644 index 1a6dcb871..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_GPIO_H_ -#define _TEGRA124_GPIO_H_ - -/* - * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, - GPIO_PFF0, /* pin 248 */ - GPIO_PFF1, - GPIO_PFF2, - GPIO_PFF3, - GPIO_PFF4, - GPIO_PFF5, - GPIO_PFF6, - GPIO_PFF7, /* pin 255 */ -}; - -#endif /* _TEGRA124_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/hardware.h deleted file mode 100644 index 114fce8ad..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/hardware.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_HARDWARE_H_ -#define _TEGRA124_HARDWARE_H_ - -/* - * Include Tegra-specific hardware definitions - * Nothing needed currently for Tegra124 - */ - -#endif /* _TEGRA124_HARDWARE_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h deleted file mode 100644 index c49801c21..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_PINMUX_H_ -#define _TEGRA124_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_PINGRP_ULPI_DATA4_PO5, - PMUX_PINGRP_ULPI_DATA5_PO6, - PMUX_PINGRP_ULPI_DATA6_PO7, - PMUX_PINGRP_ULPI_DATA7_PO0, - PMUX_PINGRP_ULPI_CLK_PY0, - PMUX_PINGRP_ULPI_DIR_PY1, - PMUX_PINGRP_ULPI_NXT_PY2, - PMUX_PINGRP_ULPI_STP_PY3, - PMUX_PINGRP_DAP3_FS_PP0, - PMUX_PINGRP_DAP3_DIN_PP1, - PMUX_PINGRP_DAP3_DOUT_PP2, - PMUX_PINGRP_DAP3_SCLK_PP3, - PMUX_PINGRP_PV0, - PMUX_PINGRP_PV1, - PMUX_PINGRP_SDMMC1_CLK_PZ0, - PMUX_PINGRP_SDMMC1_CMD_PZ1, - PMUX_PINGRP_SDMMC1_DAT3_PY4, - PMUX_PINGRP_SDMMC1_DAT2_PY5, - PMUX_PINGRP_SDMMC1_DAT1_PY6, - PMUX_PINGRP_SDMMC1_DAT0_PY7, - PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), - PMUX_PINGRP_CLK2_REQ_PCC5, - PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), - PMUX_PINGRP_DDC_SCL_PV4, - PMUX_PINGRP_DDC_SDA_PV5, - PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), - PMUX_PINGRP_UART2_TXD_PC2, - PMUX_PINGRP_UART2_RTS_N_PJ6, - PMUX_PINGRP_UART2_CTS_N_PJ5, - PMUX_PINGRP_UART3_TXD_PW6, - PMUX_PINGRP_UART3_RXD_PW7, - PMUX_PINGRP_UART3_CTS_N_PA1, - PMUX_PINGRP_UART3_RTS_N_PC0, - PMUX_PINGRP_PU0, - PMUX_PINGRP_PU1, - PMUX_PINGRP_PU2, - PMUX_PINGRP_PU3, - PMUX_PINGRP_PU4, - PMUX_PINGRP_PU5, - PMUX_PINGRP_PU6, - PMUX_PINGRP_GEN1_I2C_SDA_PC5, - PMUX_PINGRP_GEN1_I2C_SCL_PC4, - PMUX_PINGRP_DAP4_FS_PP4, - PMUX_PINGRP_DAP4_DIN_PP5, - PMUX_PINGRP_DAP4_DOUT_PP6, - PMUX_PINGRP_DAP4_SCLK_PP7, - PMUX_PINGRP_CLK3_OUT_PEE0, - PMUX_PINGRP_CLK3_REQ_PEE1, - PMUX_PINGRP_PC7, - PMUX_PINGRP_PI5, - PMUX_PINGRP_PI7, - PMUX_PINGRP_PK0, - PMUX_PINGRP_PK1, - PMUX_PINGRP_PJ0, - PMUX_PINGRP_PJ2, - PMUX_PINGRP_PK3, - PMUX_PINGRP_PK4, - PMUX_PINGRP_PK2, - PMUX_PINGRP_PI3, - PMUX_PINGRP_PI6, - PMUX_PINGRP_PG0, - PMUX_PINGRP_PG1, - PMUX_PINGRP_PG2, - PMUX_PINGRP_PG3, - PMUX_PINGRP_PG4, - PMUX_PINGRP_PG5, - PMUX_PINGRP_PG6, - PMUX_PINGRP_PG7, - PMUX_PINGRP_PH0, - PMUX_PINGRP_PH1, - PMUX_PINGRP_PH2, - PMUX_PINGRP_PH3, - PMUX_PINGRP_PH4, - PMUX_PINGRP_PH5, - PMUX_PINGRP_PH6, - PMUX_PINGRP_PH7, - PMUX_PINGRP_PJ7, - PMUX_PINGRP_PB0, - PMUX_PINGRP_PB1, - PMUX_PINGRP_PK7, - PMUX_PINGRP_PI0, - PMUX_PINGRP_PI1, - PMUX_PINGRP_PI2, - PMUX_PINGRP_PI4, - PMUX_PINGRP_GEN2_I2C_SCL_PT5, - PMUX_PINGRP_GEN2_I2C_SDA_PT6, - PMUX_PINGRP_SDMMC4_CLK_PCC4, - PMUX_PINGRP_SDMMC4_CMD_PT7, - PMUX_PINGRP_SDMMC4_DAT0_PAA0, - PMUX_PINGRP_SDMMC4_DAT1_PAA1, - PMUX_PINGRP_SDMMC4_DAT2_PAA2, - PMUX_PINGRP_SDMMC4_DAT3_PAA3, - PMUX_PINGRP_SDMMC4_DAT4_PAA4, - PMUX_PINGRP_SDMMC4_DAT5_PAA5, - PMUX_PINGRP_SDMMC4_DAT6_PAA6, - PMUX_PINGRP_SDMMC4_DAT7_PAA7, - PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), - PMUX_PINGRP_PCC1, - PMUX_PINGRP_PBB0, - PMUX_PINGRP_CAM_I2C_SCL_PBB1, - PMUX_PINGRP_CAM_I2C_SDA_PBB2, - PMUX_PINGRP_PBB3, - PMUX_PINGRP_PBB4, - PMUX_PINGRP_PBB5, - PMUX_PINGRP_PBB6, - PMUX_PINGRP_PBB7, - PMUX_PINGRP_PCC2, - PMUX_PINGRP_JTAG_RTCK, - PMUX_PINGRP_PWR_I2C_SCL_PZ6, - PMUX_PINGRP_PWR_I2C_SDA_PZ7, - PMUX_PINGRP_KB_ROW0_PR0, - PMUX_PINGRP_KB_ROW1_PR1, - PMUX_PINGRP_KB_ROW2_PR2, - PMUX_PINGRP_KB_ROW3_PR3, - PMUX_PINGRP_KB_ROW4_PR4, - PMUX_PINGRP_KB_ROW5_PR5, - PMUX_PINGRP_KB_ROW6_PR6, - PMUX_PINGRP_KB_ROW7_PR7, - PMUX_PINGRP_KB_ROW8_PS0, - PMUX_PINGRP_KB_ROW9_PS1, - PMUX_PINGRP_KB_ROW10_PS2, - PMUX_PINGRP_KB_ROW11_PS3, - PMUX_PINGRP_KB_ROW12_PS4, - PMUX_PINGRP_KB_ROW13_PS5, - PMUX_PINGRP_KB_ROW14_PS6, - PMUX_PINGRP_KB_ROW15_PS7, - PMUX_PINGRP_KB_COL0_PQ0, - PMUX_PINGRP_KB_COL1_PQ1, - PMUX_PINGRP_KB_COL2_PQ2, - PMUX_PINGRP_KB_COL3_PQ3, - PMUX_PINGRP_KB_COL4_PQ4, - PMUX_PINGRP_KB_COL5_PQ5, - PMUX_PINGRP_KB_COL6_PQ6, - PMUX_PINGRP_KB_COL7_PQ7, - PMUX_PINGRP_CLK_32K_OUT_PA0, - PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4), - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_OWR, - PMUX_PINGRP_DAP1_FS_PN0, - PMUX_PINGRP_DAP1_DIN_PN1, - PMUX_PINGRP_DAP1_DOUT_PN2, - PMUX_PINGRP_DAP1_SCLK_PN3, - PMUX_PINGRP_DAP_MCLK1_REQ_PEE2, - PMUX_PINGRP_DAP_MCLK1_PW4, - PMUX_PINGRP_SPDIF_IN_PK6, - PMUX_PINGRP_SPDIF_OUT_PK5, - PMUX_PINGRP_DAP2_FS_PA2, - PMUX_PINGRP_DAP2_DIN_PA4, - PMUX_PINGRP_DAP2_DOUT_PA5, - PMUX_PINGRP_DAP2_SCLK_PA3, - PMUX_PINGRP_DVFS_PWM_PX0, - PMUX_PINGRP_GPIO_X1_AUD_PX1, - PMUX_PINGRP_GPIO_X3_AUD_PX3, - PMUX_PINGRP_DVFS_CLK_PX2, - PMUX_PINGRP_GPIO_X4_AUD_PX4, - PMUX_PINGRP_GPIO_X5_AUD_PX5, - PMUX_PINGRP_GPIO_X6_AUD_PX6, - PMUX_PINGRP_GPIO_X7_AUD_PX7, - PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), - PMUX_PINGRP_SDMMC3_CMD_PA7, - PMUX_PINGRP_SDMMC3_DAT0_PB7, - PMUX_PINGRP_SDMMC3_DAT1_PB6, - PMUX_PINGRP_SDMMC3_DAT2_PB5, - PMUX_PINGRP_SDMMC3_DAT3_PB4, - PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4), - PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, - PMUX_PINGRP_PEX_WAKE_N_PDD3, - PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4), - PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, - PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), - PMUX_PINGRP_SDMMC1_WP_N_PV3, - PMUX_PINGRP_SDMMC3_CD_N_PV2, - PMUX_PINGRP_GPIO_W2_AUD_PW2, - PMUX_PINGRP_GPIO_W3_AUD_PW3, - PMUX_PINGRP_USB_VBUS_EN0_PN4, - PMUX_PINGRP_USB_VBUS_EN1_PN5, - PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, - PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, - PMUX_PINGRP_GMI_CLK_LB, - PMUX_PINGRP_RESET_OUT_N, - PMUX_PINGRP_KB_ROW16_PT0, - PMUX_PINGRP_KB_ROW17_PT1, - PMUX_PINGRP_USB_VBUS_EN2_PFF1, - PMUX_PINGRP_PFF2, - PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4), - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_AO1, - PMUX_DRVGRP_AO2, - PMUX_DRVGRP_AT1, - PMUX_DRVGRP_AT2, - PMUX_DRVGRP_AT3, - PMUX_DRVGRP_AT4, - PMUX_DRVGRP_AT5, - PMUX_DRVGRP_CDEV1, - PMUX_DRVGRP_CDEV2, - PMUX_DRVGRP_DAP1 = (0x28 / 4), - PMUX_DRVGRP_DAP2, - PMUX_DRVGRP_DAP3, - PMUX_DRVGRP_DAP4, - PMUX_DRVGRP_DBG, - PMUX_DRVGRP_SDIO3 = (0x48 / 4), - PMUX_DRVGRP_SPI, - PMUX_DRVGRP_UAA, - PMUX_DRVGRP_UAB, - PMUX_DRVGRP_UART2, - PMUX_DRVGRP_UART3, - PMUX_DRVGRP_SDIO1 = (0x84 / 4), - PMUX_DRVGRP_DDC = (0x94 / 4), - PMUX_DRVGRP_GMA, - PMUX_DRVGRP_GME = (0xa8 / 4), - PMUX_DRVGRP_GMF, - PMUX_DRVGRP_GMG, - PMUX_DRVGRP_GMH, - PMUX_DRVGRP_OWR, - PMUX_DRVGRP_UDA, - PMUX_DRVGRP_GPV, - PMUX_DRVGRP_DEV3, - PMUX_DRVGRP_CEC = (0xd0 / 4), - PMUX_DRVGRP_AT6 = (0x12c / 4), - PMUX_DRVGRP_DAP5, - PMUX_DRVGRP_USB_VBUS_EN, - PMUX_DRVGRP_AO3 = (0x140 / 4), - PMUX_DRVGRP_AO0 = (0x148 / 4), - PMUX_DRVGRP_HV0, - PMUX_DRVGRP_SDIO4 = (0x15c / 4), - PMUX_DRVGRP_AO4, - PMUX_DRVGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_BLINK, - PMUX_FUNC_CCLA, - PMUX_FUNC_CEC, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_CLK, - PMUX_FUNC_CLK12, - PMUX_FUNC_CPU, - PMUX_FUNC_DAP, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DEV3, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYA_ALT, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DP, - PMUX_FUNC_DTV, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_IRDA, - PMUX_FUNC_KBC, - PMUX_FUNC_OWR, - PMUX_FUNC_PE, - PMUX_FUNC_PE0, - PMUX_FUNC_PE1, - PMUX_FUNC_PMI, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_PWRON, - PMUX_FUNC_RESET_OUT_N, - PMUX_FUNC_RTCK, - PMUX_FUNC_SATA, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SOC, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYS, - PMUX_FUNC_TMDS, - PMUX_FUNC_TRACE, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_ULPI, - PMUX_FUNC_USB, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VI, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_VIMCLK2, - PMUX_FUNC_VIMCLK2_ALT, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_RCV_SEL -#define TEGRA_PMX_HAS_DRVGRPS -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pmu.h deleted file mode 100644 index b10100a63..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pmu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_PMU_H_ -#define _TEGRA124_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA124_PMU_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/spl.h deleted file mode 100644 index e2663954b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif /* _ASM_ARCH_SPL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h deleted file mode 100644 index 3f0309b78..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_SYSCTR_H_ -#define _TEGRA124_SYSCTR_H_ - -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ - -#endif /* _TEGRA124_SYSCTR_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h deleted file mode 100644 index 86ebd1945..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_H_ -#define _TEGRA124_H_ - -#define CONFIG_TEGRA124 - -#define NV_PA_SDRAM_BASE 0x80000000 -#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ -#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */ -#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */ - -#include <asm/arch-tegra/tegra.h> - -#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */ - -#undef NVBOOTINFOTABLE_BCTSIZE -#undef NVBOOTINFOTABLE_BCTPTR -#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ - -#define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000 - -#endif /* _TEGRA124_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h deleted file mode 100644 index a09cb0197..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 clock PLL tables */ - -#ifndef _CLOCK_TABLES_H_ -#define _CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - - CLOCK_ID_COUNT, /* number of clocks */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_RESERVED1, - PERIPH_ID_RESERVED2, - PERIPH_ID_AC97, - PERIPH_ID_RTC, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TWC, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_IDE, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_RESERVED30, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_SPI1, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_DVC_I2C, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_RESERVED74, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_RESERVED79, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_RESERVED81, - PERIPH_ID_RESERVED82, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_SYNC_CLK_DOUBLER, - PERIPH_ID_CLK_M_DOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUS_OUT, - PERIPH_ID_DEV2_OUT, - PERIPH_ID_DEV1_OUT, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ -#define PERIPH_REG(id) ((id) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range, and not a simple PLL */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ - (id) < CLOCK_ID_FIRST_SIMPLE) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _CLOCK_TABLES_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h deleted file mode 100644 index 889c65a16..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 clock control functions */ - -#ifndef _TEGRA20_CLOCK_H -#define _TEGRA20_CLOCK_H - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 30 -#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) - -#endif /* _TEGRA20_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/dc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/dc.h deleted file mode 100644 index 20790b6c0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/dc.h +++ /dev/null @@ -1,529 +0,0 @@ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA_DC_H -#define __ASM_ARCH_TEGRA_DC_H - -/* Register definitions for the Tegra display controller */ - -/* CMD register 0x000 ~ 0x43 */ -struct dc_cmd_reg { - /* Address 0x000 ~ 0x002 */ - uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ - uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ - uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ - - uint reserved0[5]; /* reserved_0[5] */ - - /* Address 0x008 ~ 0x00a */ - uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ - uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ - uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ - - uint reserved1[5]; /* reserved_1[5] */ - - /* Address 0x010 ~ 0x012 */ - uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ - uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ - uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ - - uint reserved2[5]; /* reserved_2[5] */ - - /* Address 0x018 ~ 0x01a */ - uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ - uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ - uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ - - uint reserved3[13]; /* reserved_3[13] */ - - /* Address 0x028 */ - uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ - - uint reserved4[7]; /* reserved_4[7] */ - - /* Address 0x030 ~ 0x033 */ - uint ctxsw; /* _CMD_CTXSW_0 */ - uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ - uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ - uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */ - - uint reserved5[2]; /* reserved_0[2] */ - - /* Address 0x036 ~ 0x03e */ - uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ - uint int_stat; /* _CMD_INT_STATUS_0 */ - uint int_mask; /* _CMD_INT_MASK_0 */ - uint int_enb; /* _CMD_INT_ENABLE_0 */ - uint int_type; /* _CMD_INT_TYPE_0 */ - uint int_polarity; /* _CMD_INT_POLARITY_0 */ - uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ - uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ - uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ - - uint reserved6; /* reserved_6 */ - - /* Address 0x040 ~ 0x043 */ - uint state_access; /* _CMD_STATE_ACCESS_0 */ - uint state_ctrl; /* _CMD_STATE_CONTROL_0 */ - uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ - uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ -}; - -enum { - PIN_REG_COUNT = 4, - PIN_OUTPUT_SEL_COUNT = 7, -}; - -/* COM register 0x300 ~ 0x329 */ -struct dc_com_reg { - /* Address 0x300 ~ 0x301 */ - uint crc_ctrl; /* _COM_CRC_CONTROL_0 */ - uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */ - - /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ - uint pin_output_enb[PIN_REG_COUNT]; - - /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ - uint pin_output_polarity[PIN_REG_COUNT]; - - /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ - uint pin_output_data[PIN_REG_COUNT]; - - /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ - uint pin_input_enb[PIN_REG_COUNT]; - - /* Address 0x312 ~ 0x313 */ - uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ - uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ - - /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ - uint pin_output_sel[PIN_OUTPUT_SEL_COUNT]; - - /* Address 0x31b ~ 0x329 */ - uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ - uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */ - uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ - uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */ - uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ - uint spi_ctrl; /* _COM_SPI_CONTROL_0 */ - uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */ - uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ - uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ - uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ - uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ - uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ - uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */ - uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ - uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ -}; - -enum dc_disp_h_pulse_pos { - H_PULSE0_POSITION_A, - H_PULSE0_POSITION_B, - H_PULSE0_POSITION_C, - H_PULSE0_POSITION_D, - H_PULSE0_POSITION_COUNT, -}; - -struct _disp_h_pulse { - /* _DISP_H_PULSE0/1/2_CONTROL_0 */ - uint h_pulse_ctrl; - /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ - uint h_pulse_pos[H_PULSE0_POSITION_COUNT]; -}; - -enum dc_disp_v_pulse_pos { - V_PULSE0_POSITION_A, - V_PULSE0_POSITION_B, - V_PULSE0_POSITION_C, - V_PULSE0_POSITION_COUNT, -}; - -struct _disp_v_pulse0 { - /* _DISP_H_PULSE0/1_CONTROL_0 */ - uint v_pulse_ctrl; - /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ - uint v_pulse_pos[V_PULSE0_POSITION_COUNT]; -}; - -struct _disp_v_pulse2 { - /* _DISP_H_PULSE2/3_CONTROL_0 */ - uint v_pulse_ctrl; - /* _DISP_H_PULSE2/3_POSITION_A_0 */ - uint v_pulse_pos_a; -}; - -enum dc_disp_h_pulse_reg { - H_PULSE0, - H_PULSE1, - H_PULSE2, - H_PULSE_COUNT, -}; - -enum dc_disp_pp_select { - PP_SELECT_A, - PP_SELECT_B, - PP_SELECT_C, - PP_SELECT_D, - PP_SELECT_COUNT, -}; - -/* DISP register 0x400 ~ 0x4c1 */ -struct dc_disp_reg { - /* Address 0x400 ~ 0x40a */ - uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ - uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ - uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ - uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ - uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ - uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ - uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ - uint sync_width; /* _DISP_SYNC_WIDTH_0 */ - uint back_porch; /* _DISP_BACK_PORCH_0 */ - uint disp_active; /* _DISP_DISP_ACTIVE_0 */ - uint front_porch; /* _DISP_FRONT_PORCH_0 */ - - /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ - struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; - - /* Address 0x41a ~ 0x421 */ - struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ - struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ - - /* Address 0x422 ~ 0x425 */ - struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ - struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ - - /* Address 0x426 ~ 0x429 */ - uint m0_ctrl; /* _DISP_M0_CONTROL_0 */ - uint m1_ctrl; /* _DISP_M1_CONTROL_0 */ - uint di_ctrl; /* _DISP_DI_CONTROL_0 */ - uint pp_ctrl; /* _DISP_PP_CONTROL_0 */ - - /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ - uint pp_select[PP_SELECT_COUNT]; - - /* Address 0x42e ~ 0x435 */ - uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ - uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ - uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ - uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ - uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ - uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ - uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ - uint border_color; /* _DISP_BORDER_COLOR_0 */ - - /* Address 0x436 ~ 0x439 */ - uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ - uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ - uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ - uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ - - uint reserved0[2]; /* reserved_0[2] */ - - /* Address 0x43c ~ 0x442 */ - uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ - uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ - uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ - uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ - uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */ - uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ - uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ - - /* Address 0x442 ~ 0x446 */ - uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ - uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ - uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ - uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ - - uint reserved1[0x39]; /* reserved1[0x39], */ - - /* Address 0x480 ~ 0x484 */ - uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ - uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ - uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ - uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ - uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ - - uint reserved2[0x3b]; /* reserved2[0x3b] */ - - /* Address 0x4c0 ~ 0x4c1 */ - uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ - uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ -}; - -enum dc_winc_filter_p { - WINC_FILTER_COUNT = 0x10, -}; - -/* Window A/B/C register 0x500 ~ 0x628 */ -struct dc_winc_reg { - - /* Address 0x500 */ - uint color_palette; /* _WINC_COLOR_PALETTE_0 */ - - uint reserved0[0xff]; /* reserved_0[0xff] */ - - /* Address 0x600 */ - uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ - - /* _WINC_H_FILTER_P00~0F_0 */ - /* Address 0x601 ~ 0x610 */ - uint h_filter_p[WINC_FILTER_COUNT]; - - /* Address 0x611 ~ 0x618 */ - uint csc_yof; /* _WINC_CSC_YOF_0 */ - uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ - uint csc_kur; /* _WINC_CSC_KUR_0 */ - uint csc_kvr; /* _WINC_CSC_KVR_0 */ - uint csc_kug; /* _WINC_CSC_KUG_0 */ - uint csc_kvg; /* _WINC_CSC_KVG_0 */ - uint csc_kub; /* _WINC_CSC_KUB_0 */ - uint csc_kvb; /* _WINC_CSC_KVB_0 */ - - /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ - uint v_filter_p[WINC_FILTER_COUNT]; -}; - -/* WIN A/B/C Register 0x700 ~ 0x714*/ -struct dc_win_reg { - /* Address 0x700 ~ 0x714 */ - uint win_opt; /* _WIN_WIN_OPTIONS_0 */ - uint byte_swap; /* _WIN_BYTE_SWAP_0 */ - uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ - uint color_depth; /* _WIN_COLOR_DEPTH_0 */ - uint pos; /* _WIN_POSITION_0 */ - uint size; /* _WIN_SIZE_0 */ - uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ - uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ - uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ - uint dda_increment; /* _WIN_DDA_INCREMENT_0 */ - uint line_stride; /* _WIN_LINE_STRIDE_0 */ - uint buf_stride; /* _WIN_BUF_STRIDE_0 */ - uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ - uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ - uint dv_ctrl; /* _WIN_DV_CONTROL_0 */ - uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */ - uint blend_1win; /* _WIN_BLEND_1WIN_0 */ - uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ - uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ - uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ - uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ -}; - -/* WINBUF A/B/C Register 0x800 ~ 0x80a */ -struct dc_winbuf_reg { - /* Address 0x800 ~ 0x80a */ - uint start_addr; /* _WINBUF_START_ADDR_0 */ - uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ - uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */ - uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ - uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */ - uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ - uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ - uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ - uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ - uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ - uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ -}; - -/* Display Controller (DC_) regs */ -struct dc_ctlr { - struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ - uint reserved0[0x2bc]; - - struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ - uint reserved1[0xd6]; - - struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */ - uint reserved2[0x3e]; - - struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ - uint reserved3[0xd7]; - - struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/ - uint reserved4[0xeb]; - - struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */ -}; - -#define BIT(pos) (1U << pos) - -/* DC_CMD_DISPLAY_COMMAND 0x032 */ -#define CTRL_MODE_SHIFT 5 -#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) -enum { - CTRL_MODE_STOP, - CTRL_MODE_C_DISPLAY, - CTRL_MODE_NC_DISPLAY, -}; - -/* _WIN_COLOR_DEPTH_0 */ -enum win_color_depth_id { - COLOR_DEPTH_P1, - COLOR_DEPTH_P2, - COLOR_DEPTH_P4, - COLOR_DEPTH_P8, - COLOR_DEPTH_B4G4R4A4, - COLOR_DEPTH_B5G5R5A, - COLOR_DEPTH_B5G6R5, - COLOR_DEPTH_AB5G5R5, - COLOR_DEPTH_B8G8R8A8 = 12, - COLOR_DEPTH_R8G8B8A8, - COLOR_DEPTH_B6x2G6x2R6x2A8, - COLOR_DEPTH_R6x2G6x2B6x2A8, - COLOR_DEPTH_YCbCr422, - COLOR_DEPTH_YUV422, - COLOR_DEPTH_YCbCr420P, - COLOR_DEPTH_YUV420P, - COLOR_DEPTH_YCbCr422P, - COLOR_DEPTH_YUV422P, - COLOR_DEPTH_YCbCr422R, - COLOR_DEPTH_YUV422R, - COLOR_DEPTH_YCbCr422RA, - COLOR_DEPTH_YUV422RA, -}; - -/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ -#define PW0_ENABLE BIT(0) -#define PW1_ENABLE BIT(2) -#define PW2_ENABLE BIT(4) -#define PW3_ENABLE BIT(6) -#define PW4_ENABLE BIT(8) -#define PM0_ENABLE BIT(16) -#define PM1_ENABLE BIT(18) -#define SPI_ENABLE BIT(24) -#define HSPI_ENABLE BIT(25) - -/* DC_CMD_STATE_CONTROL 0x041 */ -#define GENERAL_ACT_REQ BIT(0) -#define WIN_A_ACT_REQ BIT(1) -#define WIN_B_ACT_REQ BIT(2) -#define WIN_C_ACT_REQ BIT(3) -#define GENERAL_UPDATE BIT(8) -#define WIN_A_UPDATE BIT(9) -#define WIN_B_UPDATE BIT(10) -#define WIN_C_UPDATE BIT(11) - -/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ -#define WINDOW_A_SELECT BIT(4) -#define WINDOW_B_SELECT BIT(5) -#define WINDOW_C_SELECT BIT(6) - -/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ -#define SHIFT_CLK_DIVIDER_SHIFT 0 -#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) -#define PIXEL_CLK_DIVIDER_SHIFT 8 -#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) -enum { - PIXEL_CLK_DIVIDER_PCD1, - PIXEL_CLK_DIVIDER_PCD1H, - PIXEL_CLK_DIVIDER_PCD2, - PIXEL_CLK_DIVIDER_PCD3, - PIXEL_CLK_DIVIDER_PCD4, - PIXEL_CLK_DIVIDER_PCD6, - PIXEL_CLK_DIVIDER_PCD8, - PIXEL_CLK_DIVIDER_PCD9, - PIXEL_CLK_DIVIDER_PCD12, - PIXEL_CLK_DIVIDER_PCD16, - PIXEL_CLK_DIVIDER_PCD18, - PIXEL_CLK_DIVIDER_PCD24, - PIXEL_CLK_DIVIDER_PCD13, -}; - -/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ -#define DATA_FORMAT_SHIFT 0 -#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) -enum { - DATA_FORMAT_DF1P1C, - DATA_FORMAT_DF1P2C24B, - DATA_FORMAT_DF1P2C18B, - DATA_FORMAT_DF1P2C16B, - DATA_FORMAT_DF2S, - DATA_FORMAT_DF3S, - DATA_FORMAT_DFSPI, - DATA_FORMAT_DF1P3C24B, - DATA_FORMAT_DF1P3C18B, -}; -#define DATA_ALIGNMENT_SHIFT 8 -enum { - DATA_ALIGNMENT_MSB, - DATA_ALIGNMENT_LSB, -}; -#define DATA_ORDER_SHIFT 9 -enum { - DATA_ORDER_RED_BLUE, - DATA_ORDER_BLUE_RED, -}; - -/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ -#define DE_SELECT_SHIFT 0 -#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) -#define DE_SELECT_ACTIVE_BLANK 0x0 -#define DE_SELECT_ACTIVE 0x1 -#define DE_SELECT_ACTIVE_IS 0x2 -#define DE_CONTROL_SHIFT 2 -#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) -enum { - DE_CONTROL_ONECLK, - DE_CONTROL_NORMAL, - DE_CONTROL_EARLY_EXT, - DE_CONTROL_EARLY, - DE_CONTROL_ACTIVE_BLANK, -}; - -/* DC_WIN_WIN_OPTIONS 0x700 */ -#define H_DIRECTION BIT(0) -enum { - H_DIRECTION_INCREMENT, - H_DIRECTION_DECREMENT, -}; -#define V_DIRECTION BIT(2) -enum { - V_DIRECTION_INCREMENT, - V_DIRECTION_DECREMENT, -}; -#define COLOR_EXPAND BIT(6) -#define CP_ENABLE BIT(16) -#define DV_ENABLE BIT(20) -#define WIN_ENABLE BIT(30) - -/* DC_WIN_BYTE_SWAP 0x701 */ -#define BYTE_SWAP_SHIFT 0 -#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) -enum { - BYTE_SWAP_NOSWAP, - BYTE_SWAP_SWAP2, - BYTE_SWAP_SWAP4, - BYTE_SWAP_SWAP4HW -}; - -/* DC_WIN_POSITION 0x704 */ -#define H_POSITION_SHIFT 0 -#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) -#define V_POSITION_SHIFT 16 -#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) - -/* DC_WIN_SIZE 0x705 */ -#define H_SIZE_SHIFT 0 -#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) -#define V_SIZE_SHIFT 16 -#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) - -/* DC_WIN_PRESCALED_SIZE 0x706 */ -#define H_PRESCALED_SIZE_SHIFT 0 -#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) -#define V_PRESCALED_SIZE_SHIFT 16 -#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) - -/* DC_WIN_DDA_INCREMENT 0x709 */ -#define H_DDA_INC_SHIFT 0 -#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) -#define V_DDA_INC_SHIFT 16 -#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) - -#endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h deleted file mode 100644 index a04c84e54..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch/dc.h> -#include <fdtdec.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned x; /* Horizontal address offset (bytes) */ - unsigned y; /* Veritical address offset (bytes) */ - unsigned w; /* Width of source window */ - unsigned h; /* Height of source window */ - unsigned stride; /* Number of bytes per line */ - unsigned out_x; /* Left edge of output window (col) */ - unsigned out_y; /* Top edge of output window (row) */ - unsigned out_w; /* Width of output window in pixels */ - unsigned out_h; /* Height of output window in pixels */ -}; - -#define FDT_LCD_TIMINGS 4 - -enum { - FDT_LCD_TIMING_REF_TO_SYNC, - FDT_LCD_TIMING_SYNC_WIDTH, - FDT_LCD_TIMING_BACK_PORCH, - FDT_LCD_TIMING_FRONT_PORCH, - - FDT_LCD_TIMING_COUNT, -}; - -enum lcd_cache_t { - FDT_LCD_CACHE_OFF = 0, - FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, - FDT_LCD_CACHE_WRITE_BACK = 1 << 1, - FDT_LCD_CACHE_FLUSH = 1 << 2, - FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | - FDT_LCD_CACHE_FLUSH, -}; - -/* Information about the display controller */ -struct fdt_disp_config { - int valid; /* config is valid */ - int width; /* width in pixels */ - int height; /* height in pixels */ - int bpp; /* number of bits per pixel */ - - /* - * log2 of number of bpp, in general, unless it bpp is 24 in which - * case this field holds 24 also! This is a U-Boot thing. - */ - int log2_bpp; - struct disp_ctlr *disp; /* Display controller to use */ - fdt_addr_t frame_buffer; /* Address of frame buffer */ - unsigned pixel_clock; /* Pixel clock in Hz */ - uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ - uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ - int panel_node; /* node offset of panel information */ -}; - -/* Information about the LCD panel */ -struct fdt_panel_config { - int pwm_channel; /* PWM channel to use for backlight */ - enum lcd_cache_t cache_type; - - struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */ - struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */ - struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */ - struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */ - /* - * Panel required timings - * Timing 1: delay between panel_vdd-rise and data-rise - * Timing 2: delay between data-rise and backlight_vdd-rise - * Timing 3: delay between backlight_vdd and pwm-rise - * Timing 4: delay between pwm-rise and backlight_en-rise - */ - uint panel_timings[FDT_LCD_TIMINGS]; -}; - -/** - * Register a new display based on device tree configuration. - * - * The frame buffer can be positioned by U-Boot or overriden by the fdt. - * You should pass in the U-Boot address here, and check the contents of - * struct fdt_disp_config to see what was actually chosen. - * - * @param blob Device tree blob - * @param default_lcd_base Default address of LCD frame buffer - * @return 0 if ok, -1 on error (unsupported bits per pixel) - */ -int tegra_display_probe(const void *blob, void *default_lcd_base); - -/** - * Return the current display configuration - * - * @return pointer to display configuration, or NULL if there is no valid - * config - */ -struct fdt_disp_config *tegra_display_get_config(void); - -/** - * Perform the next stage of the LCD init if it is time to do so. - * - * LCD init can be time-consuming because of the number of delays we need - * while waiting for the backlight power supply, etc. This function can - * be called at various times during U-Boot operation to advance the - * initialization of the LCD to the next stage if sufficient time has - * passed since the last stage. It keeps track of what stage it is up to - * and the time that it is permitted to move to the next stage. - * - * The final call should have wait=1 to complete the init. - * - * @param blob fdt blob containing LCD information - * @param wait 1 to wait until all init is complete, and then return - * 0 to return immediately, potentially doing nothing if it is - * not yet time for the next init. - */ -int tegra_lcd_check_next_stage(const void *blob, int wait); - -/** - * Set up the maximum LCD size so we can size the frame buffer. - * - * @param blob fdt blob containing LCD information - */ -void tegra_lcd_early_init(const void *blob); - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h deleted file mode 100644 index a85f4c3d8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ARCH_EMC_H_ -#define _ARCH_EMC_H_ - -#include <asm/types.h> - -#define TEGRA_EMC_NUM_REGS 46 - -/* EMC Registers */ -struct emc_ctlr { - u32 cfg; /* 0x00: EMC_CFG */ - u32 reserved0[3]; /* 0x04 ~ 0x0C */ - u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ - u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ - u32 reserved1[2]; /* 0x18 ~ 0x18 */ - u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ - u32 pin; /* 0x24: EMC_PIN */ - u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ - u32 rc; /* 0x2C: EMC_RC */ - u32 rfc; /* 0x30: EMC_RFC */ - u32 ras; /* 0x34: EMC_RAS */ - u32 rp; /* 0x38: EMC_RP */ - u32 r2w; /* 0x3C: EMC_R2W */ - u32 w2r; /* 0x40: EMC_W2R */ - u32 r2p; /* 0x44: EMC_R2P */ - u32 w2p; /* 0x48: EMC_W2P */ - u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ - u32 wd_rcd; /* 0x50: EMC_WD_RCD */ - u32 rrd; /* 0x54: EMC_RRD */ - u32 rext; /* 0x58: EMC_REXT */ - u32 wdv; /* 0x5C: EMC_WDV */ - u32 quse; /* 0x60: EMC_QUSE */ - u32 qrst; /* 0x64: EMC_QRST */ - u32 qsafe; /* 0x68: EMC_QSAFE */ - u32 rdv; /* 0x6C: EMC_RDV */ - u32 refresh; /* 0x70: EMC_REFRESH */ - u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ - u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ - u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ - u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ - u32 act2pden; /* 0x84: EMC_ACT2PDEN */ - u32 ar2pden; /* 0x88: EMC_AR2PDEN */ - u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ - u32 txsr; /* 0x90: EMC_TXSR */ - u32 tcke; /* 0x94: EMC_TCKE */ - u32 tfaw; /* 0x98: EMC_TFAW */ - u32 trpab; /* 0x9C: EMC_TRPAB */ - u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ - u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ - u32 trefbw; /* 0xA8: EMC_TREFBW */ - u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ - u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ - u32 odt_read; /* 0xB4: EMC_ODT_READ */ - u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ - u32 mrs; /* 0xCC: EMC_MRS */ - u32 emrs; /* 0xD0: EMC_EMRS */ - u32 ref; /* 0xD4: EMC_REF */ - u32 pre; /* 0xD8: EMC_PRE */ - u32 nop; /* 0xDC: EMC_NOP */ - u32 self_ref; /* 0xE0: EMC_SELF_REF */ - u32 dpd; /* 0xE4: EMC_DPD */ - u32 mrw; /* 0xE8: EMC_MRW */ - u32 mrr; /* 0xEC: EMC_MRR */ - u32 reserved3; /* 0xF0: */ - u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ - u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ - u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ - u32 fbio_spare; /* 0x100: SBIO_SPARE */ - /* There are more registers ... */ -}; - -/** - * Set up the EMC for the given rate. The timing parameters are retrieved - * from the device tree "nvidia,tegra20-emc" node and its - * "nvidia,tegra20-emc-table" sub-nodes. - * - * @param blob Device tree blob - * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) - * @return 0 if ok, else -ve error code (look in emc.c to decode it) - */ -int tegra_set_emc(const void *blob, unsigned rate); - -/** - * Get a pointer to the EMC controller from the device tree. - * - * @param blob Device tree blob - * @return pointer to EMC controller - */ -struct emc_ctlr *emc_get_controller(const void *blob); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h deleted file mode 100644 index 8a6a78311..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FLOW_H_ -#define _FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 halt_cpu1_events; - u32 cpu1_csr; -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h deleted file mode 100644 index 39c2c9d82..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 high-level function multiplexing */ - -#ifndef _TEGRA20_FUNCMUX_H_ -#define _TEGRA20_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_IRRX_IRTX = 0, - FUNCMUX_UART1_UAA_UAB, - FUNCMUX_UART1_GPU, - FUNCMUX_UART1_SDIO1, - FUNCMUX_UART2_UAD = 0, - FUNCMUX_UART4_GMC = 0, - - /* I2C configs */ - FUNCMUX_DVC_I2CP = 0, - FUNCMUX_I2C1_RM = 0, - FUNCMUX_I2C2_DDC = 0, - FUNCMUX_I2C2_PTA, - FUNCMUX_I2C3_DTF = 0, - - /* SDMMC configs */ - FUNCMUX_SDMMC1_SDIO1_4BIT = 0, - FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, - FUNCMUX_SDMMC3_SDB_4BIT = 0, - FUNCMUX_SDMMC3_SDB_SLXA_8BIT, - FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0, - FUNCMUX_SDMMC4_ATB_GMA_4_BIT, - FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT, - - /* USB configs */ - FUNCMUX_USB2_ULPI = 0, - - /* Serial Flash configs */ - FUNCMUX_SPI1_GMC_GMD = 0, - - /* NAND flags */ - FUNCMUX_NDFLASH_ATC = 0, - FUNCMUX_NDFLASH_KBC_8_BIT, -}; -#endif /* _TEGRA20_FUNCMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h deleted file mode 100644 index 6631871ce..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA20_GP_PADCTRL_H_ -#define _TEGRA20_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ - u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ - u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ - u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ - u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ - u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ - u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ - u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ - u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ -}; - -#endif /* _TEGRA20_GP_PADCTRL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h deleted file mode 100644 index b40b1ff9c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * Portions Copyright 2011-2012 NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA20_GPIO_H_ -#define _TEGRA20_GPIO_H_ - -/* - * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 7 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, /* pin 223 */ -}; - -#endif /* TEGRA20_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/hardware.h deleted file mode 100644 index a29589490..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/hardware.h +++ /dev/null @@ -1,13 +0,0 @@ -/* -* (C) Copyright 2010-2011 -* NVIDIA Corporation <www.nvidia.com> -* - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __TEGRA2_HW_H -#define __TEGRA2_HW_H - -/* include tegra specific hardware definitions */ - -#endif /* __TEGRA2_HW_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h deleted file mode 100644 index 11c0104ff..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA20_PINMUX_H_ -#define _TEGRA20_PINMUX_H_ - -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ -enum pmux_pingrp { - /* APB_MISC_PP_TRISTATE_REG_A_0 */ - PMUX_PINGRP_ATA, - PMUX_PINGRP_ATB, - PMUX_PINGRP_ATC, - PMUX_PINGRP_ATD, - PMUX_PINGRP_CDEV1, - PMUX_PINGRP_CDEV2, - PMUX_PINGRP_CSUS, - PMUX_PINGRP_DAP1, - - PMUX_PINGRP_DAP2, - PMUX_PINGRP_DAP3, - PMUX_PINGRP_DAP4, - PMUX_PINGRP_DTA, - PMUX_PINGRP_DTB, - PMUX_PINGRP_DTC, - PMUX_PINGRP_DTD, - PMUX_PINGRP_DTE, - - PMUX_PINGRP_GPU, - PMUX_PINGRP_GPV, - PMUX_PINGRP_I2CP, - PMUX_PINGRP_IRTX, - PMUX_PINGRP_IRRX, - PMUX_PINGRP_KBCB, - PMUX_PINGRP_KBCA, - PMUX_PINGRP_PMC, - - PMUX_PINGRP_PTA, - PMUX_PINGRP_RM, - PMUX_PINGRP_KBCE, - PMUX_PINGRP_KBCF, - PMUX_PINGRP_GMA, - PMUX_PINGRP_GMC, - PMUX_PINGRP_SDIO1, - PMUX_PINGRP_OWC, - - /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ - PMUX_PINGRP_GME, - PMUX_PINGRP_SDC, - PMUX_PINGRP_SDD, - PMUX_PINGRP_RESERVED0, - PMUX_PINGRP_SLXA, - PMUX_PINGRP_SLXC, - PMUX_PINGRP_SLXD, - PMUX_PINGRP_SLXK, - - PMUX_PINGRP_SPDI, - PMUX_PINGRP_SPDO, - PMUX_PINGRP_SPIA, - PMUX_PINGRP_SPIB, - PMUX_PINGRP_SPIC, - PMUX_PINGRP_SPID, - PMUX_PINGRP_SPIE, - PMUX_PINGRP_SPIF, - - PMUX_PINGRP_SPIG, - PMUX_PINGRP_SPIH, - PMUX_PINGRP_UAA, - PMUX_PINGRP_UAB, - PMUX_PINGRP_UAC, - PMUX_PINGRP_UAD, - PMUX_PINGRP_UCA, - PMUX_PINGRP_UCB, - - PMUX_PINGRP_RESERVED1, - PMUX_PINGRP_ATE, - PMUX_PINGRP_KBCC, - PMUX_PINGRP_RESERVED2, - PMUX_PINGRP_RESERVED3, - PMUX_PINGRP_GMB, - PMUX_PINGRP_GMD, - PMUX_PINGRP_DDC, - - /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ - PMUX_PINGRP_LD0, - PMUX_PINGRP_LD1, - PMUX_PINGRP_LD2, - PMUX_PINGRP_LD3, - PMUX_PINGRP_LD4, - PMUX_PINGRP_LD5, - PMUX_PINGRP_LD6, - PMUX_PINGRP_LD7, - - PMUX_PINGRP_LD8, - PMUX_PINGRP_LD9, - PMUX_PINGRP_LD10, - PMUX_PINGRP_LD11, - PMUX_PINGRP_LD12, - PMUX_PINGRP_LD13, - PMUX_PINGRP_LD14, - PMUX_PINGRP_LD15, - - PMUX_PINGRP_LD16, - PMUX_PINGRP_LD17, - PMUX_PINGRP_LHP0, - PMUX_PINGRP_LHP1, - PMUX_PINGRP_LHP2, - PMUX_PINGRP_LVP0, - PMUX_PINGRP_LVP1, - PMUX_PINGRP_HDINT, - - PMUX_PINGRP_LM0, - PMUX_PINGRP_LM1, - PMUX_PINGRP_LVS, - PMUX_PINGRP_LSC0, - PMUX_PINGRP_LSC1, - PMUX_PINGRP_LSCK, - PMUX_PINGRP_LDC, - PMUX_PINGRP_LCSN, - - /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ - PMUX_PINGRP_LSPI, - PMUX_PINGRP_LSDA, - PMUX_PINGRP_LSDI, - PMUX_PINGRP_LPW0, - PMUX_PINGRP_LPW1, - PMUX_PINGRP_LPW2, - PMUX_PINGRP_LDI, - PMUX_PINGRP_LHS, - - PMUX_PINGRP_LPP, - PMUX_PINGRP_RESERVED4, - PMUX_PINGRP_KBCD, - PMUX_PINGRP_GPU7, - PMUX_PINGRP_DTF, - PMUX_PINGRP_UDA, - PMUX_PINGRP_CRTP, - PMUX_PINGRP_SDB, - - /* these pin groups only have pullup and pull down control */ - PMUX_PINGRP_CK32, - PMUX_PINGRP_DDRC, - PMUX_PINGRP_PMCA, - PMUX_PINGRP_PMCB, - PMUX_PINGRP_PMCC, - PMUX_PINGRP_PMCD, - PMUX_PINGRP_PMCE, - PMUX_PINGRP_XM2C, - PMUX_PINGRP_XM2D, - PMUX_PINGRP_COUNT, -}; - -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ -enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, - PMUX_FUNC_HDMI, - PMUX_FUNC_I2C, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, - PMUX_FUNC_NAND, - PMUX_FUNC_OSC, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDIO1, - PMUX_FUNC_SDIO2, - PMUX_FUNC_SDIO3, - PMUX_FUNC_SDIO4, - PMUX_FUNC_SFLASH, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA20_PINMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pmu.h deleted file mode 100644 index 46effb47e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pmu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ARCH_PMU_H_ -#define _ARCH_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _ARCH_PMU_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h deleted file mode 100644 index 8e7397d0e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Tegra pulse width frequency modulator definitions - * - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA_PWM_H -#define __ASM_ARCH_TEGRA_PWM_H - -/* This is a single PWM channel */ -struct pwm_ctlr { - uint control; /* Control register */ - uint reserved[3]; /* Space space */ -}; - -#define PWM_NUM_CHANNELS 4 - -/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ -#define PWM_ENABLE_SHIFT 31 -#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) - -#define PWM_WIDTH_SHIFT 16 -#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) - -#define PWM_DIVIDER_SHIFT 0 -#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) - -/** - * Program the PWM with the given parameters. - * - * @param channel PWM channel to update - * @param rate Clock rate to use for PWM - * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high, - * n = n/256 pulse high - * @param freq_divider frequency divider value (1 to use rate as is) - */ -void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider); - -/** - * Request a pwm channel as referenced by a device tree node. - * - * This channel can then be passed to pwm_enable(). - * - * @param blob Device tree blob - * @param node Node containing reference to pwm - * @param prop_name Property name of pwm reference - * @return channel number, if ok, else -1 - */ -int pwm_request(const void *blob, int node, const char *prop_name); - -/** - * Set up the pwm controller, by looking it up in the fdt. - * - * @return 0 if ok, -1 if the device tree node was not found or invalid. - */ -int pwm_init(const void *blob); - -#endif /* __ASM_ARCH_TEGRA_PWM_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h deleted file mode 100644 index aaf05084e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SDRAM_PARAM_H_ -#define _SDRAM_PARAM_H_ - -/* - * Defines the number of 32-bit words provided in each set of SDRAM parameters - * for arbitration configuration data. - */ -#define BCT_SDRAM_ARB_CONFIG_WORDS 27 - -enum memory_type { - MEMORY_TYPE_NONE = 0, - MEMORY_TYPE_DDR, - MEMORY_TYPE_LPDDR, - MEMORY_TYPE_DDR2, - MEMORY_TYPE_LPDDR2, - MEMORY_TYPE_NUM, - MEMORY_TYPE_FORCE32 = 0x7FFFFFFF -}; - -/* Defines the SDRAM parameter structure */ -struct sdram_params { - enum memory_type memory_type; - u32 pllm_charge_pump_setup_control; - u32 pllm_loop_filter_setup_control; - u32 pllm_input_divider; - u32 pllm_feedback_divider; - u32 pllm_post_divider; - u32 pllm_stable_time; - u32 emc_clock_divider; - u32 emc_auto_cal_interval; - u32 emc_auto_cal_config; - u32 emc_auto_cal_wait; - u32 emc_pin_program_wait; - u32 emc_rc; - u32 emc_rfc; - u32 emc_ras; - u32 emc_rp; - u32 emc_r2w; - u32 emc_w2r; - u32 emc_r2p; - u32 emc_w2p; - u32 emc_rd_rcd; - u32 emc_wr_rcd; - u32 emc_rrd; - u32 emc_rext; - u32 emc_wdv; - u32 emc_quse; - u32 emc_qrst; - u32 emc_qsafe; - u32 emc_rdv; - u32 emc_refresh; - u32 emc_burst_refresh_num; - u32 emc_pdex2wr; - u32 emc_pdex2rd; - u32 emc_pchg2pden; - u32 emc_act2pden; - u32 emc_ar2pden; - u32 emc_rw2pden; - u32 emc_txsr; - u32 emc_tcke; - u32 emc_tfaw; - u32 emc_trpab; - u32 emc_tclkstable; - u32 emc_tclkstop; - u32 emc_trefbw; - u32 emc_quseextra; - u32 emc_fbioc_fg1; - u32 emc_fbio_dqsib_dly; - u32 emc_fbio_dqsib_dly_msb; - u32 emc_fbio_quse_dly; - u32 emc_fbio_quse_dly_msb; - u32 emc_fbio_cfg5; - u32 emc_fbio_cfg6; - u32 emc_fbio_spare; - u32 emc_mrs; - u32 emc_emrs; - u32 emc_mrw1; - u32 emc_mrw2; - u32 emc_mrw3; - u32 emc_mrw_reset_command; - u32 emc_mrw_reset_init_wait; - u32 emc_adr_cfg; - u32 emc_adr_cfg1; - u32 emc_emem_cfg; - u32 emc_low_latency_config; - u32 emc_cfg; - u32 emc_cfg2; - u32 emc_dbg; - u32 ahb_arbitration_xbar_ctrl; - u32 emc_cfg_dig_dll; - u32 emc_dll_xform_dqs; - u32 emc_dll_xform_quse; - u32 warm_boot_wait; - u32 emc_ctt_term_ctrl; - u32 emc_odt_write; - u32 emc_odt_read; - u32 emc_zcal_ref_cnt; - u32 emc_zcal_wait_cnt; - u32 emc_zcal_mrw_cmd; - u32 emc_mrs_reset_dll; - u32 emc_mrw_zq_init_dev0; - u32 emc_mrw_zq_init_dev1; - u32 emc_mrw_zq_init_wait; - u32 emc_mrs_reset_dll_wait; - u32 emc_emrs_emr2; - u32 emc_emrs_emr3; - u32 emc_emrs_ddr2_dll_enable; - u32 emc_mrs_ddr2_dll_reset; - u32 emc_emrs_ddr2_ocd_calib; - u32 emc_edr2_wait; - u32 emc_cfg_clktrim0; - u32 emc_cfg_clktrim1; - u32 emc_cfg_clktrim2; - u32 pmc_ddr_pwr; - u32 apb_misc_gp_xm2cfga_padctrl; - u32 apb_misc_gp_xm2cfgc_padctrl; - u32 apb_misc_gp_xm2cfgc_padctrl2; - u32 apb_misc_gp_xm2cfgd_padctrl; - u32 apb_misc_gp_xm2cfgd_padctrl2; - u32 apb_misc_gp_xm2clkcfg_padctrl; - u32 apb_misc_gp_xm2comp_padctrl; - u32 apb_misc_gp_xm2vttgen_padctrl; - u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/spl.h deleted file mode 100644 index 8953b00a9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h deleted file mode 100644 index 6a4b40ec7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA20_H_ -#define _TEGRA20_H_ - -#define CONFIG_TEGRA20 - -#define NV_PA_SDRAM_BASE 0x00000000 - -#include <asm/arch-tegra/tegra.h> - -#define TEGRA_USB1_BASE 0xC5000000 - -#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ - -#define MAX_NUM_CPU 2 - -#endif /* TEGRA20_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h deleted file mode 100644 index e8cc68c6e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra20 SPI-FLASH controller - * - * Copyright 2010-2012 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA20_SPI_H_ -#define _TEGRA20_SPI_H_ - -#include <asm/types.h> - -int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra20_spi_free_slave(struct spi_slave *slave); -int tegra20_spi_init(int *node_list, int count); -int tegra20_spi_claim_bus(struct spi_slave *slave); -void tegra20_spi_cs_activate(struct spi_slave *slave); -void tegra20_spi_cs_deactivate(struct spi_slave *slave); -int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA20_SPI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_slink.h deleted file mode 100644 index 5aa74ddd6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_slink.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI-SLINK controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA30_SPI_H_ -#define _TEGRA30_SPI_H_ - -#include <asm/types.h> - -int tegra30_spi_init(int *node_list, int count); -int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra30_spi_free_slave(struct spi_slave *slave); -int tegra30_spi_claim_bus(struct spi_slave *slave); -void tegra30_spi_cs_activate(struct spi_slave *slave); -void tegra30_spi_cs_deactivate(struct spi_slave *slave); -int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA30_SPI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h deleted file mode 100644 index cb619f1f2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ /dev/null @@ -1,382 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra30 clock PLL tables */ - -#ifndef _TEGRA30_CLOCK_TABLES_H_ -#define _TEGRA30_CLOCK_TABLES_H_ - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - - CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_COP, - PERIPH_ID_TRIGSYS, - PERIPH_ID_RESERVED3, - PERIPH_ID_RESERVED4, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_RESERVED16, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_RESERVED24, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_I2S0, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_RESERVED43, - PERIPH_ID_SBC2, - PERIPH_ID_RESERVED45, - PERIPH_ID_SBC3, - PERIPH_ID_DVC_I2C, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_PCIEXCLK, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_DTV, - - /* 80 */ - PERIPH_ID_NANDSPEED, - PERIPH_ID_I2CSLOW, - PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, - PERIPH_ID_RESERVED93, - PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, - - PERIPH_ID_VW_FIRST, - /* V word: 31:0 */ - PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, - PERIPH_ID_CPULP, - PERIPH_ID_3D2, - PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, - PERIPH_ID_I2S3, - PERIPH_ID_I2S4, - PERIPH_ID_I2C4, - - /* 08 */ - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - PERIPH_ID_AUDIO, - PERIPH_ID_APBIF, - PERIPH_ID_DAM0, - PERIPH_ID_DAM1, - PERIPH_ID_DAM2, - PERIPH_ID_HDA2CODEC2X, - - /* 16 */ - PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, - PERIPH_ID_ACTMON, - - /* 24 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, - PERIPH_ID_SATA, - PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, - - /* W word: 31:0 */ - PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_SATACOLD, - PERIPH_ID_RESERVED0_PCIERX0, - PERIPH_ID_RESERVED1_PCIERX1, - PERIPH_ID_RESERVED2_PCIERX2, - PERIPH_ID_RESERVED3_PCIERX3, - PERIPH_ID_RESERVED4_PCIERX4, - PERIPH_ID_RESERVED5_PCIERX5, - - /* 40 */ - PERIPH_ID_CEC, - PERIPH_ID_RESERVED6_PCIE2, - PERIPH_ID_RESERVED7_EMC, - PERIPH_ID_RESERVED8_HDMI, - PERIPH_ID_RESERVED9_SATA, - PERIPH_ID_RESERVED10_MIPI, - PERIPH_ID_EX_RESERVED46, - PERIPH_ID_EX_RESERVED47, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -enum pll_out_id { - PLL_OUT1, - PLL_OUT2, - PLL_OUT3, - PLL_OUT4 -}; - -/* - * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want - * callers to use the PERIPH_ID for all access to peripheral clocks to avoid - * confusion bewteen PERIPH_ID_... and PERIPHC_... - * - * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be - * confusing. - */ -enum periphc_internal_id { - /* 0x00 */ - PERIPHC_I2S1, - PERIPHC_I2S2, - PERIPHC_SPDIF_OUT, - PERIPHC_SPDIF_IN, - PERIPHC_PWM, - PERIPHC_05h, - PERIPHC_SBC2, - PERIPHC_SBC3, - - /* 0x08 */ - PERIPHC_08h, - PERIPHC_I2C1, - PERIPHC_DVC_I2C, - PERIPHC_0bh, - PERIPHC_0ch, - PERIPHC_SBC1, - PERIPHC_DISP1, - PERIPHC_DISP2, - - /* 0x10 */ - PERIPHC_CVE, - PERIPHC_11h, - PERIPHC_VI, - PERIPHC_13h, - PERIPHC_SDMMC1, - PERIPHC_SDMMC2, - PERIPHC_G3D, - PERIPHC_G2D, - - /* 0x18 */ - PERIPHC_NDFLASH, - PERIPHC_SDMMC4, - PERIPHC_VFIR, - PERIPHC_EPP, - PERIPHC_MPE, - PERIPHC_MIPI, - PERIPHC_UART1, - PERIPHC_UART2, - - /* 0x20 */ - PERIPHC_HOST1X, - PERIPHC_21h, - PERIPHC_TVO, - PERIPHC_HDMI, - PERIPHC_24h, - PERIPHC_TVDAC, - PERIPHC_I2C2, - PERIPHC_EMC, - - /* 0x28 */ - PERIPHC_UART3, - PERIPHC_29h, - PERIPHC_VI_SENSOR, - PERIPHC_2bh, - PERIPHC_2ch, - PERIPHC_SBC4, - PERIPHC_I2C3, - PERIPHC_SDMMC3, - - /* 0x30 */ - PERIPHC_UART4, - PERIPHC_UART5, - PERIPHC_VDE, - PERIPHC_OWR, - PERIPHC_NOR, - PERIPHC_CSITE, - PERIPHC_I2S0, - PERIPHC_37h, - - PERIPHC_VW_FIRST, - /* 0x38 */ - PERIPHC_G3D2 = PERIPHC_VW_FIRST, - PERIPHC_MSELECT, - PERIPHC_TSENSOR, - PERIPHC_I2S3, - PERIPHC_I2S4, - PERIPHC_I2C4, - PERIPHC_SBC5, - PERIPHC_SBC6, - - /* 0x40 */ - PERIPHC_AUDIO, - PERIPHC_41h, - PERIPHC_DAM0, - PERIPHC_DAM1, - PERIPHC_DAM2, - PERIPHC_HDA2CODEC2X, - PERIPHC_ACTMON, - PERIPHC_EXTPERIPH1, - - /* 0x48 */ - PERIPHC_EXTPERIPH2, - PERIPHC_EXTPERIPH3, - PERIPHC_NANDSPEED, - PERIPHC_I2CSLOW, - PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, - PERIPHC_SATAOOB, - PERIPHC_SATA, - PERIPHC_HDA, - - PERIPHC_COUNT, - - PERIPHC_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ -#define PERIPH_REG(id) \ - (id < PERIPH_ID_VW_FIRST) ? \ - ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) - -#endif /* _TEGRA30_CLOCK_TABLES_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h deleted file mode 100644 index 2f24a75cc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra30 clock control functions */ - -#ifndef _TEGRA30_CLOCK_H_ -#define _TEGRA30_CLOCK_H_ - -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) - -#endif /* _TEGRA30_CLOCK_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h deleted file mode 100644 index f5966a807..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_FLOW_H_ -#define _TEGRA30_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 xrq_events; - u32 halt_cpu1_events; - u32 cpu1_csr; - u32 halt_cpu2_events; - u32 cpu2_csr; - u32 halt_cpu3_events; - u32 cpu3_csr; - u32 cluster_control; -}; - -#endif /* _TEGRA30_FLOW_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h deleted file mode 100644 index 24b2bca03..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Tegra30 high-level function multiplexing */ - -#ifndef _TEGRA30_FUNCMUX_H_ -#define _TEGRA30_FUNCMUX_H_ - -#include <asm/arch-tegra/funcmux.h> - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_ULPI = 0, -}; -#endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h deleted file mode 100644 index 23d184f2d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_GP_PADCTRL_H_ -#define _TEGRA30_GP_PADCTRL_H_ - -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ - u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ - u32 reserved1[7]; /* 0xD0-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ -}; - -/* SDMMC1/3 settings from section 24.6 of T30 TRM */ -#define SDIOCFG_DRVUP_SLWF 1 -#define SDIOCFG_DRVDN_SLWR 1 -#define SDIOCFG_DRVUP 0x2E -#define SDIOCFG_DRVDN 0x2A - -#endif /* _TEGRA30_GP_PADCTRL_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h deleted file mode 100644 index f1c89f5a8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_GPIO_H_ -#define _TEGRA30_GPIO_H_ - -/* - * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* number of banks */ - -#include <asm/arch-tegra/gpio.h> - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; - uint gpio_masked_config[TEGRA_GPIO_PORTS]; - uint gpio_masked_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_out[TEGRA_GPIO_PORTS]; - uint gpio_masked_in[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_status[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_level[TEGRA_GPIO_PORTS]; - uint gpio_masked_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, /* pin 247 */ -}; - -#endif /* _TEGRA30_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/hardware.h deleted file mode 100644 index b1a5aa9e0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_HARDWARE_H_ -#define _TEGRA30_HARDWARE_H_ - -/* include tegra specific hardware definitions */ - -#endif /* _TEGRA30-HARDWARE_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h deleted file mode 100644 index 6d83061dc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA30_PINMUX_H_ -#define _TEGRA30_PINMUX_H_ - -enum pmux_pingrp { - PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_PINGRP_ULPI_DATA4_PO5, - PMUX_PINGRP_ULPI_DATA5_PO6, - PMUX_PINGRP_ULPI_DATA6_PO7, - PMUX_PINGRP_ULPI_DATA7_PO0, - PMUX_PINGRP_ULPI_CLK_PY0, - PMUX_PINGRP_ULPI_DIR_PY1, - PMUX_PINGRP_ULPI_NXT_PY2, - PMUX_PINGRP_ULPI_STP_PY3, - PMUX_PINGRP_DAP3_FS_PP0, - PMUX_PINGRP_DAP3_DIN_PP1, - PMUX_PINGRP_DAP3_DOUT_PP2, - PMUX_PINGRP_DAP3_SCLK_PP3, - PMUX_PINGRP_PV0, - PMUX_PINGRP_PV1, - PMUX_PINGRP_SDMMC1_CLK_PZ0, - PMUX_PINGRP_SDMMC1_CMD_PZ1, - PMUX_PINGRP_SDMMC1_DAT3_PY4, - PMUX_PINGRP_SDMMC1_DAT2_PY5, - PMUX_PINGRP_SDMMC1_DAT1_PY6, - PMUX_PINGRP_SDMMC1_DAT0_PY7, - PMUX_PINGRP_PV2, - PMUX_PINGRP_PV3, - PMUX_PINGRP_CLK2_OUT_PW5, - PMUX_PINGRP_CLK2_REQ_PCC5, - PMUX_PINGRP_LCD_PWR1_PC1, - PMUX_PINGRP_LCD_PWR2_PC6, - PMUX_PINGRP_LCD_SDIN_PZ2, - PMUX_PINGRP_LCD_SDOUT_PN5, - PMUX_PINGRP_LCD_WR_N_PZ3, - PMUX_PINGRP_LCD_CS0_N_PN4, - PMUX_PINGRP_LCD_DC0_PN6, - PMUX_PINGRP_LCD_SCK_PZ4, - PMUX_PINGRP_LCD_PWR0_PB2, - PMUX_PINGRP_LCD_PCLK_PB3, - PMUX_PINGRP_LCD_DE_PJ1, - PMUX_PINGRP_LCD_HSYNC_PJ3, - PMUX_PINGRP_LCD_VSYNC_PJ4, - PMUX_PINGRP_LCD_D0_PE0, - PMUX_PINGRP_LCD_D1_PE1, - PMUX_PINGRP_LCD_D2_PE2, - PMUX_PINGRP_LCD_D3_PE3, - PMUX_PINGRP_LCD_D4_PE4, - PMUX_PINGRP_LCD_D5_PE5, - PMUX_PINGRP_LCD_D6_PE6, - PMUX_PINGRP_LCD_D7_PE7, - PMUX_PINGRP_LCD_D8_PF0, - PMUX_PINGRP_LCD_D9_PF1, - PMUX_PINGRP_LCD_D10_PF2, - PMUX_PINGRP_LCD_D11_PF3, - PMUX_PINGRP_LCD_D12_PF4, - PMUX_PINGRP_LCD_D13_PF5, - PMUX_PINGRP_LCD_D14_PF6, - PMUX_PINGRP_LCD_D15_PF7, - PMUX_PINGRP_LCD_D16_PM0, - PMUX_PINGRP_LCD_D17_PM1, - PMUX_PINGRP_LCD_D18_PM2, - PMUX_PINGRP_LCD_D19_PM3, - PMUX_PINGRP_LCD_D20_PM4, - PMUX_PINGRP_LCD_D21_PM5, - PMUX_PINGRP_LCD_D22_PM6, - PMUX_PINGRP_LCD_D23_PM7, - PMUX_PINGRP_LCD_CS1_N_PW0, - PMUX_PINGRP_LCD_M1_PW1, - PMUX_PINGRP_LCD_DC1_PD2, - PMUX_PINGRP_HDMI_INT_PN7, - PMUX_PINGRP_DDC_SCL_PV4, - PMUX_PINGRP_DDC_SDA_PV5, - PMUX_PINGRP_CRT_HSYNC_PV6, - PMUX_PINGRP_CRT_VSYNC_PV7, - PMUX_PINGRP_VI_D0_PT4, - PMUX_PINGRP_VI_D1_PD5, - PMUX_PINGRP_VI_D2_PL0, - PMUX_PINGRP_VI_D3_PL1, - PMUX_PINGRP_VI_D4_PL2, - PMUX_PINGRP_VI_D5_PL3, - PMUX_PINGRP_VI_D6_PL4, - PMUX_PINGRP_VI_D7_PL5, - PMUX_PINGRP_VI_D8_PL6, - PMUX_PINGRP_VI_D9_PL7, - PMUX_PINGRP_VI_D10_PT2, - PMUX_PINGRP_VI_D11_PT3, - PMUX_PINGRP_VI_PCLK_PT0, - PMUX_PINGRP_VI_MCLK_PT1, - PMUX_PINGRP_VI_VSYNC_PD6, - PMUX_PINGRP_VI_HSYNC_PD7, - PMUX_PINGRP_UART2_RXD_PC3, - PMUX_PINGRP_UART2_TXD_PC2, - PMUX_PINGRP_UART2_RTS_N_PJ6, - PMUX_PINGRP_UART2_CTS_N_PJ5, - PMUX_PINGRP_UART3_TXD_PW6, - PMUX_PINGRP_UART3_RXD_PW7, - PMUX_PINGRP_UART3_CTS_N_PA1, - PMUX_PINGRP_UART3_RTS_N_PC0, - PMUX_PINGRP_PU0, - PMUX_PINGRP_PU1, - PMUX_PINGRP_PU2, - PMUX_PINGRP_PU3, - PMUX_PINGRP_PU4, - PMUX_PINGRP_PU5, - PMUX_PINGRP_PU6, - PMUX_PINGRP_GEN1_I2C_SDA_PC5, - PMUX_PINGRP_GEN1_I2C_SCL_PC4, - PMUX_PINGRP_DAP4_FS_PP4, - PMUX_PINGRP_DAP4_DIN_PP5, - PMUX_PINGRP_DAP4_DOUT_PP6, - PMUX_PINGRP_DAP4_SCLK_PP7, - PMUX_PINGRP_CLK3_OUT_PEE0, - PMUX_PINGRP_CLK3_REQ_PEE1, - PMUX_PINGRP_GMI_WP_N_PC7, - PMUX_PINGRP_GMI_IORDY_PI5, - PMUX_PINGRP_GMI_WAIT_PI7, - PMUX_PINGRP_GMI_ADV_N_PK0, - PMUX_PINGRP_GMI_CLK_PK1, - PMUX_PINGRP_GMI_CS0_N_PJ0, - PMUX_PINGRP_GMI_CS1_N_PJ2, - PMUX_PINGRP_GMI_CS2_N_PK3, - PMUX_PINGRP_GMI_CS3_N_PK4, - PMUX_PINGRP_GMI_CS4_N_PK2, - PMUX_PINGRP_GMI_CS6_N_PI3, - PMUX_PINGRP_GMI_CS7_N_PI6, - PMUX_PINGRP_GMI_AD0_PG0, - PMUX_PINGRP_GMI_AD1_PG1, - PMUX_PINGRP_GMI_AD2_PG2, - PMUX_PINGRP_GMI_AD3_PG3, - PMUX_PINGRP_GMI_AD4_PG4, - PMUX_PINGRP_GMI_AD5_PG5, - PMUX_PINGRP_GMI_AD6_PG6, - PMUX_PINGRP_GMI_AD7_PG7, - PMUX_PINGRP_GMI_AD8_PH0, - PMUX_PINGRP_GMI_AD9_PH1, - PMUX_PINGRP_GMI_AD10_PH2, - PMUX_PINGRP_GMI_AD11_PH3, - PMUX_PINGRP_GMI_AD12_PH4, - PMUX_PINGRP_GMI_AD13_PH5, - PMUX_PINGRP_GMI_AD14_PH6, - PMUX_PINGRP_GMI_AD15_PH7, - PMUX_PINGRP_GMI_A16_PJ7, - PMUX_PINGRP_GMI_A17_PB0, - PMUX_PINGRP_GMI_A18_PB1, - PMUX_PINGRP_GMI_A19_PK7, - PMUX_PINGRP_GMI_WR_N_PI0, - PMUX_PINGRP_GMI_OE_N_PI1, - PMUX_PINGRP_GMI_DQS_PI2, - PMUX_PINGRP_GMI_RST_N_PI4, - PMUX_PINGRP_GEN2_I2C_SCL_PT5, - PMUX_PINGRP_GEN2_I2C_SDA_PT6, - PMUX_PINGRP_SDMMC4_CLK_PCC4, - PMUX_PINGRP_SDMMC4_CMD_PT7, - PMUX_PINGRP_SDMMC4_DAT0_PAA0, - PMUX_PINGRP_SDMMC4_DAT1_PAA1, - PMUX_PINGRP_SDMMC4_DAT2_PAA2, - PMUX_PINGRP_SDMMC4_DAT3_PAA3, - PMUX_PINGRP_SDMMC4_DAT4_PAA4, - PMUX_PINGRP_SDMMC4_DAT5_PAA5, - PMUX_PINGRP_SDMMC4_DAT6_PAA6, - PMUX_PINGRP_SDMMC4_DAT7_PAA7, - PMUX_PINGRP_SDMMC4_RST_N_PCC3, - PMUX_PINGRP_CAM_MCLK_PCC0, - PMUX_PINGRP_PCC1, - PMUX_PINGRP_PBB0, - PMUX_PINGRP_CAM_I2C_SCL_PBB1, - PMUX_PINGRP_CAM_I2C_SDA_PBB2, - PMUX_PINGRP_PBB3, - PMUX_PINGRP_PBB4, - PMUX_PINGRP_PBB5, - PMUX_PINGRP_PBB6, - PMUX_PINGRP_PBB7, - PMUX_PINGRP_PCC2, - PMUX_PINGRP_JTAG_RTCK_PU7, - PMUX_PINGRP_PWR_I2C_SCL_PZ6, - PMUX_PINGRP_PWR_I2C_SDA_PZ7, - PMUX_PINGRP_KB_ROW0_PR0, - PMUX_PINGRP_KB_ROW1_PR1, - PMUX_PINGRP_KB_ROW2_PR2, - PMUX_PINGRP_KB_ROW3_PR3, - PMUX_PINGRP_KB_ROW4_PR4, - PMUX_PINGRP_KB_ROW5_PR5, - PMUX_PINGRP_KB_ROW6_PR6, - PMUX_PINGRP_KB_ROW7_PR7, - PMUX_PINGRP_KB_ROW8_PS0, - PMUX_PINGRP_KB_ROW9_PS1, - PMUX_PINGRP_KB_ROW10_PS2, - PMUX_PINGRP_KB_ROW11_PS3, - PMUX_PINGRP_KB_ROW12_PS4, - PMUX_PINGRP_KB_ROW13_PS5, - PMUX_PINGRP_KB_ROW14_PS6, - PMUX_PINGRP_KB_ROW15_PS7, - PMUX_PINGRP_KB_COL0_PQ0, - PMUX_PINGRP_KB_COL1_PQ1, - PMUX_PINGRP_KB_COL2_PQ2, - PMUX_PINGRP_KB_COL3_PQ3, - PMUX_PINGRP_KB_COL4_PQ4, - PMUX_PINGRP_KB_COL5_PQ5, - PMUX_PINGRP_KB_COL6_PQ6, - PMUX_PINGRP_KB_COL7_PQ7, - PMUX_PINGRP_CLK_32K_OUT_PA0, - PMUX_PINGRP_SYS_CLK_REQ_PZ5, - PMUX_PINGRP_CORE_PWR_REQ, - PMUX_PINGRP_CPU_PWR_REQ, - PMUX_PINGRP_PWR_INT_N, - PMUX_PINGRP_CLK_32K_IN, - PMUX_PINGRP_OWR, - PMUX_PINGRP_DAP1_FS_PN0, - PMUX_PINGRP_DAP1_DIN_PN1, - PMUX_PINGRP_DAP1_DOUT_PN2, - PMUX_PINGRP_DAP1_SCLK_PN3, - PMUX_PINGRP_CLK1_REQ_PEE2, - PMUX_PINGRP_CLK1_OUT_PW4, - PMUX_PINGRP_SPDIF_IN_PK6, - PMUX_PINGRP_SPDIF_OUT_PK5, - PMUX_PINGRP_DAP2_FS_PA2, - PMUX_PINGRP_DAP2_DIN_PA4, - PMUX_PINGRP_DAP2_DOUT_PA5, - PMUX_PINGRP_DAP2_SCLK_PA3, - PMUX_PINGRP_SPI2_MOSI_PX0, - PMUX_PINGRP_SPI2_MISO_PX1, - PMUX_PINGRP_SPI2_CS0_N_PX3, - PMUX_PINGRP_SPI2_SCK_PX2, - PMUX_PINGRP_SPI1_MOSI_PX4, - PMUX_PINGRP_SPI1_SCK_PX5, - PMUX_PINGRP_SPI1_CS0_N_PX6, - PMUX_PINGRP_SPI1_MISO_PX7, - PMUX_PINGRP_SPI2_CS1_N_PW2, - PMUX_PINGRP_SPI2_CS2_N_PW3, - PMUX_PINGRP_SDMMC3_CLK_PA6, - PMUX_PINGRP_SDMMC3_CMD_PA7, - PMUX_PINGRP_SDMMC3_DAT0_PB7, - PMUX_PINGRP_SDMMC3_DAT1_PB6, - PMUX_PINGRP_SDMMC3_DAT2_PB5, - PMUX_PINGRP_SDMMC3_DAT3_PB4, - PMUX_PINGRP_SDMMC3_DAT4_PD1, - PMUX_PINGRP_SDMMC3_DAT5_PD0, - PMUX_PINGRP_SDMMC3_DAT6_PD3, - PMUX_PINGRP_SDMMC3_DAT7_PD4, - PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0, - PMUX_PINGRP_PEX_L0_RST_N_PDD1, - PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, - PMUX_PINGRP_PEX_WAKE_N_PDD3, - PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4, - PMUX_PINGRP_PEX_L1_RST_N_PDD5, - PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, - PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7, - PMUX_PINGRP_PEX_L2_RST_N_PCC6, - PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7, - PMUX_PINGRP_HDMI_CEC_PEE3, - PMUX_PINGRP_COUNT, -}; - -enum pmux_drvgrp { - PMUX_DRVGRP_AO1, - PMUX_DRVGRP_AO2, - PMUX_DRVGRP_AT1, - PMUX_DRVGRP_AT2, - PMUX_DRVGRP_AT3, - PMUX_DRVGRP_AT4, - PMUX_DRVGRP_AT5, - PMUX_DRVGRP_CDEV1, - PMUX_DRVGRP_CDEV2, - PMUX_DRVGRP_CSUS, - PMUX_DRVGRP_DAP1, - PMUX_DRVGRP_DAP2, - PMUX_DRVGRP_DAP3, - PMUX_DRVGRP_DAP4, - PMUX_DRVGRP_DBG, - PMUX_DRVGRP_LCD1, - PMUX_DRVGRP_LCD2, - PMUX_DRVGRP_SDIO2, - PMUX_DRVGRP_SDIO3, - PMUX_DRVGRP_SPI, - PMUX_DRVGRP_UAA, - PMUX_DRVGRP_UAB, - PMUX_DRVGRP_UART2, - PMUX_DRVGRP_UART3, - PMUX_DRVGRP_VI1, - PMUX_DRVGRP_SDIO1 = (0x84 / 4), - PMUX_DRVGRP_CRT = (0x90 / 4), - PMUX_DRVGRP_DDC, - PMUX_DRVGRP_GMA, - PMUX_DRVGRP_GMB, - PMUX_DRVGRP_GMC, - PMUX_DRVGRP_GMD, - PMUX_DRVGRP_GME, - PMUX_DRVGRP_GMF, - PMUX_DRVGRP_GMG, - PMUX_DRVGRP_GMH, - PMUX_DRVGRP_OWR, - PMUX_DRVGRP_UDA, - PMUX_DRVGRP_GPV, - PMUX_DRVGRP_DEV3, - PMUX_DRVGRP_CEC = (0xd0 / 4), - PMUX_DRVGRP_COUNT, -}; - -enum pmux_func { - PMUX_FUNC_BLINK, - PMUX_FUNC_CEC, - PMUX_FUNC_CLK_12M_OUT, - PMUX_FUNC_CLK_32K_IN, - PMUX_FUNC_CORE_PWR_REQ, - PMUX_FUNC_CPU_PWR_REQ, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP, - PMUX_FUNC_DDR, - PMUX_FUNC_DEV3, - PMUX_FUNC_DISPLAYA, - PMUX_FUNC_DISPLAYB, - PMUX_FUNC_DTV, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HDCP, - PMUX_FUNC_HDMI, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_INVALID, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_NAND, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_PWR_INT_N, - PMUX_FUNC_RTCK, - PMUX_FUNC_SATA, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, - PMUX_FUNC_TEST, - PMUX_FUNC_TRACE, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VGP1, - PMUX_FUNC_VGP2, - PMUX_FUNC_VGP3, - PMUX_FUNC_VGP4, - PMUX_FUNC_VGP5, - PMUX_FUNC_VGP6, - PMUX_FUNC_VI, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_COUNT, -}; - -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_DRVGRPS -#include <asm/arch-tegra/pinmux.h> - -#endif /* _TEGRA30_PINMUX_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pmu.h deleted file mode 100644 index 52bea29bb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pmu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_PMU_H_ -#define _TEGRA30_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA30_PMU_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/spl.h deleted file mode 100644 index 8953b00a9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h deleted file mode 100644 index 4ad8b1c05..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _TEGRA30_H_ -#define _TEGRA30_H_ - -#define CONFIG_TEGRA30 - -#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ - -#include <asm/arch-tegra/tegra.h> - -#define TEGRA_USB1_BASE 0x7D000000 - -#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ - -#define MAX_NUM_CPU 4 - -#endif /* TEGRA30_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/clock.h deleted file mode 100644 index dfc3b1bfa..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * TNETV107X: Clock APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0 -#define PSC_MDCTL_NEXT_SYNCRST 0x1 -#define PSC_MDCTL_NEXT_DISABLE 0x2 -#define PSC_MDCTL_NEXT_ENABLE 0x3 - -#define CONFIG_SYS_INT_OSC_FREQ 24000000 - -#ifndef __ASSEMBLY__ - -/* PLL identifiers */ -enum pll_type_e { - SYS_PLL, - TDM_PLL, - ETH_PLL -}; - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int internal_osc; - unsigned long pll_freq; - unsigned long div_freq[10]; -}; - -void init_plls(int num_pll, struct pll_init_data *config); -int lpsc_status(unsigned int mod); -void lpsc_control(int mod, unsigned long state, int lrstz); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -static inline void clk_enable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1); -} - -static inline void clk_disable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1); -} - -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/emif_defs.h deleted file mode 100644 index 9969a018e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/emif_defs.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm/arch-davinci/emif_defs.h> diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/hardware.h deleted file mode 100644 index 2a7ca4e00..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * TNETV107X: Hardware information - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ - -#include <linux/sizes.h> - -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - -int wdt_start(unsigned long msecs); -int wdt_stop(void); -int wdt_kick(void); - -#endif - -/* Chip configuration unlock codes and registers */ -#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38) -#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c) -#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4) -#define TNETV107X_KICK0_MAGIC 0x83e70b13 -#define TNETV107X_KICK1_MAGIC 0x95a4f1e0 - -/* Module base addresses */ -#define TNETV107X_TPCC_BASE 0x01C00000 -#define TNETV107X_TPTC0_BASE 0x01C10000 -#define TNETV107X_TPTC1_BASE 0x01C10400 -#define TNETV107X_INTC_BASE 0x03000000 -#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000 -#define TNETV107X_INTD_BASE 0x08038000 -#define TNETV107X_INTD_IPC_BASE 0x08038000 -#define TNETV107X_INTD_FAST_BASE 0x08039000 -#define TNETV107X_INTD_ASYNC_BASE 0x0803A000 -#define TNETV107X_INTD_SLOW_BASE 0x0803B000 -#define TNETV107X_PKA_BASE 0x08040000 -#define TNETV107X_RNG_BASE 0x08044000 -#define TNETV107X_TIMER0_BASE 0x08086500 -#define TNETV107X_TIMER1_BASE 0x08086600 -#define TNETV107X_WDT0_ARM_BASE 0x08086700 -#define TNETV107X_WDT1_DSP_BASE 0x08086800 -#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000 -#define TNETV107X_GPIO_BASE 0x08088000 -#define TNETV107X_UART1_BASE 0x08088400 -#define TNETV107X_TOUCHSCREEN_BASE 0x08088500 -#define TNETV107X_SDIO0_BASE 0x08088700 -#define TNETV107X_SDIO1_BASE 0x08088800 -#define TNETV107X_MDIO_BASE 0x08088900 -#define TNETV107X_KEYPAD_BASE 0x08088A00 -#define TNETV107X_SSP_BASE 0x08088C00 -#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000 -#define TNETV107X_PSC_BASE 0x0808B000 -#define TNETV107X_TDM0_BASE 0x08100000 -#define TNETV107X_TDM1_BASE 0x08100100 -#define TNETV107X_MCDMA_BASE 0x08108000 -#define TNETV107X_UART0_DMA_BASE 0x08108200 -#define TNETV107X_USBSS_BASE 0x08120000 -#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000 -#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 -#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000 -#define TNETV107X_IMCOP_BASE 0x01CC0000 -#define TNETV107X_MBX_LITE_BASE 0x07000000 -#define TNETV107X_ETHSS_BASE 0x0803C000 -#define TNETV107X_CPSW_BASE 0x0803C000 -#define TNETV107X_SPF_BASE 0x0803C800 -#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000 -#define TNETV107X_VTP_CNTRL_0 0x0803D800 -#define TNETV107X_VTP_CNTRL_1 0x0803D900 -#define TNETV107X_UART2_DMA_BASE 0x08108400 -#define TNETV107X_INTERNAL_MEMORY 0x20000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 -#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000 -#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000 - -/* LPSC module definitions */ -#define TNETV107X_LPSC_ARM 0 -#define TNETV107X_LPSC_GEM 1 -#define TNETV107X_LPSC_DDR2_PHY 2 -#define TNETV107X_LPSC_TPCC 3 -#define TNETV107X_LPSC_TPTC0 4 -#define TNETV107X_LPSC_TPTC1 5 -#define TNETV107X_LPSC_RAM 6 -#define TNETV107X_LPSC_MBX_LITE 7 -#define TNETV107X_LPSC_LCD 8 -#define TNETV107X_LPSC_ETHSS 9 -#define TNETV107X_LPSC_AEMIF 10 -#define TNETV107X_LPSC_CHIP_CFG 11 -#define TNETV107X_LPSC_TSC 12 -#define TNETV107X_LPSC_ROM 13 -#define TNETV107X_LPSC_UART2 14 -#define TNETV107X_LPSC_PKTSEC 15 -#define TNETV107X_LPSC_SECCTL 16 -#define TNETV107X_LPSC_KEYMGR 17 -#define TNETV107X_LPSC_KEYPAD 18 -#define TNETV107X_LPSC_GPIO 19 -#define TNETV107X_LPSC_MDIO 20 -#define TNETV107X_LPSC_SDIO0 21 -#define TNETV107X_LPSC_UART0 22 -#define TNETV107X_LPSC_UART1 23 -#define TNETV107X_LPSC_TIMER0 24 -#define TNETV107X_LPSC_TIMER1 25 -#define TNETV107X_LPSC_WDT_ARM 26 -#define TNETV107X_LPSC_WDT_DSP 27 -#define TNETV107X_LPSC_SSP 28 -#define TNETV107X_LPSC_TDM0 29 -#define TNETV107X_LPSC_VLYNQ 30 -#define TNETV107X_LPSC_MCDMA 31 -#define TNETV107X_LPSC_USB0 32 -#define TNETV107X_LPSC_TDM1 33 -#define TNETV107X_LPSC_DEBUGSS 34 -#define TNETV107X_LPSC_ETHSS_RGMII 35 -#define TNETV107X_LPSC_SYSTEM 36 -#define TNETV107X_LPSC_IMCOP 37 -#define TNETV107X_LPSC_SPARE 38 -#define TNETV107X_LPSC_SDIO1 39 -#define TNETV107X_LPSC_USB1 40 -#define TNETV107X_LPSC_USBSS 41 -#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 -#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 -#define TNETV107X_LPSC_MAX 44 - -/* Interrupt controller */ -#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10) -#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) -#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/mux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/mux.h deleted file mode 100644 index 3f832c414..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/mux.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * TNETV107X: Pinmux APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -struct pin_config { - unsigned char reg_index; - unsigned char mask_offset; - unsigned char mode; -}; - -#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \ - { reg, offset, mux_mode } - -int mux_select_pin(short index); -int mux_select_pins(const short *pins); - -enum tnetv107x_pin_mux_index { - TNETV107X_PIN_ASR_A00, - TNETV107X_PIN_GPIO32, - TNETV107X_PIN_ASR_A01, - TNETV107X_PIN_GPIO33, - TNETV107X_PIN_ASR_A02, - TNETV107X_PIN_GPIO34, - TNETV107X_PIN_ASR_A03, - TNETV107X_PIN_GPIO35, - TNETV107X_PIN_ASR_A04, - TNETV107X_PIN_GPIO36, - TNETV107X_PIN_ASR_A05, - TNETV107X_PIN_GPIO37, - TNETV107X_PIN_ASR_A06, - TNETV107X_PIN_GPIO38, - TNETV107X_PIN_ASR_A07, - TNETV107X_PIN_GPIO39, - TNETV107X_PIN_ASR_A08, - TNETV107X_PIN_GPIO40, - TNETV107X_PIN_ASR_A09, - TNETV107X_PIN_GPIO41, - TNETV107X_PIN_ASR_A10, - TNETV107X_PIN_GPIO42, - TNETV107X_PIN_ASR_A11, - TNETV107X_PIN_BOOT_STRP_0, - TNETV107X_PIN_ASR_A12, - TNETV107X_PIN_BOOT_STRP_1, - TNETV107X_PIN_ASR_A13, - TNETV107X_PIN_GPIO43, - TNETV107X_PIN_ASR_A14, - TNETV107X_PIN_GPIO44, - TNETV107X_PIN_ASR_A15, - TNETV107X_PIN_GPIO45, - TNETV107X_PIN_ASR_A16, - TNETV107X_PIN_GPIO46, - TNETV107X_PIN_ASR_A17, - TNETV107X_PIN_GPIO47, - TNETV107X_PIN_ASR_A18, - TNETV107X_PIN_GPIO48, - TNETV107X_PIN_SDIO1_DATA3_0, - TNETV107X_PIN_ASR_A19, - TNETV107X_PIN_GPIO49, - TNETV107X_PIN_SDIO1_DATA2_0, - TNETV107X_PIN_ASR_A20, - TNETV107X_PIN_GPIO50, - TNETV107X_PIN_SDIO1_DATA1_0, - TNETV107X_PIN_ASR_A21, - TNETV107X_PIN_GPIO51, - TNETV107X_PIN_SDIO1_DATA0_0, - TNETV107X_PIN_ASR_A22, - TNETV107X_PIN_GPIO52, - TNETV107X_PIN_SDIO1_CMD_0, - TNETV107X_PIN_ASR_A23, - TNETV107X_PIN_GPIO53, - TNETV107X_PIN_SDIO1_CLK_0, - TNETV107X_PIN_ASR_BA_1, - TNETV107X_PIN_GPIO54, - TNETV107X_PIN_SYS_PLL_CLK, - TNETV107X_PIN_ASR_CS0, - TNETV107X_PIN_ASR_CS1, - TNETV107X_PIN_ASR_CS2, - TNETV107X_PIN_TDM_PLL_CLK, - TNETV107X_PIN_ASR_CS3, - TNETV107X_PIN_ETH_PHY_CLK, - TNETV107X_PIN_ASR_D00, - TNETV107X_PIN_GPIO55, - TNETV107X_PIN_ASR_D01, - TNETV107X_PIN_GPIO56, - TNETV107X_PIN_ASR_D02, - TNETV107X_PIN_GPIO57, - TNETV107X_PIN_ASR_D03, - TNETV107X_PIN_GPIO58, - TNETV107X_PIN_ASR_D04, - TNETV107X_PIN_GPIO59_0, - TNETV107X_PIN_ASR_D05, - TNETV107X_PIN_GPIO60_0, - TNETV107X_PIN_ASR_D06, - TNETV107X_PIN_GPIO61_0, - TNETV107X_PIN_ASR_D07, - TNETV107X_PIN_GPIO62_0, - TNETV107X_PIN_ASR_D08, - TNETV107X_PIN_GPIO63_0, - TNETV107X_PIN_ASR_D09, - TNETV107X_PIN_GPIO64_0, - TNETV107X_PIN_ASR_D10, - TNETV107X_PIN_SDIO1_DATA3_1, - TNETV107X_PIN_ASR_D11, - TNETV107X_PIN_SDIO1_DATA2_1, - TNETV107X_PIN_ASR_D12, - TNETV107X_PIN_SDIO1_DATA1_1, - TNETV107X_PIN_ASR_D13, - TNETV107X_PIN_SDIO1_DATA0_1, - TNETV107X_PIN_ASR_D14, - TNETV107X_PIN_SDIO1_CMD_1, - TNETV107X_PIN_ASR_D15, - TNETV107X_PIN_SDIO1_CLK_1, - TNETV107X_PIN_ASR_OE, - TNETV107X_PIN_BOOT_STRP_2, - TNETV107X_PIN_ASR_RNW, - TNETV107X_PIN_GPIO29_0, - TNETV107X_PIN_ASR_WAIT, - TNETV107X_PIN_GPIO30_0, - TNETV107X_PIN_ASR_WE, - TNETV107X_PIN_BOOT_STRP_3, - TNETV107X_PIN_ASR_WE_DQM0, - TNETV107X_PIN_GPIO31, - TNETV107X_PIN_LCD_PD17_0, - TNETV107X_PIN_ASR_WE_DQM1, - TNETV107X_PIN_ASR_BA0_0, - TNETV107X_PIN_VLYNQ_CLK, - TNETV107X_PIN_GPIO14, - TNETV107X_PIN_LCD_PD19_0, - TNETV107X_PIN_VLYNQ_RXD0, - TNETV107X_PIN_GPIO15, - TNETV107X_PIN_LCD_PD20_0, - TNETV107X_PIN_VLYNQ_RXD1, - TNETV107X_PIN_GPIO16, - TNETV107X_PIN_LCD_PD21_0, - TNETV107X_PIN_VLYNQ_TXD0, - TNETV107X_PIN_GPIO17, - TNETV107X_PIN_LCD_PD22_0, - TNETV107X_PIN_VLYNQ_TXD1, - TNETV107X_PIN_GPIO18, - TNETV107X_PIN_LCD_PD23_0, - TNETV107X_PIN_SDIO0_CLK, - TNETV107X_PIN_GPIO19, - TNETV107X_PIN_SDIO0_CMD, - TNETV107X_PIN_GPIO20, - TNETV107X_PIN_SDIO0_DATA0, - TNETV107X_PIN_GPIO21, - TNETV107X_PIN_SDIO0_DATA1, - TNETV107X_PIN_GPIO22, - TNETV107X_PIN_SDIO0_DATA2, - TNETV107X_PIN_GPIO23, - TNETV107X_PIN_SDIO0_DATA3, - TNETV107X_PIN_GPIO24, - TNETV107X_PIN_EMU0, - TNETV107X_PIN_EMU1, - TNETV107X_PIN_RTCK, - TNETV107X_PIN_TRST_N, - TNETV107X_PIN_TCK, - TNETV107X_PIN_TDI, - TNETV107X_PIN_TDO, - TNETV107X_PIN_TMS, - TNETV107X_PIN_TDM1_CLK, - TNETV107X_PIN_TDM1_RX, - TNETV107X_PIN_TDM1_TX, - TNETV107X_PIN_TDM1_FS, - TNETV107X_PIN_KEYPAD_R0, - TNETV107X_PIN_KEYPAD_R1, - TNETV107X_PIN_KEYPAD_R2, - TNETV107X_PIN_KEYPAD_R3, - TNETV107X_PIN_KEYPAD_R4, - TNETV107X_PIN_KEYPAD_R5, - TNETV107X_PIN_KEYPAD_R6, - TNETV107X_PIN_GPIO12, - TNETV107X_PIN_KEYPAD_R7, - TNETV107X_PIN_GPIO10, - TNETV107X_PIN_KEYPAD_C0, - TNETV107X_PIN_KEYPAD_C1, - TNETV107X_PIN_KEYPAD_C2, - TNETV107X_PIN_KEYPAD_C3, - TNETV107X_PIN_KEYPAD_C4, - TNETV107X_PIN_KEYPAD_C5, - TNETV107X_PIN_KEYPAD_C6, - TNETV107X_PIN_GPIO13, - TNETV107X_PIN_TEST_CLK_IN, - TNETV107X_PIN_KEYPAD_C7, - TNETV107X_PIN_GPIO11, - TNETV107X_PIN_SSP0_0, - TNETV107X_PIN_SCC_DCLK, - TNETV107X_PIN_LCD_PD20_1, - TNETV107X_PIN_SSP0_1, - TNETV107X_PIN_SCC_CS_N, - TNETV107X_PIN_LCD_PD21_1, - TNETV107X_PIN_SSP0_2, - TNETV107X_PIN_SCC_D, - TNETV107X_PIN_LCD_PD22_1, - TNETV107X_PIN_SSP0_3, - TNETV107X_PIN_SCC_RESETN, - TNETV107X_PIN_LCD_PD23_1, - TNETV107X_PIN_SSP1_0, - TNETV107X_PIN_GPIO25, - TNETV107X_PIN_UART2_CTS, - TNETV107X_PIN_SSP1_1, - TNETV107X_PIN_GPIO26, - TNETV107X_PIN_UART2_RD, - TNETV107X_PIN_SSP1_2, - TNETV107X_PIN_GPIO27, - TNETV107X_PIN_UART2_RTS, - TNETV107X_PIN_SSP1_3, - TNETV107X_PIN_GPIO28, - TNETV107X_PIN_UART2_TD, - TNETV107X_PIN_UART0_CTS, - TNETV107X_PIN_UART0_RD, - TNETV107X_PIN_UART0_RTS, - TNETV107X_PIN_UART0_TD, - TNETV107X_PIN_UART1_RD, - TNETV107X_PIN_UART1_TD, - TNETV107X_PIN_LCD_AC_NCS, - TNETV107X_PIN_LCD_HSYNC_RNW, - TNETV107X_PIN_LCD_VSYNC_A0, - TNETV107X_PIN_LCD_MCLK, - TNETV107X_PIN_LCD_PD16_0, - TNETV107X_PIN_LCD_PCLK_E, - TNETV107X_PIN_LCD_PD00, - TNETV107X_PIN_LCD_PD01, - TNETV107X_PIN_LCD_PD02, - TNETV107X_PIN_LCD_PD03, - TNETV107X_PIN_LCD_PD04, - TNETV107X_PIN_LCD_PD05, - TNETV107X_PIN_LCD_PD06, - TNETV107X_PIN_LCD_PD07, - TNETV107X_PIN_LCD_PD08, - TNETV107X_PIN_GPIO59_1, - TNETV107X_PIN_LCD_PD09, - TNETV107X_PIN_GPIO60_1, - TNETV107X_PIN_LCD_PD10, - TNETV107X_PIN_ASR_BA0_1, - TNETV107X_PIN_GPIO61_1, - TNETV107X_PIN_LCD_PD11, - TNETV107X_PIN_GPIO62_1, - TNETV107X_PIN_LCD_PD12, - TNETV107X_PIN_GPIO63_1, - TNETV107X_PIN_LCD_PD13, - TNETV107X_PIN_GPIO64_1, - TNETV107X_PIN_LCD_PD14, - TNETV107X_PIN_GPIO29_1, - TNETV107X_PIN_LCD_PD15, - TNETV107X_PIN_GPIO30_1, - TNETV107X_PIN_EINT0, - TNETV107X_PIN_GPIO08, - TNETV107X_PIN_EINT1, - TNETV107X_PIN_GPIO09, - TNETV107X_PIN_GPIO00, - TNETV107X_PIN_LCD_PD20_2, - TNETV107X_PIN_TDM_CLK_IN_2, - TNETV107X_PIN_GPIO01, - TNETV107X_PIN_LCD_PD21_2, - TNETV107X_PIN_24M_CLK_OUT_1, - TNETV107X_PIN_GPIO02, - TNETV107X_PIN_LCD_PD22_2, - TNETV107X_PIN_GPIO03, - TNETV107X_PIN_LCD_PD23_2, - TNETV107X_PIN_GPIO04, - TNETV107X_PIN_LCD_PD16_1, - TNETV107X_PIN_USB0_RXERR, - TNETV107X_PIN_GPIO05, - TNETV107X_PIN_LCD_PD17_1, - TNETV107X_PIN_TDM_CLK_IN_1, - TNETV107X_PIN_GPIO06, - TNETV107X_PIN_LCD_PD18, - TNETV107X_PIN_24M_CLK_OUT_2, - TNETV107X_PIN_GPIO07, - TNETV107X_PIN_LCD_PD19_1, - TNETV107X_PIN_USB1_RXERR, - TNETV107X_PIN_ETH_PLL_CLK, - TNETV107X_PIN_MDIO, - TNETV107X_PIN_MDC, - TNETV107X_PIN_AIC_MUTE_STAT_N, - TNETV107X_PIN_TDM0_CLK, - TNETV107X_PIN_AIC_HNS_EN_N, - TNETV107X_PIN_TDM0_FS, - TNETV107X_PIN_AIC_HDS_EN_STAT_N, - TNETV107X_PIN_TDM0_TX, - TNETV107X_PIN_AIC_HNF_EN_STAT_N, - TNETV107X_PIN_TDM0_RX, -}; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/nand_defs.h deleted file mode 100644 index b298fba90..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * TNETV107X: NAND definitions - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include <asm/arch/hardware.h> -#include <asm/arch/emif_defs.h> - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h deleted file mode 100644 index 1b2fdb792..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK -#define __ASM_ARCH_CLOCK - -struct prcmu { - unsigned int armclkfix_mgt; - unsigned int armclk_mgt; - unsigned int svammdspclk_mgt; - unsigned int siammdspclk_mgt; - unsigned int reserved; - unsigned int sgaclk_mgt; - unsigned int uartclk_mgt; - unsigned int msp02clk_mgt; - unsigned int i2cclk_mgt; - unsigned int sdmmcclk_mgt; - unsigned int slimclk_mgt; - unsigned int per1clk_mgt; - unsigned int per2clk_mgt; - unsigned int per3clk_mgt; - unsigned int per5clk_mgt; - unsigned int per6clk_mgt; - unsigned int per7clk_mgt; - unsigned int lcdclk_mgt; - unsigned int reserved1; - unsigned int bmlclk_mgt; - unsigned int hsitxclk_mgt; - unsigned int hsirxclk_mgt; - unsigned int hdmiclk_mgt; - unsigned int apeatclk_mgt; - unsigned int apetraceclk_mgt; - unsigned int mcdeclk_mgt; - unsigned int ipi2cclk_mgt; - unsigned int dsialtclk_mgt; - unsigned int spare2clk_mgt; - unsigned int dmaclk_mgt; - unsigned int b2r2clk_mgt; - unsigned int tvclk_mgt; - unsigned int unused[82]; - unsigned int tcr; - unsigned int unused1[23]; - unsigned int ape_softrst; -}; - -extern void u8500_clock_enable(int periph, int kern, int cluster); - -void db8500_clocks_init(void); - -#endif /* __ASM_ARCH_CLOCK */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h deleted file mode 100644 index 7c85a8917..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Structures and registers for GPIO access in the Nomadik SoC - * - * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. - * The purpose is that GPIO config found in kernel should work by simply - * copy-paste it to U-boot. - * - * Ported to U-boot by: - * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> - * Copyright (C) 2008 STMicroelectronics - * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> - * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __DB8500_GPIO_H__ -#define __DB8500_GPIO_H__ - -/* Alternate functions: function C is set in hw by setting both A and B */ -enum db8500_gpio_alt { - DB8500_GPIO_ALT_GPIO = 0, - DB8500_GPIO_ALT_A = 1, - DB8500_GPIO_ALT_B = 2, - DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B) -}; - -enum db8500_gpio_pull { - DB8500_GPIO_PULL_NONE, - DB8500_GPIO_PULL_UP, - DB8500_GPIO_PULL_DOWN -}; - -void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull); -void db8500_gpio_make_input(unsigned gpio); -int db8500_gpio_get_input(unsigned gpio); -void db8500_gpio_make_output(unsigned gpio, int val); -void db8500_gpio_set_output(unsigned gpio, int val); - -#endif /* __DB8500_GPIO_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h deleted file mode 100644 index 64957016c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. - * The purpose is that GPIO config found in kernel should work by simply - * copy-paste it to U-boot. Ported 2010 to U-boot by: - * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com> - * - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * - * - * Based on arch/arm/mach-pxa/include/mach/mfp.h: - * Copyright (C) 2007 Marvell International Ltd. - * eric miao <eric.miao@marvell.com> - */ - -#ifndef __DB8500_PINCFG_H -#define __DB8500_PINCFG_H - -#include "db8500_gpio.h" - -/* - * U-boot info: - * SLPM (sleep mode) config will be ignored by U-boot but it is still - * possible to configure it in order to keep cut-n-paste compability - * with Linux kernel config. - * - * pin configurations are represented by 32-bit integers: - * - * bit 0.. 8 - Pin Number (512 Pins Maximum) - * bit 9..10 - Alternate Function Selection - * bit 11..12 - Pull up/down state - * bit 13 - Sleep mode behaviour (not used in U-boot) - * bit 14 - Direction - * bit 15 - Value (if output) - * bit 16..18 - SLPM pull up/down state (not used in U-boot) - * bit 19..20 - SLPM direction (not used in U-boot) - * bit 21..22 - SLPM Value (if output) (not used in U-boot) - * - * to facilitate the definition, the following macros are provided - * - * PIN_CFG_DEFAULT - default config (0): - * pull up/down = disabled - * sleep mode = input/wakeup - * direction = input - * value = low - * SLPM direction = same as normal - * SLPM pull = same as normal - * SLPM value = same as normal - * - * PIN_CFG - default config with alternate function - * PIN_CFG_PULL - default config with alternate function and pull up/down - */ - -/* Sleep mode */ -enum db8500_gpio_slpm { - DB8500_GPIO_SLPM_INPUT, - DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT, - DB8500_GPIO_SLPM_NOCHANGE, - DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE, -}; - -#define PIN_NUM_MASK 0x1ff -#define PIN_NUM(x) ((x) & PIN_NUM_MASK) - -#define PIN_ALT_SHIFT 9 -#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) -#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) -#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT) -#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT) -#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT) -#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT) - -#define PIN_PULL_SHIFT 11 -#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) -#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) -#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT) -#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT) -#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT) - -#define PIN_SLPM_SHIFT 13 -#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) -#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) -#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) -#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) -/* These two replace the above in DB8500v2+ */ -#define PIN_SLPM_WAKEUP_ENABLE \ - (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) -#define PIN_SLPM_WAKEUP_DISABLE \ - (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) - -#define PIN_DIR_SHIFT 14 -#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) -#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) -#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) -#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) - -#define PIN_VAL_SHIFT 15 -#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) -#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) -#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) -#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) - -#define PIN_SLPM_PULL_SHIFT 16 -#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL(x) \ - (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_NONE \ - ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_UP \ - ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_DOWN \ - ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) - -#define PIN_SLPM_DIR_SHIFT 19 -#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR(x) \ - (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) - -#define PIN_SLPM_VAL_SHIFT 21 -#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL(x) \ - (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) - -/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ -#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) -#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) -#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) -#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) -#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) - -#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) -#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) -#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) -#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) -#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) - -#define PIN_CFG_DEFAULT (0) - -#define PIN_CFG(num, alt) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt)) - -#define PIN_CFG_INPUT(num, alt, pull) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) - -#define PIN_CFG_OUTPUT(num, alt, val) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) - -#define PIN_CFG_PULL(num, alt, pull) \ - ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ - (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) - -/** - * db8500_gpio_config_pins - configure several pins at once - * @cfgs: array of pin configurations - * @num: number of elments in the array - * - * Configures several GPIO pins. - */ -void db8500_gpio_config_pins(unsigned long *cfgs, size_t num); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h deleted file mode 100644 index afa5942c9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _UX500_GPIO_h -#define _UX500_GPIO_h - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> - -#include <asm/arch/sys_proto.h> -#include <asm/arch/u8500.h> - -#define GPIO_TOTAL_PINS 268 - -#define GPIO_PINS_PER_BLOCK 32 -#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) -#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) - - -struct gpio_register { - u32 gpio_dat; /* data register : 0x000 */ - u32 gpio_dats; /* data Set register : 0x004 */ - u32 gpio_datc; /* data Clear register : 0x008 */ - u32 gpio_pdis; /* Pull disable register : 0x00C */ - u32 gpio_dir; /* data direction register : 0x010 */ - u32 gpio_dirs; /* data dir Set register : 0x014 */ - u32 gpio_dirc; /* data dir Clear register : 0x018 */ - u32 gpio_slpm; /* Sleep mode register : 0x01C */ - u32 gpio_afsa; /* AltFun A Select reg : 0x020 */ - u32 gpio_afsb; /* AltFun B Select reg : 0x024 */ - u32 gpio_lowemi;/* low EMI Select reg : 0x028 */ - u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ - u32 gpio_rimsc; /* rising edge intr set/clear : 0x040 */ - u32 gpio_fimsc; /* falling edge intr set/clear register : 0x044 */ - u32 gpio_mis; /* masked interrupt status register : 0x048 */ - u32 gpio_ic; /* Interrupt Clear register : 0x04C */ - u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */ - u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */ - u32 gpio_wks; /* Wakeup Status register : 0x058 */ -}; - -/* Error values returned by functions */ -enum gpio_error { - GPIO_OK = 0, - GPIO_UNSUPPORTED_HW = -2, - GPIO_UNSUPPORTED_FEATURE = -3, - GPIO_INVALID_PARAMETER = -4, - GPIO_REQUEST_NOT_APPLICABLE = -5, - GPIO_REQUEST_PENDING = -6, - GPIO_NOT_CONFIGURED = -7, - GPIO_INTERNAL_ERROR = -8, - GPIO_INTERNAL_EVENT = 1, - GPIO_REMAINING_EVENT = 2, - GPIO_NO_MORE_PENDING_EVENT = 3, - GPIO_INVALID_CLIENT = -25, - GPIO_INVALID_PIN = -26, - GPIO_PIN_BUSY = -27, - GPIO_PIN_NOT_ALLOCATED = -28, - GPIO_WRONG_CLIENT = -29, - GPIO_UNSUPPORTED_ALTFUNC = -30, -}; - -/*GPIO DEVICE ID */ -enum gpio_device_id { - GPIO_DEVICE_ID_0, - GPIO_DEVICE_ID_1, - GPIO_DEVICE_ID_2, - GPIO_DEVICE_ID_3, - GPIO_DEVICE_ID_INVALID -}; - -/* - * Alternate Function: - * refered in altfun_table to pointout particular altfun to be enabled - * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation - */ -enum gpio_alt_function { - GPIO_ALT_UART_0_MODEM, - GPIO_ALT_UART_0_NO_MODEM, - GPIO_ALT_UART_1, - GPIO_ALT_UART_2, - GPIO_ALT_I2C_0, - GPIO_ALT_I2C_1, - GPIO_ALT_I2C_2, - GPIO_ALT_I2C_3, - GPIO_ALT_MSP_0, - GPIO_ALT_MSP_1, - GPIO_ALT_MSP_2, - GPIO_ALT_MSP_3, - GPIO_ALT_MSP_4, - GPIO_ALT_MSP_5, - GPIO_ALT_SSP_0, - GPIO_ALT_SSP_1, - GPIO_ALT_MM_CARD0, - GPIO_ALT_SD_CARD0, - GPIO_ALT_DMA_0, - GPIO_ALT_DMA_1, - GPIO_ALT_HSI0, - GPIO_ALT_CCIR656_INPUT, - GPIO_ALT_CCIR656_OUTPUT, - GPIO_ALT_LCD_PANEL, - GPIO_ALT_MDIF, - GPIO_ALT_SDRAM, - GPIO_ALT_HAMAC_AUDIO_DBG, - GPIO_ALT_HAMAC_VIDEO_DBG, - GPIO_ALT_CLOCK_RESET, - GPIO_ALT_TSP, - GPIO_ALT_IRDA, - GPIO_ALT_USB_MINIMUM, - GPIO_ALT_USB_I2C, - GPIO_ALT_OWM, - GPIO_ALT_PWL, - GPIO_ALT_FSMC, - GPIO_ALT_COMP_FLASH, - GPIO_ALT_SRAM_NOR_FLASH, - GPIO_ALT_FSMC_ADDLINE_0_TO_15, - GPIO_ALT_SCROLL_KEY, - GPIO_ALT_MSHC, - GPIO_ALT_HPI, - GPIO_ALT_USB_OTG, - GPIO_ALT_SDIO, - GPIO_ALT_HSMMC, - GPIO_ALT_FSMC_ADD_DATA_0_TO_25, - GPIO_ALT_HSI1, - GPIO_ALT_NOR, - GPIO_ALT_NAND, - GPIO_ALT_KEYPAD, - GPIO_ALT_VPIP, - GPIO_ALT_CAM, - GPIO_ALT_CCP1, - GPIO_ALT_EMMC, - GPIO_ALT_POP_EMMC, - GPIO_ALT_FUNMAX /* Add new alt func before this */ -}; - -/* Defines pin assignment(Software mode or Alternate mode) */ -enum gpio_mode { - GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ - GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */ - GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */ - GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */ - GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */ - GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */ -}; - -/* Defines GPIO pin direction */ -enum gpio_direction { - GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_DIR_INPUT, /* GPIO set as input */ - GPIO_DIR_OUTPUT /* GPIO set as output */ -}; - -/* Interrupt trigger mode */ -enum gpio_trig { - GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_TRIG_DISABLE, /* Trigger no IT */ - GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */ - GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */ - GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */ - GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */ - GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */ -}; - -/* Configuration parameters for one GPIO pin.*/ -struct gpio_config { - enum gpio_mode mode; - enum gpio_direction direction; - enum gpio_trig trig; - char *dev_name; /* Who owns the gpio pin */ -}; - -/* GPIO pin data*/ -enum gpio_data { - GPIO_DATA_LOW, - GPIO_DATA_HIGH -}; - -/* GPIO behaviour in sleep mode */ -enum gpio_sleep_mode { - GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull - up/down enabled when in sleep - mode. */ - GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by - GPIO IP. So mode, direction - and data values for GPIO pin - in sleep mode are determined - by configuration set to GPIO - pin before entering to sleep - mode. */ -}; - -/* GPIO ability to wake the system up from sleep mode.*/ -enum gpio_wake { - GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */ - GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */ - GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */ - GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */ - GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */ - GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */ -}; - -/* Configuration parameters for one GPIO pin in sleep mode.*/ -struct gpio_sleep_config { - enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */ - enum gpio_wake wake; /* GPIO ability to wake up system. */ -}; - -extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config); -extern int gpio_resetpinconfig(int pin_id, char *dev_name); -extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name); -extern int gpio_readpin(int pin_id, enum gpio_data *value); -extern int gpio_altfuncenable(enum gpio_alt_function altfunc, - char *dev_name); -extern int gpio_altfuncdisable(enum gpio_alt_function altfunc, - char *dev_name); - -struct gpio_altfun_data { - u16 altfun; - u16 start; - u16 end; - u16 cont; - u8 type; -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h deleted file mode 100644 index e6a899dac..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* Peripheral clusters */ - -#define U8500_PER3_BASE 0x80000000 -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_PER4_BASE 0x80150000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER7_BASE 0xa03d0000 -#define U8500_PER5_BASE 0xa03e0000 - -/* GPIO */ - -#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) -#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80) - -#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000) -#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80) -#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100) -#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180) - -#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000) -#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80) - -#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000) - -/* Per7 */ -#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) - -/* Per6 */ -#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000) -#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* Per5 */ -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* Per4 */ -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) - -/* Per3 */ -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* Per2 */ -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* Per1 */ -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) - -/* Last page of Boot ROM */ -#define U8500_BOOTROM_BASE 0x90000000 -#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) -#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) - -/* AB8500 specifics */ - -/* address bank */ -#define AB8500_REGU_CTRL2 0x0004 -#define AB8500_MISC 0x0010 - -/* registers */ -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 -#define AB8500_REV_REG 0x1080 - -#define AB8500_GPIO_SEL2_REG 0x1001 -#define AB8500_GPIO_DIR2_REG 0x1011 -#define AB8500_GPIO_DIR4_REG 0x1013 -#define AB8500_GPIO_SEL4_REG 0x1003 -#define AB8500_GPIO_OUT2_REG 0x1021 -#define AB8500_GPIO_OUT4_REG 0x1023 - -#define LDO_VAUX3_ENABLE_MASK 0x3 -#define LDO_VAUX3_ENABLE_VAL 0x1 -#define LDO_VAUX3_SEL_MASK 0xf -#define LDO_VAUX3_SEL_2V9 0xd -#define LDO_VAUX3_V2_SEL_MASK 0x7 -#define LDO_VAUX3_V2_SEL_2V91 0x7 - - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h deleted file mode 100644 index e7f045007..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Copied from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __MACH_PRCMU_FW_V1_H -#define __MACH_PRCMU_FW_V1_H - -#define AP_EXECUTE 2 -#define I2CREAD 1 -#define I2C_WR_OK 1 -#define I2C_RD_OK 2 -#define I2CWRITE 0 - -#define PRCMU_BASE U8500_PRCMU_BASE -#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE -#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) -#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) -#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) -#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) -#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) -#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) -#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) -#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) -#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) -#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) -#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC) -#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) - -#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) -#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494) -#define PRCM_TCR (PRCMU_BASE + 0x1C8) -#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44) -#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4) -#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC) -/* Mailbox 5 Requests */ -#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) -#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) -#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) -#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) - -/* Mailbox 5 ACKs */ -#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) -#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) -#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) - -#define LOW_POWER_WAKEUP 1 -#define EXE_WAKEUP 0 - -#define REQ_MB5 5 - -#define ab8500_read prcmu_i2c_read -#define ab8500_write prcmu_i2c_write - -int prcmu_i2c_read(u8 reg, u16 slave); -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); - -void u8500_prcmu_enable(u32 *reg); -void db8500_prcmu_init(void); - -#endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h deleted file mode 100644 index 03a3cd35b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -void gpio_init(void); -int u8500_mmc_power_init(void); - -#endif /* _SYS_PROTO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h deleted file mode 100644 index 16ad081bc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __U8500_H -#define __U8500_H - -/* - * base register values for U8500 - */ -#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock - Management Unit */ -#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ - -/* - * U8500 GPIO register base for 9 banks - */ -#define U8500_GPIO_0_BASE 0x8012E000 -#define U8500_GPIO_1_BASE 0x8012E080 -#define U8500_GPIO_2_BASE 0x8000E000 -#define U8500_GPIO_3_BASE 0x8000E080 -#define U8500_GPIO_4_BASE 0x8000E100 -#define U8500_GPIO_5_BASE 0x8000E180 -#define U8500_GPIO_6_BASE 0x8011E000 -#define U8500_GPIO_7_BASE 0x8011E080 -#define U8500_GPIO_8_BASE 0xA03FE000 - -#endif /* __U8500_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h deleted file mode 100644 index 535adadd7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, -}; - -void enable_ocotp_clk(unsigned char enable); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h deleted file mode 100644 index e17c7d1f7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ -#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ - -#ifndef __ASSEMBLY__ - -/* Clock Controller Module (CCM) */ -struct ccm_reg { - u32 ccr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cscmr1; - u32 cscdr1; - u32 cscdr2; - u32 cscdr3; - u32 cscmr2; - u32 cscdr4; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; - u32 ccgr7; - u32 ccgr8; - u32 ccgr9; - u32 ccgr10; - u32 ccgr11; - u32 cmeor0; - u32 cmeor1; - u32 cmeor2; - u32 cmeor3; - u32 cmeor4; - u32 cmeor5; - u32 cppdsr; - u32 ccowr; - u32 ccpgr0; - u32 ccpgr1; - u32 ccpgr2; - u32 ccpgr3; -}; - -/* Analog components control digital interface (ANADIG) */ -struct anadig_reg { - u32 reserved_0x000[4]; - u32 pll3_ctrl; - u32 reserved_0x014[3]; - u32 pll7_ctrl; - u32 reserved_0x024[3]; - u32 pll2_ctrl; - u32 reserved_0x034[3]; - u32 pll2_ss; - u32 reserved_0x044[3]; - u32 pll2_num; - u32 reserved_0x054[3]; - u32 pll2_denom; - u32 reserved_0x064[3]; - u32 pll4_ctrl; - u32 reserved_0x074[3]; - u32 pll4_num; - u32 reserved_0x084[3]; - u32 pll4_denom; - u32 reserved_0x094[3]; - u32 pll6_ctrl; - u32 reserved_0x0A4[3]; - u32 pll6_num; - u32 reserved_0x0B4[3]; - u32 pll6_denom; - u32 reserved_0x0C4[7]; - u32 pll5_ctrl; - u32 reserved_0x0E4[3]; - u32 pll3_pfd; - u32 reserved_0x0F4[3]; - u32 pll2_pfd; - u32 reserved_0x104[3]; - u32 reg_1p1; - u32 reserved_0x114[3]; - u32 reg_3p0; - u32 reserved_0x124[3]; - u32 reg_2p5; - u32 reserved_0x134[7]; - u32 ana_misc0; - u32 reserved_0x154[3]; - u32 ana_misc1; - u32 reserved_0x164[63]; - u32 anadig_digprog; - u32 reserved_0x264[3]; - u32 pll1_ctrl; - u32 reserved_0x274[3]; - u32 pll1_ss; - u32 reserved_0x284[3]; - u32 pll1_num; - u32 reserved_0x294[3]; - u32 pll1_denom; - u32 reserved_0x2A4[3]; - u32 pll1_pdf; - u32 reserved_0x2B4[3]; - u32 pll_lock; -}; -#endif - -#define CCM_CCR_FIRC_EN (1 << 16) -#define CCM_CCR_OSCNT_MASK 0xff -#define CCM_CCR_OSCNT(v) ((v) & 0xff) - -#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 -#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) -#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) - -#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 -#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) -#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) - -#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) -#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) -#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) -#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) -#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) -#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) -#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) -#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) - -#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) -#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) - -#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 -#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 -#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) - -#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 -#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) -#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) -#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 -#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) -#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) -#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 -#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 -#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) - -#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 -#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) -#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) - -#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) - -#define CCM_CSCDR2_ESDHC1_EN (1 << 29) -#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 -#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) -#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) - -#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 -#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) -#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) - -#define CCM_REG_CTRL_MASK 0xffffffff -#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) -#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) -#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) -#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) -#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) -#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) -#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) -#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) -#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) -#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) -#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 -#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) -#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) -#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) -#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) -#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) -#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) -#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) -#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 -#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) - -#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL5_CTRL_DIV_SELECT 1 -#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL2_CTRL_DIV_SELECT 1 -#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL1_CTRL_DIV_SELECT 1 - -#define FASE_CLK_FREQ 24000000 -#define SLOW_CLK_FREQ 32000 -#define PLL1_PFD1_FREQ 500000000 -#define PLL1_PFD2_FREQ 452000000 -#define PLL1_PFD3_FREQ 396000000 -#define PLL1_PFD4_FREQ 528000000 -#define PLL1_MAIN_FREQ 528000000 -#define PLL2_PFD1_FREQ 500000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD3_FREQ 339000000 -#define PLL2_PFD4_FREQ 413000000 -#define PLL2_MAIN_FREQ 528000000 -#define PLL3_MAIN_FREQ 480000000 -#define PLL3_PFD3_FREQ 298000000 -#define PLL5_MAIN_FREQ 500000000 - -#define ENET_EXTERNAL_CLK 50000000 -#define AUDIO_EXTERNAL_CLK 24576000 - -#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h deleted file mode 100644 index c2f976184..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define ARCH_MXC - -#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ -#define IRAM_SIZE 0x00080000 /* 512 KB */ - -#define AIPS0_BASE_ADDR 0x40000000 -#define AIPS1_BASE_ADDR 0x40080000 - -/* AIPS 0 */ -#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) -#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) -#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) -#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) -#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) -#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) -#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) -#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) -#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) -#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) -#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) -#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) -#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) -#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) -#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) -#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) -#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) -#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) -#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) -#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) -#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) -#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) -#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) -#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) -#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) -#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) -#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) -#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) -#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) -#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) -#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) -#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) -#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) -#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) -#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) -#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) -#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) -#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) -#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) -#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) -#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) -#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) -#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) -#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) -#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) -#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) -#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) -#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) -#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) -#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) -#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) -#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) -#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) -#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) -#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) -#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) -#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) -#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) -#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) -#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) - -/* AIPS 1 */ -#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) -#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) -#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) -#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) -#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) -#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) - -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - -#define FEC_QUIRK_ENET_MAC -#define I2C_QUIRK_REG - -/* MSCM interrupt rounter */ -#define MSCM_IRSPRC_CP0_EN 1 -#define MSCM_IRSPRC_NUM 112 - -/* DDRMC */ -#define DDRMC_PHY_DQ_TIMING 0x00002613 -#define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 -#define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 - -#define DDRMC_PHY50_DDR3_MODE (1 << 12) -#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) - -#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) -#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) -#define DDRMC_CR00_START 1 -#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) -#define DDRMC_CR10_TRST_PWRON(v) (v) -#define DDRMC_CR11_CKE_INACTIVE(v) (v) -#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) -#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) -#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24) -#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16) -#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8) -#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7) -#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24) -#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16) -#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8) -#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff) -#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24) -#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16) -#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8) -#define DDRMC_CR17_TMOD(v) ((v) & 0xff) -#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) -#define DDRMC_CR18_TCKE(v) ((v) & 0x7) -#define DDRMC_CR20_AP_EN (1 << 24) -#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) -#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8) -#define DDRMC_CR21_CCMAP_EN 1 -#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) -#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) -#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) -#define DDRMC_CR25_TREF_EN (1 << 16) -#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) -#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) -#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) -#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff) -#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) -#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) -#define DDRMC_CR31_TXSR(v) ((v) & 0xffff) -#define DDRMC_CR33_EN_QK_SREF (1 << 16) -#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) -#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) -#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) -#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) -#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) -#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1 -#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16) -#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff) -#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16) -#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff) -#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) -#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) -#define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) -#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) -#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) -#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) -#define DDRMC_CR74_BANKSPLT_EN (1 << 24) -#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) -#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) -#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) -#define DDRMC_CR75_RW_PG_EN (1 << 24) -#define DDRMC_CR75_RW_EN (1 << 16) -#define DDRMC_CR75_PRI_EN (1 << 8) -#define DDRMC_CR75_PLEN 1 -#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) -#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) -#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) -#define DDRMC_CR76_CS_EN 1 -#define DDRMC_CR77_CS_MAP (1 << 24) -#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) -#define DDRMC_CR77_SWAP_EN 1 -#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff -#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) -#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) -#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) -#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) -#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) -#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) -#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) -#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) -#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) -#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) -#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) -#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) -#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) -#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16) -#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24) -#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16) -#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8) -#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24) -#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16) -#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) -#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) -#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) -#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) -#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) -#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) -#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) -#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) -#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) -#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) -#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) -#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) -#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) -#define DDRMC_CR158_TWR(v) ((v) & 0x3f) - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr1; - u32 srsr; - u32 secr; - u32 gpsr; - u32 sicr; - u32 simr; - u32 sbmr2; - u32 gpr0; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 hab0; - u32 hab1; - u32 hab2; - u32 hab3; - u32 hab4; - u32 hab5; - u32 misc0; - u32 misc1; - u32 misc2; - u32 misc3; -}; - -/* Periodic Interrupt Timer (PIT) */ -struct pit_reg { - u32 mcr; - u32 recv0[55]; - u32 ltmr64h; - u32 ltmr64l; - u32 recv1[6]; - u32 ldval0; - u32 cval0; - u32 tctrl0; - u32 tflg0; - u32 ldval1; - u32 cval1; - u32 tctrl1; - u32 tflg1; - u32 ldval2; - u32 cval2; - u32 tctrl2; - u32 tflg2; - u32 ldval3; - u32 cval3; - u32 tctrl3; - u32 tflg3; - u32 ldval4; - u32 cval4; - u32 tctrl4; - u32 tflg4; - u32 ldval5; - u32 cval5; - u32 tctrl5; - u32 tflg5; - u32 ldval6; - u32 cval6; - u32 tctrl6; - u32 tflg6; - u32 ldval7; - u32 cval7; - u32 tctrl7; - u32 tflg7; -}; - -/* Watchdog Timer (WDOG) */ -struct wdog_regs { - u16 wcr; - u16 wsr; - u16 wrsr; - u16 wicr; - u16 wmcr; -}; - -/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */ -struct ddrmr_regs { - u32 cr[162]; - u32 rsvd[94]; - u32 phy[53]; -}; - -/* On-Chip One Time Programmable Controller (OCOTP) */ -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[7]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd4[3]; - u32 crc_value; - u32 rsvd5[3]; - u32 version; - u32 rsvd6[0xdb]; - - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[16]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[0x17]; -}; - -struct fuse_bank4_regs { - u32 sjc_resp0; - u32 rsvd0[3]; - u32 sjc_resp1; - u32 rsvd1[3]; - u32 mac_addr0; - u32 rsvd2[3]; - u32 mac_addr1; - u32 rsvd3[3]; - u32 mac_addr2; - u32 rsvd4[3]; - u32 mac_addr3; - u32 rsvd5[3]; - u32 gp1; - u32 rsvd6[3]; - u32 gp2; - u32 rsvd7[3]; -}; - -/* UART */ -struct lpuart_fsl { - u8 ubdh; - u8 ubdl; - u8 uc1; - u8 uc2; - u8 us1; - u8 us2; - u8 uc3; - u8 ud; - u8 uma1; - u8 uma2; - u8 uc4; - u8 uc5; - u8 ued; - u8 umodem; - u8 uir; - u8 reserved; - u8 upfifo; - u8 ucfifo; - u8 usfifo; - u8 utwfifo; - u8 utcfifo; - u8 urwfifo; - u8 urcfifo; - u8 rsvd[28]; -}; - -/* MSCM Interrupt Router */ -struct mscm_ir { - u32 ircp0ir; - u32 ircp1ir; - u32 rsvd1[6]; - u32 ircpgir; - u32 rsvd2[23]; - u16 irsprc[112]; - u16 rsvd3[848]; -}; - -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h deleted file mode 100644 index 88807d8db..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IOMUX_VF610_H__ -#define __IOMUX_VF610_H__ - -#include <asm/imx-common/iomux-v3.h> - -/* Pad control groupings */ -#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm -#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE) - -enum { - VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), -}; - -#endif /* __IOMUX_VF610_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/clk.h deleted file mode 100644 index 250c5bc07..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/clk.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2013 Xilinx Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ZYNQ_CLK_H_ -#define _ZYNQ_CLK_H_ - -enum zynq_clk { - armpll_clk, ddrpll_clk, iopll_clk, - cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, - ddr2x_clk, ddr3x_clk, dci_clk, - lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, - fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, - sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, - usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, - sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, - can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, - uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, - smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; - -void zynq_clk_early_init(void); -int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); -unsigned long zynq_clk_get_rate(enum zynq_clk clk); -const char *zynq_clk_get_name(enum zynq_clk clk); -unsigned long get_uart_clk(int dev_id); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/gpio.h deleted file mode 100644 index 2dbba756d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/gpio.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2013 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ZYNQ_GPIO_H -#define _ZYNQ_GPIO_H - -inline int gpio_get_value(unsigned gpio) -{ - return 0; -} - -inline int gpio_set_value(unsigned gpio, int val) -{ - return 0; -} - -inline int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -#endif /* _ZYNQ_GPIO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/hardware.h deleted file mode 100644 index 39184da40..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/hardware.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2013 Xilinx Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 -#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 -#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 -#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 -#define ZYNQ_SCU_BASEADDR 0xF8F00000 -#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 -#define ZYNQ_GEM_BASEADDR0 0xE000B000 -#define ZYNQ_GEM_BASEADDR1 0xE000C000 -#define ZYNQ_SDHCI_BASEADDR0 0xE0100000 -#define ZYNQ_SDHCI_BASEADDR1 0xE0101000 -#define ZYNQ_I2C_BASEADDR0 0xE0004000 -#define ZYNQ_I2C_BASEADDR1 0xE0005000 -#define ZYNQ_SPI_BASEADDR0 0xE0006000 -#define ZYNQ_SPI_BASEADDR1 0xE0007000 -#define ZYNQ_DDRC_BASEADDR 0xF8006000 - -/* Bootmode setting values */ -#define ZYNQ_BM_MASK 0xF -#define ZYNQ_BM_NOR 0x2 -#define ZYNQ_BM_SD 0x5 -#define ZYNQ_BM_JTAG 0x0 - -/* Reflect slcr offsets */ -struct slcr_regs { - u32 scl; /* 0x0 */ - u32 slcr_lock; /* 0x4 */ - u32 slcr_unlock; /* 0x8 */ - u32 reserved0_1[61]; - u32 arm_pll_ctrl; /* 0x100 */ - u32 ddr_pll_ctrl; /* 0x104 */ - u32 io_pll_ctrl; /* 0x108 */ - u32 reserved0_2[5]; - u32 arm_clk_ctrl; /* 0x120 */ - u32 ddr_clk_ctrl; /* 0x124 */ - u32 dci_clk_ctrl; /* 0x128 */ - u32 aper_clk_ctrl; /* 0x12c */ - u32 reserved0_3[2]; - u32 gem0_rclk_ctrl; /* 0x138 */ - u32 gem1_rclk_ctrl; /* 0x13c */ - u32 gem0_clk_ctrl; /* 0x140 */ - u32 gem1_clk_ctrl; /* 0x144 */ - u32 smc_clk_ctrl; /* 0x148 */ - u32 lqspi_clk_ctrl; /* 0x14c */ - u32 sdio_clk_ctrl; /* 0x150 */ - u32 uart_clk_ctrl; /* 0x154 */ - u32 spi_clk_ctrl; /* 0x158 */ - u32 can_clk_ctrl; /* 0x15c */ - u32 can_mioclk_ctrl; /* 0x160 */ - u32 dbg_clk_ctrl; /* 0x164 */ - u32 pcap_clk_ctrl; /* 0x168 */ - u32 reserved0_4[1]; - u32 fpga0_clk_ctrl; /* 0x170 */ - u32 reserved0_5[3]; - u32 fpga1_clk_ctrl; /* 0x180 */ - u32 reserved0_6[3]; - u32 fpga2_clk_ctrl; /* 0x190 */ - u32 reserved0_7[3]; - u32 fpga3_clk_ctrl; /* 0x1a0 */ - u32 reserved0_8[8]; - u32 clk_621_true; /* 0x1c4 */ - u32 reserved1[14]; - u32 pss_rst_ctrl; /* 0x200 */ - u32 reserved2[15]; - u32 fpga_rst_ctrl; /* 0x240 */ - u32 reserved3[5]; - u32 reboot_status; /* 0x258 */ - u32 boot_mode; /* 0x25c */ - u32 reserved4[116]; - u32 trust_zone; /* 0x430 */ /* FIXME */ - u32 reserved5_1[63]; - u32 pss_idcode; /* 0x530 */ - u32 reserved5_2[51]; - u32 ddr_urgent; /* 0x600 */ - u32 reserved6[6]; - u32 ddr_urgent_sel; /* 0x61c */ - u32 reserved7[56]; - u32 mio_pin[54]; /* 0x700 - 0x7D4 */ - u32 reserved8[74]; - u32 lvl_shftr_en; /* 0x900 */ - u32 reserved9[3]; - u32 ocm_cfg; /* 0x910 */ -}; - -#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR) - -struct devcfg_regs { - u32 ctrl; /* 0x0 */ - u32 lock; /* 0x4 */ - u32 cfg; /* 0x8 */ - u32 int_sts; /* 0xc */ - u32 int_mask; /* 0x10 */ - u32 status; /* 0x14 */ - u32 dma_src_addr; /* 0x18 */ - u32 dma_dst_addr; /* 0x1c */ - u32 dma_src_len; /* 0x20 */ - u32 dma_dst_len; /* 0x24 */ - u32 rom_shadow; /* 0x28 */ - u32 reserved1[2]; - u32 unlock; /* 0x34 */ - u32 reserved2[18]; - u32 mctrl; /* 0x80 */ - u32 reserved3; - u32 write_count; /* 0x88 */ - u32 read_count; /* 0x8c */ -}; - -#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR) - -struct scu_regs { - u32 reserved1[16]; - u32 filter_start; /* 0x40 */ - u32 filter_end; /* 0x44 */ -}; - -#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR) - -struct ddrc_regs { - u32 ddrc_ctrl; /* 0x0 */ - u32 reserved[60]; - u32 ecc_scrub; /* 0xF4 */ -}; -#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/spl.h deleted file mode 100644 index 5789d28bb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/spl.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2014 Xilinx, Inc. Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -extern void ps7_init(void); - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_RAM 1 -#define BOOT_DEVICE_SPI 2 -#define BOOT_DEVICE_MMC1 3 -#define BOOT_DEVICE_MMC2 4 -#define BOOT_DEVICE_MMC2_2 5 - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h deleted file mode 100644 index a68e1b3d2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2013 Xilinx Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -extern void zynq_slcr_lock(void); -extern void zynq_slcr_unlock(void); -extern void zynq_slcr_cpu_reset(void); -extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate); -extern void zynq_slcr_devcfg_disable(void); -extern void zynq_slcr_devcfg_enable(void); -extern u32 zynq_slcr_get_boot_mode(void); -extern u32 zynq_slcr_get_idcode(void); -extern void zynq_ddrc_init(void); - -/* Driver extern functions */ -extern int zynq_sdhci_init(u32 regbase); -extern int zynq_sdhci_of_init(const void *blob); - -#endif /* _SYS_PROTO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/armv7.h b/qemu/roms/u-boot/arch/arm/include/asm/armv7.h deleted file mode 100644 index 395444ee4..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/armv7.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef ARMV7_H -#define ARMV7_H - -/* Cortex-A9 revisions */ -#define MIDR_CORTEX_A9_R0P1 0x410FC091 -#define MIDR_CORTEX_A9_R1P2 0x411FC092 -#define MIDR_CORTEX_A9_R1P3 0x411FC093 -#define MIDR_CORTEX_A9_R2P10 0x412FC09A - -/* Cortex-A15 revisions */ -#define MIDR_CORTEX_A15_R0P0 0x410FC0F0 -#define MIDR_CORTEX_A15_R2P2 0x412FC0F2 - -/* Cortex-A7 revisions */ -#define MIDR_CORTEX_A7_R0P0 0x410FC070 - -#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0 - -/* ID_PFR1 feature fields */ -#define CPUID_ARM_SEC_SHIFT 4 -#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT) -#define CPUID_ARM_VIRT_SHIFT 12 -#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT) -#define CPUID_ARM_GENTIMER_SHIFT 16 -#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT) - -/* valid bits in CBAR register / PERIPHBASE value */ -#define CBAR_MASK 0xFFFF8000 - -/* CCSIDR */ -#define CCSIDR_LINE_SIZE_OFFSET 0 -#define CCSIDR_LINE_SIZE_MASK 0x7 -#define CCSIDR_ASSOCIATIVITY_OFFSET 3 -#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) -#define CCSIDR_NUM_SETS_OFFSET 13 -#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) - -/* - * Values for InD field in CSSELR - * Selects the type of cache - */ -#define ARMV7_CSSELR_IND_DATA_UNIFIED 0 -#define ARMV7_CSSELR_IND_INSTRUCTION 1 - -/* Values for Ctype fields in CLIDR */ -#define ARMV7_CLIDR_CTYPE_NO_CACHE 0 -#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 -#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 -#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 -#define ARMV7_CLIDR_CTYPE_UNIFIED 4 - -#ifndef __ASSEMBLY__ -#include <linux/types.h> - -/* - * CP15 Barrier instructions - * Please note that we have separate barrier instructions in ARMv7 - * However, we use the CP15 based instructtions because we use - * -march=armv5 in U-Boot - */ -#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) -#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) -#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) - -void v7_outer_cache_enable(void); -void v7_outer_cache_disable(void); -void v7_outer_cache_flush_all(void); -void v7_outer_cache_inval_all(void); -void v7_outer_cache_flush_range(u32 start, u32 end); -void v7_outer_cache_inval_range(u32 start, u32 end); - -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) - -int armv7_switch_nonsec(void); -int armv7_switch_hyp(void); - -/* defined in assembly file */ -unsigned int _nonsec_init(void); -void _smp_pen(void); -void _switch_to_hyp(void); -#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */ - -#endif /* ! __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/armv8/mmu.h b/qemu/roms/u-boot/arch/arm/include/asm/armv8/mmu.h deleted file mode 100644 index 1193e76a8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/armv8/mmu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2013 - * David Feng <fenghua@phytium.com.cn> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARMV8_MMU_H_ -#define _ASM_ARMV8_MMU_H_ - -#ifdef __ASSEMBLY__ -#define _AC(X, Y) X -#else -#define _AC(X, Y) (X##Y) -#endif - -#define UL(x) _AC(x, UL) - -/***************************************************************/ -/* - * The following definitions are related each other, shoud be - * calculated specifically. - */ -#define VA_BITS (42) /* 42 bits virtual address */ - -/* PAGE_SHIFT determines the page size */ -#undef PAGE_SIZE -#define PAGE_SHIFT 16 -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -/* - * section address mask and size definitions. - */ -#define SECTION_SHIFT 29 -#define SECTION_SIZE (UL(1) << SECTION_SHIFT) -#define SECTION_MASK (~(SECTION_SIZE-1)) -/***************************************************************/ - -/* - * Memory types - */ -#define MT_DEVICE_NGNRNE 0 -#define MT_DEVICE_NGNRE 1 -#define MT_DEVICE_GRE 2 -#define MT_NORMAL_NC 3 -#define MT_NORMAL 4 - -#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ - (0x04 << (MT_DEVICE_NGNRE*8)) | \ - (0x0c << (MT_DEVICE_GRE*8)) | \ - (0x44 << (MT_NORMAL_NC*8)) | \ - (UL(0xff) << (MT_NORMAL*8))) - -/* - * Hardware page table definitions. - * - * Level 2 descriptor (PMD). - */ -#define PMD_TYPE_MASK (3 << 0) -#define PMD_TYPE_FAULT (0 << 0) -#define PMD_TYPE_TABLE (3 << 0) -#define PMD_TYPE_SECT (1 << 0) - -/* - * Section - */ -#define PMD_SECT_S (3 << 8) -#define PMD_SECT_AF (1 << 10) -#define PMD_SECT_NG (1 << 11) -#define PMD_SECT_PXN (UL(1) << 53) -#define PMD_SECT_UXN (UL(1) << 54) - -/* - * AttrIndx[2:0] - */ -#define PMD_ATTRINDX(t) ((t) << 2) -#define PMD_ATTRINDX_MASK (7 << 2) - -/* - * TCR flags. - */ -#define TCR_T0SZ(x) ((64 - (x)) << 0) -#define TCR_IRGN_NC (0 << 8) -#define TCR_IRGN_WBWA (1 << 8) -#define TCR_IRGN_WT (2 << 8) -#define TCR_IRGN_WBNWA (3 << 8) -#define TCR_IRGN_MASK (3 << 8) -#define TCR_ORGN_NC (0 << 10) -#define TCR_ORGN_WBWA (1 << 10) -#define TCR_ORGN_WT (2 << 10) -#define TCR_ORGN_WBNWA (3 << 10) -#define TCR_ORGN_MASK (3 << 10) -#define TCR_SHARED_NON (0 << 12) -#define TCR_SHARED_OUTER (1 << 12) -#define TCR_SHARED_INNER (2 << 12) -#define TCR_TG0_4K (0 << 14) -#define TCR_TG0_64K (1 << 14) -#define TCR_TG0_16K (2 << 14) -#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ -#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ -#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ - -/* PTWs cacheable, inner/outer WBWA and non-shareable */ -#define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(VA_BITS)) - -#endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/assembler.h b/qemu/roms/u-boot/arch/arm/include/asm/assembler.h deleted file mode 100644 index 5e4789b14..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/assembler.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/include/asm/assembler.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file contains arm architecture specific defines - * for the different processors. - * - * Do not include any C declarations in this file - it is included by - * assembler source. - */ - -/* - * Endian independent macros for shifting bytes within registers. - */ -#ifndef __ARMEB__ -#define pull lsr -#define push lsl -#define get_byte_0 lsl #0 -#define get_byte_1 lsr #8 -#define get_byte_2 lsr #16 -#define get_byte_3 lsr #24 -#define put_byte_0 lsl #0 -#define put_byte_1 lsl #8 -#define put_byte_2 lsl #16 -#define put_byte_3 lsl #24 -#else -#define pull lsl -#define push lsr -#define get_byte_0 lsr #24 -#define get_byte_1 lsr #16 -#define get_byte_2 lsr #8 -#define get_byte_3 lsl #0 -#define put_byte_0 lsl #24 -#define put_byte_1 lsl #16 -#define put_byte_2 lsl #8 -#define put_byte_3 lsl #0 -#endif - -/* - * Data preload for architectures that support it - */ -#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \ - defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \ - defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \ - defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \ - defined(__ARM_ARCH_7R__) -#define PLD(code...) code -#else -#define PLD(code...) -#endif - -/* - * Cache alligned - */ -#define CALGN(code...) code diff --git a/qemu/roms/u-boot/arch/arm/include/asm/atomic.h b/qemu/roms/u-boot/arch/arm/include/asm/atomic.h deleted file mode 100644 index 1b22eeb5f..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/atomic.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/include/asm-arm/atomic.h - * - * Copyright (c) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - * 13-04-1997 RMK Made functions atomic! - * 07-12-1997 RMK Upgraded for v2.1. - * 26-08-1998 PJB Added #ifdef __KERNEL__ - */ -#ifndef __ASM_ARM_ATOMIC_H -#define __ASM_ARM_ATOMIC_H - -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ -#include <asm/proc/system.h> - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += i; - local_irq_restore(flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= i; - local_irq_restore(flags); -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += 1; - local_irq_restore(flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= 1; - local_irq_restore(flags); -} - -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val -= 1; - local_irq_restore(flags); - - return val == 0; -} - -static inline int atomic_add_negative(int i, volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val += i; - local_irq_restore(flags); - - return val < 0; -} - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags; - - local_irq_save(flags); - *addr &= ~mask; - local_irq_restore(flags); -} - -/* Atomic operations are already serializing on ARM */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#endif -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/bitops.h b/qemu/roms/u-boot/arch/arm/include/asm/bitops.h deleted file mode 100644 index 879e20e02..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/bitops.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright 1995, Russell King. - * Various bits and pieces copyrights include: - * Linus Torvalds (test_bit). - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - * - * Please note that the code in this file should never be included - * from user space. Many of these are not implemented in assembler - * since they would be too costly. Also, they require priviledged - * instructions (which are not available from user mode) to ensure - * that they are atomic. - */ - -#ifndef __ASM_ARM_BITOPS_H -#define __ASM_ARM_BITOPS_H - -#ifdef __KERNEL__ - -#include <asm/proc/system.h> - -#define smp_mb__before_clear_bit() do { } while (0) -#define smp_mb__after_clear_bit() do { } while (0) - -/* - * Function prototypes to keep gcc -Wall happy. - */ -extern void set_bit(int nr, volatile void * addr); - -extern void clear_bit(int nr, volatile void * addr); - -extern void change_bit(int nr, volatile void * addr); - -static inline void __change_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - - *p ^= mask; -} - -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -static inline int test_and_set_bit(int nr, volatile void * addr) -{ - unsigned long flags; - int out; - - local_irq_save(flags); - out = __test_and_set_bit(nr, addr); - local_irq_restore(flags); - - return out; -} - -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - -static inline int test_and_clear_bit(int nr, volatile void * addr) -{ - unsigned long flags; - int out; - - local_irq_save(flags); - out = __test_and_clear_bit(nr, addr); - local_irq_restore(flags); - - return out; -} - -extern int test_and_change_bit(int nr, volatile void * addr); - -static inline int __test_and_change_bit(int nr, volatile void *addr) -{ - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old = *p; - - *p = old ^ mask; - return (old & mask) != 0; -} - -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit(void * addr, int size, int offset); - -/* - * This routine doesn't need to be atomic. - */ -static inline int test_bit(int nr, const void * addr) -{ - return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); -} - -static inline int __ilog2(unsigned int x) -{ - return generic_fls(x) - 1; -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} - -/* - * hweightN: returns the hamming weight (i.e. the number - * of bits set) of a N-bit word - */ - -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -#define ext2_set_bit test_and_set_bit -#define ext2_clear_bit test_and_clear_bit -#define ext2_test_bit test_bit -#define ext2_find_first_zero_bit find_first_zero_bit -#define ext2_find_next_zero_bit find_next_zero_bit - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* __KERNEL__ */ - -#endif /* _ARM_BITOPS_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/bootm.h b/qemu/roms/u-boot/arch/arm/include/asm/bootm.h deleted file mode 100644 index 436c35a6d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/bootm.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2013, Google Inc. - * - * Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef ARM_BOOTM_H -#define ARM_BOOTM_H - -extern void udc_disconnect(void); - -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) -# define BOOTM_ENABLE_TAGS 1 -#else -# define BOOTM_ENABLE_TAGS 0 -#endif - -#ifdef CONFIG_SETUP_MEMORY_TAGS -# define BOOTM_ENABLE_MEMORY_TAGS 1 -#else -# define BOOTM_ENABLE_MEMORY_TAGS 0 -#endif - -#ifdef CONFIG_CMDLINE_TAG - #define BOOTM_ENABLE_CMDLINE_TAG 1 -#else - #define BOOTM_ENABLE_CMDLINE_TAG 0 -#endif - -#ifdef CONFIG_INITRD_TAG - #define BOOTM_ENABLE_INITRD_TAG 1 -#else - #define BOOTM_ENABLE_INITRD_TAG 0 -#endif - -#ifdef CONFIG_SERIAL_TAG - #define BOOTM_ENABLE_SERIAL_TAG 1 -void get_board_serial(struct tag_serialnr *serialnr); -#else - #define BOOTM_ENABLE_SERIAL_TAG 0 -static inline void get_board_serial(struct tag_serialnr *serialnr) -{ -} -#endif - -#ifdef CONFIG_REVISION_TAG - #define BOOTM_ENABLE_REVISION_TAG 1 -u32 get_board_rev(void); -#else - #define BOOTM_ENABLE_REVISION_TAG 0 -static inline u32 get_board_rev(void) -{ - return 0; -} -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/byteorder.h b/qemu/roms/u-boot/arch/arm/include/asm/byteorder.h deleted file mode 100644 index 20cce7657..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/byteorder.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * linux/include/asm-arm/byteorder.h - * - * ARM Endian-ness. In little endian mode, the data bus is connected such - * that byte accesses appear as: - * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 - * and word accesses (data or instruction) appear as: - * d0...d31 - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_ARM_BYTEORDER_H -#define __ASM_ARM_BYTEORDER_H - - -#include <asm/types.h> - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#if defined(__ARMEB__) || defined(__AARCH64EB__) -#include <linux/byteorder/big_endian.h> -#else -#include <linux/byteorder/little_endian.h> -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/cache.h b/qemu/roms/u-boot/arch/arm/include/asm/cache.h deleted file mode 100644 index ddebbc8fc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/cache.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include <asm/system.h> - -#ifndef CONFIG_ARM64 - -/* - * Invalidate L2 Cache using co-proc instruction - */ -static inline void invalidate_l2_cache(void) -{ - unsigned int val=0; - - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); - isb(); -} - -void l2_cache_enable(void); -void l2_cache_disable(void); -void set_section_dcache(int section, enum dcache_option option); - -void dram_bank_mmu_setup(int bank); - -#endif - -/* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif - -#endif /* _ASM_CACHE_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/config.h b/qemu/roms/u-boot/arch/arm/include/asm/config.h deleted file mode 100644 index 2a20a770b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/config.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_SYS_GENERIC_GLOBAL_DATA - -#define CONFIG_LMB -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - -#ifdef CONFIG_ARM64 -#define CONFIG_PHYS_64BIT -#define CONFIG_STATIC_RELA -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/davinci_rtc.h b/qemu/roms/u-boot/arch/arm/include/asm/davinci_rtc.h deleted file mode 100644 index 575b59088..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/davinci_rtc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on: - * - * ------------------------------------------------------------------------- - * - * linux/include/asm-arm/arch-davinci/hardware.h - * - * Copyright (C) 2006 Texas Instruments. - * - * SPDX-License-Identifier: GPL-2.0 - */ -#ifndef __ASM_DAVINCI_RTC_H -#define __ASM_DAVINCI_RTC_H - -struct davinci_rtc { - unsigned int second; - unsigned int minutes; - unsigned int hours; - unsigned int day; - unsigned int month; /* 0x10 */ - unsigned int year; - unsigned int dotw; - unsigned int resv1; - unsigned int alarmsecond; /* 0x20 */ - unsigned int alarmminute; - unsigned int alarmhour; - unsigned int alarmday; - unsigned int alarmmonth; /* 0x30 */ - unsigned int alarmyear; - unsigned int resv2[2]; - unsigned int ctrl; /* 0x40 */ - unsigned int status; - unsigned int irq; - unsigned int complsb; - unsigned int compmsb; /* 0x50 */ - unsigned int osc; - unsigned int resv3[2]; - unsigned int scratch0; /* 0x60 */ - unsigned int scratch1; - unsigned int scratch2; - unsigned int kick0r; - unsigned int kick1r; /* 0x70 */ -}; - -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define RTC_KICK0R_WE 0x83e70b13 -#define RTC_KICK1R_WE 0x95a4f1e0 -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/dma-mapping.h b/qemu/roms/u-boot/arch/arm/include/asm/dma-mapping.h deleted file mode 100644 index 55a4e266a..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/dma-mapping.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2007 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARM_DMA_MAPPING_H -#define __ASM_ARM_DMA_MAPPING_H - -enum dma_data_direction { - DMA_BIDIRECTIONAL = 0, - DMA_TO_DEVICE = 1, - DMA_FROM_DEVICE = 2, -}; - -static void *dma_alloc_coherent(size_t len, unsigned long *handle) -{ - *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); - return (void *)*handle; -} - -static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, - enum dma_data_direction dir) -{ - return (unsigned long)vaddr; -} - -static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) -{ -} - -#endif /* __ASM_ARM_DMA_MAPPING_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/ehci-omap.h b/qemu/roms/u-boot/arch/arm/include/asm/ehci-omap.h deleted file mode 100644 index c7bca0568..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/ehci-omap.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * OMAP EHCI port support - * Based on LINUX KERNEL - * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* - * Author: Govindraj R <govindraj.raja@ti.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _OMAP_COMMON_EHCI_H_ -#define _OMAP_COMMON_EHCI_H_ - -enum usbhs_omap_port_mode { - OMAP_USBHS_PORT_MODE_UNUSED, - OMAP_EHCI_PORT_MODE_PHY, - OMAP_EHCI_PORT_MODE_TLL, - OMAP_EHCI_PORT_MODE_HSIC, -}; - -#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#else -#define OMAP_HS_USB_PORTS 3 -#endif - -#define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY) -#define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL) -#define is_ehci_hsic_mode(x) ((x) == OMAP_EHCI_PORT_MODE_HSIC) - -/* Values of UHH_REVISION - Note: these are not given in the TRM */ -#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ -#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ -#define OMAP_USBHS_REV2_1 0x50700101 /* OMAP5 */ - -/* UHH Register Set */ -#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) -#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) -#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) -#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) - -#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS 1 -#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) -#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) -#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) - -#define OMAP_P1_MODE_CLEAR (3 << 16) -#define OMAP_P1_MODE_TLL (1 << 16) -#define OMAP_P1_MODE_HSIC (3 << 16) -#define OMAP_P2_MODE_CLEAR (3 << 18) -#define OMAP_P2_MODE_TLL (1 << 18) -#define OMAP_P2_MODE_HSIC (3 << 18) -#define OMAP_P3_MODE_CLEAR (3 << 20) -#define OMAP_P3_MODE_HSIC (3 << 20) - -/* EHCI Register Set */ -#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) -#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 -#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 -#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 -#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 - -#define OMAP_REV1_TLL_CHANNEL_COUNT 3 -#define OMAP_REV2_TLL_CHANNEL_COUNT 2 - -/* TLL Register Set */ -#define OMAP_TLL_CHANNEL_CONF(num) (0x004 * num) -#define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16) -#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15) -#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) -#define OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI (2 << 1) -#define OMAP_TLL_CHANNEL_CONF_CHANEN 1 - -struct omap_usbhs_board_data { - enum usbhs_omap_port_mode port_mode[OMAP_HS_USB_PORTS]; -}; - -struct omap_usbtll { - u32 rev; /* 0x00 */ - u32 hwinfo; /* 0x04 */ - u8 reserved1[0x8]; - u32 sysc; /* 0x10 */ - u32 syss; /* 0x14 */ - u32 irqst; /* 0x18 */ - u32 irqen; /* 0x1c */ - u8 reserved2[0x10]; - u32 shared_conf; /* 0x30 */ - u8 reserved3[0xc]; - u32 channel_conf; /* 0x40 */ -}; - -struct omap_uhh { - u32 rev; /* 0x00 */ - u32 hwinfo; /* 0x04 */ - u8 reserved1[0x8]; - u32 sysc; /* 0x10 */ - u32 syss; /* 0x14 */ - u8 reserved2[0x28]; - u32 hostconfig; /* 0x40 */ - u32 debugcsr; /* 0x44 */ -}; - -struct omap_ehci { - u32 hccapbase; /* 0x00 */ - u32 hcsparams; /* 0x04 */ - u32 hccparams; /* 0x08 */ - u8 reserved1[0x04]; - u32 usbcmd; /* 0x10 */ - u32 usbsts; /* 0x14 */ - u32 usbintr; /* 0x18 */ - u32 frindex; /* 0x1c */ - u32 ctrldssegment; /* 0x20 */ - u32 periodiclistbase; /* 0x24 */ - u32 asysnclistaddr; /* 0x28 */ - u8 reserved2[0x24]; - u32 configflag; /* 0x50 */ - u32 portsc_i; /* 0x54 */ - u8 reserved3[0x38]; - u32 insreg00; /* 0x90 */ - u32 insreg01; /* 0x94 */ - u32 insreg02; /* 0x98 */ - u32 insreg03; /* 0x9c */ - u32 insreg04; /* 0xa0 */ - u32 insreg05_utmi_ulpi; /* 0xa4 */ - u32 insreg06; /* 0xa8 */ - u32 insreg07; /* 0xac */ - u32 insreg08; /* 0xb0 */ -}; - -/* - * FIXME: forward declaration of this structs needed because omap got the - * ehci implementation backwards. move out ehci_hcd_x from board files - */ -struct ehci_hccr; -struct ehci_hcor; - -int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, - struct ehci_hccr **hccr, struct ehci_hcor **hcor); -int omap_ehci_hcd_stop(void); - -#endif /* _OMAP_COMMON_EHCI_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/emif.h b/qemu/roms/u-boot/arch/arm/include/asm/emif.h deleted file mode 100644 index 45668ca4d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/emif.h +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * OMAP44xx EMIF header - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Aneesh V <aneesh@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _EMIF_H_ -#define _EMIF_H_ -#include <asm/types.h> -#include <common.h> -#include <asm/io.h> - -/* Base address */ -#define EMIF1_BASE 0x4c000000 -#define EMIF2_BASE 0x4d000000 - -#define EMIF_4D 0x4 -#define EMIF_4D5 0x5 - -/* Registers shifts, masks and values */ - -/* EMIF_MOD_ID_REV */ -#define EMIF_REG_SCHEME_SHIFT 30 -#define EMIF_REG_SCHEME_MASK (0x3 << 30) -#define EMIF_REG_MODULE_ID_SHIFT 16 -#define EMIF_REG_MODULE_ID_MASK (0xfff << 16) -#define EMIF_REG_RTL_VERSION_SHIFT 11 -#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) -#define EMIF_REG_MAJOR_REVISION_SHIFT 8 -#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) -#define EMIF_REG_MINOR_REVISION_SHIFT 0 -#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) - -/* STATUS */ -#define EMIF_REG_BE_SHIFT 31 -#define EMIF_REG_BE_MASK (1 << 31) -#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 -#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) -#define EMIF_REG_FAST_INIT_SHIFT 29 -#define EMIF_REG_FAST_INIT_MASK (1 << 29) -#define EMIF_REG_PHY_DLL_READY_SHIFT 2 -#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) - -/* SDRAM_CONFIG */ -#define EMIF_REG_SDRAM_TYPE_SHIFT 29 -#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) -#define EMIF_REG_SDRAM_TYPE_DDR1 0 -#define EMIF_REG_SDRAM_TYPE_LPDDR1 1 -#define EMIF_REG_SDRAM_TYPE_DDR2 2 -#define EMIF_REG_SDRAM_TYPE_DDR3 3 -#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4 -#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5 -#define EMIF_REG_IBANK_POS_SHIFT 27 -#define EMIF_REG_IBANK_POS_MASK (0x3 << 27) -#define EMIF_REG_DDR_TERM_SHIFT 24 -#define EMIF_REG_DDR_TERM_MASK (0x7 << 24) -#define EMIF_REG_DDR2_DDQS_SHIFT 23 -#define EMIF_REG_DDR2_DDQS_MASK (1 << 23) -#define EMIF_REG_DYN_ODT_SHIFT 21 -#define EMIF_REG_DYN_ODT_MASK (0x3 << 21) -#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 -#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) -#define EMIF_REG_SDRAM_DRIVE_SHIFT 18 -#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) -#define EMIF_REG_CWL_SHIFT 16 -#define EMIF_REG_CWL_MASK (0x3 << 16) -#define EMIF_REG_NARROW_MODE_SHIFT 14 -#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) -#define EMIF_REG_CL_SHIFT 10 -#define EMIF_REG_CL_MASK (0xf << 10) -#define EMIF_REG_ROWSIZE_SHIFT 7 -#define EMIF_REG_ROWSIZE_MASK (0x7 << 7) -#define EMIF_REG_IBANK_SHIFT 4 -#define EMIF_REG_IBANK_MASK (0x7 << 4) -#define EMIF_REG_EBANK_SHIFT 3 -#define EMIF_REG_EBANK_MASK (1 << 3) -#define EMIF_REG_PAGESIZE_SHIFT 0 -#define EMIF_REG_PAGESIZE_MASK (0x7 << 0) - -/* SDRAM_CONFIG_2 */ -#define EMIF_REG_CS1NVMEN_SHIFT 30 -#define EMIF_REG_CS1NVMEN_MASK (1 << 30) -#define EMIF_REG_EBANK_POS_SHIFT 27 -#define EMIF_REG_EBANK_POS_MASK (1 << 27) -#define EMIF_REG_RDBNUM_SHIFT 4 -#define EMIF_REG_RDBNUM_MASK (0x3 << 4) -#define EMIF_REG_RDBSIZE_SHIFT 0 -#define EMIF_REG_RDBSIZE_MASK (0x7 << 0) - -/* SDRAM_REF_CTRL */ -#define EMIF_REG_INITREF_DIS_SHIFT 31 -#define EMIF_REG_INITREF_DIS_MASK (1 << 31) -#define EMIF_REG_SRT_SHIFT 29 -#define EMIF_REG_SRT_MASK (1 << 29) -#define EMIF_REG_ASR_SHIFT 28 -#define EMIF_REG_ASR_MASK (1 << 28) -#define EMIF_REG_PASR_SHIFT 24 -#define EMIF_REG_PASR_MASK (0x7 << 24) -#define EMIF_REG_REFRESH_RATE_SHIFT 0 -#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) - -/* SDRAM_REF_CTRL_SHDW */ -#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 -#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) - -/* SDRAM_TIM_1 */ -#define EMIF_REG_T_RP_SHIFT 25 -#define EMIF_REG_T_RP_MASK (0xf << 25) -#define EMIF_REG_T_RCD_SHIFT 21 -#define EMIF_REG_T_RCD_MASK (0xf << 21) -#define EMIF_REG_T_WR_SHIFT 17 -#define EMIF_REG_T_WR_MASK (0xf << 17) -#define EMIF_REG_T_RAS_SHIFT 12 -#define EMIF_REG_T_RAS_MASK (0x1f << 12) -#define EMIF_REG_T_RC_SHIFT 6 -#define EMIF_REG_T_RC_MASK (0x3f << 6) -#define EMIF_REG_T_RRD_SHIFT 3 -#define EMIF_REG_T_RRD_MASK (0x7 << 3) -#define EMIF_REG_T_WTR_SHIFT 0 -#define EMIF_REG_T_WTR_MASK (0x7 << 0) - -/* SDRAM_TIM_1_SHDW */ -#define EMIF_REG_T_RP_SHDW_SHIFT 25 -#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) -#define EMIF_REG_T_RCD_SHDW_SHIFT 21 -#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) -#define EMIF_REG_T_WR_SHDW_SHIFT 17 -#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) -#define EMIF_REG_T_RAS_SHDW_SHIFT 12 -#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) -#define EMIF_REG_T_RC_SHDW_SHIFT 6 -#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) -#define EMIF_REG_T_RRD_SHDW_SHIFT 3 -#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) -#define EMIF_REG_T_WTR_SHDW_SHIFT 0 -#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) - -/* SDRAM_TIM_2 */ -#define EMIF_REG_T_XP_SHIFT 28 -#define EMIF_REG_T_XP_MASK (0x7 << 28) -#define EMIF_REG_T_ODT_SHIFT 25 -#define EMIF_REG_T_ODT_MASK (0x7 << 25) -#define EMIF_REG_T_XSNR_SHIFT 16 -#define EMIF_REG_T_XSNR_MASK (0x1ff << 16) -#define EMIF_REG_T_XSRD_SHIFT 6 -#define EMIF_REG_T_XSRD_MASK (0x3ff << 6) -#define EMIF_REG_T_RTP_SHIFT 3 -#define EMIF_REG_T_RTP_MASK (0x7 << 3) -#define EMIF_REG_T_CKE_SHIFT 0 -#define EMIF_REG_T_CKE_MASK (0x7 << 0) - -/* SDRAM_TIM_2_SHDW */ -#define EMIF_REG_T_XP_SHDW_SHIFT 28 -#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) -#define EMIF_REG_T_ODT_SHDW_SHIFT 25 -#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) -#define EMIF_REG_T_XSNR_SHDW_SHIFT 16 -#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) -#define EMIF_REG_T_XSRD_SHDW_SHIFT 6 -#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) -#define EMIF_REG_T_RTP_SHDW_SHIFT 3 -#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) -#define EMIF_REG_T_CKE_SHDW_SHIFT 0 -#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) - -/* SDRAM_TIM_3 */ -#define EMIF_REG_T_CKESR_SHIFT 21 -#define EMIF_REG_T_CKESR_MASK (0x7 << 21) -#define EMIF_REG_ZQ_ZQCS_SHIFT 15 -#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) -#define EMIF_REG_T_TDQSCKMAX_SHIFT 13 -#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) -#define EMIF_REG_T_RFC_SHIFT 4 -#define EMIF_REG_T_RFC_MASK (0x1ff << 4) -#define EMIF_REG_T_RAS_MAX_SHIFT 0 -#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) - -/* SDRAM_TIM_3_SHDW */ -#define EMIF_REG_T_CKESR_SHDW_SHIFT 21 -#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) -#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 -#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) -#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 -#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) -#define EMIF_REG_T_RFC_SHDW_SHIFT 4 -#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) -#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 -#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) - -/* LPDDR2_NVM_TIM */ -#define EMIF_REG_NVM_T_XP_SHIFT 28 -#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) -#define EMIF_REG_NVM_T_WTR_SHIFT 24 -#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) -#define EMIF_REG_NVM_T_RP_SHIFT 20 -#define EMIF_REG_NVM_T_RP_MASK (0xf << 20) -#define EMIF_REG_NVM_T_WRA_SHIFT 16 -#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) -#define EMIF_REG_NVM_T_RRD_SHIFT 8 -#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) -#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 -#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) - -/* LPDDR2_NVM_TIM_SHDW */ -#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 -#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) -#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 -#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) -#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 -#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) -#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 -#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) -#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 -#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) -#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 -#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) - -/* PWR_MGMT_CTRL */ -#define EMIF_REG_IDLEMODE_SHIFT 30 -#define EMIF_REG_IDLEMODE_MASK (0x3 << 30) -#define EMIF_REG_PD_TIM_SHIFT 12 -#define EMIF_REG_PD_TIM_MASK (0xf << 12) -#define EMIF_REG_DPD_EN_SHIFT 11 -#define EMIF_REG_DPD_EN_MASK (1 << 11) -#define EMIF_REG_LP_MODE_SHIFT 8 -#define EMIF_REG_LP_MODE_MASK (0x7 << 8) -#define EMIF_REG_SR_TIM_SHIFT 4 -#define EMIF_REG_SR_TIM_MASK (0xf << 4) -#define EMIF_REG_CS_TIM_SHIFT 0 -#define EMIF_REG_CS_TIM_MASK (0xf << 0) - -/* PWR_MGMT_CTRL_SHDW */ -#define EMIF_REG_PD_TIM_SHDW_SHIFT 12 -#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) -#define EMIF_REG_SR_TIM_SHDW_SHIFT 4 -#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) -#define EMIF_REG_CS_TIM_SHDW_SHIFT 0 -#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) - -/* LPDDR2_MODE_REG_DATA */ -#define EMIF_REG_VALUE_0_SHIFT 0 -#define EMIF_REG_VALUE_0_MASK (0x7f << 0) - -/* LPDDR2_MODE_REG_CFG */ -#define EMIF_REG_CS_SHIFT 31 -#define EMIF_REG_CS_MASK (1 << 31) -#define EMIF_REG_REFRESH_EN_SHIFT 30 -#define EMIF_REG_REFRESH_EN_MASK (1 << 30) -#define EMIF_REG_ADDRESS_SHIFT 0 -#define EMIF_REG_ADDRESS_MASK (0xff << 0) - -/* OCP_CONFIG */ -#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 -#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) -#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 -#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) -#define EMIF_REG_LL_THRESH_MAX_SHIFT 16 -#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) -#define EMIF_REG_PR_OLD_COUNT_SHIFT 0 -#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) - -/* OCP_CFG_VAL_1 */ -#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 -#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) -#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 -#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) -#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 -#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) -#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 -#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) - -/* OCP_CFG_VAL_2 */ -#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 -#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) -#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 -#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) -#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 -#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) - -/* IODFT_TLGC */ -#define EMIF_REG_TLEC_SHIFT 16 -#define EMIF_REG_TLEC_MASK (0xffff << 16) -#define EMIF_REG_MT_SHIFT 14 -#define EMIF_REG_MT_MASK (1 << 14) -#define EMIF_REG_ACT_CAP_EN_SHIFT 13 -#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) -#define EMIF_REG_OPG_LD_SHIFT 12 -#define EMIF_REG_OPG_LD_MASK (1 << 12) -#define EMIF_REG_RESET_PHY_SHIFT 10 -#define EMIF_REG_RESET_PHY_MASK (1 << 10) -#define EMIF_REG_MMS_SHIFT 8 -#define EMIF_REG_MMS_MASK (1 << 8) -#define EMIF_REG_MC_SHIFT 4 -#define EMIF_REG_MC_MASK (0x3 << 4) -#define EMIF_REG_PC_SHIFT 1 -#define EMIF_REG_PC_MASK (0x7 << 1) -#define EMIF_REG_TM_SHIFT 0 -#define EMIF_REG_TM_MASK (1 << 0) - -/* IODFT_CTRL_MISR_RSLT */ -#define EMIF_REG_DQM_TLMR_SHIFT 16 -#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) -#define EMIF_REG_CTL_TLMR_SHIFT 0 -#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) - -/* IODFT_ADDR_MISR_RSLT */ -#define EMIF_REG_ADDR_TLMR_SHIFT 0 -#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) - -/* IODFT_DATA_MISR_RSLT_1 */ -#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 -#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) - -/* IODFT_DATA_MISR_RSLT_2 */ -#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 -#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) - -/* IODFT_DATA_MISR_RSLT_3 */ -#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 -#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) - -/* PERF_CNT_1 */ -#define EMIF_REG_COUNTER1_SHIFT 0 -#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) - -/* PERF_CNT_2 */ -#define EMIF_REG_COUNTER2_SHIFT 0 -#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) - -/* PERF_CNT_CFG */ -#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 -#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) -#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 -#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) -#define EMIF_REG_CNTR2_CFG_SHIFT 16 -#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) -#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 -#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) -#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 -#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) -#define EMIF_REG_CNTR1_CFG_SHIFT 0 -#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) - -/* PERF_CNT_SEL */ -#define EMIF_REG_MCONNID2_SHIFT 24 -#define EMIF_REG_MCONNID2_MASK (0xff << 24) -#define EMIF_REG_REGION_SEL2_SHIFT 16 -#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) -#define EMIF_REG_MCONNID1_SHIFT 8 -#define EMIF_REG_MCONNID1_MASK (0xff << 8) -#define EMIF_REG_REGION_SEL1_SHIFT 0 -#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) - -/* PERF_CNT_TIM */ -#define EMIF_REG_TOTAL_TIME_SHIFT 0 -#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) - -/* READ_IDLE_CTRL */ -#define EMIF_REG_READ_IDLE_LEN_SHIFT 16 -#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) -#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 -#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) - -/* READ_IDLE_CTRL_SHDW */ -#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 -#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) -#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 -#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) - -/* IRQ_EOI */ -#define EMIF_REG_EOI_SHIFT 0 -#define EMIF_REG_EOI_MASK (1 << 0) - -/* IRQSTATUS_RAW_SYS */ -#define EMIF_REG_DNV_SYS_SHIFT 2 -#define EMIF_REG_DNV_SYS_MASK (1 << 2) -#define EMIF_REG_TA_SYS_SHIFT 1 -#define EMIF_REG_TA_SYS_MASK (1 << 1) -#define EMIF_REG_ERR_SYS_SHIFT 0 -#define EMIF_REG_ERR_SYS_MASK (1 << 0) - -/* IRQSTATUS_RAW_LL */ -#define EMIF_REG_DNV_LL_SHIFT 2 -#define EMIF_REG_DNV_LL_MASK (1 << 2) -#define EMIF_REG_TA_LL_SHIFT 1 -#define EMIF_REG_TA_LL_MASK (1 << 1) -#define EMIF_REG_ERR_LL_SHIFT 0 -#define EMIF_REG_ERR_LL_MASK (1 << 0) - -/* IRQSTATUS_SYS */ - -/* IRQSTATUS_LL */ - -/* IRQENABLE_SET_SYS */ -#define EMIF_REG_EN_DNV_SYS_SHIFT 2 -#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) -#define EMIF_REG_EN_TA_SYS_SHIFT 1 -#define EMIF_REG_EN_TA_SYS_MASK (1 << 1) -#define EMIF_REG_EN_ERR_SYS_SHIFT 0 -#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) - -/* IRQENABLE_SET_LL */ -#define EMIF_REG_EN_DNV_LL_SHIFT 2 -#define EMIF_REG_EN_DNV_LL_MASK (1 << 2) -#define EMIF_REG_EN_TA_LL_SHIFT 1 -#define EMIF_REG_EN_TA_LL_MASK (1 << 1) -#define EMIF_REG_EN_ERR_LL_SHIFT 0 -#define EMIF_REG_EN_ERR_LL_MASK (1 << 0) - -/* IRQENABLE_CLR_SYS */ - -/* IRQENABLE_CLR_LL */ - -/* ZQ_CONFIG */ -#define EMIF_REG_ZQ_CS1EN_SHIFT 31 -#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) -#define EMIF_REG_ZQ_CS0EN_SHIFT 30 -#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) -#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 -#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) -#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 -#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) -#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 -#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) -#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 -#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) -#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 -#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) - -/* TEMP_ALERT_CONFIG */ -#define EMIF_REG_TA_CS1EN_SHIFT 31 -#define EMIF_REG_TA_CS1EN_MASK (1 << 31) -#define EMIF_REG_TA_CS0EN_SHIFT 30 -#define EMIF_REG_TA_CS0EN_MASK (1 << 30) -#define EMIF_REG_TA_SFEXITEN_SHIFT 28 -#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) -#define EMIF_REG_TA_DEVWDT_SHIFT 26 -#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) -#define EMIF_REG_TA_DEVCNT_SHIFT 24 -#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) -#define EMIF_REG_TA_REFINTERVAL_SHIFT 0 -#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) - -/* OCP_ERR_LOG */ -#define EMIF_REG_MADDRSPACE_SHIFT 14 -#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) -#define EMIF_REG_MBURSTSEQ_SHIFT 11 -#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) -#define EMIF_REG_MCMD_SHIFT 8 -#define EMIF_REG_MCMD_MASK (0x7 << 8) -#define EMIF_REG_MCONNID_SHIFT 0 -#define EMIF_REG_MCONNID_MASK (0xff << 0) - -/* DDR_PHY_CTRL_1 */ -#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 -#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) -#define EMIF_REG_READ_LATENCY_SHIFT 0 -#define EMIF_REG_READ_LATENCY_MASK (0xf << 0) -#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 -#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) -#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 -#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) - -/* DDR_PHY_CTRL_1_SHDW */ -#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 -#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) -#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 -#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) -#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 -#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) -#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 -#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) - -/* DDR_PHY_CTRL_2 */ -#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 -#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) - -/*EMIF_READ_WRITE_LEVELING_CONTROL*/ -#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 -#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) -#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 -#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) -#define EMIF_REG_RDLVLINC_INT_SHIFT 16 -#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) -#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 -#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) -#define EMIF_REG_WRLVLINC_INT_SHIFT 0 -#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) - -/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ -#define EMIF_REG_RDWRLVL_EN_SHIFT 31 -#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) -#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 -#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) -#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 -#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) -#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 -#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) -#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 -#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) - -/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ -#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 -#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) - -/*Leveling Fields */ -#define DDR3_WR_LVL_INT 0x73 -#define DDR3_RD_LVL_INT 0x33 -#define DDR3_RD_LVL_GATE_INT 0x59 -#define RD_RW_LVL_INC_PRE 0x0 -#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) - -#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ - | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ - | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ - | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) - -#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 -#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 -#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 - -/* DMM */ -#define DMM_BASE 0x4E000040 - -/* Memory Adapter */ -#define MA_BASE 0x482AF040 - -/* DMM_LISA_MAP */ -#define EMIF_SYS_ADDR_SHIFT 24 -#define EMIF_SYS_ADDR_MASK (0xff << 24) -#define EMIF_SYS_SIZE_SHIFT 20 -#define EMIF_SYS_SIZE_MASK (0x7 << 20) -#define EMIF_SDRC_INTL_SHIFT 18 -#define EMIF_SDRC_INTL_MASK (0x3 << 18) -#define EMIF_SDRC_ADDRSPC_SHIFT 16 -#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) -#define EMIF_SDRC_MAP_SHIFT 8 -#define EMIF_SDRC_MAP_MASK (0x3 << 8) -#define EMIF_SDRC_ADDR_SHIFT 0 -#define EMIF_SDRC_ADDR_MASK (0xff << 0) - -/* DMM_LISA_MAP fields */ -#define DMM_SDRC_MAP_UNMAPPED 0 -#define DMM_SDRC_MAP_EMIF1_ONLY 1 -#define DMM_SDRC_MAP_EMIF2_ONLY 2 -#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 - -#define DMM_SDRC_INTL_NONE 0 -#define DMM_SDRC_INTL_128B 1 -#define DMM_SDRC_INTL_256B 2 -#define DMM_SDRC_INTL_512 3 - -#define DMM_SDRC_ADDR_SPC_SDRAM 0 -#define DMM_SDRC_ADDR_SPC_NVM 1 -#define DMM_SDRC_ADDR_SPC_INVALID 2 - -#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ - (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ - (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) - -#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) - -#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) - -/* Trap for invalid TILER PAT entries */ -#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ - (0 << EMIF_SDRC_ADDR_SHIFT) |\ - (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ - (0xFF << EMIF_SYS_ADDR_SHIFT)) - -#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 - -/* Reg mapping structure */ -struct emif_reg_struct { - u32 emif_mod_id_rev; - u32 emif_status; - u32 emif_sdram_config; - u32 emif_lpddr2_nvm_config; - u32 emif_sdram_ref_ctrl; - u32 emif_sdram_ref_ctrl_shdw; - u32 emif_sdram_tim_1; - u32 emif_sdram_tim_1_shdw; - u32 emif_sdram_tim_2; - u32 emif_sdram_tim_2_shdw; - u32 emif_sdram_tim_3; - u32 emif_sdram_tim_3_shdw; - u32 emif_lpddr2_nvm_tim; - u32 emif_lpddr2_nvm_tim_shdw; - u32 emif_pwr_mgmt_ctrl; - u32 emif_pwr_mgmt_ctrl_shdw; - u32 emif_lpddr2_mode_reg_data; - u32 padding1[1]; - u32 emif_lpddr2_mode_reg_data_es2; - u32 padding11[1]; - u32 emif_lpddr2_mode_reg_cfg; - u32 emif_l3_config; - u32 emif_l3_cfg_val_1; - u32 emif_l3_cfg_val_2; - u32 emif_iodft_tlgc; - u32 padding2[7]; - u32 emif_perf_cnt_1; - u32 emif_perf_cnt_2; - u32 emif_perf_cnt_cfg; - u32 emif_perf_cnt_sel; - u32 emif_perf_cnt_tim; - u32 padding3; - u32 emif_read_idlectrl; - u32 emif_read_idlectrl_shdw; - u32 padding4; - u32 emif_irqstatus_raw_sys; - u32 emif_irqstatus_raw_ll; - u32 emif_irqstatus_sys; - u32 emif_irqstatus_ll; - u32 emif_irqenable_set_sys; - u32 emif_irqenable_set_ll; - u32 emif_irqenable_clr_sys; - u32 emif_irqenable_clr_ll; - u32 padding5; - u32 emif_zq_config; - u32 emif_temp_alert_config; - u32 emif_l3_err_log; - u32 emif_rd_wr_lvl_rmp_win; - u32 emif_rd_wr_lvl_rmp_ctl; - u32 emif_rd_wr_lvl_ctl; - u32 padding6[1]; - u32 emif_ddr_phy_ctrl_1; - u32 emif_ddr_phy_ctrl_1_shdw; - u32 emif_ddr_phy_ctrl_2; - u32 padding7[12]; - u32 emif_rd_wr_exec_thresh; - u32 padding8[7]; - u32 emif_ddr_phy_status[21]; - u32 padding9[27]; - u32 emif_ddr_ext_phy_ctrl_1; - u32 emif_ddr_ext_phy_ctrl_1_shdw; - u32 emif_ddr_ext_phy_ctrl_2; - u32 emif_ddr_ext_phy_ctrl_2_shdw; - u32 emif_ddr_ext_phy_ctrl_3; - u32 emif_ddr_ext_phy_ctrl_3_shdw; - u32 emif_ddr_ext_phy_ctrl_4; - u32 emif_ddr_ext_phy_ctrl_4_shdw; - u32 emif_ddr_ext_phy_ctrl_5; - u32 emif_ddr_ext_phy_ctrl_5_shdw; - u32 emif_ddr_ext_phy_ctrl_6; - u32 emif_ddr_ext_phy_ctrl_6_shdw; - u32 emif_ddr_ext_phy_ctrl_7; - u32 emif_ddr_ext_phy_ctrl_7_shdw; - u32 emif_ddr_ext_phy_ctrl_8; - u32 emif_ddr_ext_phy_ctrl_8_shdw; - u32 emif_ddr_ext_phy_ctrl_9; - u32 emif_ddr_ext_phy_ctrl_9_shdw; - u32 emif_ddr_ext_phy_ctrl_10; - u32 emif_ddr_ext_phy_ctrl_10_shdw; - u32 emif_ddr_ext_phy_ctrl_11; - u32 emif_ddr_ext_phy_ctrl_11_shdw; - u32 emif_ddr_ext_phy_ctrl_12; - u32 emif_ddr_ext_phy_ctrl_12_shdw; - u32 emif_ddr_ext_phy_ctrl_13; - u32 emif_ddr_ext_phy_ctrl_13_shdw; - u32 emif_ddr_ext_phy_ctrl_14; - u32 emif_ddr_ext_phy_ctrl_14_shdw; - u32 emif_ddr_ext_phy_ctrl_15; - u32 emif_ddr_ext_phy_ctrl_15_shdw; - u32 emif_ddr_ext_phy_ctrl_16; - u32 emif_ddr_ext_phy_ctrl_16_shdw; - u32 emif_ddr_ext_phy_ctrl_17; - u32 emif_ddr_ext_phy_ctrl_17_shdw; - u32 emif_ddr_ext_phy_ctrl_18; - u32 emif_ddr_ext_phy_ctrl_18_shdw; - u32 emif_ddr_ext_phy_ctrl_19; - u32 emif_ddr_ext_phy_ctrl_19_shdw; - u32 emif_ddr_ext_phy_ctrl_20; - u32 emif_ddr_ext_phy_ctrl_20_shdw; - u32 emif_ddr_ext_phy_ctrl_21; - u32 emif_ddr_ext_phy_ctrl_21_shdw; - u32 emif_ddr_ext_phy_ctrl_22; - u32 emif_ddr_ext_phy_ctrl_22_shdw; - u32 emif_ddr_ext_phy_ctrl_23; - u32 emif_ddr_ext_phy_ctrl_23_shdw; - u32 emif_ddr_ext_phy_ctrl_24; - u32 emif_ddr_ext_phy_ctrl_24_shdw; - u32 padding[22]; - u32 emif_ddr_fifo_misaligned_clear_1; - u32 emif_ddr_fifo_misaligned_clear_2; -}; - -struct dmm_lisa_map_regs { - u32 dmm_lisa_map_0; - u32 dmm_lisa_map_1; - u32 dmm_lisa_map_2; - u32 dmm_lisa_map_3; - u8 is_ma_present; -}; - -#define CS0 0 -#define CS1 1 -/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ -#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ - -/* - * The period of DDR clk is represented as numerator and denominator for - * better accuracy in integer based calculations. However, if the numerator - * and denominator are very huge there may be chances of overflow in - * calculations. So, as a trade-off keep denominator(and consequently - * numerator) within a limit sacrificing some accuracy - but not much - * If denominator and numerator are already small (such as at 400 MHz) - * no adjustment is needed - */ -#define EMIF_PERIOD_DEN_LIMIT 1000 -/* - * Maximum number of different frequencies supported by EMIF driver - * Determines the number of entries in the pointer array for register - * cache - */ -#define EMIF_MAX_NUM_FREQUENCIES 6 -/* - * Indices into the Addressing Table array. - * One entry each for all the different types of devices with different - * addressing schemes - */ -#define ADDR_TABLE_INDEX64M 0 -#define ADDR_TABLE_INDEX128M 1 -#define ADDR_TABLE_INDEX256M 2 -#define ADDR_TABLE_INDEX512M 3 -#define ADDR_TABLE_INDEX1GS4 4 -#define ADDR_TABLE_INDEX2GS4 5 -#define ADDR_TABLE_INDEX4G 6 -#define ADDR_TABLE_INDEX8G 7 -#define ADDR_TABLE_INDEX1GS2 8 -#define ADDR_TABLE_INDEX2GS2 9 -#define ADDR_TABLE_INDEXMAX 10 - -/* Number of Row bits */ -#define ROW_9 0 -#define ROW_10 1 -#define ROW_11 2 -#define ROW_12 3 -#define ROW_13 4 -#define ROW_14 5 -#define ROW_15 6 -#define ROW_16 7 - -/* Number of Column bits */ -#define COL_8 0 -#define COL_9 1 -#define COL_10 2 -#define COL_11 3 -#define COL_7 4 /*Not supported by OMAP included for completeness */ - -/* Number of Banks*/ -#define BANKS1 0 -#define BANKS2 1 -#define BANKS4 2 -#define BANKS8 3 - -/* Refresh rate in micro seconds x 10 */ -#define T_REFI_15_6 156 -#define T_REFI_7_8 78 -#define T_REFI_3_9 39 - -#define EBANK_CS1_DIS 0 -#define EBANK_CS1_EN 1 - -/* Read Latency used by the device at reset */ -#define RL_BOOT 3 -/* Read Latency for the highest frequency you want to use */ -#ifdef CONFIG_OMAP54XX -#define RL_FINAL 8 -#else -#define RL_FINAL 6 -#endif - - -/* Interleaving policies at EMIF level- between banks and Chip Selects */ -#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 -#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 - -/* - * Interleaving policy to be used - * Currently set to MAX interleaving for better performance - */ -#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING - -/* State of the core voltage: - * This is important for some parameters such as read idle control and - * ZQ calibration timings. Timings are much stricter when voltage ramp - * is happening compared to when the voltage is stable. - * We need to calculate two sets of values for these parameters and use - * them accordingly - */ -#define LPDDR2_VOLTAGE_STABLE 0 -#define LPDDR2_VOLTAGE_RAMPING 1 - -/* Length of the forced read idle period in terms of cycles */ -#define EMIF_REG_READ_IDLE_LEN_VAL 5 - -/* Interval between forced 'read idles' */ -/* To be used when voltage is changed for DPS/DVFS - 1us */ -#define READ_IDLE_INTERVAL_DVFS (1*1000) -/* - * To be used when voltage is not scaled except by Smart Reflex - * 50us - or maximum value will do - */ -#define READ_IDLE_INTERVAL_NORMAL (50*1000) - - -/* - * Unless voltage is changing due to DVFS one ZQCS command every 50ms should - * be enough. This shoule be enough also in the case when voltage is changing - * due to smart-reflex. - */ -#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) -/* - * If voltage is changing due to DVFS ZQCS should be performed more - * often(every 50us) - */ -#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 - -/* The interval between ZQCL commands as a multiple of ZQCS interval */ -#define REG_ZQ_ZQCL_MULT 4 -/* The interval between ZQINIT commands as a multiple of ZQCL interval */ -#define REG_ZQ_ZQINIT_MULT 3 -/* Enable ZQ Calibration on exiting Self-refresh */ -#define REG_ZQ_SFEXITEN_ENABLE 1 -/* - * ZQ Calibration simultaneously on both chip-selects: - * Needs one calibration resistor per CS - * None of the boards that we know of have this capability - * So disabled by default - */ -#define REG_ZQ_DUALCALEN_DISABLE 0 -/* - * Enable ZQ Calibration by default on CS0. If we are asked to program - * the EMIF there will be something connected to CS0 for sure - */ -#define REG_ZQ_CS0EN_ENABLE 1 - -/* EMIF_PWR_MGMT_CTRL register */ -/* Low power modes */ -#define LP_MODE_DISABLE 0 -#define LP_MODE_CLOCK_STOP 1 -#define LP_MODE_SELF_REFRESH 2 -#define LP_MODE_PWR_DN 3 - -/* REG_DPD_EN */ -#define DPD_DISABLE 0 -#define DPD_ENABLE 1 - -/* Maximum delay before Low Power Modes */ -#define REG_CS_TIM 0x0 -#define REG_SR_TIM 0x0 -#define REG_PD_TIM 0x0 - - -/* EMIF_PWR_MGMT_CTRL register */ -#define EMIF_PWR_MGMT_CTRL (\ - ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ - ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ - ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ - ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ - ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\ - & EMIF_REG_LP_MODE_MASK) |\ - ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ - & EMIF_REG_DPD_EN_MASK))\ - -#define EMIF_PWR_MGMT_CTRL_SHDW (\ - ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ - & EMIF_REG_CS_TIM_SHDW_MASK) |\ - ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ - & EMIF_REG_SR_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ - & EMIF_REG_PD_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ - & EMIF_REG_PD_TIM_SHDW_MASK)) - -/* EMIF_L3_CONFIG register value */ -#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF -#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 -#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000 - -/* - * Value of bits 12:31 of DDR_PHY_CTRL_1 register: - * All these fields have magic values dependent on frequency and - * determined by PHY and DLL integration with EMIF. Setting the magic - * values suggested by hw team. - */ -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF -#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 -#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 -#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF - -/* -* MR1 value: -* Burst length : 8 -* Burst type : sequential -* Wrap : enabled -* nWR : 3(default). EMIF does not do pre-charge. -* : So nWR is don't care -*/ -#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 -#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3 - -/* MR2 */ -#define MR2_RL3_WL1 1 -#define MR2_RL4_WL2 2 -#define MR2_RL5_WL2 3 -#define MR2_RL6_WL3 4 - -/* MR10: ZQ calibration codes */ -#define MR10_ZQ_ZQCS 0x56 -#define MR10_ZQ_ZQCL 0xAB -#define MR10_ZQ_ZQINIT 0xFF -#define MR10_ZQ_ZQRESET 0xC3 - -/* TEMP_ALERT_CONFIG */ -#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ -#define TEMP_ALERT_CONFIG_DEVCT_1 0 -#define TEMP_ALERT_CONFIG_DEVWDT_32 2 - -/* MR16 value: refresh full array(no partial array self refresh) */ -#define MR16_REF_FULL_ARRAY 0 - -/* - * Maximum number of entries we keep in our array of timing tables - * We need not keep all the speed bins supported by the device - * We need to keep timing tables for only the speed bins that we - * are interested in - */ -#define MAX_NUM_SPEEDBINS 4 - -/* LPDDR2 Densities */ -#define LPDDR2_DENSITY_64Mb 0 -#define LPDDR2_DENSITY_128Mb 1 -#define LPDDR2_DENSITY_256Mb 2 -#define LPDDR2_DENSITY_512Mb 3 -#define LPDDR2_DENSITY_1Gb 4 -#define LPDDR2_DENSITY_2Gb 5 -#define LPDDR2_DENSITY_4Gb 6 -#define LPDDR2_DENSITY_8Gb 7 -#define LPDDR2_DENSITY_16Gb 8 -#define LPDDR2_DENSITY_32Gb 9 - -/* LPDDR2 type */ -#define LPDDR2_TYPE_S4 0 -#define LPDDR2_TYPE_S2 1 -#define LPDDR2_TYPE_NVM 2 - -/* LPDDR2 IO width */ -#define LPDDR2_IO_WIDTH_32 0 -#define LPDDR2_IO_WIDTH_16 1 -#define LPDDR2_IO_WIDTH_8 2 - -/* Mode register numbers */ -#define LPDDR2_MR0 0 -#define LPDDR2_MR1 1 -#define LPDDR2_MR2 2 -#define LPDDR2_MR3 3 -#define LPDDR2_MR4 4 -#define LPDDR2_MR5 5 -#define LPDDR2_MR6 6 -#define LPDDR2_MR7 7 -#define LPDDR2_MR8 8 -#define LPDDR2_MR9 9 -#define LPDDR2_MR10 10 -#define LPDDR2_MR11 11 -#define LPDDR2_MR16 16 -#define LPDDR2_MR17 17 -#define LPDDR2_MR18 18 - -/* MR0 */ -#define LPDDR2_MR0_DAI_SHIFT 0 -#define LPDDR2_MR0_DAI_MASK 1 -#define LPDDR2_MR0_DI_SHIFT 1 -#define LPDDR2_MR0_DI_MASK (1 << 1) -#define LPDDR2_MR0_DNVI_SHIFT 2 -#define LPDDR2_MR0_DNVI_MASK (1 << 2) - -/* MR4 */ -#define MR4_SDRAM_REF_RATE_SHIFT 0 -#define MR4_SDRAM_REF_RATE_MASK 7 -#define MR4_TUF_SHIFT 7 -#define MR4_TUF_MASK (1 << 7) - -/* MR4 SDRAM Refresh Rate field values */ -#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 -#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 -#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 -#define SDRAM_TEMP_NOMINAL 0x3 -#define SDRAM_TEMP_RESERVED_4 0x4 -#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 -#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 -#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 - -#define LPDDR2_MANUFACTURER_SAMSUNG 1 -#define LPDDR2_MANUFACTURER_QIMONDA 2 -#define LPDDR2_MANUFACTURER_ELPIDA 3 -#define LPDDR2_MANUFACTURER_ETRON 4 -#define LPDDR2_MANUFACTURER_NANYA 5 -#define LPDDR2_MANUFACTURER_HYNIX 6 -#define LPDDR2_MANUFACTURER_MOSEL 7 -#define LPDDR2_MANUFACTURER_WINBOND 8 -#define LPDDR2_MANUFACTURER_ESMT 9 -#define LPDDR2_MANUFACTURER_SPANSION 11 -#define LPDDR2_MANUFACTURER_SST 12 -#define LPDDR2_MANUFACTURER_ZMOS 13 -#define LPDDR2_MANUFACTURER_INTEL 14 -#define LPDDR2_MANUFACTURER_NUMONYX 254 -#define LPDDR2_MANUFACTURER_MICRON 255 - -/* MR8 register fields */ -#define MR8_TYPE_SHIFT 0x0 -#define MR8_TYPE_MASK 0x3 -#define MR8_DENSITY_SHIFT 0x2 -#define MR8_DENSITY_MASK (0xF << 0x2) -#define MR8_IO_WIDTH_SHIFT 0x6 -#define MR8_IO_WIDTH_MASK (0x3 << 0x6) - -/* SDRAM TYPE */ -#define EMIF_SDRAM_TYPE_DDR2 0x2 -#define EMIF_SDRAM_TYPE_DDR3 0x3 -#define EMIF_SDRAM_TYPE_LPDDR2 0x4 - -struct lpddr2_addressing { - u8 num_banks; - u8 t_REFI_us_x10; - u8 row_sz[2]; /* One entry each for x32 and x16 */ - u8 col_sz[2]; /* One entry each for x32 and x16 */ -}; - -/* Structure for timings from the DDR datasheet */ -struct lpddr2_ac_timings { - u32 max_freq; - u8 RL; - u8 tRPab; - u8 tRCD; - u8 tWR; - u8 tRASmin; - u8 tRRD; - u8 tWTRx2; - u8 tXSR; - u8 tXPx2; - u8 tRFCab; - u8 tRTPx2; - u8 tCKE; - u8 tCKESR; - u8 tZQCS; - u32 tZQCL; - u32 tZQINIT; - u8 tDQSCKMAXx2; - u8 tRASmax; - u8 tFAW; - -}; - -/* - * Min tCK values for some of the parameters: - * If the calculated clock cycles for the respective parameter is - * less than the corresponding min tCK value, we need to set the min - * tCK value. This may happen at lower frequencies. - */ -struct lpddr2_min_tck { - u32 tRL; - u32 tRP_AB; - u32 tRCD; - u32 tWR; - u32 tRAS_MIN; - u32 tRRD; - u32 tWTR; - u32 tXP; - u32 tRTP; - u8 tCKE; - u32 tCKESR; - u32 tFAW; -}; - -struct lpddr2_device_details { - u8 type; - u8 density; - u8 io_width; - u8 manufacturer; -}; - -struct lpddr2_device_timings { - const struct lpddr2_ac_timings **ac_timings; - const struct lpddr2_min_tck *min_tck; -}; - -/* Details of the devices connected to each chip-select of an EMIF instance */ -struct emif_device_details { - const struct lpddr2_device_details *cs0_device_details; - const struct lpddr2_device_details *cs1_device_details; - const struct lpddr2_device_timings *cs0_device_timings; - const struct lpddr2_device_timings *cs1_device_timings; -}; - -/* - * Structure containing shadow of important registers in EMIF - * The calculation function fills in this structure to be later used for - * initialization and DVFS - */ -struct emif_regs { - u32 freq; - u32 sdram_config_init; - u32 sdram_config; - u32 sdram_config2; - u32 ref_ctrl; - u32 sdram_tim1; - u32 sdram_tim2; - u32 sdram_tim3; - u32 read_idle_ctrl; - u32 zq_config; - u32 temp_alert_config; - u32 emif_ddr_phy_ctlr_1_init; - u32 emif_ddr_phy_ctlr_1; - u32 emif_ddr_ext_phy_ctrl_1; - u32 emif_ddr_ext_phy_ctrl_2; - u32 emif_ddr_ext_phy_ctrl_3; - u32 emif_ddr_ext_phy_ctrl_4; - u32 emif_ddr_ext_phy_ctrl_5; - u32 emif_rd_wr_lvl_rmp_win; - u32 emif_rd_wr_lvl_rmp_ctl; - u32 emif_rd_wr_lvl_ctl; - u32 emif_rd_wr_exec_thresh; -}; - -struct lpddr2_mr_regs { - s8 mr1; - s8 mr2; - s8 mr3; - s8 mr10; - s8 mr16; -}; - -struct read_write_regs { - u32 read_reg; - u32 write_reg; -}; - -static inline u32 get_emif_rev(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) - >> EMIF_REG_MAJOR_REVISION_SHIFT; -} - -/* - * Get SDRAM type connected to EMIF. - * Assuming similar SDRAM parts are connected to both EMIF's - * which is typically the case. So it is sufficient to get - * SDRAM type from EMIF1. - */ -static inline u32 emif_sdram_type(void) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; -} - -/* assert macros */ -#if defined(DEBUG) -#define emif_assert(c) ({ if (!(c)) for (;;); }) -#else -#define emif_assert(c) ({ if (0) hang(); }) -#endif - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); -#else -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details); -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings); -#endif - -void do_ext_phy_settings(u32 base, const struct emif_regs *regs); -void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -extern u32 *const T_num; -extern u32 *const T_den; -#endif - -void config_data_eye_leveling_samples(u32 emif_base); -u32 emif_sdram_type(void); -const struct read_write_regs *get_bug_regs(u32 *iterations); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/errno.h b/qemu/roms/u-boot/arch/arm/include/asm/errno.h deleted file mode 100644 index 4c82b503d..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/qemu/roms/u-boot/arch/arm/include/asm/gic.h b/qemu/roms/u-boot/arch/arm/include/asm/gic.h deleted file mode 100644 index bd3a80cdf..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/gic.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef __GIC_H__ -#define __GIC_H__ - -/* Register offsets for the ARM generic interrupt controller (GIC) */ - -#define GIC_DIST_OFFSET 0x1000 -#define GIC_CPU_OFFSET_A9 0x0100 -#define GIC_CPU_OFFSET_A15 0x2000 - -/* Distributor Registers */ -#define GICD_CTLR 0x0000 -#define GICD_TYPER 0x0004 -#define GICD_IIDR 0x0008 -#define GICD_STATUSR 0x0010 -#define GICD_SETSPI_NSR 0x0040 -#define GICD_CLRSPI_NSR 0x0048 -#define GICD_SETSPI_SR 0x0050 -#define GICD_CLRSPI_SR 0x0058 -#define GICD_SEIR 0x0068 -#define GICD_IGROUPRn 0x0080 -#define GICD_ISENABLERn 0x0100 -#define GICD_ICENABLERn 0x0180 -#define GICD_ISPENDRn 0x0200 -#define GICD_ICPENDRn 0x0280 -#define GICD_ISACTIVERn 0x0300 -#define GICD_ICACTIVERn 0x0380 -#define GICD_IPRIORITYRn 0x0400 -#define GICD_ITARGETSRn 0x0800 -#define GICD_ICFGR 0x0c00 -#define GICD_IGROUPMODRn 0x0d00 -#define GICD_NSACRn 0x0e00 -#define GICD_SGIR 0x0f00 -#define GICD_CPENDSGIRn 0x0f10 -#define GICD_SPENDSGIRn 0x0f20 -#define GICD_IROUTERn 0x6000 - -/* Cpu Interface Memory Mapped Registers */ -#define GICC_CTLR 0x0000 -#define GICC_PMR 0x0004 -#define GICC_BPR 0x0008 -#define GICC_IAR 0x000C -#define GICC_EOIR 0x0010 -#define GICC_RPR 0x0014 -#define GICC_HPPIR 0x0018 -#define GICC_ABPR 0x001c -#define GICC_AIAR 0x0020 -#define GICC_AEOIR 0x0024 -#define GICC_AHPPIR 0x0028 -#define GICC_APRn 0x00d0 -#define GICC_NSAPRn 0x00e0 -#define GICC_IIDR 0x00fc -#define GICC_DIR 0x1000 - -/* ReDistributor Registers for Control and Physical LPIs */ -#define GICR_CTLR 0x0000 -#define GICR_IIDR 0x0004 -#define GICR_TYPER 0x0008 -#define GICR_STATUSR 0x0010 -#define GICR_WAKER 0x0014 -#define GICR_SETLPIR 0x0040 -#define GICR_CLRLPIR 0x0048 -#define GICR_SEIR 0x0068 -#define GICR_PROPBASER 0x0070 -#define GICR_PENDBASER 0x0078 -#define GICR_INVLPIR 0x00a0 -#define GICR_INVALLR 0x00b0 -#define GICR_SYNCR 0x00c0 -#define GICR_MOVLPIR 0x0100 -#define GICR_MOVALLR 0x0110 - -/* ReDistributor Registers for SGIs and PPIs */ -#define GICR_IGROUPRn 0x0080 -#define GICR_ISENABLERn 0x0100 -#define GICR_ICENABLERn 0x0180 -#define GICR_ISPENDRn 0x0200 -#define GICR_ICPENDRn 0x0280 -#define GICR_ISACTIVERn 0x0300 -#define GICR_ICACTIVERn 0x0380 -#define GICR_IPRIORITYRn 0x0400 -#define GICR_ICFGR0 0x0c00 -#define GICR_ICFGR1 0x0c04 -#define GICR_IGROUPMODRn 0x0d00 -#define GICR_NSACRn 0x0e00 - -/* Cpu Interface System Registers */ -#define ICC_IAR0_EL1 S3_0_C12_C8_0 -#define ICC_IAR1_EL1 S3_0_C12_C12_0 -#define ICC_EOIR0_EL1 S3_0_C12_C8_1 -#define ICC_EOIR1_EL1 S3_0_C12_C12_1 -#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 -#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 -#define ICC_BPR0_EL1 S3_0_C12_C8_3 -#define ICC_BPR1_EL1 S3_0_C12_C12_3 -#define ICC_DIR_EL1 S3_0_C12_C11_1 -#define ICC_PMR_EL1 S3_0_C4_C6_0 -#define ICC_RPR_EL1 S3_0_C12_C11_3 -#define ICC_CTLR_EL1 S3_0_C12_C12_4 -#define ICC_CTLR_EL3 S3_6_C12_C12_4 -#define ICC_SRE_EL1 S3_0_C12_C12_5 -#define ICC_SRE_EL2 S3_4_C12_C9_5 -#define ICC_SRE_EL3 S3_6_C12_C12_5 -#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 -#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 -#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 -#define ICC_SEIEN_EL1 S3_0_C12_C13_0 -#define ICC_SGI0R_EL1 S3_0_C12_C11_7 -#define ICC_SGI1R_EL1 S3_0_C12_C11_5 -#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 - -#endif /* __GIC_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/global_data.h b/qemu/roms/u-boot/arch/arm/include/asm/global_data.h deleted file mode 100644 index 63e4ad5a6..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/global_data.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -#ifdef CONFIG_OMAP -#include <asm/omap_boot.h> -#endif - -/* Architecture-specific global data */ -struct arch_global_data { -#if defined(CONFIG_FSL_ESDHC) - u32 sdhc_clk; -#endif -#ifdef CONFIG_AT91FAMILY - /* "static data" needed by at91's clock.c */ - unsigned long cpu_clk_rate_hz; - unsigned long main_clk_rate_hz; - unsigned long mck_rate_hz; - unsigned long plla_rate_hz; - unsigned long pllb_rate_hz; - unsigned long at91_pllb_usb_init; -#endif - /* "static data" needed by most of timer.c on ARM platforms */ - unsigned long timer_rate_hz; - unsigned long tbu; - unsigned long tbl; - unsigned long lastinc; - unsigned long long timer_reset_value; -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - unsigned long tlb_addr; - unsigned long tlb_size; -#endif - -#ifdef CONFIG_OMAP - struct omap_boot_parameters omap_boot_params; -#endif -}; - -#include <asm-generic/global_data.h> - -#ifdef CONFIG_ARM64 -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") -#else -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") -#endif - -#endif /* __ASM_GBL_DATA_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/gpio.h deleted file mode 100644 index d49ad080e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/gpio.h +++ /dev/null @@ -1,2 +0,0 @@ -#include <asm/arch/gpio.h> -#include <asm-generic/gpio.h> diff --git a/qemu/roms/u-boot/arch/arm/include/asm/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/hardware.h deleted file mode 100644 index 1fd1a5b65..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/hardware.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * linux/include/asm-arm/hardware.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Common hardware definitions - */ - -#ifndef __ASM_HARDWARE_H -#define __ASM_HARDWARE_H - -#include <asm/arch/hardware.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/boot_mode.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/boot_mode.h deleted file mode 100644 index de0205c11..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/boot_mode.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2012 Boundary Devices Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_BOOT_MODE_H -#define _ASM_BOOT_MODE_H -#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ - ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1) - -struct boot_mode { - const char *name; - unsigned cfg_val; -}; - -void add_board_boot_modes(const struct boot_mode *p); -void boot_mode_apply(unsigned cfg_val); -extern const struct boot_mode soc_boot_modes[]; -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/dma.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/dma.h deleted file mode 100644 index d5c1f7f25..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/dma.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Freescale i.MX28 APBH DMA - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DMA_H__ -#define __DMA_H__ - -#include <linux/list.h> -#include <linux/compiler.h> - -#ifndef CONFIG_ARCH_DMA_PIO_WORDS -#define DMA_PIO_WORDS 15 -#else -#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS -#endif - -#define MXS_DMA_ALIGNMENT 32 - -/* - * MXS DMA channels - */ -#if defined(CONFIG_MX23) -enum { - MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0, - MXS_DMA_CHANNEL_AHB_APBH_SSP0, - MXS_DMA_CHANNEL_AHB_APBH_SSP1, - MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI1, - MXS_DMA_CHANNEL_AHB_APBH_GPMI2, - MXS_DMA_CHANNEL_AHB_APBH_GPMI3, - MXS_MAX_DMA_CHANNELS, -}; -#elif defined(CONFIG_MX28) -enum { - MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, - MXS_DMA_CHANNEL_AHB_APBH_SSP1, - MXS_DMA_CHANNEL_AHB_APBH_SSP2, - MXS_DMA_CHANNEL_AHB_APBH_SSP3, - MXS_DMA_CHANNEL_AHB_APBH_GPMI0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI1, - MXS_DMA_CHANNEL_AHB_APBH_GPMI2, - MXS_DMA_CHANNEL_AHB_APBH_GPMI3, - MXS_DMA_CHANNEL_AHB_APBH_GPMI4, - MXS_DMA_CHANNEL_AHB_APBH_GPMI5, - MXS_DMA_CHANNEL_AHB_APBH_GPMI6, - MXS_DMA_CHANNEL_AHB_APBH_GPMI7, - MXS_DMA_CHANNEL_AHB_APBH_HSADC, - MXS_DMA_CHANNEL_AHB_APBH_LCDIF, - MXS_DMA_CHANNEL_AHB_APBH_RESERVED0, - MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, - MXS_MAX_DMA_CHANNELS, -}; -#elif defined(CONFIG_MX6) -enum { - MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, - MXS_DMA_CHANNEL_AHB_APBH_GPMI1, - MXS_DMA_CHANNEL_AHB_APBH_GPMI2, - MXS_DMA_CHANNEL_AHB_APBH_GPMI3, - MXS_DMA_CHANNEL_AHB_APBH_GPMI4, - MXS_DMA_CHANNEL_AHB_APBH_GPMI5, - MXS_DMA_CHANNEL_AHB_APBH_GPMI6, - MXS_DMA_CHANNEL_AHB_APBH_GPMI7, - MXS_MAX_DMA_CHANNELS, -}; -#endif - -/* - * MXS DMA hardware command. - * - * This structure describes the in-memory layout of an entire DMA command, - * including space for the maximum number of PIO accesses. See the appropriate - * reference manual for a detailed description of what these fields mean to the - * DMA hardware. - */ -#define MXS_DMA_DESC_COMMAND_MASK 0x3 -#define MXS_DMA_DESC_COMMAND_OFFSET 0 -#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 -#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 -#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 -#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 -#define MXS_DMA_DESC_CHAIN (1 << 2) -#define MXS_DMA_DESC_IRQ (1 << 3) -#define MXS_DMA_DESC_NAND_LOCK (1 << 4) -#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) -#define MXS_DMA_DESC_DEC_SEM (1 << 6) -#define MXS_DMA_DESC_WAIT4END (1 << 7) -#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) -#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) -#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) -#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 -#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) -#define MXS_DMA_DESC_BYTES_OFFSET 16 - -struct mxs_dma_cmd { - unsigned long next; - unsigned long data; - union { - dma_addr_t address; - unsigned long alternate; - }; - unsigned long pio_words[DMA_PIO_WORDS]; -}; - -/* - * MXS DMA command descriptor. - * - * This structure incorporates an MXS DMA hardware command structure, along - * with metadata. - */ -#define MXS_DMA_DESC_FIRST (1 << 0) -#define MXS_DMA_DESC_LAST (1 << 1) -#define MXS_DMA_DESC_READY (1 << 31) - -struct mxs_dma_desc { - struct mxs_dma_cmd cmd; - unsigned int flags; - dma_addr_t address; - void *buffer; - struct list_head node; -} __aligned(MXS_DMA_ALIGNMENT); - -/** - * MXS DMA channel - * - * This structure represents a single DMA channel. The MXS platform code - * maintains an array of these structures to represent every DMA channel in the - * system (see mxs_dma_channels). - */ -#define MXS_DMA_FLAGS_IDLE 0 -#define MXS_DMA_FLAGS_BUSY (1 << 0) -#define MXS_DMA_FLAGS_FREE 0 -#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) -#define MXS_DMA_FLAGS_VALID (1 << 31) - -struct mxs_dma_chan { - const char *name; - unsigned long dev; - struct mxs_dma_device *dma; - unsigned int flags; - unsigned int active_num; - unsigned int pending_num; - struct list_head active; - struct list_head done; -}; - -struct mxs_dma_desc *mxs_dma_desc_alloc(void); -void mxs_dma_desc_free(struct mxs_dma_desc *); -int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); - -int mxs_dma_go(int chan); -void mxs_dma_init(void); -int mxs_dma_init_channel(int chan); -int mxs_dma_release(int chan); - -void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc); - -#endif /* __DMA_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/gpio.h deleted file mode 100644 index 26b296b21..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/gpio.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __ASM_ARCH_IMX_GPIO_H -#define __ASM_ARCH_IMX_GPIO_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; /* data */ - u32 gpio_dir; /* direction */ - u32 gpio_psr; /* pad satus */ -}; -#endif - -#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/imximage.cfg b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/imximage.cfg deleted file mode 100644 index d62166fd0..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/imximage.cfg +++ /dev/null @@ -1,24 +0,0 @@ -/* - * i.MX image header offset values - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * NOTE: This file must be kept in sync with tools/imximage.h because - * tools/imximage.c can not cross-include headers from arch/arm/ - * and vice-versa. - */ - -#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__ -#define __ASM_IMX_COMMON_IMXIMAGE_CFG__ - -/* Standard image header offset for NAND, SATA, SD, SPI flash. */ -#define FLASH_OFFSET_STANDARD 0x400 -/* Specific image header offset for booting from OneNAND. */ -#define FLASH_OFFSET_ONENAND 0x100 -/* Specific image header offset for booting from memory-mapped NOR. */ -#define FLASH_OFFSET_NOR 0x1000 - -#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/iomux-v3.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/iomux-v3.h deleted file mode 100644 index dec11a133..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/iomux-v3.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Based on Linux i.MX iomux-v3.h file: - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ - -#include <common.h> - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * - * IOMUX/PAD Bit field definitions - * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) - * SEL_INP: 59..62 (4) - * reserved: 63 (1) -*/ - -typedef u64 iomux_v3_cfg_t; - -#define MUX_CTRL_OFS_SHIFT 0 -#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) -#define MUX_PAD_CTRL_OFS_SHIFT 12 -#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ - MUX_PAD_CTRL_OFS_SHIFT) -#define MUX_SEL_INPUT_OFS_SHIFT 24 -#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ - MUX_SEL_INPUT_OFS_SHIFT) - -#define MUX_MODE_SHIFT 36 -#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) -#define MUX_PAD_CTRL_SHIFT 41 -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) -#define MUX_SEL_INPUT_SHIFT 59 -#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) - -#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ - MUX_MODE_SHIFT) -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ - sel_input, pad_ctrl) \ - (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ - ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ - ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ - ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) - -#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ - MUX_PAD_CTRL(pad)) - -#define __NA_ 0x000 -#define NO_MUX_I 0 -#define NO_PAD_I 0 - -#define NO_PAD_CTRL (1 << 17) - -#ifdef CONFIG_MX6 - -#define PAD_CTL_HYS (1 << 16) - -#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) -#define PAD_CTL_PKE (1 << 12) - -#define PAD_CTL_ODE (1 << 11) - -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) - -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) - -#elif defined(CONFIG_VF610) - -#define PAD_MUX_MODE_SHIFT 20 - -#define PAD_CTL_SPEED_MED (1 << 12) -#define PAD_CTL_SPEED_HIGH (3 << 12) - -#define PAD_CTL_DSE_50ohm (3 << 6) -#define PAD_CTL_DSE_25ohm (6 << 6) -#define PAD_CTL_DSE_20ohm (7 << 6) - -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PKE (1 << 3) -#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) - -#define PAD_CTL_OBE_IBE_ENABLE (3 << 0) - -#else - -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_INPUT_DDR (1 << 9) -#define PAD_CTL_HYS (1 << 8) - -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) -#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) - -#define PAD_CTL_ODE (1 << 3) - -#define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) -#define PAD_CTL_DSE_HIGH (2 << 1) -#define PAD_CTL_DSE_MAX (3 << 1) - -#endif - -#define PAD_CTL_SRE_SLOW (0 << 0) -#define PAD_CTL_SRE_FAST (1 << 0) - -#define IOMUX_CONFIG_SION 0x10 - -#define GPIO_PIN_MASK 0x1f -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); -void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, - unsigned count); - -#endif /* __MACH_IOMUX_V3_H__*/ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mx5_video.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mx5_video.h deleted file mode 100644 index ccaf010b7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mx5_video.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2012 - * Anatolij Gustschin, DENX Software Engineering, <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __MX5_VIDEO_H -#define __MX5_VIDEO_H - -#ifdef CONFIG_VIDEO -void lcd_enable(void); -void setup_iomux_lcd(void); -#else -static inline void lcd_enable(void) { } -static inline void setup_iomux_lcd(void) { } -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h deleted file mode 100644 index 47a9edc81..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_MXC_MXC_I2C_H__ -#define __ASM_ARCH_MXC_MXC_I2C_H__ -#include <asm/imx-common/iomux-v3.h> - -struct i2c_pin_ctrl { - iomux_v3_cfg_t i2c_mode; - iomux_v3_cfg_t gpio_mode; - unsigned char gp; - unsigned char spare; -}; - -struct i2c_pads_info { - struct i2c_pin_ctrl scl; - struct i2c_pin_ctrl sda; -}; - -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p); -void bus_i2c_init(void *base, int speed, int slave_addr, - int (*idle_bus_fn)(void *p), void *p); -int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, - int len); -int bus_i2c_write(void *base, uchar chip, uint addr, int alen, - const uchar *buf, int len); -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-apbh.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-apbh.h deleted file mode 100644 index ca7743600..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-apbh.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * Freescale i.MX28 APBH Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REGS_APBH_H__ -#define __REGS_APBH_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_MX23) -struct mxs_apbh_regs { - mxs_reg_32(hw_apbh_ctrl0) - mxs_reg_32(hw_apbh_ctrl1) - mxs_reg_32(hw_apbh_ctrl2) - mxs_reg_32(hw_apbh_channel_ctrl) - - union { - struct { - mxs_reg_32(hw_apbh_ch_curcmdar) - mxs_reg_32(hw_apbh_ch_nxtcmdar) - mxs_reg_32(hw_apbh_ch_cmd) - mxs_reg_32(hw_apbh_ch_bar) - mxs_reg_32(hw_apbh_ch_sema) - mxs_reg_32(hw_apbh_ch_debug1) - mxs_reg_32(hw_apbh_ch_debug2) - } ch[8]; - struct { - mxs_reg_32(hw_apbh_ch0_curcmdar) - mxs_reg_32(hw_apbh_ch0_nxtcmdar) - mxs_reg_32(hw_apbh_ch0_cmd) - mxs_reg_32(hw_apbh_ch0_bar) - mxs_reg_32(hw_apbh_ch0_sema) - mxs_reg_32(hw_apbh_ch0_debug1) - mxs_reg_32(hw_apbh_ch0_debug2) - mxs_reg_32(hw_apbh_ch1_curcmdar) - mxs_reg_32(hw_apbh_ch1_nxtcmdar) - mxs_reg_32(hw_apbh_ch1_cmd) - mxs_reg_32(hw_apbh_ch1_bar) - mxs_reg_32(hw_apbh_ch1_sema) - mxs_reg_32(hw_apbh_ch1_debug1) - mxs_reg_32(hw_apbh_ch1_debug2) - mxs_reg_32(hw_apbh_ch2_curcmdar) - mxs_reg_32(hw_apbh_ch2_nxtcmdar) - mxs_reg_32(hw_apbh_ch2_cmd) - mxs_reg_32(hw_apbh_ch2_bar) - mxs_reg_32(hw_apbh_ch2_sema) - mxs_reg_32(hw_apbh_ch2_debug1) - mxs_reg_32(hw_apbh_ch2_debug2) - mxs_reg_32(hw_apbh_ch3_curcmdar) - mxs_reg_32(hw_apbh_ch3_nxtcmdar) - mxs_reg_32(hw_apbh_ch3_cmd) - mxs_reg_32(hw_apbh_ch3_bar) - mxs_reg_32(hw_apbh_ch3_sema) - mxs_reg_32(hw_apbh_ch3_debug1) - mxs_reg_32(hw_apbh_ch3_debug2) - mxs_reg_32(hw_apbh_ch4_curcmdar) - mxs_reg_32(hw_apbh_ch4_nxtcmdar) - mxs_reg_32(hw_apbh_ch4_cmd) - mxs_reg_32(hw_apbh_ch4_bar) - mxs_reg_32(hw_apbh_ch4_sema) - mxs_reg_32(hw_apbh_ch4_debug1) - mxs_reg_32(hw_apbh_ch4_debug2) - mxs_reg_32(hw_apbh_ch5_curcmdar) - mxs_reg_32(hw_apbh_ch5_nxtcmdar) - mxs_reg_32(hw_apbh_ch5_cmd) - mxs_reg_32(hw_apbh_ch5_bar) - mxs_reg_32(hw_apbh_ch5_sema) - mxs_reg_32(hw_apbh_ch5_debug1) - mxs_reg_32(hw_apbh_ch5_debug2) - mxs_reg_32(hw_apbh_ch6_curcmdar) - mxs_reg_32(hw_apbh_ch6_nxtcmdar) - mxs_reg_32(hw_apbh_ch6_cmd) - mxs_reg_32(hw_apbh_ch6_bar) - mxs_reg_32(hw_apbh_ch6_sema) - mxs_reg_32(hw_apbh_ch6_debug1) - mxs_reg_32(hw_apbh_ch6_debug2) - mxs_reg_32(hw_apbh_ch7_curcmdar) - mxs_reg_32(hw_apbh_ch7_nxtcmdar) - mxs_reg_32(hw_apbh_ch7_cmd) - mxs_reg_32(hw_apbh_ch7_bar) - mxs_reg_32(hw_apbh_ch7_sema) - mxs_reg_32(hw_apbh_ch7_debug1) - mxs_reg_32(hw_apbh_ch7_debug2) - }; - }; - mxs_reg_32(hw_apbh_version) -}; - -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) -struct mxs_apbh_regs { - mxs_reg_32(hw_apbh_ctrl0) - mxs_reg_32(hw_apbh_ctrl1) - mxs_reg_32(hw_apbh_ctrl2) - mxs_reg_32(hw_apbh_channel_ctrl) - mxs_reg_32(hw_apbh_devsel) - mxs_reg_32(hw_apbh_dma_burst_size) - mxs_reg_32(hw_apbh_debug) - - uint32_t reserved[36]; - - union { - struct { - mxs_reg_32(hw_apbh_ch_curcmdar) - mxs_reg_32(hw_apbh_ch_nxtcmdar) - mxs_reg_32(hw_apbh_ch_cmd) - mxs_reg_32(hw_apbh_ch_bar) - mxs_reg_32(hw_apbh_ch_sema) - mxs_reg_32(hw_apbh_ch_debug1) - mxs_reg_32(hw_apbh_ch_debug2) - } ch[16]; - struct { - mxs_reg_32(hw_apbh_ch0_curcmdar) - mxs_reg_32(hw_apbh_ch0_nxtcmdar) - mxs_reg_32(hw_apbh_ch0_cmd) - mxs_reg_32(hw_apbh_ch0_bar) - mxs_reg_32(hw_apbh_ch0_sema) - mxs_reg_32(hw_apbh_ch0_debug1) - mxs_reg_32(hw_apbh_ch0_debug2) - mxs_reg_32(hw_apbh_ch1_curcmdar) - mxs_reg_32(hw_apbh_ch1_nxtcmdar) - mxs_reg_32(hw_apbh_ch1_cmd) - mxs_reg_32(hw_apbh_ch1_bar) - mxs_reg_32(hw_apbh_ch1_sema) - mxs_reg_32(hw_apbh_ch1_debug1) - mxs_reg_32(hw_apbh_ch1_debug2) - mxs_reg_32(hw_apbh_ch2_curcmdar) - mxs_reg_32(hw_apbh_ch2_nxtcmdar) - mxs_reg_32(hw_apbh_ch2_cmd) - mxs_reg_32(hw_apbh_ch2_bar) - mxs_reg_32(hw_apbh_ch2_sema) - mxs_reg_32(hw_apbh_ch2_debug1) - mxs_reg_32(hw_apbh_ch2_debug2) - mxs_reg_32(hw_apbh_ch3_curcmdar) - mxs_reg_32(hw_apbh_ch3_nxtcmdar) - mxs_reg_32(hw_apbh_ch3_cmd) - mxs_reg_32(hw_apbh_ch3_bar) - mxs_reg_32(hw_apbh_ch3_sema) - mxs_reg_32(hw_apbh_ch3_debug1) - mxs_reg_32(hw_apbh_ch3_debug2) - mxs_reg_32(hw_apbh_ch4_curcmdar) - mxs_reg_32(hw_apbh_ch4_nxtcmdar) - mxs_reg_32(hw_apbh_ch4_cmd) - mxs_reg_32(hw_apbh_ch4_bar) - mxs_reg_32(hw_apbh_ch4_sema) - mxs_reg_32(hw_apbh_ch4_debug1) - mxs_reg_32(hw_apbh_ch4_debug2) - mxs_reg_32(hw_apbh_ch5_curcmdar) - mxs_reg_32(hw_apbh_ch5_nxtcmdar) - mxs_reg_32(hw_apbh_ch5_cmd) - mxs_reg_32(hw_apbh_ch5_bar) - mxs_reg_32(hw_apbh_ch5_sema) - mxs_reg_32(hw_apbh_ch5_debug1) - mxs_reg_32(hw_apbh_ch5_debug2) - mxs_reg_32(hw_apbh_ch6_curcmdar) - mxs_reg_32(hw_apbh_ch6_nxtcmdar) - mxs_reg_32(hw_apbh_ch6_cmd) - mxs_reg_32(hw_apbh_ch6_bar) - mxs_reg_32(hw_apbh_ch6_sema) - mxs_reg_32(hw_apbh_ch6_debug1) - mxs_reg_32(hw_apbh_ch6_debug2) - mxs_reg_32(hw_apbh_ch7_curcmdar) - mxs_reg_32(hw_apbh_ch7_nxtcmdar) - mxs_reg_32(hw_apbh_ch7_cmd) - mxs_reg_32(hw_apbh_ch7_bar) - mxs_reg_32(hw_apbh_ch7_sema) - mxs_reg_32(hw_apbh_ch7_debug1) - mxs_reg_32(hw_apbh_ch7_debug2) - mxs_reg_32(hw_apbh_ch8_curcmdar) - mxs_reg_32(hw_apbh_ch8_nxtcmdar) - mxs_reg_32(hw_apbh_ch8_cmd) - mxs_reg_32(hw_apbh_ch8_bar) - mxs_reg_32(hw_apbh_ch8_sema) - mxs_reg_32(hw_apbh_ch8_debug1) - mxs_reg_32(hw_apbh_ch8_debug2) - mxs_reg_32(hw_apbh_ch9_curcmdar) - mxs_reg_32(hw_apbh_ch9_nxtcmdar) - mxs_reg_32(hw_apbh_ch9_cmd) - mxs_reg_32(hw_apbh_ch9_bar) - mxs_reg_32(hw_apbh_ch9_sema) - mxs_reg_32(hw_apbh_ch9_debug1) - mxs_reg_32(hw_apbh_ch9_debug2) - mxs_reg_32(hw_apbh_ch10_curcmdar) - mxs_reg_32(hw_apbh_ch10_nxtcmdar) - mxs_reg_32(hw_apbh_ch10_cmd) - mxs_reg_32(hw_apbh_ch10_bar) - mxs_reg_32(hw_apbh_ch10_sema) - mxs_reg_32(hw_apbh_ch10_debug1) - mxs_reg_32(hw_apbh_ch10_debug2) - mxs_reg_32(hw_apbh_ch11_curcmdar) - mxs_reg_32(hw_apbh_ch11_nxtcmdar) - mxs_reg_32(hw_apbh_ch11_cmd) - mxs_reg_32(hw_apbh_ch11_bar) - mxs_reg_32(hw_apbh_ch11_sema) - mxs_reg_32(hw_apbh_ch11_debug1) - mxs_reg_32(hw_apbh_ch11_debug2) - mxs_reg_32(hw_apbh_ch12_curcmdar) - mxs_reg_32(hw_apbh_ch12_nxtcmdar) - mxs_reg_32(hw_apbh_ch12_cmd) - mxs_reg_32(hw_apbh_ch12_bar) - mxs_reg_32(hw_apbh_ch12_sema) - mxs_reg_32(hw_apbh_ch12_debug1) - mxs_reg_32(hw_apbh_ch12_debug2) - mxs_reg_32(hw_apbh_ch13_curcmdar) - mxs_reg_32(hw_apbh_ch13_nxtcmdar) - mxs_reg_32(hw_apbh_ch13_cmd) - mxs_reg_32(hw_apbh_ch13_bar) - mxs_reg_32(hw_apbh_ch13_sema) - mxs_reg_32(hw_apbh_ch13_debug1) - mxs_reg_32(hw_apbh_ch13_debug2) - mxs_reg_32(hw_apbh_ch14_curcmdar) - mxs_reg_32(hw_apbh_ch14_nxtcmdar) - mxs_reg_32(hw_apbh_ch14_cmd) - mxs_reg_32(hw_apbh_ch14_bar) - mxs_reg_32(hw_apbh_ch14_sema) - mxs_reg_32(hw_apbh_ch14_debug1) - mxs_reg_32(hw_apbh_ch14_debug2) - mxs_reg_32(hw_apbh_ch15_curcmdar) - mxs_reg_32(hw_apbh_ch15_nxtcmdar) - mxs_reg_32(hw_apbh_ch15_cmd) - mxs_reg_32(hw_apbh_ch15_bar) - mxs_reg_32(hw_apbh_ch15_sema) - mxs_reg_32(hw_apbh_ch15_debug1) - mxs_reg_32(hw_apbh_ch15_debug2) - }; - }; - mxs_reg_32(hw_apbh_version) -}; -#endif - -#endif - -#define APBH_CTRL0_SFTRST (1 << 31) -#define APBH_CTRL0_CLKGATE (1 << 30) -#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) -#define APBH_CTRL0_APB_BURST_EN (1 << 28) -#if defined(CONFIG_MX23) -#define APBH_CTRL0_RSVD0_MASK (0xf << 24) -#define APBH_CTRL0_RSVD0_OFFSET 24 -#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) -#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16 -#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8) -#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 -#elif defined(CONFIG_MX28) -#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) -#define APBH_CTRL0_RSVD0_OFFSET 16 -#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff -#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 -#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 -#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 -#elif defined(CONFIG_MX6) -#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040 -#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080 -#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100 -#endif - -#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) -#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) -#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) -#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) -#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) -#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) -#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) -#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) -#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) -#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) -#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) -#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) -#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) -#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) -#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) -#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) -#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 -#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) -#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) -#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) -#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) -#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) -#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) -#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) -#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) -#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) -#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) -#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) -#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) -#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) -#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) -#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) -#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) -#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) - -#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) -#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) -#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) -#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) -#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) -#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) -#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) -#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) -#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) -#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) -#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) -#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) -#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) -#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) -#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) -#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) -#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) -#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) -#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) -#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) -#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) -#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) -#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) -#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) -#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) -#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) -#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) -#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) -#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) -#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) -#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) -#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) - -#if defined(CONFIG_MX28) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 -#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 -#endif - -#if defined(CONFIG_MX6) -#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 -#endif - -#if defined(CONFIG_MX23) -#define APBH_DEVSEL_CH7_MASK (0xf << 28) -#define APBH_DEVSEL_CH7_OFFSET 28 -#define APBH_DEVSEL_CH6_MASK (0xf << 24) -#define APBH_DEVSEL_CH6_OFFSET 24 -#define APBH_DEVSEL_CH5_MASK (0xf << 20) -#define APBH_DEVSEL_CH5_OFFSET 20 -#define APBH_DEVSEL_CH4_MASK (0xf << 16) -#define APBH_DEVSEL_CH4_OFFSET 16 -#define APBH_DEVSEL_CH3_MASK (0xf << 12) -#define APBH_DEVSEL_CH3_OFFSET 12 -#define APBH_DEVSEL_CH2_MASK (0xf << 8) -#define APBH_DEVSEL_CH2_OFFSET 8 -#define APBH_DEVSEL_CH1_MASK (0xf << 4) -#define APBH_DEVSEL_CH1_OFFSET 4 -#define APBH_DEVSEL_CH0_MASK (0xf << 0) -#define APBH_DEVSEL_CH0_OFFSET 0 -#elif defined(CONFIG_MX28) -#define APBH_DEVSEL_CH15_MASK (0x3 << 30) -#define APBH_DEVSEL_CH15_OFFSET 30 -#define APBH_DEVSEL_CH14_MASK (0x3 << 28) -#define APBH_DEVSEL_CH14_OFFSET 28 -#define APBH_DEVSEL_CH13_MASK (0x3 << 26) -#define APBH_DEVSEL_CH13_OFFSET 26 -#define APBH_DEVSEL_CH12_MASK (0x3 << 24) -#define APBH_DEVSEL_CH12_OFFSET 24 -#define APBH_DEVSEL_CH11_MASK (0x3 << 22) -#define APBH_DEVSEL_CH11_OFFSET 22 -#define APBH_DEVSEL_CH10_MASK (0x3 << 20) -#define APBH_DEVSEL_CH10_OFFSET 20 -#define APBH_DEVSEL_CH9_MASK (0x3 << 18) -#define APBH_DEVSEL_CH9_OFFSET 18 -#define APBH_DEVSEL_CH8_MASK (0x3 << 16) -#define APBH_DEVSEL_CH8_OFFSET 16 -#define APBH_DEVSEL_CH7_MASK (0x3 << 14) -#define APBH_DEVSEL_CH7_OFFSET 14 -#define APBH_DEVSEL_CH6_MASK (0x3 << 12) -#define APBH_DEVSEL_CH6_OFFSET 12 -#define APBH_DEVSEL_CH5_MASK (0x3 << 10) -#define APBH_DEVSEL_CH5_OFFSET 10 -#define APBH_DEVSEL_CH4_MASK (0x3 << 8) -#define APBH_DEVSEL_CH4_OFFSET 8 -#define APBH_DEVSEL_CH3_MASK (0x3 << 6) -#define APBH_DEVSEL_CH3_OFFSET 6 -#define APBH_DEVSEL_CH2_MASK (0x3 << 4) -#define APBH_DEVSEL_CH2_OFFSET 4 -#define APBH_DEVSEL_CH1_MASK (0x3 << 2) -#define APBH_DEVSEL_CH1_OFFSET 2 -#define APBH_DEVSEL_CH0_MASK (0x3 << 0) -#define APBH_DEVSEL_CH0_OFFSET 0 -#endif - -#if defined(CONFIG_MX28) -#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) -#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 -#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) -#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 -#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) -#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 -#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) -#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 -#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) -#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 -#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) -#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 -#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) -#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 -#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) -#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 -#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) -#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) -#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) -#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) -#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 -#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) -#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 -#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) -#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 -#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) -#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 -#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) -#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 -#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) -#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) -#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) - -#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) -#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 -#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) -#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) -#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) -#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) -#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 -#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) -#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) -#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) - -#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 -#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 -#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 -#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 -#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 - -#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) -#endif - -#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff -#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 - -#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff -#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 - -#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) -#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 -#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) -#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 -#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) -#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) -#define APBH_CHn_CMD_SEMAPHORE (1 << 6) -#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) -#define APBH_CHn_CMD_NANDLOCK (1 << 4) -#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) -#define APBH_CHn_CMD_CHAIN (1 << 2) -#define APBH_CHn_CMD_COMMAND_MASK 0x3 -#define APBH_CHn_CMD_COMMAND_OFFSET 0 -#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 -#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 -#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 -#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 - -#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff -#define APBH_CHn_BAR_ADDRESS_OFFSET 0 - -#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) -#define APBH_CHn_SEMA_RSVD2_OFFSET 24 -#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) -#define APBH_CHn_SEMA_PHORE_OFFSET 16 -#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) -#define APBH_CHn_SEMA_RSVD1_OFFSET 8 -#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) -#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 - -#define APBH_CHn_DEBUG1_REQ (1 << 31) -#define APBH_CHn_DEBUG1_BURST (1 << 30) -#define APBH_CHn_DEBUG1_KICK (1 << 29) -#define APBH_CHn_DEBUG1_END (1 << 28) -#define APBH_CHn_DEBUG1_SENSE (1 << 27) -#define APBH_CHn_DEBUG1_READY (1 << 26) -#define APBH_CHn_DEBUG1_LOCK (1 << 25) -#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) -#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) -#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) -#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) -#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) -#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) -#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 -#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f -#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 -#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 -#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 -#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 -#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 -#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 -#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 -#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c -#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d -#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e -#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f -#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 -#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 -#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c -#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d -#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e -#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f - -#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) -#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 -#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff -#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 - -#define APBH_VERSION_MAJOR_MASK (0xff << 24) -#define APBH_VERSION_MAJOR_OFFSET 24 -#define APBH_VERSION_MINOR_MASK (0xff << 16) -#define APBH_VERSION_MINOR_OFFSET 16 -#define APBH_VERSION_STEP_MASK 0xffff -#define APBH_VERSION_STEP_OFFSET 0 - -#endif /* __REGS_APBH_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-bch.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-bch.h deleted file mode 100644 index a33d3419b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-bch.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Freescale i.MX28 BCH Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_BCH_H__ -#define __MX28_REGS_BCH_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_bch_regs { - mxs_reg_32(hw_bch_ctrl) - mxs_reg_32(hw_bch_status0) - mxs_reg_32(hw_bch_mode) - mxs_reg_32(hw_bch_encodeptr) - mxs_reg_32(hw_bch_dataptr) - mxs_reg_32(hw_bch_metaptr) - - uint32_t reserved[4]; - - mxs_reg_32(hw_bch_layoutselect) - mxs_reg_32(hw_bch_flash0layout0) - mxs_reg_32(hw_bch_flash0layout1) - mxs_reg_32(hw_bch_flash1layout0) - mxs_reg_32(hw_bch_flash1layout1) - mxs_reg_32(hw_bch_flash2layout0) - mxs_reg_32(hw_bch_flash2layout1) - mxs_reg_32(hw_bch_flash3layout0) - mxs_reg_32(hw_bch_flash3layout1) - mxs_reg_32(hw_bch_dbgkesread) - mxs_reg_32(hw_bch_dbgcsferead) - mxs_reg_32(hw_bch_dbgsyndegread) - mxs_reg_32(hw_bch_dbgahbmread) - mxs_reg_32(hw_bch_blockname) - mxs_reg_32(hw_bch_version) -}; -#endif - -#define BCH_CTRL_SFTRST (1 << 31) -#define BCH_CTRL_CLKGATE (1 << 30) -#define BCH_CTRL_DEBUGSYNDROME (1 << 22) -#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) -#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 -#define BCH_CTRL_M2M_ENCODE (1 << 17) -#define BCH_CTRL_M2M_ENABLE (1 << 16) -#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) -#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) -#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) -#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) -#define BCH_CTRL_COMPLETE_IRQ (1 << 0) - -#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) -#define BCH_STATUS0_HANDLE_OFFSET 20 -#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) -#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 -#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) -#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 -#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) -#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) -#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) -#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) -#define BCH_STATUS0_ALLONES (1 << 4) -#define BCH_STATUS0_CORRECTED (1 << 3) -#define BCH_STATUS0_UNCORRECTABLE (1 << 2) - -#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff -#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 - -#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff -#define BCH_ENCODEPTR_ADDR_OFFSET 0 - -#define BCH_DATAPTR_ADDR_MASK 0xffffffff -#define BCH_DATAPTR_ADDR_OFFSET 0 - -#define BCH_METAPTR_ADDR_MASK 0xffffffff -#define BCH_METAPTR_ADDR_OFFSET 0 - -#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) -#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 -#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) -#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 -#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) -#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 -#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) -#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 -#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) -#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 -#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) -#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 -#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) -#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 -#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) -#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 -#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) -#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 -#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) -#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 -#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) -#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 -#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) -#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 -#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) -#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 -#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) -#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 -#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) -#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 -#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) -#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 - -#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) -#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 -#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) -#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 -#if defined(CONFIG_MX6) -#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) -#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 -#else -#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) -#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 -#endif -#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) -#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) -#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff -#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 - -#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) -#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 -#if defined(CONFIG_MX6) -#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) -#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 -#else -#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) -#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 -#endif -#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) -#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) -#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff -#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 - -#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) -#define BCH_DEBUG0_RSVD1_OFFSET 27 -#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) -#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) -#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) -#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) -#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) -#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) -#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) -#define BCH_DEBUG0_KES_STANDALONE (1 << 11) -#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) -#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) -#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) -#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) -#define BCH_DEBUG0_RSVD0_OFFSET 6 -#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f -#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 - -#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff -#define BCH_DBGKESREAD_VALUES_OFFSET 0 - -#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff -#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 - -#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff -#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 - -#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff -#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 - -#define BCH_BLOCKNAME_NAME_MASK 0xffffffff -#define BCH_BLOCKNAME_NAME_OFFSET 0 - -#define BCH_VERSION_MAJOR_MASK (0xff << 24) -#define BCH_VERSION_MAJOR_OFFSET 24 -#define BCH_VERSION_MINOR_MASK (0xff << 16) -#define BCH_VERSION_MINOR_OFFSET 16 -#define BCH_VERSION_STEP_MASK 0xffff -#define BCH_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_BCH_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-common.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-common.h deleted file mode 100644 index e54a220fa..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-common.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Freescale i.MXS Register Accessors - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MXS_REGS_COMMON_H__ -#define __MXS_REGS_COMMON_H__ - -/* - * The i.MXS has interesting feature when it comes to register access. There - * are four kinds of access to one particular register. Those are: - * - * 1) Common read/write access. To use this mode, just write to the address of - * the register. - * 2) Set bits only access. To set bits, write which bits you want to set to the - * address of the register + 0x4. - * 3) Clear bits only access. To clear bits, write which bits you want to clear - * to the address of the register + 0x8. - * 4) Toggle bits only access. To toggle bits, write which bits you want to - * toggle to the address of the register + 0xc. - * - * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits - * can be set/cleared by pure write as in access type 1, some need to be - * explicitly set/cleared by using access type 2-3. - * - * The following macros and structures allow the user to either access the - * register in all aforementioned modes (by accessing reg_name, reg_name_set, - * reg_name_clr, reg_name_tog) or pass the register structure further into - * various functions with correct type information (by accessing reg_name_reg). - * - */ - -#define __mxs_reg_8(name) \ - uint8_t name[4]; \ - uint8_t name##_set[4]; \ - uint8_t name##_clr[4]; \ - uint8_t name##_tog[4]; \ - -#define __mxs_reg_32(name) \ - uint32_t name; \ - uint32_t name##_set; \ - uint32_t name##_clr; \ - uint32_t name##_tog; - -struct mxs_register_8 { - __mxs_reg_8(reg) -}; - -struct mxs_register_32 { - __mxs_reg_32(reg) -}; - -#define mxs_reg_8(name) \ - union { \ - struct { __mxs_reg_8(name) }; \ - struct mxs_register_8 name##_reg; \ - }; - -#define mxs_reg_32(name) \ - union { \ - struct { __mxs_reg_32(name) }; \ - struct mxs_register_32 name##_reg; \ - }; - -#endif /* __MXS_REGS_COMMON_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-gpmi.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-gpmi.h deleted file mode 100644 index b93bfe55c..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-gpmi.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Freescale i.MX28 GPMI Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MX28_REGS_GPMI_H__ -#define __MX28_REGS_GPMI_H__ - -#include <asm/imx-common/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_gpmi_regs { - mxs_reg_32(hw_gpmi_ctrl0) - mxs_reg_32(hw_gpmi_compare) - mxs_reg_32(hw_gpmi_eccctrl) - mxs_reg_32(hw_gpmi_ecccount) - mxs_reg_32(hw_gpmi_payload) - mxs_reg_32(hw_gpmi_auxiliary) - mxs_reg_32(hw_gpmi_ctrl1) - mxs_reg_32(hw_gpmi_timing0) - mxs_reg_32(hw_gpmi_timing1) - - uint32_t reserved[4]; - - mxs_reg_32(hw_gpmi_data) - mxs_reg_32(hw_gpmi_stat) - mxs_reg_32(hw_gpmi_debug) - mxs_reg_32(hw_gpmi_version) -}; -#endif - -#define GPMI_CTRL0_SFTRST (1 << 31) -#define GPMI_CTRL0_CLKGATE (1 << 30) -#define GPMI_CTRL0_RUN (1 << 29) -#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) -#define GPMI_CTRL0_LOCK_CS (1 << 27) -#define GPMI_CTRL0_UDMA (1 << 26) -#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) -#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 -#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) -#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) -#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) -#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) -#define GPMI_CTRL0_WORD_LENGTH (1 << 23) -#define GPMI_CTRL0_CS_MASK (0x7 << 20) -#define GPMI_CTRL0_CS_OFFSET 20 -#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) -#define GPMI_CTRL0_ADDRESS_OFFSET 17 -#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) -#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) -#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) -#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) -#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff -#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 - -#define GPMI_COMPARE_MASK_MASK (0xffff << 16) -#define GPMI_COMPARE_MASK_OFFSET 16 -#define GPMI_COMPARE_REFERENCE_MASK 0xffff -#define GPMI_COMPARE_REFERENCE_OFFSET 0 - -#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) -#define GPMI_ECCCTRL_HANDLE_OFFSET 16 -#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) -#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 -#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) -#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) -#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) -#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff -#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 -#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 -#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff - -#define GPMI_ECCCOUNT_COUNT_MASK 0xffff -#define GPMI_ECCCOUNT_COUNT_OFFSET 0 - -#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) -#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 - -#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) -#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 - -#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) -#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) -#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 -#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) -#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) -#define GPMI_CTRL1_BCH_MODE (1 << 18) -#define GPMI_CTRL1_DLL_ENABLE (1 << 17) -#define GPMI_CTRL1_HALF_PERIOD (1 << 16) -#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) -#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 -#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) -#define GPMI_CTRL1_DEV_IRQ (1 << 10) -#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) -#define GPMI_CTRL1_BURST_EN (1 << 8) -#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) -#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) -#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 -#define GPMI_CTRL1_DEV_RESET (1 << 3) -#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) -#define GPMI_CTRL1_CAMERA_MODE (1 << 1) -#define GPMI_CTRL1_GPMI_MODE (1 << 0) - -#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) -#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 -#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) -#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 -#define GPMI_TIMING0_DATA_SETUP_MASK 0xff -#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 - -#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) -#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 - -#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) -#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 -#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) -#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 -#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) -#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 -#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff -#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 - -#define GPMI_DATA_DATA_MASK 0xffffffff -#define GPMI_DATA_DATA_OFFSET 0 - -#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) -#define GPMI_STAT_READY_BUSY_OFFSET 24 -#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) -#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 -#define GPMI_STAT_DEV7_ERROR (1 << 15) -#define GPMI_STAT_DEV6_ERROR (1 << 14) -#define GPMI_STAT_DEV5_ERROR (1 << 13) -#define GPMI_STAT_DEV4_ERROR (1 << 12) -#define GPMI_STAT_DEV3_ERROR (1 << 11) -#define GPMI_STAT_DEV2_ERROR (1 << 10) -#define GPMI_STAT_DEV1_ERROR (1 << 9) -#define GPMI_STAT_DEV0_ERROR (1 << 8) -#define GPMI_STAT_ATA_IRQ (1 << 4) -#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) -#define GPMI_STAT_FIFO_EMPTY (1 << 2) -#define GPMI_STAT_FIFO_FULL (1 << 1) -#define GPMI_STAT_PRESENT (1 << 0) - -#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) -#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 -#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) -#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 -#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) -#define GPMI_DEBUG_DMAREQ_OFFSET 8 -#define GPMI_DEBUG_CMD_END_MASK 0xff -#define GPMI_DEBUG_CMD_END_OFFSET 0 - -#define GPMI_VERSION_MAJOR_MASK (0xff << 24) -#define GPMI_VERSION_MAJOR_OFFSET 24 -#define GPMI_VERSION_MINOR_MASK (0xff << 16) -#define GPMI_VERSION_MINOR_OFFSET 16 -#define GPMI_VERSION_STEP_MASK 0xffff -#define GPMI_VERSION_STEP_OFFSET 0 - -#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) -#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 -#define GPMI_DEBUG2_BUSY (1 << 23) -#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) -#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 -#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) -#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) -#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) -#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 -#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) -#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) -#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) -#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 -#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) -#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) -#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) -#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) -#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) -#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) -#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f -#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 - -#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) -#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 -#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff -#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 - -#endif /* __MX28_REGS_GPMI_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/sata.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/sata.h deleted file mode 100644 index 6b864cbd1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/sata.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __IMX_SATA_H_ -#define __IMX_SATA_H_ - -/* - * SATA setup for i.mx6 quad based platform - */ - -int setup_sata(void); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/io.h b/qemu/roms/u-boot/arch/arm/include/asm/io.h deleted file mode 100644 index 6a1f05ac3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/io.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <asm/byteorder.h> -#include <asm/memory.h> -#if 0 /* XXX###XXX */ -#include <asm/arch/hardware.h> -#endif /* XXX###XXX */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern inline void __raw_writesb(unsigned long addr, const void *data, - int bytelen) -{ - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - __arch_putb(*buf++, addr); -} - -extern inline void __raw_writesw(unsigned long addr, const void *data, - int wordlen) -{ - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - __arch_putw(*buf++, addr); -} - -extern inline void __raw_writesl(unsigned long addr, const void *data, - int longlen) -{ - uint32_t *buf = (uint32_t *)data; - while(longlen--) - __arch_putl(*buf++, addr); -} - -extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen) -{ - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - *buf++ = __arch_getb(addr); -} - -extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen) -{ - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - *buf++ = __arch_getw(addr); -} - -extern inline void __raw_readsl(unsigned long addr, void *data, int longlen) -{ - uint32_t *buf = (uint32_t *)data; - while(longlen--) - *buf++ = __arch_getl(addr); -} - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define dmb() __asm__ __volatile__ ("" : : : "memory") -#define __iormb() dmb() -#define __iowmb() dmb() - -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) - -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) - -#define out_le32(a,v) out_arch(l,le32,a,v) -#define out_le16(a,v) out_arch(w,le16,a,v) - -#define in_le32(a) in_arch(l,le32,a) -#define in_le16(a) in_arch(w,le16,a) - -#define out_be32(a,v) out_arch(l,be32,a,v) -#define out_be16(a,v) out_arch(w,be16,a,v) - -#define in_be32(a) in_arch(l,be32,a) -#define in_be16(a) in_arch(w,be16,a) - -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) - -#define clrbits(type, addr, clear) \ - out_##type((addr), in_##type(addr) & ~(clear)) - -#define setbits(type, addr, set) \ - out_##type((addr), in_##type(addr) | (set)) - -#define clrsetbits(type, addr, clear, set) \ - out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) - -#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) -#define setbits_be32(addr, set) setbits(be32, addr, set) -#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) - -#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) -#define setbits_le32(addr, set) setbits(le32, addr, set) -#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) - -#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) -#define setbits_be16(addr, set) setbits(be16, addr, set) -#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) - -#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) -#define setbits_le16(addr, set) setbits(le16, addr, set) -#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) - -#define clrbits_8(addr, clear) clrbits(8, addr, clear) -#define setbits_8(addr, set) setbits(8, addr, set) -#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The ARM doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerous - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,nocache); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_IO_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/kona-common/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/kona-common/clk.h deleted file mode 100644 index 2c7e82999..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/kona-common/clk.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright 2013 Broadcom Corporation. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */ - -#ifndef __KONA_COMMON_CLK_H -#define __KONA_COMMON_CLK_H - -#include <linux/types.h> - -struct clk; - -/* Only implement required functions for your specific architecture */ -int clk_init(void); -struct clk *clk_get(const char *id); -int clk_enable(struct clk *clk); -void clk_disable(struct clk *clk); -unsigned long clk_get_rate(struct clk *clk); -long clk_round_rate(struct clk *clk, unsigned long rate); -int clk_set_rate(struct clk *clk, unsigned long rate); -int clk_set_parent(struct clk *clk, struct clk *parent); -struct clk *clk_get_parent(struct clk *clk); -int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep); -int clk_bsc_enable(void *base); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h b/qemu/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h deleted file mode 100644 index 1ff0e55d1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2013 Broadcom Corporation. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KONA_SDHCI_H -#define __KONA_SDHCI_H - -int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/linkage.h b/qemu/roms/u-boot/arch/arm/include/asm/linkage.h deleted file mode 100644 index dbe4b4e31..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/linkage.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -#define __ALIGN .align 0 -#define __ALIGN_STR ".align 0" - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/mach-types.h b/qemu/roms/u-boot/arch/arm/include/asm/mach-types.h deleted file mode 100644 index 440b041a1..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/mach-types.h +++ /dev/null @@ -1,14246 +0,0 @@ -/* - * This was automagically generated from arch/arm/tools/mach-types! - * Do NOT edit - */ - -#ifndef __ASM_ARM_MACH_TYPE_H -#define __ASM_ARM_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/arm/kernel/arch.c for a description of these */ -#define MACH_TYPE_EBSA110 0 -#define MACH_TYPE_RISCPC 1 -#define MACH_TYPE_EBSA285 4 -#define MACH_TYPE_NETWINDER 5 -#define MACH_TYPE_CATS 6 -#define MACH_TYPE_SHARK 15 -#define MACH_TYPE_BRUTUS 16 -#define MACH_TYPE_PERSONAL_SERVER 17 -#define MACH_TYPE_L7200 19 -#define MACH_TYPE_PLEB 20 -#define MACH_TYPE_INTEGRATOR 21 -#define MACH_TYPE_H3600 22 -#define MACH_TYPE_P720T 24 -#define MACH_TYPE_ASSABET 25 -#define MACH_TYPE_LART 27 -#define MACH_TYPE_GRAPHICSCLIENT 29 -#define MACH_TYPE_XP860 30 -#define MACH_TYPE_CERF 31 -#define MACH_TYPE_NANOENGINE 32 -#define MACH_TYPE_JORNADA720 48 -#define MACH_TYPE_EDB7211 50 -#define MACH_TYPE_PFS168 52 -#define MACH_TYPE_FLEXANET 54 -#define MACH_TYPE_SIMPAD 87 -#define MACH_TYPE_LUBBOCK 89 -#define MACH_TYPE_CLEP7212 91 -#define MACH_TYPE_SHANNON 97 -#define MACH_TYPE_CONSUS 105 -#define MACH_TYPE_AAED2000 106 -#define MACH_TYPE_CDB89712 107 -#define MACH_TYPE_GRAPHICSMASTER 108 -#define MACH_TYPE_ADSBITSY 109 -#define MACH_TYPE_PXA_IDP 110 -#define MACH_TYPE_PT_SYSTEM3 112 -#define MACH_TYPE_AUTCPU12 118 -#define MACH_TYPE_H3100 136 -#define MACH_TYPE_COLLIE 146 -#define MACH_TYPE_BADGE4 148 -#define MACH_TYPE_FORTUNET 152 -#define MACH_TYPE_MX1ADS 160 -#define MACH_TYPE_H7201 161 -#define MACH_TYPE_H7202 162 -#define MACH_TYPE_IQ80321 169 -#define MACH_TYPE_KS8695 180 -#define MACH_TYPE_SMDK2410 193 -#define MACH_TYPE_CEIVA 200 -#define MACH_TYPE_VOICEBLUE 218 -#define MACH_TYPE_H5400 220 -#define MACH_TYPE_OMAP_INNOVATOR 234 -#define MACH_TYPE_IXDP2400 242 -#define MACH_TYPE_IXDP2800 243 -#define MACH_TYPE_IXDP425 245 -#define MACH_TYPE_HACKKIT 254 -#define MACH_TYPE_IXCDP1100 260 -#define MACH_TYPE_AT91RM9200DK 262 -#define MACH_TYPE_CINTEGRATOR 275 -#define MACH_TYPE_VIPER 283 -#define MACH_TYPE_ADI_COYOTE 290 -#define MACH_TYPE_IXDP2401 299 -#define MACH_TYPE_IXDP2801 300 -#define MACH_TYPE_IQ31244 327 -#define MACH_TYPE_BAST 331 -#define MACH_TYPE_H1940 347 -#define MACH_TYPE_ENP2611 356 -#define MACH_TYPE_S3C2440 362 -#define MACH_TYPE_GUMSTIX 373 -#define MACH_TYPE_OMAP_H2 382 -#define MACH_TYPE_E740 384 -#define MACH_TYPE_IQ80331 385 -#define MACH_TYPE_VERSATILE_PB 387 -#define MACH_TYPE_KEV7A400 388 -#define MACH_TYPE_LPD7A400 389 -#define MACH_TYPE_LPD7A404 390 -#define MACH_TYPE_CSB337 399 -#define MACH_TYPE_MAINSTONE 406 -#define MACH_TYPE_XCEP 413 -#define MACH_TYPE_ARCOM_VULCAN 414 -#define MACH_TYPE_NOMADIK 420 -#define MACH_TYPE_CORGI 423 -#define MACH_TYPE_POODLE 424 -#define MACH_TYPE_ARMCORE 438 -#define MACH_TYPE_MX31ADS 447 -#define MACH_TYPE_HIMALAYA 448 -#define MACH_TYPE_EDB9312 451 -#define MACH_TYPE_OMAP_GENERIC 452 -#define MACH_TYPE_EDB9301 462 -#define MACH_TYPE_EDB9315 463 -#define MACH_TYPE_VR1000 475 -#define MACH_TYPE_OMAP_PERSEUS2 491 -#define MACH_TYPE_E800 496 -#define MACH_TYPE_E750 497 -#define MACH_TYPE_SCB9328 508 -#define MACH_TYPE_OMAP_H3 509 -#define MACH_TYPE_OMAP_H4 510 -#define MACH_TYPE_OMAP_OSK 515 -#define MACH_TYPE_TOSA 520 -#define MACH_TYPE_AVILA 526 -#define MACH_TYPE_EDB9302 538 -#define MACH_TYPE_HUSKY 543 -#define MACH_TYPE_SHEPHERD 545 -#define MACH_TYPE_H4700 562 -#define MACH_TYPE_RX3715 592 -#define MACH_TYPE_NSLU2 597 -#define MACH_TYPE_E400 598 -#define MACH_TYPE_IXDPG425 604 -#define MACH_TYPE_VERSATILE_AB 606 -#define MACH_TYPE_EDB9307 607 -#define MACH_TYPE_KB9200 612 -#define MACH_TYPE_SX1 613 -#define MACH_TYPE_IXDP465 618 -#define MACH_TYPE_IXDP2351 619 -#define MACH_TYPE_IQ80332 629 -#define MACH_TYPE_GTWX5715 641 -#define MACH_TYPE_CSB637 648 -#define MACH_TYPE_N30 656 -#define MACH_TYPE_NEC_MP900 659 -#define MACH_TYPE_KAFA 662 -#define MACH_TYPE_TS72XX 673 -#define MACH_TYPE_OTOM 680 -#define MACH_TYPE_NEXCODER_2440 681 -#define MACH_TYPE_ECO920 702 -#define MACH_TYPE_ROADRUNNER 704 -#define MACH_TYPE_AT91RM9200EK 705 -#define MACH_TYPE_SPITZ 713 -#define MACH_TYPE_ADSSPHERE 723 -#define MACH_TYPE_COLIBRI 729 -#define MACH_TYPE_GATEWAY7001 731 -#define MACH_TYPE_PCM027 732 -#define MACH_TYPE_ANUBIS 734 -#define MACH_TYPE_AKITA 744 -#define MACH_TYPE_E330 753 -#define MACH_TYPE_NOKIA770 755 -#define MACH_TYPE_CARMEVA 769 -#define MACH_TYPE_EDB9315A 772 -#define MACH_TYPE_STARGATE2 774 -#define MACH_TYPE_INTELMOTE2 775 -#define MACH_TYPE_TRIZEPS4 776 -#define MACH_TYPE_PNX4008 782 -#define MACH_TYPE_CPUAT91 787 -#define MACH_TYPE_IQ81340SC 799 -#define MACH_TYPE_IQ81340MC 801 -#define MACH_TYPE_MICRO9 811 -#define MACH_TYPE_MICRO9L 812 -#define MACH_TYPE_OMAP_PALMTE 817 -#define MACH_TYPE_REALVIEW_EB 827 -#define MACH_TYPE_BORZOI 831 -#define MACH_TYPE_PALMLD 835 -#define MACH_TYPE_IXDP28X5 838 -#define MACH_TYPE_OMAP_PALMTT 839 -#define MACH_TYPE_ARCOM_ZEUS 841 -#define MACH_TYPE_OSIRIS 842 -#define MACH_TYPE_PALMTE2 844 -#define MACH_TYPE_MX27ADS 846 -#define MACH_TYPE_AT91SAM9261EK 848 -#define MACH_TYPE_LOFT 849 -#define MACH_TYPE_MX21ADS 851 -#define MACH_TYPE_AMS_DELTA 862 -#define MACH_TYPE_NAS100D 865 -#define MACH_TYPE_MAGICIAN 875 -#define MACH_TYPE_NXDKN 880 -#define MACH_TYPE_PALMTX 885 -#define MACH_TYPE_S3C2413 887 -#define MACH_TYPE_WG302V2 890 -#define MACH_TYPE_OMAP_2430SDP 900 -#define MACH_TYPE_DAVINCI_EVM 901 -#define MACH_TYPE_PALMZ72 904 -#define MACH_TYPE_NXDB500 905 -#define MACH_TYPE_PALMT5 917 -#define MACH_TYPE_PALMTC 918 -#define MACH_TYPE_OMAP_APOLLON 919 -#define MACH_TYPE_ATEB9200 923 -#define MACH_TYPE_N35 927 -#define MACH_TYPE_LOGICPD_PXA270 930 -#define MACH_TYPE_NXEB500HMI 941 -#define MACH_TYPE_ESPRESSO 949 -#define MACH_TYPE_RX1950 952 -#define MACH_TYPE_GESBC9312 958 -#define MACH_TYPE_PICOTUX2XX 963 -#define MACH_TYPE_DSMG600 964 -#define MACH_TYPE_OMAP_FSAMPLE 970 -#define MACH_TYPE_SNAPPER_CL15 986 -#define MACH_TYPE_OMAP_PALMZ71 993 -#define MACH_TYPE_SMDK2412 1009 -#define MACH_TYPE_SMDK2413 1022 -#define MACH_TYPE_AML_M5900 1024 -#define MACH_TYPE_BALLOON3 1029 -#define MACH_TYPE_ECBAT91 1072 -#define MACH_TYPE_ONEARM 1075 -#define MACH_TYPE_SMDK2443 1084 -#define MACH_TYPE_FSG 1091 -#define MACH_TYPE_AT91SAM9260EK 1099 -#define MACH_TYPE_GLANTANK 1100 -#define MACH_TYPE_N2100 1101 -#define MACH_TYPE_QT2410 1108 -#define MACH_TYPE_KIXRP435 1109 -#define MACH_TYPE_CC9P9360DEV 1114 -#define MACH_TYPE_EDB9302A 1127 -#define MACH_TYPE_EDB9307A 1128 -#define MACH_TYPE_OMAP_3430SDP 1138 -#define MACH_TYPE_VSTMS 1140 -#define MACH_TYPE_MICRO9M 1169 -#define MACH_TYPE_BUG 1179 -#define MACH_TYPE_AT91SAM9263EK 1202 -#define MACH_TYPE_EM7210 1212 -#define MACH_TYPE_VPAC270 1227 -#define MACH_TYPE_TREO680 1230 -#define MACH_TYPE_ZYLONITE 1233 -#define MACH_TYPE_MX31LITE 1236 -#define MACH_TYPE_MIOA701 1257 -#define MACH_TYPE_ARMADILLO5X0 1260 -#define MACH_TYPE_CC9P9360JS 1264 -#define MACH_TYPE_NOKIA_N800 1271 -#define MACH_TYPE_EP80219 1281 -#define MACH_TYPE_GORAMO_MLR 1292 -#define MACH_TYPE_EM_X270 1297 -#define MACH_TYPE_NEO1973_GTA02 1304 -#define MACH_TYPE_AT91SAM9RLEK 1326 -#define MACH_TYPE_COLIBRI320 1340 -#define MACH_TYPE_CAM60 1351 -#define MACH_TYPE_AT91EB01 1354 -#define MACH_TYPE_DB88F5281 1358 -#define MACH_TYPE_CSB726 1359 -#define MACH_TYPE_DAVINCI_DM6467_EVM 1380 -#define MACH_TYPE_DAVINCI_DM355_EVM 1381 -#define MACH_TYPE_LITTLETON 1388 -#define MACH_TYPE_REALVIEW_PB11MP 1407 -#define MACH_TYPE_MX27_3DS 1430 -#define MACH_TYPE_HALIBUT 1439 -#define MACH_TYPE_TROUT 1440 -#define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERALD 1461 -#define MACH_TYPE_SIM_ONE 1476 -#define MACH_TYPE_JIVE 1490 -#define MACH_TYPE_SAM9_L9260 1501 -#define MACH_TYPE_REALVIEW_PB1176 1504 -#define MACH_TYPE_YL9200 1507 -#define MACH_TYPE_RD88F5182 1508 -#define MACH_TYPE_KUROBOX_PRO 1509 -#define MACH_TYPE_MX31_3DS 1511 -#define MACH_TYPE_QONG 1524 -#define MACH_TYPE_OMAP2EVM 1534 -#define MACH_TYPE_OMAP3EVM 1535 -#define MACH_TYPE_DNS323 1542 -#define MACH_TYPE_OMAP3_BEAGLE 1546 -#define MACH_TYPE_NOKIA_N810 1548 -#define MACH_TYPE_PCM038 1551 -#define MACH_TYPE_TS209 1565 -#define MACH_TYPE_AT91CAP9ADK 1566 -#define MACH_TYPE_MX31MOBOARD 1574 -#define MACH_TYPE_TERASTATION_PRO2 1584 -#define MACH_TYPE_LINKSTATION_PRO 1585 -#define MACH_TYPE_E350 1596 -#define MACH_TYPE_TS409 1601 -#define MACH_TYPE_CM_X300 1616 -#define MACH_TYPE_AT91SAM9G20EK 1624 -#define MACH_TYPE_SMDK6410 1626 -#define MACH_TYPE_U300 1627 -#define MACH_TYPE_WRT350N_V2 1633 -#define MACH_TYPE_OMAP_LDP 1639 -#define MACH_TYPE_MX35_3DS 1645 -#define MACH_TYPE_NEUROS_OSD2 1647 -#define MACH_TYPE_TRIZEPS4WL 1649 -#define MACH_TYPE_TS78XX 1652 -#define MACH_TYPE_SFFSDR 1657 -#define MACH_TYPE_PCM037 1673 -#define MACH_TYPE_DB88F6281_BP 1680 -#define MACH_TYPE_RD88F6192_NAS 1681 -#define MACH_TYPE_RD88F6281 1682 -#define MACH_TYPE_DB78X00_BP 1683 -#define MACH_TYPE_SMDK2416 1685 -#define MACH_TYPE_WBD111 1690 -#define MACH_TYPE_MV2120 1693 -#define MACH_TYPE_MX51_3DS 1696 -#define MACH_TYPE_IMX27LITE 1701 -#define MACH_TYPE_USB_A9260 1709 -#define MACH_TYPE_USB_A9263 1710 -#define MACH_TYPE_QIL_A9260 1711 -#define MACH_TYPE_KZM_ARM11_01 1722 -#define MACH_TYPE_NOKIA_N810_WIMAX 1727 -#define MACH_TYPE_SAPPHIRE 1729 -#define MACH_TYPE_STMP37XX 1732 -#define MACH_TYPE_STMP378X 1733 -#define MACH_TYPE_EZX_A780 1740 -#define MACH_TYPE_EZX_E680 1741 -#define MACH_TYPE_EZX_A1200 1742 -#define MACH_TYPE_EZX_E6 1743 -#define MACH_TYPE_EZX_E2 1744 -#define MACH_TYPE_EZX_A910 1745 -#define MACH_TYPE_EDMINI_V2 1756 -#define MACH_TYPE_ZIPIT2 1757 -#define MACH_TYPE_OMAP3_PANDORA 1761 -#define MACH_TYPE_MSS2 1766 -#define MACH_TYPE_LB88RC8480 1769 -#define MACH_TYPE_MX25_3DS 1771 -#define MACH_TYPE_OMAP3530_LV_SOM 1773 -#define MACH_TYPE_DAVINCI_DA830_EVM 1781 -#define MACH_TYPE_AT572D940HFEB 1783 -#define MACH_TYPE_DOVE_DB 1788 -#define MACH_TYPE_OVERO 1798 -#define MACH_TYPE_AT2440EVB 1799 -#define MACH_TYPE_NEOCORE926 1800 -#define MACH_TYPE_WNR854T 1801 -#define MACH_TYPE_RD88F5181L_GE 1812 -#define MACH_TYPE_RD88F5181L_FXO 1818 -#define MACH_TYPE_STAMP9G20 1824 -#define MACH_TYPE_SMDKC100 1826 -#define MACH_TYPE_TAVOREVB 1827 -#define MACH_TYPE_SAAR 1828 -#define MACH_TYPE_AT91SAM9M10G45EK 1830 -#define MACH_TYPE_MXLADS 1851 -#define MACH_TYPE_LINKSTATION_MINI 1858 -#define MACH_TYPE_AFEB9260 1859 -#define MACH_TYPE_IMX27IPCAM 1871 -#define MACH_TYPE_RD88F6183AP_GE 1894 -#define MACH_TYPE_REALVIEW_PBA8 1897 -#define MACH_TYPE_REALVIEW_PBX 1901 -#define MACH_TYPE_MICRO9S 1902 -#define MACH_TYPE_RUT100 1908 -#define MACH_TYPE_G3EVM 1919 -#define MACH_TYPE_W90P910EVB 1921 -#define MACH_TYPE_W90P950EVB 1923 -#define MACH_TYPE_W90N960EVB 1924 -#define MACH_TYPE_MV88F6281GTW_GE 1932 -#define MACH_TYPE_NCP 1933 -#define MACH_TYPE_DAVINCI_DM365_EVM 1939 -#define MACH_TYPE_CENTRO 1944 -#define MACH_TYPE_NOKIA_RX51 1955 -#define MACH_TYPE_OMAP_ZOOM2 1967 -#define MACH_TYPE_CPUAT9260 1973 -#define MACH_TYPE_EUKREA_CPUIMX27 1975 -#define MACH_TYPE_ACS5K 1982 -#define MACH_TYPE_SNAPPER_9260 1987 -#define MACH_TYPE_DSM320 1988 -#define MACH_TYPE_EXEDA 1994 -#define MACH_TYPE_MINI2440 1999 -#define MACH_TYPE_COLIBRI300 2000 -#define MACH_TYPE_LINKSTATION_LS_HGL 2005 -#define MACH_TYPE_CPUAT9G20 2031 -#define MACH_TYPE_SMDK6440 2032 -#define MACH_TYPE_NAS4220B 2038 -#define MACH_TYPE_ZYLONITE2 2042 -#define MACH_TYPE_ASPENITE 2043 -#define MACH_TYPE_TTC_DKB 2045 -#define MACH_TYPE_PCM043 2072 -#define MACH_TYPE_SHEEVAPLUG 2097 -#define MACH_TYPE_AVENGERS_LITE 2104 -#define MACH_TYPE_MX51_BABBAGE 2125 -#define MACH_TYPE_RD78X00_MASA 2135 -#define MACH_TYPE_DM355_LEOPARD 2138 -#define MACH_TYPE_TS219 2139 -#define MACH_TYPE_PCA100 2149 -#define MACH_TYPE_DAVINCI_DA850_EVM 2157 -#define MACH_TYPE_AT91SAM9G10EK 2159 -#define MACH_TYPE_OMAP_4430SDP 2160 -#define MACH_TYPE_MAGX_ZN5 2162 -#define MACH_TYPE_BTMAVB101 2172 -#define MACH_TYPE_BTMAWB101 2173 -#define MACH_TYPE_OMAP3_TORPEDO 2178 -#define MACH_TYPE_ANW6410 2183 -#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 -#define MACH_TYPE_PORTUXG20 2191 -#define MACH_TYPE_SMDKC110 2193 -#define MACH_TYPE_OMAP3517EVM 2200 -#define MACH_TYPE_NETSPACE_V2 2201 -#define MACH_TYPE_NETSPACE_MAX_V2 2202 -#define MACH_TYPE_D2NET_V2 2203 -#define MACH_TYPE_NET2BIG_V2 2204 -#define MACH_TYPE_NET5BIG_V2 2206 -#define MACH_TYPE_INETSPACE_V2 2208 -#define MACH_TYPE_AT91SAM9G45EKES 2212 -#define MACH_TYPE_PC7302 2220 -#define MACH_TYPE_SPEAR600 2236 -#define MACH_TYPE_SPEAR300 2237 -#define MACH_TYPE_LILLY1131 2239 -#define MACH_TYPE_HMT 2254 -#define MACH_TYPE_VEXPRESS 2272 -#define MACH_TYPE_D2NET 2282 -#define MACH_TYPE_BIGDISK 2283 -#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 -#define MACH_TYPE_BCMRING 2289 -#define MACH_TYPE_DP6XX 2302 -#define MACH_TYPE_MAHIMAHI 2304 -#define MACH_TYPE_SMDK6442 2324 -#define MACH_TYPE_OPENRD_BASE 2325 -#define MACH_TYPE_DEVKIT8000 2330 -#define MACH_TYPE_MX51_EFIKAMX 2336 -#define MACH_TYPE_CM_T35 2341 -#define MACH_TYPE_NET2BIG 2342 -#define MACH_TYPE_IGEP0020 2344 -#define MACH_TYPE_NUC932EVB 2356 -#define MACH_TYPE_OPENRD_CLIENT 2361 -#define MACH_TYPE_U8500 2368 -#define MACH_TYPE_MX51_EFIKASB 2370 -#define MACH_TYPE_MARVELL_JASPER 2382 -#define MACH_TYPE_FLINT 2383 -#define MACH_TYPE_TAVOREVB3 2384 -#define MACH_TYPE_TOUCHBOOK 2393 -#define MACH_TYPE_RAUMFELD_RC 2413 -#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 -#define MACH_TYPE_RAUMFELD_SPEAKER 2415 -#define MACH_TYPE_TNETV107X 2418 -#define MACH_TYPE_SMDKV210 2456 -#define MACH_TYPE_OMAP_ZOOM3 2464 -#define MACH_TYPE_OMAP_3630SDP 2465 -#define MACH_TYPE_SMARTQ7 2479 -#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 -#define MACH_TYPE_G4EVM 2493 -#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 -#define MACH_TYPE_TS41X 2502 -#define MACH_TYPE_PHY3250 2511 -#define MACH_TYPE_MINI6410 2520 -#define MACH_TYPE_MX28EVK 2531 -#define MACH_TYPE_SMARTQ5 2534 -#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 -#define MACH_TYPE_MXT_TD60 2550 -#define MACH_TYPE_RIOT_BEI2 2576 -#define MACH_TYPE_RIOT_X37 2578 -#define MACH_TYPE_CAPC7117 2612 -#define MACH_TYPE_ICONTROL 2624 -#define MACH_TYPE_QSD8X50A_ST1_5 2627 -#define MACH_TYPE_MX23EVK 2629 -#define MACH_TYPE_AP4EVB 2630 -#define MACH_TYPE_MITYOMAPL138 2650 -#define MACH_TYPE_GURUPLUG 2659 -#define MACH_TYPE_SPEAR310 2660 -#define MACH_TYPE_SPEAR320 2661 -#define MACH_TYPE_AQUILA 2676 -#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 -#define MACH_TYPE_MSM7X30_SURF 2679 -#define MACH_TYPE_EA2478DEVKIT 2683 -#define MACH_TYPE_TERASTATION_WXL 2697 -#define MACH_TYPE_MSM7X25_SURF 2703 -#define MACH_TYPE_MSM7X25_FFA 2704 -#define MACH_TYPE_MSM7X27_SURF 2705 -#define MACH_TYPE_MSM7X27_FFA 2706 -#define MACH_TYPE_MSM7X30_FFA 2707 -#define MACH_TYPE_QSD8X50_SURF 2708 -#define MACH_TYPE_MX53_EVK 2716 -#define MACH_TYPE_IGEP0030 2717 -#define MACH_TYPE_SBC3530 2722 -#define MACH_TYPE_SAARB 2727 -#define MACH_TYPE_HARMONY 2731 -#define MACH_TYPE_MSM7X30_FLUID 2741 -#define MACH_TYPE_CM_T3517 2750 -#define MACH_TYPE_WBD222 2753 -#define MACH_TYPE_MSM8X60_SURF 2755 -#define MACH_TYPE_MSM8X60_SIM 2756 -#define MACH_TYPE_TCC8000_SDK 2758 -#define MACH_TYPE_NANOS 2759 -#define MACH_TYPE_STAMP9G45 2761 -#define MACH_TYPE_CNS3420VB 2776 -#define MACH_TYPE_OMAP4_PANDA 2791 -#define MACH_TYPE_TI8168EVM 2800 -#define MACH_TYPE_TETON_BGA 2816 -#define MACH_TYPE_EUKREA_CPUIMX25SD 2820 -#define MACH_TYPE_EUKREA_CPUIMX35SD 2821 -#define MACH_TYPE_EUKREA_CPUIMX51SD 2822 -#define MACH_TYPE_EUKREA_CPUIMX51 2823 -#define MACH_TYPE_SMDKC210 2838 -#define MACH_TYPE_OMAP3_BRAILLO 2839 -#define MACH_TYPE_SPYPLUG 2840 -#define MACH_TYPE_GINGER 2841 -#define MACH_TYPE_TNY_T3530 2842 -#define MACH_TYPE_PCA102 2843 -#define MACH_TYPE_SPADE 2844 -#define MACH_TYPE_MXC25_TOPAZ 2845 -#define MACH_TYPE_T5325 2846 -#define MACH_TYPE_GW2361 2847 -#define MACH_TYPE_ELOG 2848 -#define MACH_TYPE_INCOME 2849 -#define MACH_TYPE_BCM589X 2850 -#define MACH_TYPE_ETNA 2851 -#define MACH_TYPE_HAWKS 2852 -#define MACH_TYPE_MESON 2853 -#define MACH_TYPE_XSBASE255 2854 -#define MACH_TYPE_PVM2030 2855 -#define MACH_TYPE_MIOA502 2856 -#define MACH_TYPE_VVBOX_SDORIG2 2857 -#define MACH_TYPE_VVBOX_SDLITE2 2858 -#define MACH_TYPE_VVBOX_SDPRO4 2859 -#define MACH_TYPE_HTC_SPV_M700 2860 -#define MACH_TYPE_MX257SX 2861 -#define MACH_TYPE_GONI 2862 -#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863 -#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864 -#define MACH_TYPE_QUICKSTEP 2865 -#define MACH_TYPE_DMW96 2866 -#define MACH_TYPE_HAMMERHEAD 2867 -#define MACH_TYPE_TRIDENT 2868 -#define MACH_TYPE_LIGHTNING 2869 -#define MACH_TYPE_ICONNECT 2870 -#define MACH_TYPE_AUTOBOT 2871 -#define MACH_TYPE_COCONUT 2872 -#define MACH_TYPE_DURIAN 2873 -#define MACH_TYPE_CAYENNE 2874 -#define MACH_TYPE_FUJI 2875 -#define MACH_TYPE_SYNOLOGY_6282 2876 -#define MACH_TYPE_EM1SY 2877 -#define MACH_TYPE_M502 2878 -#define MACH_TYPE_MATRIX518 2879 -#define MACH_TYPE_TINY_GURNARD 2880 -#define MACH_TYPE_SPEAR1310 2881 -#define MACH_TYPE_BV07 2882 -#define MACH_TYPE_MXT_TD61 2883 -#define MACH_TYPE_OPENRD_ULTIMATE 2884 -#define MACH_TYPE_DEVIXP 2885 -#define MACH_TYPE_MICCPT 2886 -#define MACH_TYPE_MIC256 2887 -#define MACH_TYPE_AS1167 2888 -#define MACH_TYPE_OMAP3_IBIZA 2889 -#define MACH_TYPE_U5500 2890 -#define MACH_TYPE_DAVINCI_PICTO 2891 -#define MACH_TYPE_MECHA 2892 -#define MACH_TYPE_BUBBA3 2893 -#define MACH_TYPE_PUPITRE 2894 -#define MACH_TYPE_TEGRA_VOGUE 2896 -#define MACH_TYPE_TEGRA_E1165 2897 -#define MACH_TYPE_SIMPLENET 2898 -#define MACH_TYPE_EC4350TBM 2899 -#define MACH_TYPE_PEC_TC 2900 -#define MACH_TYPE_PEC_HC2 2901 -#define MACH_TYPE_ESL_MOBILIS_A 2902 -#define MACH_TYPE_ESL_MOBILIS_B 2903 -#define MACH_TYPE_ESL_WAVE_A 2904 -#define MACH_TYPE_ESL_WAVE_B 2905 -#define MACH_TYPE_UNISENSE_MMM 2906 -#define MACH_TYPE_BLUESHARK 2907 -#define MACH_TYPE_E10 2908 -#define MACH_TYPE_APP3K_ROBIN 2909 -#define MACH_TYPE_POV15HD 2910 -#define MACH_TYPE_STELLA 2911 -#define MACH_TYPE_LINKSTATION_LSCHL 2913 -#define MACH_TYPE_NETWALKER 2914 -#define MACH_TYPE_ACSX106 2915 -#define MACH_TYPE_ATLAS5_C1 2916 -#define MACH_TYPE_NSB3AST 2917 -#define MACH_TYPE_GNET_SLC 2918 -#define MACH_TYPE_AF4000 2919 -#define MACH_TYPE_ARK9431 2920 -#define MACH_TYPE_FS_S5PC100 2921 -#define MACH_TYPE_OMAP3505NOVA8 2922 -#define MACH_TYPE_OMAP3621_EDP1 2923 -#define MACH_TYPE_ORATISAES 2924 -#define MACH_TYPE_SMDKV310 2925 -#define MACH_TYPE_SIEMENS_L0 2926 -#define MACH_TYPE_VENTANA 2927 -#define MACH_TYPE_WM8505_7IN_NETBOOK 2928 -#define MACH_TYPE_EC4350SDB 2929 -#define MACH_TYPE_MIMAS 2930 -#define MACH_TYPE_TITAN 2931 -#define MACH_TYPE_CRANEBOARD 2932 -#define MACH_TYPE_ES2440 2933 -#define MACH_TYPE_NAJAY_A9263 2934 -#define MACH_TYPE_HTCTORNADO 2935 -#define MACH_TYPE_DIMM_MX257 2936 -#define MACH_TYPE_JIGEN 2937 -#define MACH_TYPE_SMDK6450 2938 -#define MACH_TYPE_MENO_QNG 2939 -#define MACH_TYPE_NS2416 2940 -#define MACH_TYPE_RPC353 2941 -#define MACH_TYPE_TQ6410 2942 -#define MACH_TYPE_SKY6410 2943 -#define MACH_TYPE_DYNASTY 2944 -#define MACH_TYPE_VIVO 2945 -#define MACH_TYPE_BURY_BL7582 2946 -#define MACH_TYPE_BURY_BPS5270 2947 -#define MACH_TYPE_BASI 2948 -#define MACH_TYPE_TN200 2949 -#define MACH_TYPE_C2MMI 2950 -#define MACH_TYPE_MESON_6236M 2951 -#define MACH_TYPE_MESON_8626M 2952 -#define MACH_TYPE_TUBE 2953 -#define MACH_TYPE_MESSINA 2954 -#define MACH_TYPE_MX50_ARM2 2955 -#define MACH_TYPE_CETUS9263 2956 -#define MACH_TYPE_BROWNSTONE 2957 -#define MACH_TYPE_VMX25 2958 -#define MACH_TYPE_VMX51 2959 -#define MACH_TYPE_ABACUS 2960 -#define MACH_TYPE_CM4745 2961 -#define MACH_TYPE_ORATISLINK 2962 -#define MACH_TYPE_DAVINCI_DM365_DVR 2963 -#define MACH_TYPE_NETVIZ 2964 -#define MACH_TYPE_FLEXIBITY 2965 -#define MACH_TYPE_WLAN_COMPUTER 2966 -#define MACH_TYPE_LPC24XX 2967 -#define MACH_TYPE_SPICA 2968 -#define MACH_TYPE_GPSDISPLAY 2969 -#define MACH_TYPE_BIPNET 2970 -#define MACH_TYPE_OVERO_CTU_INERTIAL 2971 -#define MACH_TYPE_DAVINCI_DM355_MMM 2972 -#define MACH_TYPE_PC9260_V2 2973 -#define MACH_TYPE_PTX7545 2974 -#define MACH_TYPE_TM_EFDC 2975 -#define MACH_TYPE_OMAP3_WALDO1 2977 -#define MACH_TYPE_FLYER 2978 -#define MACH_TYPE_TORNADO3240 2979 -#define MACH_TYPE_SOLI_01 2980 -#define MACH_TYPE_OMAPL138_EUROPALC 2981 -#define MACH_TYPE_HELIOS_V1 2982 -#define MACH_TYPE_NETSPACE_LITE_V2 2983 -#define MACH_TYPE_SSC 2984 -#define MACH_TYPE_PREMIERWAVE_EN 2985 -#define MACH_TYPE_WASABI 2986 -#define MACH_TYPE_MX50_RDP 2988 -#define MACH_TYPE_UNIVERSAL_C210 2989 -#define MACH_TYPE_REAL6410 2990 -#define MACH_TYPE_SPX_SAKURA 2991 -#define MACH_TYPE_IJ3K_2440 2992 -#define MACH_TYPE_OMAP3_BC10 2993 -#define MACH_TYPE_THEBE 2994 -#define MACH_TYPE_RV082 2995 -#define MACH_TYPE_ARMLGUEST 2996 -#define MACH_TYPE_TJINC1000 2997 -#define MACH_TYPE_DOCKSTAR 2998 -#define MACH_TYPE_AX8008 2999 -#define MACH_TYPE_GNET_SGCE 3000 -#define MACH_TYPE_PXWNAS_500_1000 3001 -#define MACH_TYPE_EA20 3002 -#define MACH_TYPE_AWM2 3003 -#define MACH_TYPE_TI8148EVM 3004 -#define MACH_TYPE_SEABOARD 3005 -#define MACH_TYPE_LINKSTATION_CHLV2 3006 -#define MACH_TYPE_TERA_PRO2_RACK 3007 -#define MACH_TYPE_RUBYS 3008 -#define MACH_TYPE_AQUARIUS 3009 -#define MACH_TYPE_MX53_ARD 3010 -#define MACH_TYPE_MX53_SMD 3011 -#define MACH_TYPE_LSWXL 3012 -#define MACH_TYPE_DOVE_AVNG_V3 3013 -#define MACH_TYPE_SDI_ESS_9263 3014 -#define MACH_TYPE_JOCPU550 3015 -#define MACH_TYPE_MSM8X60_RUMI3 3016 -#define MACH_TYPE_MSM8X60_FFA 3017 -#define MACH_TYPE_YANOMAMI 3018 -#define MACH_TYPE_GTA04 3019 -#define MACH_TYPE_CM_A510 3020 -#define MACH_TYPE_OMAP3_RFS200 3021 -#define MACH_TYPE_KX33XX 3022 -#define MACH_TYPE_PTX7510 3023 -#define MACH_TYPE_TOP9000 3024 -#define MACH_TYPE_TEENOTE 3025 -#define MACH_TYPE_TS3 3026 -#define MACH_TYPE_A0 3027 -#define MACH_TYPE_FSM9XXX_SURF 3028 -#define MACH_TYPE_FSM9XXX_FFA 3029 -#define MACH_TYPE_FRRHWCDMA60W 3030 -#define MACH_TYPE_REMUS 3031 -#define MACH_TYPE_AT91CAP7XDK 3032 -#define MACH_TYPE_AT91CAP7STK 3033 -#define MACH_TYPE_KT_SBC_SAM9_1 3034 -#define MACH_TYPE_ARMADA_XP_DB 3036 -#define MACH_TYPE_SPDM 3037 -#define MACH_TYPE_GTIB 3038 -#define MACH_TYPE_DGM3240 3039 -#define MACH_TYPE_HTCMEGA 3041 -#define MACH_TYPE_TRICORDER 3042 -#define MACH_TYPE_TX28 3043 -#define MACH_TYPE_BSTBRD 3044 -#define MACH_TYPE_PWB3090 3045 -#define MACH_TYPE_IDEA6410 3046 -#define MACH_TYPE_QBC9263 3047 -#define MACH_TYPE_BORABORA 3048 -#define MACH_TYPE_VALDEZ 3049 -#define MACH_TYPE_LS9G20 3050 -#define MACH_TYPE_MIOS_V1 3051 -#define MACH_TYPE_S5PC110_CRESPO 3052 -#define MACH_TYPE_CONTROLTEK9G20 3053 -#define MACH_TYPE_TIN307 3054 -#define MACH_TYPE_TIN510 3055 -#define MACH_TYPE_BLUECHEESE 3057 -#define MACH_TYPE_TEM3X30 3058 -#define MACH_TYPE_HARVEST_DESOTO 3059 -#define MACH_TYPE_MSM8X60_QRDC 3060 -#define MACH_TYPE_SPEAR900 3061 -#define MACH_TYPE_PCONTROL_G20 3062 -#define MACH_TYPE_RDSTOR 3063 -#define MACH_TYPE_USDLOADER 3064 -#define MACH_TYPE_TSOPLOADER 3065 -#define MACH_TYPE_KRONOS 3066 -#define MACH_TYPE_FFCORE 3067 -#define MACH_TYPE_MONE 3068 -#define MACH_TYPE_UNIT2S 3069 -#define MACH_TYPE_ACER_A5 3070 -#define MACH_TYPE_ETHERPRO_ISP 3071 -#define MACH_TYPE_STRETCHS7000 3072 -#define MACH_TYPE_P87_SMARTSIM 3073 -#define MACH_TYPE_TULIP 3074 -#define MACH_TYPE_SUNFLOWER 3075 -#define MACH_TYPE_RIB 3076 -#define MACH_TYPE_CLOD 3077 -#define MACH_TYPE_RUMP 3078 -#define MACH_TYPE_TENDERLOIN 3079 -#define MACH_TYPE_SHORTLOIN 3080 -#define MACH_TYPE_ANTARES 3082 -#define MACH_TYPE_WB40N 3083 -#define MACH_TYPE_HERRING 3084 -#define MACH_TYPE_NAXY400 3085 -#define MACH_TYPE_NAXY1200 3086 -#define MACH_TYPE_VPR200 3087 -#define MACH_TYPE_BUG20 3088 -#define MACH_TYPE_GOFLEXNET 3089 -#define MACH_TYPE_TORBRECK 3090 -#define MACH_TYPE_SAARB_MG1 3091 -#define MACH_TYPE_CALLISTO 3092 -#define MACH_TYPE_MULTHSU 3093 -#define MACH_TYPE_SALUDA 3094 -#define MACH_TYPE_PEMP_OMAP3_APOLLO 3095 -#define MACH_TYPE_VC0718 3096 -#define MACH_TYPE_MVBLX 3097 -#define MACH_TYPE_INHAND_APEIRON 3098 -#define MACH_TYPE_INHAND_FURY 3099 -#define MACH_TYPE_INHAND_SIREN 3100 -#define MACH_TYPE_HDNVP 3101 -#define MACH_TYPE_SOFTWINNER 3102 -#define MACH_TYPE_PRIMA2_EVB 3103 -#define MACH_TYPE_NAS6210 3104 -#define MACH_TYPE_UNISDEV 3105 -#define MACH_TYPE_SBCA11 3106 -#define MACH_TYPE_SAGA 3107 -#define MACH_TYPE_NS_K330 3108 -#define MACH_TYPE_TANNA 3109 -#define MACH_TYPE_IMATE8502 3110 -#define MACH_TYPE_ASPEN 3111 -#define MACH_TYPE_DAINTREE_CWAC 3112 -#define MACH_TYPE_ZMX25 3113 -#define MACH_TYPE_MAPLE1 3114 -#define MACH_TYPE_QSD8X72_SURF 3115 -#define MACH_TYPE_QSD8X72_FFA 3116 -#define MACH_TYPE_ABILENE 3117 -#define MACH_TYPE_EIGEN_TTR 3118 -#define MACH_TYPE_IOMEGA_IX2_200 3119 -#define MACH_TYPE_CORETEC_VCX7400 3120 -#define MACH_TYPE_SANTIAGO 3121 -#define MACH_TYPE_MX257SOL 3122 -#define MACH_TYPE_STRASBOURG 3123 -#define MACH_TYPE_MSM8X60_FLUID 3124 -#define MACH_TYPE_SMARTQV5 3125 -#define MACH_TYPE_SMARTQV3 3126 -#define MACH_TYPE_SMARTQV7 3127 -#define MACH_TYPE_PAZ00 3128 -#define MACH_TYPE_ACMENETUSFOXG20 3129 -#define MACH_TYPE_FWBD_0404 3131 -#define MACH_TYPE_HDGU 3132 -#define MACH_TYPE_PYRAMID 3133 -#define MACH_TYPE_EPIPHAN 3134 -#define MACH_TYPE_OMAP_BENDER 3135 -#define MACH_TYPE_GURNARD 3136 -#define MACH_TYPE_GTL_IT5100 3137 -#define MACH_TYPE_BCM2708 3138 -#define MACH_TYPE_MX51_GGC 3139 -#define MACH_TYPE_SHARESPACE 3140 -#define MACH_TYPE_HABA_KNX_EXPLORER 3141 -#define MACH_TYPE_SIMTEC_KIRKMOD 3142 -#define MACH_TYPE_CRUX 3143 -#define MACH_TYPE_MX51_BRAVO 3144 -#define MACH_TYPE_CHARON 3145 -#define MACH_TYPE_PICOCOM3 3146 -#define MACH_TYPE_PICOCOM4 3147 -#define MACH_TYPE_SERRANO 3148 -#define MACH_TYPE_DOUBLESHOT 3149 -#define MACH_TYPE_EVSY 3150 -#define MACH_TYPE_HUASHAN 3151 -#define MACH_TYPE_LAUSANNE 3152 -#define MACH_TYPE_EMERALD 3153 -#define MACH_TYPE_TQMA35 3154 -#define MACH_TYPE_MARVEL 3155 -#define MACH_TYPE_MANUAE 3156 -#define MACH_TYPE_CHACHA 3157 -#define MACH_TYPE_LEMON 3158 -#define MACH_TYPE_CSC 3159 -#define MACH_TYPE_GIRA_KNXIP_ROUTER 3160 -#define MACH_TYPE_T20 3161 -#define MACH_TYPE_HDMINI 3162 -#define MACH_TYPE_SCIPHONE_G2 3163 -#define MACH_TYPE_EXPRESS 3164 -#define MACH_TYPE_EXPRESS_KT 3165 -#define MACH_TYPE_MAXIMASP 3166 -#define MACH_TYPE_NITROGEN_IMX51 3167 -#define MACH_TYPE_NITROGEN_IMX53 3168 -#define MACH_TYPE_SUNFIRE 3169 -#define MACH_TYPE_AROWANA 3170 -#define MACH_TYPE_TEGRA_DAYTONA 3171 -#define MACH_TYPE_TEGRA_SWORDFISH 3172 -#define MACH_TYPE_EDISON 3173 -#define MACH_TYPE_SVP8500V1 3174 -#define MACH_TYPE_SVP8500V2 3175 -#define MACH_TYPE_SVP5500 3176 -#define MACH_TYPE_B5500 3177 -#define MACH_TYPE_S5500 3178 -#define MACH_TYPE_ICON 3179 -#define MACH_TYPE_ELEPHANT 3180 -#define MACH_TYPE_SHOOTER 3182 -#define MACH_TYPE_SPADE_LTE 3183 -#define MACH_TYPE_PHILHWANI 3184 -#define MACH_TYPE_GSNCOMM 3185 -#define MACH_TYPE_STRASBOURG_A2 3186 -#define MACH_TYPE_MMM 3187 -#define MACH_TYPE_DAVINCI_DM365_BV 3188 -#define MACH_TYPE_AG5EVM 3189 -#define MACH_TYPE_SC575PLC 3190 -#define MACH_TYPE_SC575IPC 3191 -#define MACH_TYPE_OMAP3_TDM3730 3192 -#define MACH_TYPE_TOP9000_EVAL 3194 -#define MACH_TYPE_TOP9000_SU 3195 -#define MACH_TYPE_UTM300 3196 -#define MACH_TYPE_TSUNAGI 3197 -#define MACH_TYPE_TS75XX 3198 -#define MACH_TYPE_TS47XX 3200 -#define MACH_TYPE_DA850_K5 3201 -#define MACH_TYPE_AX502 3202 -#define MACH_TYPE_IGEP0032 3203 -#define MACH_TYPE_ANTERO 3204 -#define MACH_TYPE_SYNERGY 3205 -#define MACH_TYPE_ICS_IF_VOIP 3206 -#define MACH_TYPE_WLF_CRAGG_6410 3207 -#define MACH_TYPE_PUNICA 3208 -#define MACH_TYPE_TRIMSLICE 3209 -#define MACH_TYPE_MX27_WMULTRA 3210 -#define MACH_TYPE_MACKEREL 3211 -#define MACH_TYPE_FA9X27 3213 -#define MACH_TYPE_NS2816TB 3214 -#define MACH_TYPE_NS2816_NTPAD 3215 -#define MACH_TYPE_NS2816_NTNB 3216 -#define MACH_TYPE_KAEN 3217 -#define MACH_TYPE_NV1000 3218 -#define MACH_TYPE_NUC950TS 3219 -#define MACH_TYPE_NOKIA_RM680 3220 -#define MACH_TYPE_AST2200 3221 -#define MACH_TYPE_LEAD 3222 -#define MACH_TYPE_UNINO1 3223 -#define MACH_TYPE_GREECO 3224 -#define MACH_TYPE_VERDI 3225 -#define MACH_TYPE_DM6446_ADBOX 3226 -#define MACH_TYPE_QUAD_SALSA 3227 -#define MACH_TYPE_ABB_GMA_1_1 3228 -#define MACH_TYPE_SVCID 3229 -#define MACH_TYPE_MSM8960_SIM 3230 -#define MACH_TYPE_MSM8960_RUMI3 3231 -#define MACH_TYPE_ICON_G 3232 -#define MACH_TYPE_MB3 3233 -#define MACH_TYPE_GSIA18S 3234 -#define MACH_TYPE_PIVICC 3235 -#define MACH_TYPE_PCM048 3236 -#define MACH_TYPE_DDS 3237 -#define MACH_TYPE_CHALTEN_XA1 3238 -#define MACH_TYPE_TS48XX 3239 -#define MACH_TYPE_TONGA2_TFTTIMER 3240 -#define MACH_TYPE_WHISTLER 3241 -#define MACH_TYPE_ASL_PHOENIX 3242 -#define MACH_TYPE_AT91SAM9263OTLITE 3243 -#define MACH_TYPE_DDPLUG 3244 -#define MACH_TYPE_D2PLUG 3245 -#define MACH_TYPE_KZM9D 3246 -#define MACH_TYPE_VERDI_LTE 3247 -#define MACH_TYPE_NANOZOOM 3248 -#define MACH_TYPE_DM3730_SOM_LV 3249 -#define MACH_TYPE_DM3730_TORPEDO 3250 -#define MACH_TYPE_ANCHOVY 3251 -#define MACH_TYPE_RE2REV20 3253 -#define MACH_TYPE_RE2REV21 3254 -#define MACH_TYPE_CNS21XX 3255 -#define MACH_TYPE_RIDER 3257 -#define MACH_TYPE_NSK330 3258 -#define MACH_TYPE_CNS2133EVB 3259 -#define MACH_TYPE_Z3_816X_MOD 3260 -#define MACH_TYPE_Z3_814X_MOD 3261 -#define MACH_TYPE_BEECT 3262 -#define MACH_TYPE_DMA_THUNDERBUG 3263 -#define MACH_TYPE_OMN_AT91SAM9G20 3264 -#define MACH_TYPE_MX25_E2S_UC 3265 -#define MACH_TYPE_MIONE 3266 -#define MACH_TYPE_TOP9000_TCU 3267 -#define MACH_TYPE_TOP9000_BSL 3268 -#define MACH_TYPE_KINGDOM 3269 -#define MACH_TYPE_ARMADILLO460 3270 -#define MACH_TYPE_LQ2 3271 -#define MACH_TYPE_SWEDA_TMS2 3272 -#define MACH_TYPE_MX53_LOCO 3273 -#define MACH_TYPE_ACER_A8 3275 -#define MACH_TYPE_ACER_GAUGUIN 3276 -#define MACH_TYPE_GUPPY 3277 -#define MACH_TYPE_MX61_ARD 3278 -#define MACH_TYPE_TX53 3279 -#define MACH_TYPE_OMAPL138_CASE_A3 3280 -#define MACH_TYPE_UEMD 3281 -#define MACH_TYPE_CCWMX51MUT 3282 -#define MACH_TYPE_ROCKHOPPER 3283 -#define MACH_TYPE_ENCORE 3284 -#define MACH_TYPE_HKDKC100 3285 -#define MACH_TYPE_TS42XX 3286 -#define MACH_TYPE_AEBL 3287 -#define MACH_TYPE_WARIO 3288 -#define MACH_TYPE_GFS_SPM 3289 -#define MACH_TYPE_CM_T3730 3290 -#define MACH_TYPE_ISC3 3291 -#define MACH_TYPE_RASCAL 3292 -#define MACH_TYPE_HREFV60 3293 -#define MACH_TYPE_TPT_2_0 3294 -#define MACH_TYPE_SPLENDOR 3296 -#define MACH_TYPE_MSM8X60_QT 3298 -#define MACH_TYPE_HTC_HD_MINI 3299 -#define MACH_TYPE_ATHENE 3300 -#define MACH_TYPE_DEEP_R_EK_1 3301 -#define MACH_TYPE_VIVOW_CT 3302 -#define MACH_TYPE_NERY_1000 3303 -#define MACH_TYPE_RFL109145_SSRV 3304 -#define MACH_TYPE_NMH 3305 -#define MACH_TYPE_WN802T 3306 -#define MACH_TYPE_DRAGONET 3307 -#define MACH_TYPE_AT91SAM9263DESK16L 3309 -#define MACH_TYPE_BCMHANA_SV 3310 -#define MACH_TYPE_BCMHANA_TABLET 3311 -#define MACH_TYPE_KOI 3312 -#define MACH_TYPE_TS4800 3313 -#define MACH_TYPE_TQMA9263 3314 -#define MACH_TYPE_HOLIDAY 3315 -#define MACH_TYPE_DMA6410 3316 -#define MACH_TYPE_PCATS_OVERLAY 3317 -#define MACH_TYPE_HWGW6410 3318 -#define MACH_TYPE_SHENZHOU 3319 -#define MACH_TYPE_CWME9210 3320 -#define MACH_TYPE_CWME9210JS 3321 -#define MACH_TYPE_PGS_SITARA 3322 -#define MACH_TYPE_COLIBRI_TEGRA2 3323 -#define MACH_TYPE_W21 3324 -#define MACH_TYPE_POLYSAT1 3325 -#define MACH_TYPE_DATAWAY 3326 -#define MACH_TYPE_COBRAL138 3327 -#define MACH_TYPE_ROVERPCS8 3328 -#define MACH_TYPE_MARVELC 3329 -#define MACH_TYPE_NAVEFIHID 3330 -#define MACH_TYPE_DM365_CV100 3331 -#define MACH_TYPE_ABLE 3332 -#define MACH_TYPE_LEGACY 3333 -#define MACH_TYPE_ICONG 3334 -#define MACH_TYPE_ROVER_G8 3335 -#define MACH_TYPE_T5388P 3336 -#define MACH_TYPE_DINGO 3337 -#define MACH_TYPE_GOFLEXHOME 3338 -#define MACH_TYPE_LANREADYFN511 3340 -#define MACH_TYPE_OMAP3_BAIA 3341 -#define MACH_TYPE_OMAP3SMARTDISPLAY 3342 -#define MACH_TYPE_XILINX 3343 -#define MACH_TYPE_A2F 3344 -#define MACH_TYPE_SKY25 3345 -#define MACH_TYPE_CCMX53 3346 -#define MACH_TYPE_CCMX53JS 3347 -#define MACH_TYPE_CCWMX53 3348 -#define MACH_TYPE_CCWMX53JS 3349 -#define MACH_TYPE_FRISMS 3350 -#define MACH_TYPE_MSM7X27A_FFA 3351 -#define MACH_TYPE_MSM7X27A_SURF 3352 -#define MACH_TYPE_MSM7X27A_RUMI3 3353 -#define MACH_TYPE_DIMMSAM9G20 3354 -#define MACH_TYPE_DIMM_IMX28 3355 -#define MACH_TYPE_AMK_A4 3356 -#define MACH_TYPE_GNET_SGME 3357 -#define MACH_TYPE_SHOOTER_U 3358 -#define MACH_TYPE_VMX53 3359 -#define MACH_TYPE_RHINO 3360 -#define MACH_TYPE_ARMLEX4210 3361 -#define MACH_TYPE_SWARCOEXTMODEM 3362 -#define MACH_TYPE_SNOWBALL 3363 -#define MACH_TYPE_PCM049 3364 -#define MACH_TYPE_VIGOR 3365 -#define MACH_TYPE_OSLO_AMUNDSEN 3366 -#define MACH_TYPE_GSL_DIAMOND 3367 -#define MACH_TYPE_CV2201 3368 -#define MACH_TYPE_CV2202 3369 -#define MACH_TYPE_CV2203 3370 -#define MACH_TYPE_VIT_IBOX 3371 -#define MACH_TYPE_DM6441_ESP 3372 -#define MACH_TYPE_AT91SAM9X5EK 3373 -#define MACH_TYPE_LIBRA 3374 -#define MACH_TYPE_EASYCRRH 3375 -#define MACH_TYPE_TRIPEL 3376 -#define MACH_TYPE_ENDIAN_MINI 3377 -#define MACH_TYPE_XILINX_EP107 3378 -#define MACH_TYPE_NURI 3379 -#define MACH_TYPE_JANUS 3380 -#define MACH_TYPE_DDNAS 3381 -#define MACH_TYPE_TAG 3382 -#define MACH_TYPE_TAGW 3383 -#define MACH_TYPE_NITROGEN_VM_IMX51 3384 -#define MACH_TYPE_VIPRINET 3385 -#define MACH_TYPE_BOCKW 3386 -#define MACH_TYPE_EVA2000 3387 -#define MACH_TYPE_STEELYARD 3388 -#define MACH_TYPE_MACH_SDH001 3390 -#define MACH_TYPE_NSSLSBOARD 3392 -#define MACH_TYPE_GENEVA_B5 3393 -#define MACH_TYPE_SPEAR1340 3394 -#define MACH_TYPE_REXMAS 3395 -#define MACH_TYPE_MSM8960_CDP 3396 -#define MACH_TYPE_MSM8960_MDP 3397 -#define MACH_TYPE_MSM8960_FLUID 3398 -#define MACH_TYPE_MSM8960_APQ 3399 -#define MACH_TYPE_HELIOS_V2 3400 -#define MACH_TYPE_MIF10P 3401 -#define MACH_TYPE_IAM28 3402 -#define MACH_TYPE_PICASSO 3403 -#define MACH_TYPE_MR301A 3404 -#define MACH_TYPE_NOTLE 3405 -#define MACH_TYPE_EELX2 3406 -#define MACH_TYPE_MOON 3407 -#define MACH_TYPE_RUBY 3408 -#define MACH_TYPE_GOLDENGATE 3409 -#define MACH_TYPE_CTBU_GEN2 3410 -#define MACH_TYPE_KMP_AM17_01 3411 -#define MACH_TYPE_WTPLUG 3412 -#define MACH_TYPE_MX27SU2 3413 -#define MACH_TYPE_NB31 3414 -#define MACH_TYPE_HJSDU 3415 -#define MACH_TYPE_TD3_REV1 3416 -#define MACH_TYPE_EAG_CI4000 3417 -#define MACH_TYPE_NET5BIG_NAND_V2 3418 -#define MACH_TYPE_CPX2 3419 -#define MACH_TYPE_NET2BIG_NAND_V2 3420 -#define MACH_TYPE_ECUV5 3421 -#define MACH_TYPE_HSGX6D 3422 -#define MACH_TYPE_DAWAD7 3423 -#define MACH_TYPE_SAM9REPEATER 3424 -#define MACH_TYPE_GT_I5700 3425 -#define MACH_TYPE_CTERA_PLUG_C2 3426 -#define MACH_TYPE_MARVELCT 3427 -#define MACH_TYPE_AG11005 3428 -#define MACH_TYPE_VANGOGH 3430 -#define MACH_TYPE_MATRIX505 3431 -#define MACH_TYPE_OCE_NIGMA 3432 -#define MACH_TYPE_T55 3433 -#define MACH_TYPE_BIO3K 3434 -#define MACH_TYPE_EXPRESSCT 3435 -#define MACH_TYPE_CARDHU 3436 -#define MACH_TYPE_ARUBA 3437 -#define MACH_TYPE_BONAIRE 3438 -#define MACH_TYPE_NUC700EVB 3439 -#define MACH_TYPE_NUC710EVB 3440 -#define MACH_TYPE_NUC740EVB 3441 -#define MACH_TYPE_NUC745EVB 3442 -#define MACH_TYPE_TRANSCEDE 3443 -#define MACH_TYPE_MORA 3444 -#define MACH_TYPE_NDA_EVM 3445 -#define MACH_TYPE_TIMU 3446 -#define MACH_TYPE_EXPRESSH 3447 -#define MACH_TYPE_VERIDIS_A300 3448 -#define MACH_TYPE_DM368_LEOPARD 3449 -#define MACH_TYPE_OMAP_MCOP 3450 -#define MACH_TYPE_TRITIP 3451 -#define MACH_TYPE_SM1K 3452 -#define MACH_TYPE_MONCH 3453 -#define MACH_TYPE_CURACAO 3454 -#define MACH_TYPE_ORIGEN 3455 -#define MACH_TYPE_EPC10 3456 -#define MACH_TYPE_SGH_I740 3457 -#define MACH_TYPE_TUNA 3458 -#define MACH_TYPE_MX51_TULIP 3459 -#define MACH_TYPE_MX51_ASTER7 3460 -#define MACH_TYPE_ACRO37XBRD 3461 -#define MACH_TYPE_ELKE 3462 -#define MACH_TYPE_SBC6000X 3463 -#define MACH_TYPE_R1801E 3464 -#define MACH_TYPE_H1600 3465 -#define MACH_TYPE_MINI210 3466 -#define MACH_TYPE_MINI8168 3467 -#define MACH_TYPE_PC7308 3468 -#define MACH_TYPE_KMM2M01 3470 -#define MACH_TYPE_MX51EREBUS 3471 -#define MACH_TYPE_WM8650REFBOARD 3472 -#define MACH_TYPE_TUXRAIL 3473 -#define MACH_TYPE_ARTHUR 3474 -#define MACH_TYPE_DOORBOY 3475 -#define MACH_TYPE_XARINA 3476 -#define MACH_TYPE_ROVERX7 3477 -#define MACH_TYPE_SDVR 3478 -#define MACH_TYPE_ACER_MAYA 3479 -#define MACH_TYPE_PICO 3480 -#define MACH_TYPE_CWMX233 3481 -#define MACH_TYPE_CWAM1808 3482 -#define MACH_TYPE_CWDM365 3483 -#define MACH_TYPE_MX51_MORAY 3484 -#define MACH_TYPE_THALES_CBC 3485 -#define MACH_TYPE_BLUEPOINT 3486 -#define MACH_TYPE_DIR665 3487 -#define MACH_TYPE_ACMEROVER1 3488 -#define MACH_TYPE_SHOOTER_CT 3489 -#define MACH_TYPE_BLISS 3490 -#define MACH_TYPE_BLISSC 3491 -#define MACH_TYPE_THALES_ADC 3492 -#define MACH_TYPE_UBISYS_P9D_EVP 3493 -#define MACH_TYPE_ATDGP318 3494 -#define MACH_TYPE_OMAP5_SEVM 3777 -#define MACH_TYPE_ARMADILLO_800EVA 3863 -#define MACH_TYPE_KZM9G 4140 - -#ifdef CONFIG_ARCH_EBSA110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA110 -# endif -# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110) -#else -# define machine_is_ebsa110() (0) -#endif - -#ifdef CONFIG_ARCH_RPC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RISCPC -# endif -# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC) -#else -# define machine_is_riscpc() (0) -#endif - -#ifdef CONFIG_ARCH_EBSA285 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EBSA285 -# endif -# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285) -#else -# define machine_is_ebsa285() (0) -#endif - -#ifdef CONFIG_ARCH_NETWINDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETWINDER -# endif -# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER) -#else -# define machine_is_netwinder() (0) -#endif - -#ifdef CONFIG_ARCH_CATS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CATS -# endif -# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS) -#else -# define machine_is_cats() (0) -#endif - -#ifdef CONFIG_ARCH_SHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHARK -# endif -# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK) -#else -# define machine_is_shark() (0) -#endif - -#ifdef CONFIG_SA1100_BRUTUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BRUTUS -# endif -# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS) -#else -# define machine_is_brutus() (0) -#endif - -#ifdef CONFIG_ARCH_PERSONAL_SERVER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PERSONAL_SERVER -# endif -# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER) -#else -# define machine_is_personal_server() (0) -#endif - -#ifdef CONFIG_ARCH_L7200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_L7200 -# endif -# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200) -#else -# define machine_is_l7200() (0) -#endif - -#ifdef CONFIG_SA1100_PLEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PLEB -# endif -# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB) -#else -# define machine_is_pleb() (0) -#endif - -#ifdef CONFIG_ARCH_INTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTEGRATOR -# endif -# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR) -#else -# define machine_is_integrator() (0) -#endif - -#ifdef CONFIG_SA1100_H3600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3600 -# endif -# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600) -#else -# define machine_is_h3600() (0) -#endif - -#ifdef CONFIG_ARCH_P720T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P720T -# endif -# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T) -#else -# define machine_is_p720t() (0) -#endif - -#ifdef CONFIG_SA1100_ASSABET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASSABET -# endif -# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET) -#else -# define machine_is_assabet() (0) -#endif - -#ifdef CONFIG_SA1100_LART -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LART -# endif -# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART) -#else -# define machine_is_lart() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSCLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT -# endif -# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT) -#else -# define machine_is_graphicsclient() (0) -#endif - -#ifdef CONFIG_SA1100_XP860 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XP860 -# endif -# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860) -#else -# define machine_is_xp860() (0) -#endif - -#ifdef CONFIG_SA1100_CERF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CERF -# endif -# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF) -#else -# define machine_is_cerf() (0) -#endif - -#ifdef CONFIG_SA1100_NANOENGINE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOENGINE -# endif -# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE) -#else -# define machine_is_nanoengine() (0) -#endif - -#ifdef CONFIG_SA1100_JORNADA720 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JORNADA720 -# endif -# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720) -#else -# define machine_is_jornada720() (0) -#endif - -#ifdef CONFIG_ARCH_EDB7211 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB7211 -# endif -# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211) -#else -# define machine_is_edb7211() (0) -#endif - -#ifdef CONFIG_SA1100_PFS168 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PFS168 -# endif -# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168) -#else -# define machine_is_pfs168() (0) -#endif - -#ifdef CONFIG_SA1100_FLEXANET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXANET -# endif -# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET) -#else -# define machine_is_flexanet() (0) -#endif - -#ifdef CONFIG_SA1100_SIMPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPAD -# endif -# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD) -#else -# define machine_is_simpad() (0) -#endif - -#ifdef CONFIG_ARCH_LUBBOCK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LUBBOCK -# endif -# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK) -#else -# define machine_is_lubbock() (0) -#endif - -#ifdef CONFIG_ARCH_CLEP7212 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLEP7212 -# endif -# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212) -#else -# define machine_is_clep7212() (0) -#endif - -#ifdef CONFIG_SA1100_SHANNON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHANNON -# endif -# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON) -#else -# define machine_is_shannon() (0) -#endif - -#ifdef CONFIG_SA1100_CONSUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONSUS -# endif -# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS) -#else -# define machine_is_consus() (0) -#endif - -#ifdef CONFIG_ARCH_AAED2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AAED2000 -# endif -# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000) -#else -# define machine_is_aaed2000() (0) -#endif - -#ifdef CONFIG_ARCH_CDB89712 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CDB89712 -# endif -# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712) -#else -# define machine_is_cdb89712() (0) -#endif - -#ifdef CONFIG_SA1100_GRAPHICSMASTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GRAPHICSMASTER -# endif -# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER) -#else -# define machine_is_graphicsmaster() (0) -#endif - -#ifdef CONFIG_SA1100_ADSBITSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSBITSY -# endif -# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY) -#else -# define machine_is_adsbitsy() (0) -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXA_IDP -# endif -# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP) -#else -# define machine_is_pxa_idp() (0) -#endif - -#ifdef CONFIG_SA1100_PT_SYSTEM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PT_SYSTEM3 -# endif -# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3) -#else -# define machine_is_pt_system3() (0) -#endif - -#ifdef CONFIG_ARCH_AUTCPU12 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUTCPU12 -# endif -# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12) -#else -# define machine_is_autcpu12() (0) -#endif - -#ifdef CONFIG_SA1100_H3100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H3100 -# endif -# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100) -#else -# define machine_is_h3100() (0) -#endif - -#ifdef CONFIG_SA1100_COLLIE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLLIE -# endif -# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE) -#else -# define machine_is_collie() (0) -#endif - -#ifdef CONFIG_SA1100_BADGE4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BADGE4 -# endif -# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4) -#else -# define machine_is_badge4() (0) -#endif - -#ifdef CONFIG_ARCH_FORTUNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FORTUNET -# endif -# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET) -#else -# define machine_is_fortunet() (0) -#endif - -#ifdef CONFIG_ARCH_MX1ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX1ADS -# endif -# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS) -#else -# define machine_is_mx1ads() (0) -#endif - -#ifdef CONFIG_ARCH_H7201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7201 -# endif -# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201) -#else -# define machine_is_h7201() (0) -#endif - -#ifdef CONFIG_ARCH_H7202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H7202 -# endif -# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202) -#else -# define machine_is_h7202() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80321 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80321 -# endif -# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321) -#else -# define machine_is_iq80321() (0) -#endif - -#ifdef CONFIG_ARCH_KS8695 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KS8695 -# endif -# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695) -#else -# define machine_is_ks8695() (0) -#endif - -#ifdef CONFIG_ARCH_SMDK2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2410 -# endif -# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410) -#else -# define machine_is_smdk2410() (0) -#endif - -#ifdef CONFIG_ARCH_CEIVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CEIVA -# endif -# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA) -#else -# define machine_is_ceiva() (0) -#endif - -#ifdef CONFIG_MACH_VOICEBLUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VOICEBLUE -# endif -# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE) -#else -# define machine_is_voiceblue() (0) -#endif - -#ifdef CONFIG_ARCH_H5400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H5400 -# endif -# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400) -#else -# define machine_is_h5400() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_INNOVATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR -# endif -# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR) -#else -# define machine_is_omap_innovator() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2400 -# endif -# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400) -#else -# define machine_is_ixdp2400() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2800 -# endif -# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800) -#else -# define machine_is_ixdp2800() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP425 -# endif -# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425) -#else -# define machine_is_ixdp425() (0) -#endif - -#ifdef CONFIG_SA1100_HACKKIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HACKKIT -# endif -# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT) -#else -# define machine_is_hackkit() (0) -#endif - -#ifdef CONFIG_ARCH_IXCDP1100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXCDP1100 -# endif -# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100) -#else -# define machine_is_ixcdp1100() (0) -#endif - -#ifdef CONFIG_ARCH_AT91RM9200DK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200DK -# endif -# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK) -#else -# define machine_is_at91rm9200dk() (0) -#endif - -#ifdef CONFIG_ARCH_CINTEGRATOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CINTEGRATOR -# endif -# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR) -#else -# define machine_is_cintegrator() (0) -#endif - -#ifdef CONFIG_ARCH_VIPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIPER -# endif -# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER) -#else -# define machine_is_viper() (0) -#endif - -#ifdef CONFIG_ARCH_ADI_COYOTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADI_COYOTE -# endif -# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE) -#else -# define machine_is_adi_coyote() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2401 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2401 -# endif -# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401) -#else -# define machine_is_ixdp2401() (0) -#endif - -#ifdef CONFIG_ARCH_IXDP2801 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2801 -# endif -# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801) -#else -# define machine_is_ixdp2801() (0) -#endif - -#ifdef CONFIG_ARCH_IQ31244 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ31244 -# endif -# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244) -#else -# define machine_is_iq31244() (0) -#endif - -#ifdef CONFIG_ARCH_BAST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BAST -# endif -# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST) -#else -# define machine_is_bast() (0) -#endif - -#ifdef CONFIG_ARCH_H1940 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1940 -# endif -# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940) -#else -# define machine_is_h1940() (0) -#endif - -#ifdef CONFIG_ARCH_ENP2611 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENP2611 -# endif -# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611) -#else -# define machine_is_enp2611() (0) -#endif - -#ifdef CONFIG_ARCH_S3C2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2440 -# endif -# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440) -#else -# define machine_is_s3c2440() (0) -#endif - -#ifdef CONFIG_ARCH_GUMSTIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUMSTIX -# endif -# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX) -#else -# define machine_is_gumstix() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H2 -# endif -# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2) -#else -# define machine_is_omap_h2() (0) -#endif - -#ifdef CONFIG_MACH_E740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E740 -# endif -# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740) -#else -# define machine_is_e740() (0) -#endif - -#ifdef CONFIG_ARCH_IQ80331 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80331 -# endif -# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331) -#else -# define machine_is_iq80331() (0) -#endif - -#ifdef CONFIG_ARCH_VERSATILE_PB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_PB -# endif -# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB) -#else -# define machine_is_versatile_pb() (0) -#endif - -#ifdef CONFIG_MACH_KEV7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KEV7A400 -# endif -# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400) -#else -# define machine_is_kev7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A400 -# endif -# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400) -#else -# define machine_is_lpd7a400() (0) -#endif - -#ifdef CONFIG_MACH_LPD7A404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPD7A404 -# endif -# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404) -#else -# define machine_is_lpd7a404() (0) -#endif - -#ifdef CONFIG_MACH_CSB337 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB337 -# endif -# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337) -#else -# define machine_is_csb337() (0) -#endif - -#ifdef CONFIG_MACH_MAINSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAINSTONE -# endif -# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE) -#else -# define machine_is_mainstone() (0) -#endif - -#ifdef CONFIG_MACH_XCEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XCEP -# endif -# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP) -#else -# define machine_is_xcep() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_VULCAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_VULCAN -# endif -# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) -#else -# define machine_is_arcom_vulcan() (0) -#endif - -#ifdef CONFIG_MACH_NOMADIK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOMADIK -# endif -# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK) -#else -# define machine_is_nomadik() (0) -#endif - -#ifdef CONFIG_MACH_CORGI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORGI -# endif -# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI) -#else -# define machine_is_corgi() (0) -#endif - -#ifdef CONFIG_MACH_POODLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POODLE -# endif -# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE) -#else -# define machine_is_poodle() (0) -#endif - -#ifdef CONFIG_MACH_ARMCORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMCORE -# endif -# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE) -#else -# define machine_is_armcore() (0) -#endif - -#ifdef CONFIG_MACH_MX31ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31ADS -# endif -# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) -#else -# define machine_is_mx31ads() (0) -#endif - -#ifdef CONFIG_MACH_HIMALAYA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HIMALAYA -# endif -# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA) -#else -# define machine_is_himalaya() (0) -#endif - -#ifdef CONFIG_MACH_EDB9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9312 -# endif -# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312) -#else -# define machine_is_edb9312() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_GENERIC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_GENERIC -# endif -# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC) -#else -# define machine_is_omap_generic() (0) -#endif - -#ifdef CONFIG_MACH_EDB9301 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9301 -# endif -# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301) -#else -# define machine_is_edb9301() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315 -# endif -# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315) -#else -# define machine_is_edb9315() (0) -#endif - -#ifdef CONFIG_MACH_VR1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VR1000 -# endif -# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000) -#else -# define machine_is_vr1000() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2 -# endif -# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2) -#else -# define machine_is_omap_perseus2() (0) -#endif - -#ifdef CONFIG_MACH_E800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E800 -# endif -# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800) -#else -# define machine_is_e800() (0) -#endif - -#ifdef CONFIG_MACH_E750 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E750 -# endif -# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750) -#else -# define machine_is_e750() (0) -#endif - -#ifdef CONFIG_MACH_SCB9328 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCB9328 -# endif -# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328) -#else -# define machine_is_scb9328() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H3 -# endif -# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3) -#else -# define machine_is_omap_h3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_H4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_H4 -# endif -# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4) -#else -# define machine_is_omap_h4() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_OSK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_OSK -# endif -# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK) -#else -# define machine_is_omap_osk() (0) -#endif - -#ifdef CONFIG_MACH_TOSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOSA -# endif -# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA) -#else -# define machine_is_tosa() (0) -#endif - -#ifdef CONFIG_MACH_AVILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVILA -# endif -# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA) -#else -# define machine_is_avila() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302 -# endif -# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302) -#else -# define machine_is_edb9302() (0) -#endif - -#ifdef CONFIG_MACH_HUSKY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUSKY -# endif -# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY) -#else -# define machine_is_husky() (0) -#endif - -#ifdef CONFIG_MACH_SHEPHERD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEPHERD -# endif -# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD) -#else -# define machine_is_shepherd() (0) -#endif - -#ifdef CONFIG_MACH_H4700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H4700 -# endif -# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700) -#else -# define machine_is_h4700() (0) -#endif - -#ifdef CONFIG_MACH_RX3715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX3715 -# endif -# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715) -#else -# define machine_is_rx3715() (0) -#endif - -#ifdef CONFIG_MACH_NSLU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSLU2 -# endif -# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2) -#else -# define machine_is_nslu2() (0) -#endif - -#ifdef CONFIG_MACH_E400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E400 -# endif -# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400) -#else -# define machine_is_e400() (0) -#endif - -#ifdef CONFIG_MACH_IXDPG425 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDPG425 -# endif -# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425) -#else -# define machine_is_ixdpg425() (0) -#endif - -#ifdef CONFIG_MACH_VERSATILE_AB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERSATILE_AB -# endif -# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB) -#else -# define machine_is_versatile_ab() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307 -# endif -# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307) -#else -# define machine_is_edb9307() (0) -#endif - -#ifdef CONFIG_MACH_KB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KB9200 -# endif -# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200) -#else -# define machine_is_kb9200() (0) -#endif - -#ifdef CONFIG_MACH_SX1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SX1 -# endif -# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1) -#else -# define machine_is_sx1() (0) -#endif - -#ifdef CONFIG_MACH_IXDP465 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP465 -# endif -# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465) -#else -# define machine_is_ixdp465() (0) -#endif - -#ifdef CONFIG_MACH_IXDP2351 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP2351 -# endif -# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351) -#else -# define machine_is_ixdp2351() (0) -#endif - -#ifdef CONFIG_MACH_IQ80332 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ80332 -# endif -# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332) -#else -# define machine_is_iq80332() (0) -#endif - -#ifdef CONFIG_MACH_GTWX5715 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTWX5715 -# endif -# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715) -#else -# define machine_is_gtwx5715() (0) -#endif - -#ifdef CONFIG_MACH_CSB637 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB637 -# endif -# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637) -#else -# define machine_is_csb637() (0) -#endif - -#ifdef CONFIG_MACH_N30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N30 -# endif -# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30) -#else -# define machine_is_n30() (0) -#endif - -#ifdef CONFIG_MACH_NEC_MP900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEC_MP900 -# endif -# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900) -#else -# define machine_is_nec_mp900() (0) -#endif - -#ifdef CONFIG_MACH_KAFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KAFA -# endif -# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA) -#else -# define machine_is_kafa() (0) -#endif - -#ifdef CONFIG_MACH_TS72XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS72XX -# endif -# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX) -#else -# define machine_is_ts72xx() (0) -#endif - -#ifdef CONFIG_MACH_OTOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OTOM -# endif -# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM) -#else -# define machine_is_otom() (0) -#endif - -#ifdef CONFIG_MACH_NEXCODER_2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEXCODER_2440 -# endif -# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440) -#else -# define machine_is_nexcoder_2440() (0) -#endif - -#ifdef CONFIG_MACH_ECO920 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECO920 -# endif -# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920) -#else -# define machine_is_eco920() (0) -#endif - -#ifdef CONFIG_MACH_ROADRUNNER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROADRUNNER -# endif -# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER) -#else -# define machine_is_roadrunner() (0) -#endif - -#ifdef CONFIG_MACH_AT91RM9200EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91RM9200EK -# endif -# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK) -#else -# define machine_is_at91rm9200ek() (0) -#endif - -#ifdef CONFIG_MACH_SPITZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPITZ -# endif -# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ) -#else -# define machine_is_spitz() (0) -#endif - -#ifdef CONFIG_MACH_ADSSPHERE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADSSPHERE -# endif -# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE) -#else -# define machine_is_adssphere() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI -# endif -# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) -#else -# define machine_is_colibri() (0) -#endif - -#ifdef CONFIG_MACH_GATEWAY7001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GATEWAY7001 -# endif -# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) -#else -# define machine_is_gateway7001() (0) -#endif - -#ifdef CONFIG_MACH_PCM027 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM027 -# endif -# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) -#else -# define machine_is_pcm027() (0) -#endif - -#ifdef CONFIG_MACH_ANUBIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANUBIS -# endif -# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) -#else -# define machine_is_anubis() (0) -#endif - -#ifdef CONFIG_MACH_AKITA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AKITA -# endif -# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) -#else -# define machine_is_akita() (0) -#endif - -#ifdef CONFIG_MACH_E330 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E330 -# endif -# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) -#else -# define machine_is_e330() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA770 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA770 -# endif -# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) -#else -# define machine_is_nokia770() (0) -#endif - -#ifdef CONFIG_MACH_CARMEVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARMEVA -# endif -# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) -#else -# define machine_is_carmeva() (0) -#endif - -#ifdef CONFIG_MACH_EDB9315A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9315A -# endif -# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) -#else -# define machine_is_edb9315a() (0) -#endif - -#ifdef CONFIG_MACH_STARGATE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STARGATE2 -# endif -# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) -#else -# define machine_is_stargate2() (0) -#endif - -#ifdef CONFIG_MACH_INTELMOTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INTELMOTE2 -# endif -# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) -#else -# define machine_is_intelmote2() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4 -# endif -# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) -#else -# define machine_is_trizeps4() (0) -#endif - -#ifdef CONFIG_MACH_PNX4008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PNX4008 -# endif -# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) -#else -# define machine_is_pnx4008() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT91 -# endif -# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) -#else -# define machine_is_cpuat91() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340SC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340SC -# endif -# define machine_is_iq81340sc() (machine_arch_type == MACH_TYPE_IQ81340SC) -#else -# define machine_is_iq81340sc() (0) -#endif - -#ifdef CONFIG_MACH_IQ81340MC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IQ81340MC -# endif -# define machine_is_iq81340mc() (machine_arch_type == MACH_TYPE_IQ81340MC) -#else -# define machine_is_iq81340mc() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9 -# endif -# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) -#else -# define machine_is_micro9() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9L -# endif -# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) -#else -# define machine_is_micro9l() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTE -# endif -# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) -#else -# define machine_is_omap_palmte() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_EB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_EB -# endif -# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) -#else -# define machine_is_realview_eb() (0) -#endif - -#ifdef CONFIG_MACH_BORZOI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BORZOI -# endif -# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) -#else -# define machine_is_borzoi() (0) -#endif - -#ifdef CONFIG_MACH_PALMLD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMLD -# endif -# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD) -#else -# define machine_is_palmld() (0) -#endif - -#ifdef CONFIG_MACH_IXDP28X5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IXDP28X5 -# endif -# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) -#else -# define machine_is_ixdp28x5() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMTT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMTT -# endif -# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) -#else -# define machine_is_omap_palmtt() (0) -#endif - -#ifdef CONFIG_MACH_ARCOM_ZEUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARCOM_ZEUS -# endif -# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) -#else -# define machine_is_arcom_zeus() (0) -#endif - -#ifdef CONFIG_MACH_OSIRIS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSIRIS -# endif -# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) -#else -# define machine_is_osiris() (0) -#endif - -#ifdef CONFIG_MACH_PALMTE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTE2 -# endif -# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2) -#else -# define machine_is_palmte2() (0) -#endif - -#ifdef CONFIG_MACH_MX27ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27ADS -# endif -# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27ADS) -#else -# define machine_is_mx27ads() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9261EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9261EK -# endif -# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) -#else -# define machine_is_at91sam9261ek() (0) -#endif - -#ifdef CONFIG_MACH_LOFT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOFT -# endif -# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) -#else -# define machine_is_loft() (0) -#endif - -#ifdef CONFIG_MACH_MX21ADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX21ADS -# endif -# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21ADS) -#else -# define machine_is_mx21ads() (0) -#endif - -#ifdef CONFIG_MACH_AMS_DELTA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMS_DELTA -# endif -# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) -#else -# define machine_is_ams_delta() (0) -#endif - -#ifdef CONFIG_MACH_NAS100D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS100D -# endif -# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) -#else -# define machine_is_nas100d() (0) -#endif - -#ifdef CONFIG_MACH_MAGICIAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGICIAN -# endif -# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) -#else -# define machine_is_magician() (0) -#endif - -#ifdef CONFIG_MACH_NXDKN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDKN -# endif -# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) -#else -# define machine_is_nxdkn() (0) -#endif - -#ifdef CONFIG_MACH_PALMTX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTX -# endif -# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX) -#else -# define machine_is_palmtx() (0) -#endif - -#ifdef CONFIG_MACH_S3C2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S3C2413 -# endif -# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) -#else -# define machine_is_s3c2413() (0) -#endif - -#ifdef CONFIG_MACH_WG302V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WG302V2 -# endif -# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) -#else -# define machine_is_wg302v2() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_2430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_2430SDP -# endif -# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) -#else -# define machine_is_omap_2430sdp() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_EVM -# endif -# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) -#else -# define machine_is_davinci_evm() (0) -#endif - -#ifdef CONFIG_MACH_PALMZ72 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMZ72 -# endif -# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) -#else -# define machine_is_palmz72() (0) -#endif - -#ifdef CONFIG_MACH_NXDB500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXDB500 -# endif -# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) -#else -# define machine_is_nxdb500() (0) -#endif - -#ifdef CONFIG_MACH_PALMT5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMT5 -# endif -# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5) -#else -# define machine_is_palmt5() (0) -#endif - -#ifdef CONFIG_MACH_PALMTC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PALMTC -# endif -# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC) -#else -# define machine_is_palmtc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_APOLLON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_APOLLON -# endif -# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) -#else -# define machine_is_omap_apollon() (0) -#endif - -#ifdef CONFIG_MACH_ATEB9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATEB9200 -# endif -# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) -#else -# define machine_is_ateb9200() (0) -#endif - -#ifdef CONFIG_MACH_N35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N35 -# endif -# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) -#else -# define machine_is_n35() (0) -#endif - -#ifdef CONFIG_MACH_LOGICPD_PXA270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 -# endif -# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) -#else -# define machine_is_logicpd_pxa270() (0) -#endif - -#ifdef CONFIG_MACH_NXEB500HMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NXEB500HMI -# endif -# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) -#else -# define machine_is_nxeb500hmi() (0) -#endif - -#ifdef CONFIG_MACH_ESPRESSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESPRESSO -# endif -# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) -#else -# define machine_is_espresso() (0) -#endif - -#ifdef CONFIG_MACH_RX1950 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RX1950 -# endif -# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) -#else -# define machine_is_rx1950() (0) -#endif - -#ifdef CONFIG_MACH_GESBC9312 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GESBC9312 -# endif -# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) -#else -# define machine_is_gesbc9312() (0) -#endif - -#ifdef CONFIG_MACH_PICOTUX2XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOTUX2XX -# endif -# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) -#else -# define machine_is_picotux2xx() (0) -#endif - -#ifdef CONFIG_MACH_DSMG600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSMG600 -# endif -# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) -#else -# define machine_is_dsmg600() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_FSAMPLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE -# endif -# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) -#else -# define machine_is_omap_fsample() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_CL15 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_CL15 -# endif -# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) -#else -# define machine_is_snapper_cl15() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_PALMZ71 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 -# endif -# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) -#else -# define machine_is_omap_palmz71() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2412 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2412 -# endif -# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) -#else -# define machine_is_smdk2412() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2413 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2413 -# endif -# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) -#else -# define machine_is_smdk2413() (0) -#endif - -#ifdef CONFIG_MACH_AML_M5900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AML_M5900 -# endif -# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) -#else -# define machine_is_aml_m5900() (0) -#endif - -#ifdef CONFIG_MACH_BALLOON3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BALLOON3 -# endif -# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) -#else -# define machine_is_balloon3() (0) -#endif - -#ifdef CONFIG_MACH_ECBAT91 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECBAT91 -# endif -# define machine_is_ecbat91() (machine_arch_type == MACH_TYPE_ECBAT91) -#else -# define machine_is_ecbat91() (0) -#endif - -#ifdef CONFIG_MACH_ONEARM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ONEARM -# endif -# define machine_is_onearm() (machine_arch_type == MACH_TYPE_ONEARM) -#else -# define machine_is_onearm() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2443 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2443 -# endif -# define machine_is_smdk2443() (machine_arch_type == MACH_TYPE_SMDK2443) -#else -# define machine_is_smdk2443() (0) -#endif - -#ifdef CONFIG_MACH_FSG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FSG -# endif -# define machine_is_fsg() (machine_arch_type == MACH_TYPE_FSG) -#else -# define machine_is_fsg() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9260EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9260EK -# endif -# define machine_is_at91sam9260ek() (machine_arch_type == MACH_TYPE_AT91SAM9260EK) -#else -# define machine_is_at91sam9260ek() (0) -#endif - -#ifdef CONFIG_MACH_GLANTANK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GLANTANK -# endif -# define machine_is_glantank() (machine_arch_type == MACH_TYPE_GLANTANK) -#else -# define machine_is_glantank() (0) -#endif - -#ifdef CONFIG_MACH_N2100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_N2100 -# endif -# define machine_is_n2100() (machine_arch_type == MACH_TYPE_N2100) -#else -# define machine_is_n2100() (0) -#endif - -#ifdef CONFIG_MACH_QT2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QT2410 -# endif -# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410) -#else -# define machine_is_qt2410() (0) -#endif - -#ifdef CONFIG_MACH_KIXRP435 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KIXRP435 -# endif -# define machine_is_kixrp435() (machine_arch_type == MACH_TYPE_KIXRP435) -#else -# define machine_is_kixrp435() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360DEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360DEV -# endif -# define machine_is_cc9p9360dev() (machine_arch_type == MACH_TYPE_CC9P9360DEV) -#else -# define machine_is_cc9p9360dev() (0) -#endif - -#ifdef CONFIG_MACH_EDB9302A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9302A -# endif -# define machine_is_edb9302a() (machine_arch_type == MACH_TYPE_EDB9302A) -#else -# define machine_is_edb9302a() (0) -#endif - -#ifdef CONFIG_MACH_EDB9307A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDB9307A -# endif -# define machine_is_edb9307a() (machine_arch_type == MACH_TYPE_EDB9307A) -#else -# define machine_is_edb9307a() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3430SDP -# endif -# define machine_is_omap_3430sdp() (machine_arch_type == MACH_TYPE_OMAP_3430SDP) -#else -# define machine_is_omap_3430sdp() (0) -#endif - -#ifdef CONFIG_MACH_VSTMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VSTMS -# endif -# define machine_is_vstms() (machine_arch_type == MACH_TYPE_VSTMS) -#else -# define machine_is_vstms() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9M -# endif -# define machine_is_micro9m() (machine_arch_type == MACH_TYPE_MICRO9M) -#else -# define machine_is_micro9m() (0) -#endif - -#ifdef CONFIG_MACH_BUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUG -# endif -# define machine_is_bug() (machine_arch_type == MACH_TYPE_BUG) -#else -# define machine_is_bug() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263EK -# endif -# define machine_is_at91sam9263ek() (machine_arch_type == MACH_TYPE_AT91SAM9263EK) -#else -# define machine_is_at91sam9263ek() (0) -#endif - -#ifdef CONFIG_MACH_EM7210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM7210 -# endif -# define machine_is_em7210() (machine_arch_type == MACH_TYPE_EM7210) -#else -# define machine_is_em7210() (0) -#endif - -#ifdef CONFIG_MACH_VPAC270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPAC270 -# endif -# define machine_is_vpac270() (machine_arch_type == MACH_TYPE_VPAC270) -#else -# define machine_is_vpac270() (0) -#endif - -#ifdef CONFIG_MACH_TREO680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TREO680 -# endif -# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680) -#else -# define machine_is_treo680() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE -# endif -# define machine_is_zylonite() (machine_arch_type == MACH_TYPE_ZYLONITE) -#else -# define machine_is_zylonite() (0) -#endif - -#ifdef CONFIG_MACH_MX31LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31LITE -# endif -# define machine_is_mx31lite() (machine_arch_type == MACH_TYPE_MX31LITE) -#else -# define machine_is_mx31lite() (0) -#endif - -#ifdef CONFIG_MACH_MIOA701 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA701 -# endif -# define machine_is_mioa701() (machine_arch_type == MACH_TYPE_MIOA701) -#else -# define machine_is_mioa701() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO5X0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO5X0 -# endif -# define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0) -#else -# define machine_is_armadillo5x0() (0) -#endif - -#ifdef CONFIG_MACH_CC9P9360JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CC9P9360JS -# endif -# define machine_is_cc9p9360js() (machine_arch_type == MACH_TYPE_CC9P9360JS) -#else -# define machine_is_cc9p9360js() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N800 -# endif -# define machine_is_nokia_n800() (machine_arch_type == MACH_TYPE_NOKIA_N800) -#else -# define machine_is_nokia_n800() (0) -#endif - -#ifdef CONFIG_MACH_EP80219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EP80219 -# endif -# define machine_is_ep80219() (machine_arch_type == MACH_TYPE_EP80219) -#else -# define machine_is_ep80219() (0) -#endif - -#ifdef CONFIG_MACH_GORAMO_MLR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GORAMO_MLR -# endif -# define machine_is_goramo_mlr() (machine_arch_type == MACH_TYPE_GORAMO_MLR) -#else -# define machine_is_goramo_mlr() (0) -#endif - -#ifdef CONFIG_MACH_EM_X270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM_X270 -# endif -# define machine_is_em_x270() (machine_arch_type == MACH_TYPE_EM_X270) -#else -# define machine_is_em_x270() (0) -#endif - -#ifdef CONFIG_MACH_NEO1973_GTA02 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEO1973_GTA02 -# endif -# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02) -#else -# define machine_is_neo1973_gta02() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9RLEK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9RLEK -# endif -# define machine_is_at91sam9rlek() (machine_arch_type == MACH_TYPE_AT91SAM9RLEK) -#else -# define machine_is_at91sam9rlek() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI320 -# endif -# define machine_is_colibri320() (machine_arch_type == MACH_TYPE_COLIBRI320) -#else -# define machine_is_colibri320() (0) -#endif - -#ifdef CONFIG_MACH_CAM60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAM60 -# endif -# define machine_is_cam60() (machine_arch_type == MACH_TYPE_CAM60) -#else -# define machine_is_cam60() (0) -#endif - -#ifdef CONFIG_MACH_AT91EB01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91EB01 -# endif -# define machine_is_at91eb01() (machine_arch_type == MACH_TYPE_AT91EB01) -#else -# define machine_is_at91eb01() (0) -#endif - -#ifdef CONFIG_MACH_DB88F5281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F5281 -# endif -# define machine_is_db88f5281() (machine_arch_type == MACH_TYPE_DB88F5281) -#else -# define machine_is_db88f5281() (0) -#endif - -#ifdef CONFIG_MACH_CSB726 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSB726 -# endif -# define machine_is_csb726() (machine_arch_type == MACH_TYPE_CSB726) -#else -# define machine_is_csb726() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467_EVM -# endif -# define machine_is_davinci_dm6467_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM) -#else -# define machine_is_davinci_dm6467_evm() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM355_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM -# endif -# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) -#else -# define machine_is_davinci_dm355_evm() (0) -#endif - -#ifdef CONFIG_MACH_LITTLETON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LITTLETON -# endif -# define machine_is_littleton() (machine_arch_type == MACH_TYPE_LITTLETON) -#else -# define machine_is_littleton() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB11MP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB11MP -# endif -# define machine_is_realview_pb11mp() (machine_arch_type == MACH_TYPE_REALVIEW_PB11MP) -#else -# define machine_is_realview_pb11mp() (0) -#endif - -#ifdef CONFIG_MACH_MX27_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27_3DS -# endif -# define machine_is_mx27_3ds() (machine_arch_type == MACH_TYPE_MX27_3DS) -#else -# define machine_is_mx27_3ds() (0) -#endif - -#ifdef CONFIG_MACH_HALIBUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HALIBUT -# endif -# define machine_is_halibut() (machine_arch_type == MACH_TYPE_HALIBUT) -#else -# define machine_is_halibut() (0) -#endif - -#ifdef CONFIG_MACH_TROUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TROUT -# endif -# define machine_is_trout() (machine_arch_type == MACH_TYPE_TROUT) -#else -# define machine_is_trout() (0) -#endif - -#ifdef CONFIG_MACH_TCT_HAMMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCT_HAMMER -# endif -# define machine_is_tct_hammer() (machine_arch_type == MACH_TYPE_TCT_HAMMER) -#else -# define machine_is_tct_hammer() (0) -#endif - -#ifdef CONFIG_MACH_HERALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERALD -# endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) -#else -# define machine_is_herald() (0) -#endif - -#ifdef CONFIG_MACH_SIM_ONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIM_ONE -# endif -# define machine_is_sim_one() (machine_arch_type == MACH_TYPE_SIM_ONE) -#else -# define machine_is_sim_one() (0) -#endif - -#ifdef CONFIG_MACH_JIVE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JIVE -# endif -# define machine_is_jive() (machine_arch_type == MACH_TYPE_JIVE) -#else -# define machine_is_jive() (0) -#endif - -#ifdef CONFIG_MACH_SAM9_L9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9_L9260 -# endif -# define machine_is_sam9_l9260() (machine_arch_type == MACH_TYPE_SAM9_L9260) -#else -# define machine_is_sam9_l9260() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PB1176 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PB1176 -# endif -# define machine_is_realview_pb1176() (machine_arch_type == MACH_TYPE_REALVIEW_PB1176) -#else -# define machine_is_realview_pb1176() (0) -#endif - -#ifdef CONFIG_MACH_YL9200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YL9200 -# endif -# define machine_is_yl9200() (machine_arch_type == MACH_TYPE_YL9200) -#else -# define machine_is_yl9200() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5182 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5182 -# endif -# define machine_is_rd88f5182() (machine_arch_type == MACH_TYPE_RD88F5182) -#else -# define machine_is_rd88f5182() (0) -#endif - -#ifdef CONFIG_MACH_KUROBOX_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KUROBOX_PRO -# endif -# define machine_is_kurobox_pro() (machine_arch_type == MACH_TYPE_KUROBOX_PRO) -#else -# define machine_is_kurobox_pro() (0) -#endif - -#ifdef CONFIG_MACH_MX31_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31_3DS -# endif -# define machine_is_mx31_3ds() (machine_arch_type == MACH_TYPE_MX31_3DS) -#else -# define machine_is_mx31_3ds() (0) -#endif - -#ifdef CONFIG_MACH_QONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QONG -# endif -# define machine_is_qong() (machine_arch_type == MACH_TYPE_QONG) -#else -# define machine_is_qong() (0) -#endif - -#ifdef CONFIG_MACH_OMAP2EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP2EVM -# endif -# define machine_is_omap2evm() (machine_arch_type == MACH_TYPE_OMAP2EVM) -#else -# define machine_is_omap2evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3EVM -# endif -# define machine_is_omap3evm() (machine_arch_type == MACH_TYPE_OMAP3EVM) -#else -# define machine_is_omap3evm() (0) -#endif - -#ifdef CONFIG_MACH_DNS323 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DNS323 -# endif -# define machine_is_dns323() (machine_arch_type == MACH_TYPE_DNS323) -#else -# define machine_is_dns323() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BEAGLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BEAGLE -# endif -# define machine_is_omap3_beagle() (machine_arch_type == MACH_TYPE_OMAP3_BEAGLE) -#else -# define machine_is_omap3_beagle() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810 -# endif -# define machine_is_nokia_n810() (machine_arch_type == MACH_TYPE_NOKIA_N810) -#else -# define machine_is_nokia_n810() (0) -#endif - -#ifdef CONFIG_MACH_PCM038 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM038 -# endif -# define machine_is_pcm038() (machine_arch_type == MACH_TYPE_PCM038) -#else -# define machine_is_pcm038() (0) -#endif - -#ifdef CONFIG_MACH_TS209 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS209 -# endif -# define machine_is_ts_x09() (machine_arch_type == MACH_TYPE_TS209) -#else -# define machine_is_ts_x09() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP9ADK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP9ADK -# endif -# define machine_is_at91cap9adk() (machine_arch_type == MACH_TYPE_AT91CAP9ADK) -#else -# define machine_is_at91cap9adk() (0) -#endif - -#ifdef CONFIG_MACH_MX31MOBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX31MOBOARD -# endif -# define machine_is_mx31moboard() (machine_arch_type == MACH_TYPE_MX31MOBOARD) -#else -# define machine_is_mx31moboard() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_PRO2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_PRO2 -# endif -# define machine_is_terastation_pro2() (machine_arch_type == MACH_TYPE_TERASTATION_PRO2) -#else -# define machine_is_terastation_pro2() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_PRO -# endif -# define machine_is_linkstation_pro() (machine_arch_type == MACH_TYPE_LINKSTATION_PRO) -#else -# define machine_is_linkstation_pro() (0) -#endif - -#ifdef CONFIG_MACH_E350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E350 -# endif -# define machine_is_e350() (machine_arch_type == MACH_TYPE_E350) -#else -# define machine_is_e350() (0) -#endif - -#ifdef CONFIG_MACH_TS409 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS409 -# endif -# define machine_is_ts409() (machine_arch_type == MACH_TYPE_TS409) -#else -# define machine_is_ts409() (0) -#endif - -#ifdef CONFIG_MACH_CM_X300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_X300 -# endif -# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300) -#else -# define machine_is_cm_x300() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK -# endif -# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) -#else -# define machine_is_at91sam9g20ek() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6410 -# endif -# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410) -#else -# define machine_is_smdk6410() (0) -#endif - -#ifdef CONFIG_MACH_U300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U300 -# endif -# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300) -#else -# define machine_is_u300() (0) -#endif - -#ifdef CONFIG_MACH_WRT350N_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WRT350N_V2 -# endif -# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2) -#else -# define machine_is_wrt350n_v2() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_LDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_LDP -# endif -# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP) -#else -# define machine_is_omap_ldp() (0) -#endif - -#ifdef CONFIG_MACH_MX35_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX35_3DS -# endif -# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS) -#else -# define machine_is_mx35_3ds() (0) -#endif - -#ifdef CONFIG_MACH_NEUROS_OSD2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEUROS_OSD2 -# endif -# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) -#else -# define machine_is_neuros_osd2() (0) -#endif - -#ifdef CONFIG_MACH_TRIZEPS4WL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIZEPS4WL -# endif -# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL) -#else -# define machine_is_trizeps4wl() (0) -#endif - -#ifdef CONFIG_MACH_TS78XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS78XX -# endif -# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX) -#else -# define machine_is_ts78xx() (0) -#endif - -#ifdef CONFIG_MACH_SFFSDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFFSDR -# endif -# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) -#else -# define machine_is_sffsdr() (0) -#endif - -#ifdef CONFIG_MACH_PCM037 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM037 -# endif -# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037) -#else -# define machine_is_pcm037() (0) -#endif - -#ifdef CONFIG_MACH_DB88F6281_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB88F6281_BP -# endif -# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP) -#else -# define machine_is_db88f6281_bp() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6192_NAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6192_NAS -# endif -# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS) -#else -# define machine_is_rd88f6192_nas() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6281 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6281 -# endif -# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281) -#else -# define machine_is_rd88f6281() (0) -#endif - -#ifdef CONFIG_MACH_DB78X00_BP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DB78X00_BP -# endif -# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP) -#else -# define machine_is_db78x00_bp() (0) -#endif - -#ifdef CONFIG_MACH_SMDK2416 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK2416 -# endif -# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416) -#else -# define machine_is_smdk2416() (0) -#endif - -#ifdef CONFIG_MACH_WBD111 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WBD111 -# endif -# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111) -#else -# define machine_is_wbd111() (0) -#endif - -#ifdef CONFIG_MACH_MV2120 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV2120 -# endif -# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120) -#else -# define machine_is_mv2120() (0) -#endif - -#ifdef CONFIG_MACH_MX51_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_3DS -# endif -# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS) -#else -# define machine_is_mx51_3ds() (0) -#endif - -#ifdef CONFIG_MACH_IMX27LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27LITE -# endif -# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE) -#else -# define machine_is_imx27lite() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9260 -# endif -# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260) -#else -# define machine_is_usb_a9260() (0) -#endif - -#ifdef CONFIG_MACH_USB_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USB_A9263 -# endif -# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263) -#else -# define machine_is_usb_a9263() (0) -#endif - -#ifdef CONFIG_MACH_QIL_A9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QIL_A9260 -# endif -# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260) -#else -# define machine_is_qil_a9260() (0) -#endif - -#ifdef CONFIG_MACH_KZM_ARM11_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KZM_ARM11_01 -# endif -# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01) -#else -# define machine_is_kzm_arm11_01() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_N810_WIMAX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX -# endif -# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX) -#else -# define machine_is_nokia_n810_wimax() (0) -#endif - -#ifdef CONFIG_MACH_SAPPHIRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAPPHIRE -# endif -# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE) -#else -# define machine_is_sapphire() (0) -#endif - -#ifdef CONFIG_MACH_STMP37XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP37XX -# endif -# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX) -#else -# define machine_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_MACH_STMP378X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STMP378X -# endif -# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X) -#else -# define machine_is_stmp378x() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A780 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A780 -# endif -# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780) -#else -# define machine_is_ezx_a780() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E680 -# endif -# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680) -#else -# define machine_is_ezx_e680() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A1200 -# endif -# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200) -#else -# define machine_is_ezx_a1200() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E6 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E6 -# endif -# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6) -#else -# define machine_is_ezx_e6() (0) -#endif - -#ifdef CONFIG_MACH_EZX_E2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_E2 -# endif -# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2) -#else -# define machine_is_ezx_e2() (0) -#endif - -#ifdef CONFIG_MACH_EZX_A910 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EZX_A910 -# endif -# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910) -#else -# define machine_is_ezx_a910() (0) -#endif - -#ifdef CONFIG_MACH_EDMINI_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDMINI_V2 -# endif -# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2) -#else -# define machine_is_edmini_v2() (0) -#endif - -#ifdef CONFIG_MACH_ZIPIT2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZIPIT2 -# endif -# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2) -#else -# define machine_is_zipit2() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_PANDORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_PANDORA -# endif -# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA) -#else -# define machine_is_omap3_pandora() (0) -#endif - -#ifdef CONFIG_MACH_MSS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSS2 -# endif -# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2) -#else -# define machine_is_mss2() (0) -#endif - -#ifdef CONFIG_MACH_LB88RC8480 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LB88RC8480 -# endif -# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480) -#else -# define machine_is_lb88rc8480() (0) -#endif - -#ifdef CONFIG_MACH_MX25_3DS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX25_3DS -# endif -# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS) -#else -# define machine_is_mx25_3ds() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3530_LV_SOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM -# endif -# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM) -#else -# define machine_is_omap3530_lv_som() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA830_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM -# endif -# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) -#else -# define machine_is_davinci_da830_evm() (0) -#endif - -#ifdef CONFIG_MACH_AT572D940HFEB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT572D940HFEB -# endif -# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) -#else -# define machine_is_at572d940hfek() (0) -#endif - -#ifdef CONFIG_MACH_DOVE_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOVE_DB -# endif -# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) -#else -# define machine_is_dove_db() (0) -#endif - -#ifdef CONFIG_MACH_OVERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OVERO -# endif -# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO) -#else -# define machine_is_overo() (0) -#endif - -#ifdef CONFIG_MACH_AT2440EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT2440EVB -# endif -# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB) -#else -# define machine_is_at2440evb() (0) -#endif - -#ifdef CONFIG_MACH_NEOCORE926 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NEOCORE926 -# endif -# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926) -#else -# define machine_is_neocore926() (0) -#endif - -#ifdef CONFIG_MACH_WNR854T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WNR854T -# endif -# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T) -#else -# define machine_is_wnr854t() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_GE -# endif -# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE) -#else -# define machine_is_rd88f5181l_ge() (0) -#endif - -#ifdef CONFIG_MACH_RD88F5181L_FXO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F5181L_FXO -# endif -# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO) -#else -# define machine_is_rd88f5181l_fxo() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9G20 -# endif -# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20) -#else -# define machine_is_stamp9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC100 -# endif -# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100) -#else -# define machine_is_smdkc100() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB -# endif -# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB) -#else -# define machine_is_tavorevb() (0) -#endif - -#ifdef CONFIG_MACH_SAAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAAR -# endif -# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR) -#else -# define machine_is_saar() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9M10G45EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK -# endif -# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK) -#else -# define machine_is_at91sam9m10g45ek() (0) -#endif - -#ifdef CONFIG_MACH_MXLADS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXLADS -# endif -# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS) -#else -# define machine_is_mxlads() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_MINI -# endif -# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI) -#else -# define machine_is_linkstation_mini() (0) -#endif - -#ifdef CONFIG_MACH_AFEB9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AFEB9260 -# endif -# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260) -#else -# define machine_is_afeb9260() (0) -#endif - -#ifdef CONFIG_MACH_IMX27IPCAM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27IPCAM -# endif -# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM) -#else -# define machine_is_imx27ipcam() (0) -#endif - -#ifdef CONFIG_MACH_RD88F6183AP_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD88F6183AP_GE -# endif -# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) -#else -# define machine_is_rd88f6183ap_ge() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBA8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 -# endif -# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) -#else -# define machine_is_realview_pba8() (0) -#endif - -#ifdef CONFIG_MACH_REALVIEW_PBX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REALVIEW_PBX -# endif -# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) -#else -# define machine_is_realview_pbx() (0) -#endif - -#ifdef CONFIG_MACH_MICRO9S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICRO9S -# endif -# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) -#else -# define machine_is_micro9s() (0) -#endif - -#ifdef CONFIG_MACH_RUT100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUT100 -# endif -# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) -#else -# define machine_is_rut100() (0) -#endif - -#ifdef CONFIG_MACH_G3EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G3EVM -# endif -# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) -#else -# define machine_is_g3evm() (0) -#endif - -#ifdef CONFIG_MACH_W90P910EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P910EVB -# endif -# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) -#else -# define machine_is_w90p910evb() (0) -#endif - -#ifdef CONFIG_MACH_W90P950EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90P950EVB -# endif -# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) -#else -# define machine_is_w90p950evb() (0) -#endif - -#ifdef CONFIG_MACH_W90N960EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W90N960EVB -# endif -# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) -#else -# define machine_is_w90n960evb() (0) -#endif - -#ifdef CONFIG_MACH_MV88F6281GTW_GE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE -# endif -# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) -#else -# define machine_is_mv88f6281gtw_ge() (0) -#endif - -#ifdef CONFIG_MACH_NCP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NCP -# endif -# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) -#else -# define machine_is_ncp() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM365_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM -# endif -# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) -#else -# define machine_is_davinci_dm365_evm() (0) -#endif - -#ifdef CONFIG_MACH_CENTRO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CENTRO -# endif -# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) -#else -# define machine_is_centro() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_RX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_RX51 -# endif -# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) -#else -# define machine_is_nokia_rx51() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 -# endif -# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) -#else -# define machine_is_omap_zoom2() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9260 -# endif -# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) -#else -# define machine_is_cpuat9260() (0) -#endif - -#ifdef CONFIG_MACH_EUKREA_CPUIMX27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX27 -# endif -# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27) -#else -# define machine_is_eukrea_cpuimx27() (0) -#endif - -#ifdef CONFIG_MACH_ACS5K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACS5K -# endif -# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) -#else -# define machine_is_acs5k() (0) -#endif - -#ifdef CONFIG_MACH_SNAPPER_9260 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNAPPER_9260 -# endif -# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) -#else -# define machine_is_snapper_9260() (0) -#endif - -#ifdef CONFIG_MACH_DSM320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DSM320 -# endif -# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) -#else -# define machine_is_dsm320() (0) -#endif - -#ifdef CONFIG_MACH_EXEDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXEDA -# endif -# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) -#else -# define machine_is_exeda() (0) -#endif - -#ifdef CONFIG_MACH_MINI2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI2440 -# endif -# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) -#else -# define machine_is_mini2440() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI300 -# endif -# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) -#else -# define machine_is_colibri300() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_LS_HGL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL -# endif -# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) -#else -# define machine_is_linkstation_ls_hgl() (0) -#endif - -#ifdef CONFIG_MACH_CPUAT9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPUAT9G20 -# endif -# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20) -#else -# define machine_is_cpuat9g20() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6440 -# endif -# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440) -#else -# define machine_is_smdk6440() (0) -#endif - -#ifdef CONFIG_MACH_NAS4220B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS4220B -# endif -# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B) -#else -# define machine_is_nas4220b() (0) -#endif - -#ifdef CONFIG_MACH_ZYLONITE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZYLONITE2 -# endif -# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2) -#else -# define machine_is_zylonite2() (0) -#endif - -#ifdef CONFIG_MACH_ASPENITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASPENITE -# endif -# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE) -#else -# define machine_is_aspenite() (0) -#endif - -#ifdef CONFIG_MACH_TTC_DKB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TTC_DKB -# endif -# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB) -#else -# define machine_is_ttc_dkb() (0) -#endif - -#ifdef CONFIG_MACH_PCM043 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM043 -# endif -# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043) -#else -# define machine_is_pcm043() (0) -#endif - -#ifdef CONFIG_MACH_SHEEVAPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHEEVAPLUG -# endif -# define machine_is_sheevaplug() (machine_arch_type == MACH_TYPE_SHEEVAPLUG) -#else -# define machine_is_sheevaplug() (0) -#endif - -#ifdef CONFIG_MACH_AVENGERS_LITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AVENGERS_LITE -# endif -# define machine_is_avengers_lite() (machine_arch_type == MACH_TYPE_AVENGERS_LITE) -#else -# define machine_is_avengers_lite() (0) -#endif - -#ifdef CONFIG_MACH_MX51_BABBAGE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_BABBAGE -# endif -# define machine_is_mx51_babbage() (machine_arch_type == MACH_TYPE_MX51_BABBAGE) -#else -# define machine_is_mx51_babbage() (0) -#endif - -#ifdef CONFIG_MACH_RD78X00_MASA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RD78X00_MASA -# endif -# define machine_is_rd78x00_masa() (machine_arch_type == MACH_TYPE_RD78X00_MASA) -#else -# define machine_is_rd78x00_masa() (0) -#endif - -#ifdef CONFIG_MACH_DM355_LEOPARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM355_LEOPARD -# endif -# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD) -#else -# define machine_is_dm355_leopard() (0) -#endif - -#ifdef CONFIG_MACH_TS219 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS219 -# endif -# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219) -#else -# define machine_is_ts219() (0) -#endif - -#ifdef CONFIG_MACH_PCA100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCA100 -# endif -# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100) -#else -# define machine_is_pca100() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DA850_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM -# endif -# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) -#else -# define machine_is_davinci_da850_evm() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G10EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G10EK -# endif -# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK) -#else -# define machine_is_at91sam9g10ek() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_4430SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_4430SDP -# endif -# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP) -#else -# define machine_is_omap_4430sdp() (0) -#endif - -#ifdef CONFIG_MACH_MAGX_ZN5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAGX_ZN5 -# endif -# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5) -#else -# define machine_is_magx_zn5() (0) -#endif - -#ifdef CONFIG_MACH_BTMAVB101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMAVB101 -# endif -# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101) -#else -# define machine_is_btmavb101() (0) -#endif - -#ifdef CONFIG_MACH_BTMAWB101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BTMAWB101 -# endif -# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101) -#else -# define machine_is_btmawb101() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_TORPEDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO -# endif -# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO) -#else -# define machine_is_omap3_torpedo() (0) -#endif - -#ifdef CONFIG_MACH_ANW6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANW6410 -# endif -# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410) -#else -# define machine_is_anw6410() (0) -#endif - -#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10 -# endif -# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10) -#else -# define machine_is_imx27_visstrim_m10() (0) -#endif - -#ifdef CONFIG_MACH_PORTUXG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PORTUXG20 -# endif -# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20) -#else -# define machine_is_portuxg20() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC110 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC110 -# endif -# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110) -#else -# define machine_is_smdkc110() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3517EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3517EVM -# endif -# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM) -#else -# define machine_is_omap3517evm() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_V2 -# endif -# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2) -#else -# define machine_is_netspace_v2() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_MAX_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2 -# endif -# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2) -#else -# define machine_is_netspace_max_v2() (0) -#endif - -#ifdef CONFIG_MACH_D2NET_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2NET_V2 -# endif -# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2) -#else -# define machine_is_d2net_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG_V2 -# endif -# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2) -#else -# define machine_is_net2big_v2() (0) -#endif - -#ifdef CONFIG_MACH_NET5BIG_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET5BIG_V2 -# endif -# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2) -#else -# define machine_is_net5big_v2() (0) -#endif - -#ifdef CONFIG_MACH_INETSPACE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INETSPACE_V2 -# endif -# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2) -#else -# define machine_is_inetspace_v2() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G45EKES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES -# endif -# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES) -#else -# define machine_is_at91sam9g45ekes() (0) -#endif - -#ifdef CONFIG_MACH_PC7302 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7302 -# endif -# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302) -#else -# define machine_is_pc7302() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR600 -# endif -# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600) -#else -# define machine_is_spear600() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR300 -# endif -# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300) -#else -# define machine_is_spear300() (0) -#endif - -#ifdef CONFIG_MACH_LILLY1131 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LILLY1131 -# endif -# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131) -#else -# define machine_is_lilly1131() (0) -#endif - -#ifdef CONFIG_MACH_HMT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HMT -# endif -# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT) -#else -# define machine_is_hmt() (0) -#endif - -#ifdef CONFIG_MACH_VEXPRESS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VEXPRESS -# endif -# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) -#else -# define machine_is_vexpress() (0) -#endif - -#ifdef CONFIG_MACH_D2NET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2NET -# endif -# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) -#else -# define machine_is_d2net() (0) -#endif - -#ifdef CONFIG_MACH_BIGDISK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIGDISK -# endif -# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) -#else -# define machine_is_bigdisk() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC -# endif -# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) -#else -# define machine_is_at91sam9g20ek_2mmc() (0) -#endif - -#ifdef CONFIG_MACH_BCMRING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMRING -# endif -# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) -#else -# define machine_is_bcmring() (0) -#endif - -#ifdef CONFIG_MACH_DP6XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DP6XX -# endif -# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) -#else -# define machine_is_dp6xx() (0) -#endif - -#ifdef CONFIG_MACH_MAHIMAHI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAHIMAHI -# endif -# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) -#else -# define machine_is_mahimahi() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6442 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6442 -# endif -# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) -#else -# define machine_is_smdk6442() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_BASE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_BASE -# endif -# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) -#else -# define machine_is_openrd_base() (0) -#endif - -#ifdef CONFIG_MACH_DEVKIT8000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEVKIT8000 -# endif -# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) -#else -# define machine_is_devkit8000() (0) -#endif - -#ifdef CONFIG_MACH_MX51_EFIKAMX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_EFIKAMX -# endif -# define machine_is_mx51_efikamx() (machine_arch_type == MACH_TYPE_MX51_EFIKAMX) -#else -# define machine_is_mx51_efikamx() (0) -#endif - -#ifdef CONFIG_MACH_CM_T35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_T35 -# endif -# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) -#else -# define machine_is_cm_t35() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG -# endif -# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) -#else -# define machine_is_net2big() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0020 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0020 -# endif -# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) -#else -# define machine_is_igep0020() (0) -#endif - -#ifdef CONFIG_MACH_NUC932EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC932EVB -# endif -# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) -#else -# define machine_is_nuc932evb() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_CLIENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_CLIENT -# endif -# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) -#else -# define machine_is_openrd_client() (0) -#endif - -#ifdef CONFIG_MACH_U8500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U8500 -# endif -# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) -#else -# define machine_is_u8500() (0) -#endif - -#ifdef CONFIG_MACH_MX51_EFIKASB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_EFIKASB -# endif -# define machine_is_mx51_efikasb() (machine_arch_type == MACH_TYPE_MX51_EFIKASB) -#else -# define machine_is_mx51_efikasb() (0) -#endif - -#ifdef CONFIG_MACH_MARVELL_JASPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELL_JASPER -# endif -# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) -#else -# define machine_is_marvell_jasper() (0) -#endif - -#ifdef CONFIG_MACH_FLINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLINT -# endif -# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) -#else -# define machine_is_flint() (0) -#endif - -#ifdef CONFIG_MACH_TAVOREVB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAVOREVB3 -# endif -# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) -#else -# define machine_is_tavorevb3() (0) -#endif - -#ifdef CONFIG_MACH_TOUCHBOOK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOUCHBOOK -# endif -# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) -#else -# define machine_is_touchbook() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_RC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_RC -# endif -# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) -#else -# define machine_is_raumfeld_rc() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR -# endif -# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) -#else -# define machine_is_raumfeld_connector() (0) -#endif - -#ifdef CONFIG_MACH_RAUMFELD_SPEAKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER -# endif -# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) -#else -# define machine_is_raumfeld_speaker() (0) -#endif - -#ifdef CONFIG_MACH_TNETV107X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNETV107X -# endif -# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) -#else -# define machine_is_tnetv107x() (0) -#endif - -#ifdef CONFIG_MACH_SMDKV210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKV210 -# endif -# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) -#else -# define machine_is_smdkv210() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_ZOOM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 -# endif -# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) -#else -# define machine_is_omap_zoom3() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_3630SDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_3630SDP -# endif -# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) -#else -# define machine_is_omap_3630sdp() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQ7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQ7 -# endif -# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) -#else -# define machine_is_smartq7() (0) -#endif - -#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN -# endif -# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) -#else -# define machine_is_watson_efm_plugin() (0) -#endif - -#ifdef CONFIG_MACH_G4EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_G4EVM -# endif -# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) -#else -# define machine_is_g4evm() (0) -#endif - -#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD -# endif -# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) -#else -# define machine_is_omapl138_hawkboard() (0) -#endif - -#ifdef CONFIG_MACH_TS41X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS41X -# endif -# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) -#else -# define machine_is_ts41x() (0) -#endif - -#ifdef CONFIG_MACH_PHY3250 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHY3250 -# endif -# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) -#else -# define machine_is_phy3250() (0) -#endif - -#ifdef CONFIG_MACH_MINI6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI6410 -# endif -# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) -#else -# define machine_is_mini6410() (0) -#endif - -#ifdef CONFIG_MACH_MX28EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX28EVK -# endif -# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) -#else -# define machine_is_mx28evk() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQ5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQ5 -# endif -# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) -#else -# define machine_is_smartq5() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM -# endif -# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) -#else -# define machine_is_davinci_dm6467tevm() (0) -#endif - -#ifdef CONFIG_MACH_MXT_TD60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXT_TD60 -# endif -# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) -#else -# define machine_is_mxt_td60() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_BEI2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_BEI2 -# endif -# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) -#else -# define machine_is_riot_bei2() (0) -#endif - -#ifdef CONFIG_MACH_RIOT_X37 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIOT_X37 -# endif -# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) -#else -# define machine_is_riot_x37() (0) -#endif - -#ifdef CONFIG_MACH_CAPC7117 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAPC7117 -# endif -# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) -#else -# define machine_is_capc7117() (0) -#endif - -#ifdef CONFIG_MACH_ICONTROL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONTROL -# endif -# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) -#else -# define machine_is_icontrol() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50A_ST1_5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 -# endif -# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) -#else -# define machine_is_qsd8x50a_st1_5() (0) -#endif - -#ifdef CONFIG_MACH_MX23EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX23EVK -# endif -# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) -#else -# define machine_is_mx23evk() (0) -#endif - -#ifdef CONFIG_MACH_AP4EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AP4EVB -# endif -# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) -#else -# define machine_is_ap4evb() (0) -#endif - -#ifdef CONFIG_MACH_MITYOMAPL138 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MITYOMAPL138 -# endif -# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) -#else -# define machine_is_mityomapl138() (0) -#endif - -#ifdef CONFIG_MACH_GURUPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURUPLUG -# endif -# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) -#else -# define machine_is_guruplug() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR310 -# endif -# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) -#else -# define machine_is_spear310() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR320 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR320 -# endif -# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) -#else -# define machine_is_spear320() (0) -#endif - -#ifdef CONFIG_MACH_AQUILA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AQUILA -# endif -# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) -#else -# define machine_is_aquila() (0) -#endif - -#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG -# endif -# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) -#else -# define machine_is_sheeva_esata() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X30_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X30_SURF -# endif -# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF) -#else -# define machine_is_msm7x30_surf() (0) -#endif - -#ifdef CONFIG_MACH_EA2478DEVKIT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EA2478DEVKIT -# endif -# define machine_is_ea2478devkit() (machine_arch_type == MACH_TYPE_EA2478DEVKIT) -#else -# define machine_is_ea2478devkit() (0) -#endif - -#ifdef CONFIG_MACH_TERASTATION_WXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERASTATION_WXL -# endif -# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) -#else -# define machine_is_terastation_wxl() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X25_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X25_SURF -# endif -# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) -#else -# define machine_is_msm7x25_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X25_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X25_FFA -# endif -# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) -#else -# define machine_is_msm7x25_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27_SURF -# endif -# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) -#else -# define machine_is_msm7x27_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27_FFA -# endif -# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) -#else -# define machine_is_msm7x27_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X30_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X30_FFA -# endif -# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) -#else -# define machine_is_msm7x30_ffa() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X50_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X50_SURF -# endif -# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) -#else -# define machine_is_qsd8x50_surf() (0) -#endif - -#ifdef CONFIG_MACH_MX53_EVK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX53_EVK -# endif -# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) -#else -# define machine_is_mx53_evk() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0030 -# endif -# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) -#else -# define machine_is_igep0030() (0) -#endif - -#ifdef CONFIG_MACH_SBC3530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC3530 -# endif -# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530) -#else -# define machine_is_sbc3530() (0) -#endif - -#ifdef CONFIG_MACH_SAARB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAARB -# endif -# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB) -#else -# define machine_is_saarb() (0) -#endif - -#ifdef CONFIG_MACH_HARMONY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HARMONY -# endif -# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY) -#else -# define machine_is_harmony() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X30_FLUID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X30_FLUID -# endif -# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID) -#else -# define machine_is_msm7x30_fluid() (0) -#endif - -#ifdef CONFIG_MACH_CM_T3517 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_T3517 -# endif -# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517) -#else -# define machine_is_cm_t3517() (0) -#endif - -#ifdef CONFIG_MACH_WBD222 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WBD222 -# endif -# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222) -#else -# define machine_is_wbd222() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_SURF -# endif -# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF) -#else -# define machine_is_msm8x60_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_SIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_SIM -# endif -# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM) -#else -# define machine_is_msm8x60_sim() (0) -#endif - -#ifdef CONFIG_MACH_TCC8000_SDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TCC8000_SDK -# endif -# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK) -#else -# define machine_is_tcc8000_sdk() (0) -#endif - -#ifdef CONFIG_MACH_NANOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOS -# endif -# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS) -#else -# define machine_is_nanos() (0) -#endif - -#ifdef CONFIG_MACH_STAMP9G45 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STAMP9G45 -# endif -# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45) -#else -# define machine_is_stamp9g45() (0) -#endif - -#ifdef CONFIG_MACH_CNS3420VB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNS3420VB -# endif -# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB) -#else -# define machine_is_cns3420vb() (0) -#endif - -#ifdef CONFIG_MACH_OMAP4_PANDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP4_PANDA -# endif -# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA) -#else -# define machine_is_omap4_panda() (0) -#endif - -#ifdef CONFIG_MACH_TI8168EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI8168EVM -# endif -# define machine_is_ti8168evm() (machine_arch_type == MACH_TYPE_TI8168EVM) -#else -# define machine_is_ti8168evm() (0) -#endif - -#ifdef CONFIG_MACH_TETON_BGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TETON_BGA -# endif -# define machine_is_teton_bga() (machine_arch_type == MACH_TYPE_TETON_BGA) -#else -# define machine_is_teton_bga() (0) -#endif - -#ifdef CONFIG_MACH_EUKREA_CPUIMX25SD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX25SD -# endif -# define machine_is_eukrea_cpuimx25sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25SD) -#else -# define machine_is_eukrea_cpuimx25sd() (0) -#endif - -#ifdef CONFIG_MACH_EUKREA_CPUIMX35SD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX35SD -# endif -# define machine_is_eukrea_cpuimx35sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35SD) -#else -# define machine_is_eukrea_cpuimx35sd() (0) -#endif - -#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51SD -# endif -# define machine_is_eukrea_cpuimx51sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD) -#else -# define machine_is_eukrea_cpuimx51sd() (0) -#endif - -#ifdef CONFIG_MACH_EUKREA_CPUIMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51 -# endif -# define machine_is_eukrea_cpuimx51() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51) -#else -# define machine_is_eukrea_cpuimx51() (0) -#endif - -#ifdef CONFIG_MACH_SMDKC210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKC210 -# endif -# define machine_is_smdkc210() (machine_arch_type == MACH_TYPE_SMDKC210) -#else -# define machine_is_smdkc210() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BRAILLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BRAILLO -# endif -# define machine_is_omap3_braillo() (machine_arch_type == MACH_TYPE_OMAP3_BRAILLO) -#else -# define machine_is_omap3_braillo() (0) -#endif - -#ifdef CONFIG_MACH_SPYPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPYPLUG -# endif -# define machine_is_spyplug() (machine_arch_type == MACH_TYPE_SPYPLUG) -#else -# define machine_is_spyplug() (0) -#endif - -#ifdef CONFIG_MACH_GINGER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GINGER -# endif -# define machine_is_ginger() (machine_arch_type == MACH_TYPE_GINGER) -#else -# define machine_is_ginger() (0) -#endif - -#ifdef CONFIG_MACH_TNY_T3530 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TNY_T3530 -# endif -# define machine_is_tny_t3530() (machine_arch_type == MACH_TYPE_TNY_T3530) -#else -# define machine_is_tny_t3530() (0) -#endif - -#ifdef CONFIG_MACH_PCA102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCA102 -# endif -# define machine_is_pca102() (machine_arch_type == MACH_TYPE_PCA102) -#else -# define machine_is_pca102() (0) -#endif - -#ifdef CONFIG_MACH_SPADE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPADE -# endif -# define machine_is_spade() (machine_arch_type == MACH_TYPE_SPADE) -#else -# define machine_is_spade() (0) -#endif - -#ifdef CONFIG_MACH_MXC25_TOPAZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXC25_TOPAZ -# endif -# define machine_is_mxc25_topaz() (machine_arch_type == MACH_TYPE_MXC25_TOPAZ) -#else -# define machine_is_mxc25_topaz() (0) -#endif - -#ifdef CONFIG_MACH_T5325 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T5325 -# endif -# define machine_is_t5325() (machine_arch_type == MACH_TYPE_T5325) -#else -# define machine_is_t5325() (0) -#endif - -#ifdef CONFIG_MACH_GW2361 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GW2361 -# endif -# define machine_is_gw2361() (machine_arch_type == MACH_TYPE_GW2361) -#else -# define machine_is_gw2361() (0) -#endif - -#ifdef CONFIG_MACH_ELOG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELOG -# endif -# define machine_is_elog() (machine_arch_type == MACH_TYPE_ELOG) -#else -# define machine_is_elog() (0) -#endif - -#ifdef CONFIG_MACH_INCOME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INCOME -# endif -# define machine_is_income() (machine_arch_type == MACH_TYPE_INCOME) -#else -# define machine_is_income() (0) -#endif - -#ifdef CONFIG_MACH_BCM589X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM589X -# endif -# define machine_is_bcm589x() (machine_arch_type == MACH_TYPE_BCM589X) -#else -# define machine_is_bcm589x() (0) -#endif - -#ifdef CONFIG_MACH_ETNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETNA -# endif -# define machine_is_etna() (machine_arch_type == MACH_TYPE_ETNA) -#else -# define machine_is_etna() (0) -#endif - -#ifdef CONFIG_MACH_HAWKS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAWKS -# endif -# define machine_is_hawks() (machine_arch_type == MACH_TYPE_HAWKS) -#else -# define machine_is_hawks() (0) -#endif - -#ifdef CONFIG_MACH_MESON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MESON -# endif -# define machine_is_meson() (machine_arch_type == MACH_TYPE_MESON) -#else -# define machine_is_meson() (0) -#endif - -#ifdef CONFIG_MACH_XSBASE255 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XSBASE255 -# endif -# define machine_is_xsbase255() (machine_arch_type == MACH_TYPE_XSBASE255) -#else -# define machine_is_xsbase255() (0) -#endif - -#ifdef CONFIG_MACH_PVM2030 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PVM2030 -# endif -# define machine_is_pvm2030() (machine_arch_type == MACH_TYPE_PVM2030) -#else -# define machine_is_pvm2030() (0) -#endif - -#ifdef CONFIG_MACH_MIOA502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOA502 -# endif -# define machine_is_mioa502() (machine_arch_type == MACH_TYPE_MIOA502) -#else -# define machine_is_mioa502() (0) -#endif - -#ifdef CONFIG_MACH_VVBOX_SDORIG2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVBOX_SDORIG2 -# endif -# define machine_is_vvbox_sdorig2() (machine_arch_type == MACH_TYPE_VVBOX_SDORIG2) -#else -# define machine_is_vvbox_sdorig2() (0) -#endif - -#ifdef CONFIG_MACH_VVBOX_SDLITE2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVBOX_SDLITE2 -# endif -# define machine_is_vvbox_sdlite2() (machine_arch_type == MACH_TYPE_VVBOX_SDLITE2) -#else -# define machine_is_vvbox_sdlite2() (0) -#endif - -#ifdef CONFIG_MACH_VVBOX_SDPRO4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VVBOX_SDPRO4 -# endif -# define machine_is_vvbox_sdpro4() (machine_arch_type == MACH_TYPE_VVBOX_SDPRO4) -#else -# define machine_is_vvbox_sdpro4() (0) -#endif - -#ifdef CONFIG_MACH_HTC_SPV_M700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_SPV_M700 -# endif -# define machine_is_htc_spv_m700() (machine_arch_type == MACH_TYPE_HTC_SPV_M700) -#else -# define machine_is_htc_spv_m700() (0) -#endif - -#ifdef CONFIG_MACH_MX257SX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX257SX -# endif -# define machine_is_mx257sx() (machine_arch_type == MACH_TYPE_MX257SX) -#else -# define machine_is_mx257sx() (0) -#endif - -#ifdef CONFIG_MACH_GONI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GONI -# endif -# define machine_is_goni() (machine_arch_type == MACH_TYPE_GONI) -#else -# define machine_is_goni() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_FFA -# endif -# define machine_is_msm8x55_svlte_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA) -#else -# define machine_is_msm8x55_svlte_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_SURF -# endif -# define machine_is_msm8x55_svlte_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF) -#else -# define machine_is_msm8x55_svlte_surf() (0) -#endif - -#ifdef CONFIG_MACH_QUICKSTEP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUICKSTEP -# endif -# define machine_is_quickstep() (machine_arch_type == MACH_TYPE_QUICKSTEP) -#else -# define machine_is_quickstep() (0) -#endif - -#ifdef CONFIG_MACH_DMW96 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DMW96 -# endif -# define machine_is_dmw96() (machine_arch_type == MACH_TYPE_DMW96) -#else -# define machine_is_dmw96() (0) -#endif - -#ifdef CONFIG_MACH_HAMMERHEAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HAMMERHEAD -# endif -# define machine_is_hammerhead() (machine_arch_type == MACH_TYPE_HAMMERHEAD) -#else -# define machine_is_hammerhead() (0) -#endif - -#ifdef CONFIG_MACH_TRIDENT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIDENT -# endif -# define machine_is_trident() (machine_arch_type == MACH_TYPE_TRIDENT) -#else -# define machine_is_trident() (0) -#endif - -#ifdef CONFIG_MACH_LIGHTNING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIGHTNING -# endif -# define machine_is_lightning() (machine_arch_type == MACH_TYPE_LIGHTNING) -#else -# define machine_is_lightning() (0) -#endif - -#ifdef CONFIG_MACH_ICONNECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONNECT -# endif -# define machine_is_iconnect() (machine_arch_type == MACH_TYPE_ICONNECT) -#else -# define machine_is_iconnect() (0) -#endif - -#ifdef CONFIG_MACH_AUTOBOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AUTOBOT -# endif -# define machine_is_autobot() (machine_arch_type == MACH_TYPE_AUTOBOT) -#else -# define machine_is_autobot() (0) -#endif - -#ifdef CONFIG_MACH_COCONUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COCONUT -# endif -# define machine_is_coconut() (machine_arch_type == MACH_TYPE_COCONUT) -#else -# define machine_is_coconut() (0) -#endif - -#ifdef CONFIG_MACH_DURIAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DURIAN -# endif -# define machine_is_durian() (machine_arch_type == MACH_TYPE_DURIAN) -#else -# define machine_is_durian() (0) -#endif - -#ifdef CONFIG_MACH_CAYENNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CAYENNE -# endif -# define machine_is_cayenne() (machine_arch_type == MACH_TYPE_CAYENNE) -#else -# define machine_is_cayenne() (0) -#endif - -#ifdef CONFIG_MACH_FUJI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FUJI -# endif -# define machine_is_fuji() (machine_arch_type == MACH_TYPE_FUJI) -#else -# define machine_is_fuji() (0) -#endif - -#ifdef CONFIG_MACH_SYNOLOGY_6282 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYNOLOGY_6282 -# endif -# define machine_is_synology_6282() (machine_arch_type == MACH_TYPE_SYNOLOGY_6282) -#else -# define machine_is_synology_6282() (0) -#endif - -#ifdef CONFIG_MACH_EM1SY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EM1SY -# endif -# define machine_is_em1sy() (machine_arch_type == MACH_TYPE_EM1SY) -#else -# define machine_is_em1sy() (0) -#endif - -#ifdef CONFIG_MACH_M502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_M502 -# endif -# define machine_is_m502() (machine_arch_type == MACH_TYPE_M502) -#else -# define machine_is_m502() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX518 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX518 -# endif -# define machine_is_matrix518() (machine_arch_type == MACH_TYPE_MATRIX518) -#else -# define machine_is_matrix518() (0) -#endif - -#ifdef CONFIG_MACH_TINY_GURNARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TINY_GURNARD -# endif -# define machine_is_tiny_gurnard() (machine_arch_type == MACH_TYPE_TINY_GURNARD) -#else -# define machine_is_tiny_gurnard() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR1310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR1310 -# endif -# define machine_is_spear1310() (machine_arch_type == MACH_TYPE_SPEAR1310) -#else -# define machine_is_spear1310() (0) -#endif - -#ifdef CONFIG_MACH_BV07 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BV07 -# endif -# define machine_is_bv07() (machine_arch_type == MACH_TYPE_BV07) -#else -# define machine_is_bv07() (0) -#endif - -#ifdef CONFIG_MACH_MXT_TD61 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MXT_TD61 -# endif -# define machine_is_mxt_td61() (machine_arch_type == MACH_TYPE_MXT_TD61) -#else -# define machine_is_mxt_td61() (0) -#endif - -#ifdef CONFIG_MACH_OPENRD_ULTIMATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OPENRD_ULTIMATE -# endif -# define machine_is_openrd_ultimate() (machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE) -#else -# define machine_is_openrd_ultimate() (0) -#endif - -#ifdef CONFIG_MACH_DEVIXP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEVIXP -# endif -# define machine_is_devixp() (machine_arch_type == MACH_TYPE_DEVIXP) -#else -# define machine_is_devixp() (0) -#endif - -#ifdef CONFIG_MACH_MICCPT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MICCPT -# endif -# define machine_is_miccpt() (machine_arch_type == MACH_TYPE_MICCPT) -#else -# define machine_is_miccpt() (0) -#endif - -#ifdef CONFIG_MACH_MIC256 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIC256 -# endif -# define machine_is_mic256() (machine_arch_type == MACH_TYPE_MIC256) -#else -# define machine_is_mic256() (0) -#endif - -#ifdef CONFIG_MACH_AS1167 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AS1167 -# endif -# define machine_is_as1167() (machine_arch_type == MACH_TYPE_AS1167) -#else -# define machine_is_as1167() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_IBIZA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_IBIZA -# endif -# define machine_is_omap3_ibiza() (machine_arch_type == MACH_TYPE_OMAP3_IBIZA) -#else -# define machine_is_omap3_ibiza() (0) -#endif - -#ifdef CONFIG_MACH_U5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_U5500 -# endif -# define machine_is_u5500() (machine_arch_type == MACH_TYPE_U5500) -#else -# define machine_is_u5500() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_PICTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_PICTO -# endif -# define machine_is_davinci_picto() (machine_arch_type == MACH_TYPE_DAVINCI_PICTO) -#else -# define machine_is_davinci_picto() (0) -#endif - -#ifdef CONFIG_MACH_MECHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MECHA -# endif -# define machine_is_mecha() (machine_arch_type == MACH_TYPE_MECHA) -#else -# define machine_is_mecha() (0) -#endif - -#ifdef CONFIG_MACH_BUBBA3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUBBA3 -# endif -# define machine_is_bubba3() (machine_arch_type == MACH_TYPE_BUBBA3) -#else -# define machine_is_bubba3() (0) -#endif - -#ifdef CONFIG_MACH_PUPITRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUPITRE -# endif -# define machine_is_pupitre() (machine_arch_type == MACH_TYPE_PUPITRE) -#else -# define machine_is_pupitre() (0) -#endif - -#ifdef CONFIG_MACH_TEGRA_VOGUE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEGRA_VOGUE -# endif -# define machine_is_tegra_vogue() (machine_arch_type == MACH_TYPE_TEGRA_VOGUE) -#else -# define machine_is_tegra_vogue() (0) -#endif - -#ifdef CONFIG_MACH_TEGRA_E1165 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEGRA_E1165 -# endif -# define machine_is_tegra_e1165() (machine_arch_type == MACH_TYPE_TEGRA_E1165) -#else -# define machine_is_tegra_e1165() (0) -#endif - -#ifdef CONFIG_MACH_SIMPLENET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMPLENET -# endif -# define machine_is_simplenet() (machine_arch_type == MACH_TYPE_SIMPLENET) -#else -# define machine_is_simplenet() (0) -#endif - -#ifdef CONFIG_MACH_EC4350TBM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EC4350TBM -# endif -# define machine_is_ec4350tbm() (machine_arch_type == MACH_TYPE_EC4350TBM) -#else -# define machine_is_ec4350tbm() (0) -#endif - -#ifdef CONFIG_MACH_PEC_TC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEC_TC -# endif -# define machine_is_pec_tc() (machine_arch_type == MACH_TYPE_PEC_TC) -#else -# define machine_is_pec_tc() (0) -#endif - -#ifdef CONFIG_MACH_PEC_HC2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEC_HC2 -# endif -# define machine_is_pec_hc2() (machine_arch_type == MACH_TYPE_PEC_HC2) -#else -# define machine_is_pec_hc2() (0) -#endif - -#ifdef CONFIG_MACH_ESL_MOBILIS_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_MOBILIS_A -# endif -# define machine_is_esl_mobilis_a() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_A) -#else -# define machine_is_esl_mobilis_a() (0) -#endif - -#ifdef CONFIG_MACH_ESL_MOBILIS_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_MOBILIS_B -# endif -# define machine_is_esl_mobilis_b() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_B) -#else -# define machine_is_esl_mobilis_b() (0) -#endif - -#ifdef CONFIG_MACH_ESL_WAVE_A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_WAVE_A -# endif -# define machine_is_esl_wave_a() (machine_arch_type == MACH_TYPE_ESL_WAVE_A) -#else -# define machine_is_esl_wave_a() (0) -#endif - -#ifdef CONFIG_MACH_ESL_WAVE_B -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ESL_WAVE_B -# endif -# define machine_is_esl_wave_b() (machine_arch_type == MACH_TYPE_ESL_WAVE_B) -#else -# define machine_is_esl_wave_b() (0) -#endif - -#ifdef CONFIG_MACH_UNISENSE_MMM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNISENSE_MMM -# endif -# define machine_is_unisense_mmm() (machine_arch_type == MACH_TYPE_UNISENSE_MMM) -#else -# define machine_is_unisense_mmm() (0) -#endif - -#ifdef CONFIG_MACH_BLUESHARK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUESHARK -# endif -# define machine_is_blueshark() (machine_arch_type == MACH_TYPE_BLUESHARK) -#else -# define machine_is_blueshark() (0) -#endif - -#ifdef CONFIG_MACH_E10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_E10 -# endif -# define machine_is_e10() (machine_arch_type == MACH_TYPE_E10) -#else -# define machine_is_e10() (0) -#endif - -#ifdef CONFIG_MACH_APP3K_ROBIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_APP3K_ROBIN -# endif -# define machine_is_app3k_robin() (machine_arch_type == MACH_TYPE_APP3K_ROBIN) -#else -# define machine_is_app3k_robin() (0) -#endif - -#ifdef CONFIG_MACH_POV15HD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POV15HD -# endif -# define machine_is_pov15hd() (machine_arch_type == MACH_TYPE_POV15HD) -#else -# define machine_is_pov15hd() (0) -#endif - -#ifdef CONFIG_MACH_STELLA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STELLA -# endif -# define machine_is_stella() (machine_arch_type == MACH_TYPE_STELLA) -#else -# define machine_is_stella() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_LSCHL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_LSCHL -# endif -# define machine_is_linkstation_lschl() (machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL) -#else -# define machine_is_linkstation_lschl() (0) -#endif - -#ifdef CONFIG_MACH_NETWALKER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETWALKER -# endif -# define machine_is_netwalker() (machine_arch_type == MACH_TYPE_NETWALKER) -#else -# define machine_is_netwalker() (0) -#endif - -#ifdef CONFIG_MACH_ACSX106 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACSX106 -# endif -# define machine_is_acsx106() (machine_arch_type == MACH_TYPE_ACSX106) -#else -# define machine_is_acsx106() (0) -#endif - -#ifdef CONFIG_MACH_ATLAS5_C1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATLAS5_C1 -# endif -# define machine_is_atlas5_c1() (machine_arch_type == MACH_TYPE_ATLAS5_C1) -#else -# define machine_is_atlas5_c1() (0) -#endif - -#ifdef CONFIG_MACH_NSB3AST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSB3AST -# endif -# define machine_is_nsb3ast() (machine_arch_type == MACH_TYPE_NSB3AST) -#else -# define machine_is_nsb3ast() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SLC -# endif -# define machine_is_gnet_slc() (machine_arch_type == MACH_TYPE_GNET_SLC) -#else -# define machine_is_gnet_slc() (0) -#endif - -#ifdef CONFIG_MACH_AF4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AF4000 -# endif -# define machine_is_af4000() (machine_arch_type == MACH_TYPE_AF4000) -#else -# define machine_is_af4000() (0) -#endif - -#ifdef CONFIG_MACH_ARK9431 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARK9431 -# endif -# define machine_is_ark9431() (machine_arch_type == MACH_TYPE_ARK9431) -#else -# define machine_is_ark9431() (0) -#endif - -#ifdef CONFIG_MACH_FS_S5PC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FS_S5PC100 -# endif -# define machine_is_fs_s5pc100() (machine_arch_type == MACH_TYPE_FS_S5PC100) -#else -# define machine_is_fs_s5pc100() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3505NOVA8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3505NOVA8 -# endif -# define machine_is_omap3505nova8() (machine_arch_type == MACH_TYPE_OMAP3505NOVA8) -#else -# define machine_is_omap3505nova8() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3621_EDP1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3621_EDP1 -# endif -# define machine_is_omap3621_edp1() (machine_arch_type == MACH_TYPE_OMAP3621_EDP1) -#else -# define machine_is_omap3621_edp1() (0) -#endif - -#ifdef CONFIG_MACH_ORATISAES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISAES -# endif -# define machine_is_oratisaes() (machine_arch_type == MACH_TYPE_ORATISAES) -#else -# define machine_is_oratisaes() (0) -#endif - -#ifdef CONFIG_MACH_SMDKV310 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDKV310 -# endif -# define machine_is_smdkv310() (machine_arch_type == MACH_TYPE_SMDKV310) -#else -# define machine_is_smdkv310() (0) -#endif - -#ifdef CONFIG_MACH_SIEMENS_L0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIEMENS_L0 -# endif -# define machine_is_siemens_l0() (machine_arch_type == MACH_TYPE_SIEMENS_L0) -#else -# define machine_is_siemens_l0() (0) -#endif - -#ifdef CONFIG_MACH_VENTANA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VENTANA -# endif -# define machine_is_ventana() (machine_arch_type == MACH_TYPE_VENTANA) -#else -# define machine_is_ventana() (0) -#endif - -#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WM8505_7IN_NETBOOK -# endif -# define machine_is_wm8505_7in_netbook() (machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK) -#else -# define machine_is_wm8505_7in_netbook() (0) -#endif - -#ifdef CONFIG_MACH_EC4350SDB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EC4350SDB -# endif -# define machine_is_ec4350sdb() (machine_arch_type == MACH_TYPE_EC4350SDB) -#else -# define machine_is_ec4350sdb() (0) -#endif - -#ifdef CONFIG_MACH_MIMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIMAS -# endif -# define machine_is_mimas() (machine_arch_type == MACH_TYPE_MIMAS) -#else -# define machine_is_mimas() (0) -#endif - -#ifdef CONFIG_MACH_TITAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TITAN -# endif -# define machine_is_titan() (machine_arch_type == MACH_TYPE_TITAN) -#else -# define machine_is_titan() (0) -#endif - -#ifdef CONFIG_MACH_CRANEBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRANEBOARD -# endif -# define machine_is_craneboard() (machine_arch_type == MACH_TYPE_CRANEBOARD) -#else -# define machine_is_craneboard() (0) -#endif - -#ifdef CONFIG_MACH_ES2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ES2440 -# endif -# define machine_is_es2440() (machine_arch_type == MACH_TYPE_ES2440) -#else -# define machine_is_es2440() (0) -#endif - -#ifdef CONFIG_MACH_NAJAY_A9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAJAY_A9263 -# endif -# define machine_is_najay_a9263() (machine_arch_type == MACH_TYPE_NAJAY_A9263) -#else -# define machine_is_najay_a9263() (0) -#endif - -#ifdef CONFIG_MACH_HTCTORNADO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCTORNADO -# endif -# define machine_is_htctornado() (machine_arch_type == MACH_TYPE_HTCTORNADO) -#else -# define machine_is_htctornado() (0) -#endif - -#ifdef CONFIG_MACH_DIMM_MX257 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIMM_MX257 -# endif -# define machine_is_dimm_mx257() (machine_arch_type == MACH_TYPE_DIMM_MX257) -#else -# define machine_is_dimm_mx257() (0) -#endif - -#ifdef CONFIG_MACH_JIGEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JIGEN -# endif -# define machine_is_jigen301() (machine_arch_type == MACH_TYPE_JIGEN) -#else -# define machine_is_jigen301() (0) -#endif - -#ifdef CONFIG_MACH_SMDK6450 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6450 -# endif -# define machine_is_smdk6450() (machine_arch_type == MACH_TYPE_SMDK6450) -#else -# define machine_is_smdk6450() (0) -#endif - -#ifdef CONFIG_MACH_MENO_QNG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MENO_QNG -# endif -# define machine_is_meno_qng() (machine_arch_type == MACH_TYPE_MENO_QNG) -#else -# define machine_is_meno_qng() (0) -#endif - -#ifdef CONFIG_MACH_NS2416 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS2416 -# endif -# define machine_is_ns2416() (machine_arch_type == MACH_TYPE_NS2416) -#else -# define machine_is_ns2416() (0) -#endif - -#ifdef CONFIG_MACH_RPC353 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RPC353 -# endif -# define machine_is_rpc353() (machine_arch_type == MACH_TYPE_RPC353) -#else -# define machine_is_rpc353() (0) -#endif - -#ifdef CONFIG_MACH_TQ6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQ6410 -# endif -# define machine_is_tq6410() (machine_arch_type == MACH_TYPE_TQ6410) -#else -# define machine_is_tq6410() (0) -#endif - -#ifdef CONFIG_MACH_SKY6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKY6410 -# endif -# define machine_is_sky6410() (machine_arch_type == MACH_TYPE_SKY6410) -#else -# define machine_is_sky6410() (0) -#endif - -#ifdef CONFIG_MACH_DYNASTY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DYNASTY -# endif -# define machine_is_dynasty() (machine_arch_type == MACH_TYPE_DYNASTY) -#else -# define machine_is_dynasty() (0) -#endif - -#ifdef CONFIG_MACH_VIVO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIVO -# endif -# define machine_is_vivo() (machine_arch_type == MACH_TYPE_VIVO) -#else -# define machine_is_vivo() (0) -#endif - -#ifdef CONFIG_MACH_BURY_BL7582 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BURY_BL7582 -# endif -# define machine_is_bury_bl7582() (machine_arch_type == MACH_TYPE_BURY_BL7582) -#else -# define machine_is_bury_bl7582() (0) -#endif - -#ifdef CONFIG_MACH_BURY_BPS5270 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BURY_BPS5270 -# endif -# define machine_is_bury_bps5270() (machine_arch_type == MACH_TYPE_BURY_BPS5270) -#else -# define machine_is_bury_bps5270() (0) -#endif - -#ifdef CONFIG_MACH_BASI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BASI -# endif -# define machine_is_basi() (machine_arch_type == MACH_TYPE_BASI) -#else -# define machine_is_basi() (0) -#endif - -#ifdef CONFIG_MACH_TN200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TN200 -# endif -# define machine_is_tn200() (machine_arch_type == MACH_TYPE_TN200) -#else -# define machine_is_tn200() (0) -#endif - -#ifdef CONFIG_MACH_C2MMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_C2MMI -# endif -# define machine_is_c2mmi() (machine_arch_type == MACH_TYPE_C2MMI) -#else -# define machine_is_c2mmi() (0) -#endif - -#ifdef CONFIG_MACH_MESON_6236M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MESON_6236M -# endif -# define machine_is_meson_6236m() (machine_arch_type == MACH_TYPE_MESON_6236M) -#else -# define machine_is_meson_6236m() (0) -#endif - -#ifdef CONFIG_MACH_MESON_8626M -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MESON_8626M -# endif -# define machine_is_meson_8626m() (machine_arch_type == MACH_TYPE_MESON_8626M) -#else -# define machine_is_meson_8626m() (0) -#endif - -#ifdef CONFIG_MACH_TUBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TUBE -# endif -# define machine_is_tube() (machine_arch_type == MACH_TYPE_TUBE) -#else -# define machine_is_tube() (0) -#endif - -#ifdef CONFIG_MACH_MESSINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MESSINA -# endif -# define machine_is_messina() (machine_arch_type == MACH_TYPE_MESSINA) -#else -# define machine_is_messina() (0) -#endif - -#ifdef CONFIG_MACH_MX50_ARM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX50_ARM2 -# endif -# define machine_is_mx50_arm2() (machine_arch_type == MACH_TYPE_MX50_ARM2) -#else -# define machine_is_mx50_arm2() (0) -#endif - -#ifdef CONFIG_MACH_CETUS9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CETUS9263 -# endif -# define machine_is_cetus9263() (machine_arch_type == MACH_TYPE_CETUS9263) -#else -# define machine_is_cetus9263() (0) -#endif - -#ifdef CONFIG_MACH_BROWNSTONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BROWNSTONE -# endif -# define machine_is_brownstone() (machine_arch_type == MACH_TYPE_BROWNSTONE) -#else -# define machine_is_brownstone() (0) -#endif - -#ifdef CONFIG_MACH_VMX25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMX25 -# endif -# define machine_is_vmx25() (machine_arch_type == MACH_TYPE_VMX25) -#else -# define machine_is_vmx25() (0) -#endif - -#ifdef CONFIG_MACH_VMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMX51 -# endif -# define machine_is_vmx51() (machine_arch_type == MACH_TYPE_VMX51) -#else -# define machine_is_vmx51() (0) -#endif - -#ifdef CONFIG_MACH_ABACUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABACUS -# endif -# define machine_is_abacus() (machine_arch_type == MACH_TYPE_ABACUS) -#else -# define machine_is_abacus() (0) -#endif - -#ifdef CONFIG_MACH_CM4745 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM4745 -# endif -# define machine_is_cm4745() (machine_arch_type == MACH_TYPE_CM4745) -#else -# define machine_is_cm4745() (0) -#endif - -#ifdef CONFIG_MACH_ORATISLINK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORATISLINK -# endif -# define machine_is_oratislink() (machine_arch_type == MACH_TYPE_ORATISLINK) -#else -# define machine_is_oratislink() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM365_DVR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM365_DVR -# endif -# define machine_is_davinci_dm365_dvr() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR) -#else -# define machine_is_davinci_dm365_dvr() (0) -#endif - -#ifdef CONFIG_MACH_NETVIZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETVIZ -# endif -# define machine_is_netviz() (machine_arch_type == MACH_TYPE_NETVIZ) -#else -# define machine_is_netviz() (0) -#endif - -#ifdef CONFIG_MACH_FLEXIBITY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLEXIBITY -# endif -# define machine_is_flexibity() (machine_arch_type == MACH_TYPE_FLEXIBITY) -#else -# define machine_is_flexibity() (0) -#endif - -#ifdef CONFIG_MACH_WLAN_COMPUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLAN_COMPUTER -# endif -# define machine_is_wlan_computer() (machine_arch_type == MACH_TYPE_WLAN_COMPUTER) -#else -# define machine_is_wlan_computer() (0) -#endif - -#ifdef CONFIG_MACH_LPC24XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LPC24XX -# endif -# define machine_is_lpc24xx() (machine_arch_type == MACH_TYPE_LPC24XX) -#else -# define machine_is_lpc24xx() (0) -#endif - -#ifdef CONFIG_MACH_SPICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPICA -# endif -# define machine_is_spica() (machine_arch_type == MACH_TYPE_SPICA) -#else -# define machine_is_spica() (0) -#endif - -#ifdef CONFIG_MACH_GPSDISPLAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GPSDISPLAY -# endif -# define machine_is_gpsdisplay() (machine_arch_type == MACH_TYPE_GPSDISPLAY) -#else -# define machine_is_gpsdisplay() (0) -#endif - -#ifdef CONFIG_MACH_BIPNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIPNET -# endif -# define machine_is_bipnet() (machine_arch_type == MACH_TYPE_BIPNET) -#else -# define machine_is_bipnet() (0) -#endif - -#ifdef CONFIG_MACH_OVERO_CTU_INERTIAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OVERO_CTU_INERTIAL -# endif -# define machine_is_overo_ctu_inertial() (machine_arch_type == MACH_TYPE_OVERO_CTU_INERTIAL) -#else -# define machine_is_overo_ctu_inertial() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM355_MMM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM355_MMM -# endif -# define machine_is_davinci_dm355_mmm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_MMM) -#else -# define machine_is_davinci_dm355_mmm() (0) -#endif - -#ifdef CONFIG_MACH_PC9260_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC9260_V2 -# endif -# define machine_is_pc9260_v2() (machine_arch_type == MACH_TYPE_PC9260_V2) -#else -# define machine_is_pc9260_v2() (0) -#endif - -#ifdef CONFIG_MACH_PTX7545 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTX7545 -# endif -# define machine_is_ptx7545() (machine_arch_type == MACH_TYPE_PTX7545) -#else -# define machine_is_ptx7545() (0) -#endif - -#ifdef CONFIG_MACH_TM_EFDC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TM_EFDC -# endif -# define machine_is_tm_efdc() (machine_arch_type == MACH_TYPE_TM_EFDC) -#else -# define machine_is_tm_efdc() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_WALDO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_WALDO1 -# endif -# define machine_is_omap3_waldo1() (machine_arch_type == MACH_TYPE_OMAP3_WALDO1) -#else -# define machine_is_omap3_waldo1() (0) -#endif - -#ifdef CONFIG_MACH_FLYER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FLYER -# endif -# define machine_is_flyer() (machine_arch_type == MACH_TYPE_FLYER) -#else -# define machine_is_flyer() (0) -#endif - -#ifdef CONFIG_MACH_TORNADO3240 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TORNADO3240 -# endif -# define machine_is_tornado3240() (machine_arch_type == MACH_TYPE_TORNADO3240) -#else -# define machine_is_tornado3240() (0) -#endif - -#ifdef CONFIG_MACH_SOLI_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOLI_01 -# endif -# define machine_is_soli_01() (machine_arch_type == MACH_TYPE_SOLI_01) -#else -# define machine_is_soli_01() (0) -#endif - -#ifdef CONFIG_MACH_OMAPL138_EUROPALC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAPL138_EUROPALC -# endif -# define machine_is_omapl138_europalc() (machine_arch_type == MACH_TYPE_OMAPL138_EUROPALC) -#else -# define machine_is_omapl138_europalc() (0) -#endif - -#ifdef CONFIG_MACH_HELIOS_V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HELIOS_V1 -# endif -# define machine_is_helios_v1() (machine_arch_type == MACH_TYPE_HELIOS_V1) -#else -# define machine_is_helios_v1() (0) -#endif - -#ifdef CONFIG_MACH_NETSPACE_LITE_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NETSPACE_LITE_V2 -# endif -# define machine_is_netspace_lite_v2() (machine_arch_type == MACH_TYPE_NETSPACE_LITE_V2) -#else -# define machine_is_netspace_lite_v2() (0) -#endif - -#ifdef CONFIG_MACH_SSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SSC -# endif -# define machine_is_ssc() (machine_arch_type == MACH_TYPE_SSC) -#else -# define machine_is_ssc() (0) -#endif - -#ifdef CONFIG_MACH_PREMIERWAVE_EN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PREMIERWAVE_EN -# endif -# define machine_is_premierwave_en() (machine_arch_type == MACH_TYPE_PREMIERWAVE_EN) -#else -# define machine_is_premierwave_en() (0) -#endif - -#ifdef CONFIG_MACH_WASABI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WASABI -# endif -# define machine_is_wasabi() (machine_arch_type == MACH_TYPE_WASABI) -#else -# define machine_is_wasabi() (0) -#endif - -#ifdef CONFIG_MACH_MX50_RDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX50_RDP -# endif -# define machine_is_mx50_rdp() (machine_arch_type == MACH_TYPE_MX50_RDP) -#else -# define machine_is_mx50_rdp() (0) -#endif - -#ifdef CONFIG_MACH_UNIVERSAL_C210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIVERSAL_C210 -# endif -# define machine_is_universal_c210() (machine_arch_type == MACH_TYPE_UNIVERSAL_C210) -#else -# define machine_is_universal_c210() (0) -#endif - -#ifdef CONFIG_MACH_REAL6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REAL6410 -# endif -# define machine_is_real6410() (machine_arch_type == MACH_TYPE_REAL6410) -#else -# define machine_is_real6410() (0) -#endif - -#ifdef CONFIG_MACH_SPX_SAKURA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPX_SAKURA -# endif -# define machine_is_spx_sakura() (machine_arch_type == MACH_TYPE_SPX_SAKURA) -#else -# define machine_is_spx_sakura() (0) -#endif - -#ifdef CONFIG_MACH_IJ3K_2440 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IJ3K_2440 -# endif -# define machine_is_ij3k_2440() (machine_arch_type == MACH_TYPE_IJ3K_2440) -#else -# define machine_is_ij3k_2440() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BC10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BC10 -# endif -# define machine_is_omap3_bc10() (machine_arch_type == MACH_TYPE_OMAP3_BC10) -#else -# define machine_is_omap3_bc10() (0) -#endif - -#ifdef CONFIG_MACH_THEBE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_THEBE -# endif -# define machine_is_thebe() (machine_arch_type == MACH_TYPE_THEBE) -#else -# define machine_is_thebe() (0) -#endif - -#ifdef CONFIG_MACH_RV082 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RV082 -# endif -# define machine_is_rv082() (machine_arch_type == MACH_TYPE_RV082) -#else -# define machine_is_rv082() (0) -#endif - -#ifdef CONFIG_MACH_ARMLGUEST -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMLGUEST -# endif -# define machine_is_armlguest() (machine_arch_type == MACH_TYPE_ARMLGUEST) -#else -# define machine_is_armlguest() (0) -#endif - -#ifdef CONFIG_MACH_TJINC1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TJINC1000 -# endif -# define machine_is_tjinc1000() (machine_arch_type == MACH_TYPE_TJINC1000) -#else -# define machine_is_tjinc1000() (0) -#endif - -#ifdef CONFIG_MACH_DOCKSTAR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOCKSTAR -# endif -# define machine_is_dockstar() (machine_arch_type == MACH_TYPE_DOCKSTAR) -#else -# define machine_is_dockstar() (0) -#endif - -#ifdef CONFIG_MACH_AX8008 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AX8008 -# endif -# define machine_is_ax8008() (machine_arch_type == MACH_TYPE_AX8008) -#else -# define machine_is_ax8008() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGCE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGCE -# endif -# define machine_is_gnet_sgce() (machine_arch_type == MACH_TYPE_GNET_SGCE) -#else -# define machine_is_gnet_sgce() (0) -#endif - -#ifdef CONFIG_MACH_PXWNAS_500_1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PXWNAS_500_1000 -# endif -# define machine_is_pxwnas_500_1000() (machine_arch_type == MACH_TYPE_PXWNAS_500_1000) -#else -# define machine_is_pxwnas_500_1000() (0) -#endif - -#ifdef CONFIG_MACH_EA20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EA20 -# endif -# define machine_is_ea20() (machine_arch_type == MACH_TYPE_EA20) -#else -# define machine_is_ea20() (0) -#endif - -#ifdef CONFIG_MACH_AWM2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AWM2 -# endif -# define machine_is_awm2() (machine_arch_type == MACH_TYPE_AWM2) -#else -# define machine_is_awm2() (0) -#endif - -#ifdef CONFIG_MACH_TI8148EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TI8148EVM -# endif -# define machine_is_ti8148evm() (machine_arch_type == MACH_TYPE_TI8148EVM) -#else -# define machine_is_ti8148evm() (0) -#endif - -#ifdef CONFIG_MACH_SEABOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SEABOARD -# endif -# define machine_is_seaboard() (machine_arch_type == MACH_TYPE_SEABOARD) -#else -# define machine_is_seaboard() (0) -#endif - -#ifdef CONFIG_MACH_LINKSTATION_CHLV2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LINKSTATION_CHLV2 -# endif -# define machine_is_linkstation_chlv2() (machine_arch_type == MACH_TYPE_LINKSTATION_CHLV2) -#else -# define machine_is_linkstation_chlv2() (0) -#endif - -#ifdef CONFIG_MACH_TERA_PRO2_RACK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TERA_PRO2_RACK -# endif -# define machine_is_tera_pro2_rack() (machine_arch_type == MACH_TYPE_TERA_PRO2_RACK) -#else -# define machine_is_tera_pro2_rack() (0) -#endif - -#ifdef CONFIG_MACH_RUBYS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUBYS -# endif -# define machine_is_rubys() (machine_arch_type == MACH_TYPE_RUBYS) -#else -# define machine_is_rubys() (0) -#endif - -#ifdef CONFIG_MACH_AQUARIUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AQUARIUS -# endif -# define machine_is_aquarius() (machine_arch_type == MACH_TYPE_AQUARIUS) -#else -# define machine_is_aquarius() (0) -#endif - -#ifdef CONFIG_MACH_MX53_ARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX53_ARD -# endif -# define machine_is_mx53_ard() (machine_arch_type == MACH_TYPE_MX53_ARD) -#else -# define machine_is_mx53_ard() (0) -#endif - -#ifdef CONFIG_MACH_MX53_SMD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX53_SMD -# endif -# define machine_is_mx53_smd() (machine_arch_type == MACH_TYPE_MX53_SMD) -#else -# define machine_is_mx53_smd() (0) -#endif - -#ifdef CONFIG_MACH_LSWXL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LSWXL -# endif -# define machine_is_lswxl() (machine_arch_type == MACH_TYPE_LSWXL) -#else -# define machine_is_lswxl() (0) -#endif - -#ifdef CONFIG_MACH_DOVE_AVNG_V3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOVE_AVNG_V3 -# endif -# define machine_is_dove_avng_v3() (machine_arch_type == MACH_TYPE_DOVE_AVNG_V3) -#else -# define machine_is_dove_avng_v3() (0) -#endif - -#ifdef CONFIG_MACH_SDI_ESS_9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SDI_ESS_9263 -# endif -# define machine_is_sdi_ess_9263() (machine_arch_type == MACH_TYPE_SDI_ESS_9263) -#else -# define machine_is_sdi_ess_9263() (0) -#endif - -#ifdef CONFIG_MACH_JOCPU550 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JOCPU550 -# endif -# define machine_is_jocpu550() (machine_arch_type == MACH_TYPE_JOCPU550) -#else -# define machine_is_jocpu550() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_RUMI3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_RUMI3 -# endif -# define machine_is_msm8x60_rumi3() (machine_arch_type == MACH_TYPE_MSM8X60_RUMI3) -#else -# define machine_is_msm8x60_rumi3() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_FFA -# endif -# define machine_is_msm8x60_ffa() (machine_arch_type == MACH_TYPE_MSM8X60_FFA) -#else -# define machine_is_msm8x60_ffa() (0) -#endif - -#ifdef CONFIG_MACH_YANOMAMI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_YANOMAMI -# endif -# define machine_is_yanomami() (machine_arch_type == MACH_TYPE_YANOMAMI) -#else -# define machine_is_yanomami() (0) -#endif - -#ifdef CONFIG_MACH_GTA04 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTA04 -# endif -# define machine_is_gta04() (machine_arch_type == MACH_TYPE_GTA04) -#else -# define machine_is_gta04() (0) -#endif - -#ifdef CONFIG_MACH_CM_A510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_A510 -# endif -# define machine_is_cm_a510() (machine_arch_type == MACH_TYPE_CM_A510) -#else -# define machine_is_cm_a510() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_RFS200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_RFS200 -# endif -# define machine_is_omap3_rfs200() (machine_arch_type == MACH_TYPE_OMAP3_RFS200) -#else -# define machine_is_omap3_rfs200() (0) -#endif - -#ifdef CONFIG_MACH_KX33XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KX33XX -# endif -# define machine_is_kx33xx() (machine_arch_type == MACH_TYPE_KX33XX) -#else -# define machine_is_kx33xx() (0) -#endif - -#ifdef CONFIG_MACH_PTX7510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PTX7510 -# endif -# define machine_is_ptx7510() (machine_arch_type == MACH_TYPE_PTX7510) -#else -# define machine_is_ptx7510() (0) -#endif - -#ifdef CONFIG_MACH_TOP9000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOP9000 -# endif -# define machine_is_top9000() (machine_arch_type == MACH_TYPE_TOP9000) -#else -# define machine_is_top9000() (0) -#endif - -#ifdef CONFIG_MACH_TEENOTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEENOTE -# endif -# define machine_is_teenote() (machine_arch_type == MACH_TYPE_TEENOTE) -#else -# define machine_is_teenote() (0) -#endif - -#ifdef CONFIG_MACH_TS3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS3 -# endif -# define machine_is_ts3() (machine_arch_type == MACH_TYPE_TS3) -#else -# define machine_is_ts3() (0) -#endif - -#ifdef CONFIG_MACH_A0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A0 -# endif -# define machine_is_a0() (machine_arch_type == MACH_TYPE_A0) -#else -# define machine_is_a0() (0) -#endif - -#ifdef CONFIG_MACH_FSM9XXX_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FSM9XXX_SURF -# endif -# define machine_is_fsm9xxx_surf() (machine_arch_type == MACH_TYPE_FSM9XXX_SURF) -#else -# define machine_is_fsm9xxx_surf() (0) -#endif - -#ifdef CONFIG_MACH_FSM9XXX_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FSM9XXX_FFA -# endif -# define machine_is_fsm9xxx_ffa() (machine_arch_type == MACH_TYPE_FSM9XXX_FFA) -#else -# define machine_is_fsm9xxx_ffa() (0) -#endif - -#ifdef CONFIG_MACH_FRRHWCDMA60W -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRRHWCDMA60W -# endif -# define machine_is_frrhwcdma60w() (machine_arch_type == MACH_TYPE_FRRHWCDMA60W) -#else -# define machine_is_frrhwcdma60w() (0) -#endif - -#ifdef CONFIG_MACH_REMUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REMUS -# endif -# define machine_is_remus() (machine_arch_type == MACH_TYPE_REMUS) -#else -# define machine_is_remus() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP7XDK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP7XDK -# endif -# define machine_is_at91cap7xdk() (machine_arch_type == MACH_TYPE_AT91CAP7XDK) -#else -# define machine_is_at91cap7xdk() (0) -#endif - -#ifdef CONFIG_MACH_AT91CAP7STK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91CAP7STK -# endif -# define machine_is_at91cap7stk() (machine_arch_type == MACH_TYPE_AT91CAP7STK) -#else -# define machine_is_at91cap7stk() (0) -#endif - -#ifdef CONFIG_MACH_KT_SBC_SAM9_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KT_SBC_SAM9_1 -# endif -# define machine_is_kt_sbc_sam9_1() (machine_arch_type == MACH_TYPE_KT_SBC_SAM9_1) -#else -# define machine_is_kt_sbc_sam9_1() (0) -#endif - -#ifdef CONFIG_MACH_ARMADA_XP_DB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADA_XP_DB -# endif -# define machine_is_armada_xp_db() (machine_arch_type == MACH_TYPE_ARMADA_XP_DB) -#else -# define machine_is_armada_xp_db() (0) -#endif - -#ifdef CONFIG_MACH_SPDM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPDM -# endif -# define machine_is_spdm() (machine_arch_type == MACH_TYPE_SPDM) -#else -# define machine_is_spdm() (0) -#endif - -#ifdef CONFIG_MACH_GTIB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTIB -# endif -# define machine_is_gtib() (machine_arch_type == MACH_TYPE_GTIB) -#else -# define machine_is_gtib() (0) -#endif - -#ifdef CONFIG_MACH_DGM3240 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DGM3240 -# endif -# define machine_is_dgm3240() (machine_arch_type == MACH_TYPE_DGM3240) -#else -# define machine_is_dgm3240() (0) -#endif - -#ifdef CONFIG_MACH_HTCMEGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTCMEGA -# endif -# define machine_is_htcmega() (machine_arch_type == MACH_TYPE_HTCMEGA) -#else -# define machine_is_htcmega() (0) -#endif - -#ifdef CONFIG_MACH_TRICORDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRICORDER -# endif -# define machine_is_tricorder() (machine_arch_type == MACH_TYPE_TRICORDER) -#else -# define machine_is_tricorder() (0) -#endif - -#ifdef CONFIG_MACH_TX28 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX28 -# endif -# define machine_is_tx28() (machine_arch_type == MACH_TYPE_TX28) -#else -# define machine_is_tx28() (0) -#endif - -#ifdef CONFIG_MACH_BSTBRD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BSTBRD -# endif -# define machine_is_bstbrd() (machine_arch_type == MACH_TYPE_BSTBRD) -#else -# define machine_is_bstbrd() (0) -#endif - -#ifdef CONFIG_MACH_PWB3090 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PWB3090 -# endif -# define machine_is_pwb3090() (machine_arch_type == MACH_TYPE_PWB3090) -#else -# define machine_is_pwb3090() (0) -#endif - -#ifdef CONFIG_MACH_IDEA6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IDEA6410 -# endif -# define machine_is_idea6410() (machine_arch_type == MACH_TYPE_IDEA6410) -#else -# define machine_is_idea6410() (0) -#endif - -#ifdef CONFIG_MACH_QBC9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QBC9263 -# endif -# define machine_is_qbc9263() (machine_arch_type == MACH_TYPE_QBC9263) -#else -# define machine_is_qbc9263() (0) -#endif - -#ifdef CONFIG_MACH_BORABORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BORABORA -# endif -# define machine_is_borabora() (machine_arch_type == MACH_TYPE_BORABORA) -#else -# define machine_is_borabora() (0) -#endif - -#ifdef CONFIG_MACH_VALDEZ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VALDEZ -# endif -# define machine_is_valdez() (machine_arch_type == MACH_TYPE_VALDEZ) -#else -# define machine_is_valdez() (0) -#endif - -#ifdef CONFIG_MACH_LS9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LS9G20 -# endif -# define machine_is_ls9g20() (machine_arch_type == MACH_TYPE_LS9G20) -#else -# define machine_is_ls9g20() (0) -#endif - -#ifdef CONFIG_MACH_MIOS_V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIOS_V1 -# endif -# define machine_is_mios_v1() (machine_arch_type == MACH_TYPE_MIOS_V1) -#else -# define machine_is_mios_v1() (0) -#endif - -#ifdef CONFIG_MACH_S5PC110_CRESPO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5PC110_CRESPO -# endif -# define machine_is_s5pc110_crespo() (machine_arch_type == MACH_TYPE_S5PC110_CRESPO) -#else -# define machine_is_s5pc110_crespo() (0) -#endif - -#ifdef CONFIG_MACH_CONTROLTEK9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CONTROLTEK9G20 -# endif -# define machine_is_controltek9g20() (machine_arch_type == MACH_TYPE_CONTROLTEK9G20) -#else -# define machine_is_controltek9g20() (0) -#endif - -#ifdef CONFIG_MACH_TIN307 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIN307 -# endif -# define machine_is_tin307() (machine_arch_type == MACH_TYPE_TIN307) -#else -# define machine_is_tin307() (0) -#endif - -#ifdef CONFIG_MACH_TIN510 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIN510 -# endif -# define machine_is_tin510() (machine_arch_type == MACH_TYPE_TIN510) -#else -# define machine_is_tin510() (0) -#endif - -#ifdef CONFIG_MACH_BLUECHEESE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUECHEESE -# endif -# define machine_is_bluecheese() (machine_arch_type == MACH_TYPE_BLUECHEESE) -#else -# define machine_is_bluecheese() (0) -#endif - -#ifdef CONFIG_MACH_TEM3X30 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEM3X30 -# endif -# define machine_is_tem3x30() (machine_arch_type == MACH_TYPE_TEM3X30) -#else -# define machine_is_tem3x30() (0) -#endif - -#ifdef CONFIG_MACH_HARVEST_DESOTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HARVEST_DESOTO -# endif -# define machine_is_harvest_desoto() (machine_arch_type == MACH_TYPE_HARVEST_DESOTO) -#else -# define machine_is_harvest_desoto() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_QRDC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_QRDC -# endif -# define machine_is_msm8x60_qrdc() (machine_arch_type == MACH_TYPE_MSM8X60_QRDC) -#else -# define machine_is_msm8x60_qrdc() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR900 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR900 -# endif -# define machine_is_spear900() (machine_arch_type == MACH_TYPE_SPEAR900) -#else -# define machine_is_spear900() (0) -#endif - -#ifdef CONFIG_MACH_PCONTROL_G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCONTROL_G20 -# endif -# define machine_is_pcontrol_g20() (machine_arch_type == MACH_TYPE_PCONTROL_G20) -#else -# define machine_is_pcontrol_g20() (0) -#endif - -#ifdef CONFIG_MACH_RDSTOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RDSTOR -# endif -# define machine_is_rdstor() (machine_arch_type == MACH_TYPE_RDSTOR) -#else -# define machine_is_rdstor() (0) -#endif - -#ifdef CONFIG_MACH_USDLOADER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_USDLOADER -# endif -# define machine_is_usdloader() (machine_arch_type == MACH_TYPE_USDLOADER) -#else -# define machine_is_usdloader() (0) -#endif - -#ifdef CONFIG_MACH_TSOPLOADER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TSOPLOADER -# endif -# define machine_is_tsoploader() (machine_arch_type == MACH_TYPE_TSOPLOADER) -#else -# define machine_is_tsoploader() (0) -#endif - -#ifdef CONFIG_MACH_KRONOS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KRONOS -# endif -# define machine_is_kronos() (machine_arch_type == MACH_TYPE_KRONOS) -#else -# define machine_is_kronos() (0) -#endif - -#ifdef CONFIG_MACH_FFCORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FFCORE -# endif -# define machine_is_ffcore() (machine_arch_type == MACH_TYPE_FFCORE) -#else -# define machine_is_ffcore() (0) -#endif - -#ifdef CONFIG_MACH_MONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONE -# endif -# define machine_is_mone() (machine_arch_type == MACH_TYPE_MONE) -#else -# define machine_is_mone() (0) -#endif - -#ifdef CONFIG_MACH_UNIT2S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNIT2S -# endif -# define machine_is_unit2s() (machine_arch_type == MACH_TYPE_UNIT2S) -#else -# define machine_is_unit2s() (0) -#endif - -#ifdef CONFIG_MACH_ACER_A5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_A5 -# endif -# define machine_is_acer_a5() (machine_arch_type == MACH_TYPE_ACER_A5) -#else -# define machine_is_acer_a5() (0) -#endif - -#ifdef CONFIG_MACH_ETHERPRO_ISP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ETHERPRO_ISP -# endif -# define machine_is_etherpro_isp() (machine_arch_type == MACH_TYPE_ETHERPRO_ISP) -#else -# define machine_is_etherpro_isp() (0) -#endif - -#ifdef CONFIG_MACH_STRETCHS7000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STRETCHS7000 -# endif -# define machine_is_stretchs7000() (machine_arch_type == MACH_TYPE_STRETCHS7000) -#else -# define machine_is_stretchs7000() (0) -#endif - -#ifdef CONFIG_MACH_P87_SMARTSIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_P87_SMARTSIM -# endif -# define machine_is_p87_smartsim() (machine_arch_type == MACH_TYPE_P87_SMARTSIM) -#else -# define machine_is_p87_smartsim() (0) -#endif - -#ifdef CONFIG_MACH_TULIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TULIP -# endif -# define machine_is_tulip() (machine_arch_type == MACH_TYPE_TULIP) -#else -# define machine_is_tulip() (0) -#endif - -#ifdef CONFIG_MACH_SUNFLOWER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNFLOWER -# endif -# define machine_is_sunflower() (machine_arch_type == MACH_TYPE_SUNFLOWER) -#else -# define machine_is_sunflower() (0) -#endif - -#ifdef CONFIG_MACH_RIB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIB -# endif -# define machine_is_rib() (machine_arch_type == MACH_TYPE_RIB) -#else -# define machine_is_rib() (0) -#endif - -#ifdef CONFIG_MACH_CLOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CLOD -# endif -# define machine_is_clod() (machine_arch_type == MACH_TYPE_CLOD) -#else -# define machine_is_clod() (0) -#endif - -#ifdef CONFIG_MACH_RUMP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUMP -# endif -# define machine_is_rump() (machine_arch_type == MACH_TYPE_RUMP) -#else -# define machine_is_rump() (0) -#endif - -#ifdef CONFIG_MACH_TENDERLOIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TENDERLOIN -# endif -# define machine_is_tenderloin() (machine_arch_type == MACH_TYPE_TENDERLOIN) -#else -# define machine_is_tenderloin() (0) -#endif - -#ifdef CONFIG_MACH_SHORTLOIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHORTLOIN -# endif -# define machine_is_shortloin() (machine_arch_type == MACH_TYPE_SHORTLOIN) -#else -# define machine_is_shortloin() (0) -#endif - -#ifdef CONFIG_MACH_ANTARES -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANTARES -# endif -# define machine_is_antares() (machine_arch_type == MACH_TYPE_ANTARES) -#else -# define machine_is_antares() (0) -#endif - -#ifdef CONFIG_MACH_WB40N -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WB40N -# endif -# define machine_is_wb40n() (machine_arch_type == MACH_TYPE_WB40N) -#else -# define machine_is_wb40n() (0) -#endif - -#ifdef CONFIG_MACH_HERRING -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HERRING -# endif -# define machine_is_herring() (machine_arch_type == MACH_TYPE_HERRING) -#else -# define machine_is_herring() (0) -#endif - -#ifdef CONFIG_MACH_NAXY400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAXY400 -# endif -# define machine_is_naxy400() (machine_arch_type == MACH_TYPE_NAXY400) -#else -# define machine_is_naxy400() (0) -#endif - -#ifdef CONFIG_MACH_NAXY1200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAXY1200 -# endif -# define machine_is_naxy1200() (machine_arch_type == MACH_TYPE_NAXY1200) -#else -# define machine_is_naxy1200() (0) -#endif - -#ifdef CONFIG_MACH_VPR200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VPR200 -# endif -# define machine_is_vpr200() (machine_arch_type == MACH_TYPE_VPR200) -#else -# define machine_is_vpr200() (0) -#endif - -#ifdef CONFIG_MACH_BUG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BUG20 -# endif -# define machine_is_bug20() (machine_arch_type == MACH_TYPE_BUG20) -#else -# define machine_is_bug20() (0) -#endif - -#ifdef CONFIG_MACH_GOFLEXNET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOFLEXNET -# endif -# define machine_is_goflexnet() (machine_arch_type == MACH_TYPE_GOFLEXNET) -#else -# define machine_is_goflexnet() (0) -#endif - -#ifdef CONFIG_MACH_TORBRECK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TORBRECK -# endif -# define machine_is_torbreck() (machine_arch_type == MACH_TYPE_TORBRECK) -#else -# define machine_is_torbreck() (0) -#endif - -#ifdef CONFIG_MACH_SAARB_MG1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAARB_MG1 -# endif -# define machine_is_saarb_mg1() (machine_arch_type == MACH_TYPE_SAARB_MG1) -#else -# define machine_is_saarb_mg1() (0) -#endif - -#ifdef CONFIG_MACH_CALLISTO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CALLISTO -# endif -# define machine_is_callisto() (machine_arch_type == MACH_TYPE_CALLISTO) -#else -# define machine_is_callisto() (0) -#endif - -#ifdef CONFIG_MACH_MULTHSU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MULTHSU -# endif -# define machine_is_multhsu() (machine_arch_type == MACH_TYPE_MULTHSU) -#else -# define machine_is_multhsu() (0) -#endif - -#ifdef CONFIG_MACH_SALUDA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SALUDA -# endif -# define machine_is_saluda() (machine_arch_type == MACH_TYPE_SALUDA) -#else -# define machine_is_saluda() (0) -#endif - -#ifdef CONFIG_MACH_PEMP_OMAP3_APOLLO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PEMP_OMAP3_APOLLO -# endif -# define machine_is_pemp_omap3_apollo() (machine_arch_type == MACH_TYPE_PEMP_OMAP3_APOLLO) -#else -# define machine_is_pemp_omap3_apollo() (0) -#endif - -#ifdef CONFIG_MACH_VC0718 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VC0718 -# endif -# define machine_is_vc0718() (machine_arch_type == MACH_TYPE_VC0718) -#else -# define machine_is_vc0718() (0) -#endif - -#ifdef CONFIG_MACH_MVBLX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MVBLX -# endif -# define machine_is_mvblx() (machine_arch_type == MACH_TYPE_MVBLX) -#else -# define machine_is_mvblx() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_APEIRON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_APEIRON -# endif -# define machine_is_inhand_apeiron() (machine_arch_type == MACH_TYPE_INHAND_APEIRON) -#else -# define machine_is_inhand_apeiron() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_FURY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_FURY -# endif -# define machine_is_inhand_fury() (machine_arch_type == MACH_TYPE_INHAND_FURY) -#else -# define machine_is_inhand_fury() (0) -#endif - -#ifdef CONFIG_MACH_INHAND_SIREN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_INHAND_SIREN -# endif -# define machine_is_inhand_siren() (machine_arch_type == MACH_TYPE_INHAND_SIREN) -#else -# define machine_is_inhand_siren() (0) -#endif - -#ifdef CONFIG_MACH_HDNVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDNVP -# endif -# define machine_is_hdnvp() (machine_arch_type == MACH_TYPE_HDNVP) -#else -# define machine_is_hdnvp() (0) -#endif - -#ifdef CONFIG_MACH_SOFTWINNER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SOFTWINNER -# endif -# define machine_is_softwinner() (machine_arch_type == MACH_TYPE_SOFTWINNER) -#else -# define machine_is_softwinner() (0) -#endif - -#ifdef CONFIG_MACH_PRIMA2_EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PRIMA2_EVB -# endif -# define machine_is_prima2_evb() (machine_arch_type == MACH_TYPE_PRIMA2_EVB) -#else -# define machine_is_prima2_evb() (0) -#endif - -#ifdef CONFIG_MACH_NAS6210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAS6210 -# endif -# define machine_is_nas6210() (machine_arch_type == MACH_TYPE_NAS6210) -#else -# define machine_is_nas6210() (0) -#endif - -#ifdef CONFIG_MACH_UNISDEV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNISDEV -# endif -# define machine_is_unisdev() (machine_arch_type == MACH_TYPE_UNISDEV) -#else -# define machine_is_unisdev() (0) -#endif - -#ifdef CONFIG_MACH_SBCA11 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBCA11 -# endif -# define machine_is_sbca11() (machine_arch_type == MACH_TYPE_SBCA11) -#else -# define machine_is_sbca11() (0) -#endif - -#ifdef CONFIG_MACH_SAGA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAGA -# endif -# define machine_is_saga() (machine_arch_type == MACH_TYPE_SAGA) -#else -# define machine_is_saga() (0) -#endif - -#ifdef CONFIG_MACH_NS_K330 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS_K330 -# endif -# define machine_is_ns_k330() (machine_arch_type == MACH_TYPE_NS_K330) -#else -# define machine_is_ns_k330() (0) -#endif - -#ifdef CONFIG_MACH_TANNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TANNA -# endif -# define machine_is_tanna() (machine_arch_type == MACH_TYPE_TANNA) -#else -# define machine_is_tanna() (0) -#endif - -#ifdef CONFIG_MACH_IMATE8502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IMATE8502 -# endif -# define machine_is_imate8502() (machine_arch_type == MACH_TYPE_IMATE8502) -#else -# define machine_is_imate8502() (0) -#endif - -#ifdef CONFIG_MACH_ASPEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASPEN -# endif -# define machine_is_aspen() (machine_arch_type == MACH_TYPE_ASPEN) -#else -# define machine_is_aspen() (0) -#endif - -#ifdef CONFIG_MACH_DAINTREE_CWAC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAINTREE_CWAC -# endif -# define machine_is_daintree_cwac() (machine_arch_type == MACH_TYPE_DAINTREE_CWAC) -#else -# define machine_is_daintree_cwac() (0) -#endif - -#ifdef CONFIG_MACH_ZMX25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ZMX25 -# endif -# define machine_is_zmx25() (machine_arch_type == MACH_TYPE_ZMX25) -#else -# define machine_is_zmx25() (0) -#endif - -#ifdef CONFIG_MACH_MAPLE1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAPLE1 -# endif -# define machine_is_maple1() (machine_arch_type == MACH_TYPE_MAPLE1) -#else -# define machine_is_maple1() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X72_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X72_SURF -# endif -# define machine_is_qsd8x72_surf() (machine_arch_type == MACH_TYPE_QSD8X72_SURF) -#else -# define machine_is_qsd8x72_surf() (0) -#endif - -#ifdef CONFIG_MACH_QSD8X72_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QSD8X72_FFA -# endif -# define machine_is_qsd8x72_ffa() (machine_arch_type == MACH_TYPE_QSD8X72_FFA) -#else -# define machine_is_qsd8x72_ffa() (0) -#endif - -#ifdef CONFIG_MACH_ABILENE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABILENE -# endif -# define machine_is_abilene() (machine_arch_type == MACH_TYPE_ABILENE) -#else -# define machine_is_abilene() (0) -#endif - -#ifdef CONFIG_MACH_EIGEN_TTR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EIGEN_TTR -# endif -# define machine_is_eigen_ttr() (machine_arch_type == MACH_TYPE_EIGEN_TTR) -#else -# define machine_is_eigen_ttr() (0) -#endif - -#ifdef CONFIG_MACH_IOMEGA_IX2_200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IOMEGA_IX2_200 -# endif -# define machine_is_iomega_ix2_200() (machine_arch_type == MACH_TYPE_IOMEGA_IX2_200) -#else -# define machine_is_iomega_ix2_200() (0) -#endif - -#ifdef CONFIG_MACH_CORETEC_VCX7400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CORETEC_VCX7400 -# endif -# define machine_is_coretec_vcx7400() (machine_arch_type == MACH_TYPE_CORETEC_VCX7400) -#else -# define machine_is_coretec_vcx7400() (0) -#endif - -#ifdef CONFIG_MACH_SANTIAGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SANTIAGO -# endif -# define machine_is_santiago() (machine_arch_type == MACH_TYPE_SANTIAGO) -#else -# define machine_is_santiago() (0) -#endif - -#ifdef CONFIG_MACH_MX257SOL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX257SOL -# endif -# define machine_is_mx257sol() (machine_arch_type == MACH_TYPE_MX257SOL) -#else -# define machine_is_mx257sol() (0) -#endif - -#ifdef CONFIG_MACH_STRASBOURG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STRASBOURG -# endif -# define machine_is_strasbourg() (machine_arch_type == MACH_TYPE_STRASBOURG) -#else -# define machine_is_strasbourg() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_FLUID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_FLUID -# endif -# define machine_is_msm8x60_fluid() (machine_arch_type == MACH_TYPE_MSM8X60_FLUID) -#else -# define machine_is_msm8x60_fluid() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQV5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQV5 -# endif -# define machine_is_smartqv5() (machine_arch_type == MACH_TYPE_SMARTQV5) -#else -# define machine_is_smartqv5() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQV3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQV3 -# endif -# define machine_is_smartqv3() (machine_arch_type == MACH_TYPE_SMARTQV3) -#else -# define machine_is_smartqv3() (0) -#endif - -#ifdef CONFIG_MACH_SMARTQV7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMARTQV7 -# endif -# define machine_is_smartqv7() (machine_arch_type == MACH_TYPE_SMARTQV7) -#else -# define machine_is_smartqv7() (0) -#endif - -#ifdef CONFIG_MACH_PAZ00 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PAZ00 -# endif -# define machine_is_paz00() (machine_arch_type == MACH_TYPE_PAZ00) -#else -# define machine_is_paz00() (0) -#endif - -#ifdef CONFIG_MACH_ACMENETUSFOXG20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACMENETUSFOXG20 -# endif -# define machine_is_acmenetusfoxg20() (machine_arch_type == MACH_TYPE_ACMENETUSFOXG20) -#else -# define machine_is_acmenetusfoxg20() (0) -#endif - -#ifdef CONFIG_MACH_FWBD_0404 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FWBD_0404 -# endif -# define machine_is_fwbd_0404() (machine_arch_type == MACH_TYPE_FWBD_0404) -#else -# define machine_is_fwbd_0404() (0) -#endif - -#ifdef CONFIG_MACH_HDGU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDGU -# endif -# define machine_is_hdgu() (machine_arch_type == MACH_TYPE_HDGU) -#else -# define machine_is_hdgu() (0) -#endif - -#ifdef CONFIG_MACH_PYRAMID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PYRAMID -# endif -# define machine_is_pyramid() (machine_arch_type == MACH_TYPE_PYRAMID) -#else -# define machine_is_pyramid() (0) -#endif - -#ifdef CONFIG_MACH_EPIPHAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPIPHAN -# endif -# define machine_is_epiphan() (machine_arch_type == MACH_TYPE_EPIPHAN) -#else -# define machine_is_epiphan() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_BENDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_BENDER -# endif -# define machine_is_omap_bender() (machine_arch_type == MACH_TYPE_OMAP_BENDER) -#else -# define machine_is_omap_bender() (0) -#endif - -#ifdef CONFIG_MACH_GURNARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GURNARD -# endif -# define machine_is_gurnard() (machine_arch_type == MACH_TYPE_GURNARD) -#else -# define machine_is_gurnard() (0) -#endif - -#ifdef CONFIG_MACH_GTL_IT5100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GTL_IT5100 -# endif -# define machine_is_gtl_it5100() (machine_arch_type == MACH_TYPE_GTL_IT5100) -#else -# define machine_is_gtl_it5100() (0) -#endif - -#ifdef CONFIG_MACH_BCM2708 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCM2708 -# endif -# define machine_is_bcm2708() (machine_arch_type == MACH_TYPE_BCM2708) -#else -# define machine_is_bcm2708() (0) -#endif - -#ifdef CONFIG_MACH_MX51_GGC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_GGC -# endif -# define machine_is_mx51_ggc() (machine_arch_type == MACH_TYPE_MX51_GGC) -#else -# define machine_is_mx51_ggc() (0) -#endif - -#ifdef CONFIG_MACH_SHARESPACE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHARESPACE -# endif -# define machine_is_sharespace() (machine_arch_type == MACH_TYPE_SHARESPACE) -#else -# define machine_is_sharespace() (0) -#endif - -#ifdef CONFIG_MACH_HABA_KNX_EXPLORER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HABA_KNX_EXPLORER -# endif -# define machine_is_haba_knx_explorer() (machine_arch_type == MACH_TYPE_HABA_KNX_EXPLORER) -#else -# define machine_is_haba_knx_explorer() (0) -#endif - -#ifdef CONFIG_MACH_SIMTEC_KIRKMOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SIMTEC_KIRKMOD -# endif -# define machine_is_simtec_kirkmod() (machine_arch_type == MACH_TYPE_SIMTEC_KIRKMOD) -#else -# define machine_is_simtec_kirkmod() (0) -#endif - -#ifdef CONFIG_MACH_CRUX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CRUX -# endif -# define machine_is_crux() (machine_arch_type == MACH_TYPE_CRUX) -#else -# define machine_is_crux() (0) -#endif - -#ifdef CONFIG_MACH_MX51_BRAVO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_BRAVO -# endif -# define machine_is_mx51_bravo() (machine_arch_type == MACH_TYPE_MX51_BRAVO) -#else -# define machine_is_mx51_bravo() (0) -#endif - -#ifdef CONFIG_MACH_CHARON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHARON -# endif -# define machine_is_charon() (machine_arch_type == MACH_TYPE_CHARON) -#else -# define machine_is_charon() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM3 -# endif -# define machine_is_picocom3() (machine_arch_type == MACH_TYPE_PICOCOM3) -#else -# define machine_is_picocom3() (0) -#endif - -#ifdef CONFIG_MACH_PICOCOM4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICOCOM4 -# endif -# define machine_is_picocom4() (machine_arch_type == MACH_TYPE_PICOCOM4) -#else -# define machine_is_picocom4() (0) -#endif - -#ifdef CONFIG_MACH_SERRANO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SERRANO -# endif -# define machine_is_serrano() (machine_arch_type == MACH_TYPE_SERRANO) -#else -# define machine_is_serrano() (0) -#endif - -#ifdef CONFIG_MACH_DOUBLESHOT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOUBLESHOT -# endif -# define machine_is_doubleshot() (machine_arch_type == MACH_TYPE_DOUBLESHOT) -#else -# define machine_is_doubleshot() (0) -#endif - -#ifdef CONFIG_MACH_EVSY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVSY -# endif -# define machine_is_evsy() (machine_arch_type == MACH_TYPE_EVSY) -#else -# define machine_is_evsy() (0) -#endif - -#ifdef CONFIG_MACH_HUASHAN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HUASHAN -# endif -# define machine_is_huashan() (machine_arch_type == MACH_TYPE_HUASHAN) -#else -# define machine_is_huashan() (0) -#endif - -#ifdef CONFIG_MACH_LAUSANNE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LAUSANNE -# endif -# define machine_is_lausanne() (machine_arch_type == MACH_TYPE_LAUSANNE) -#else -# define machine_is_lausanne() (0) -#endif - -#ifdef CONFIG_MACH_EMERALD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EMERALD -# endif -# define machine_is_emerald() (machine_arch_type == MACH_TYPE_EMERALD) -#else -# define machine_is_emerald() (0) -#endif - -#ifdef CONFIG_MACH_TQMA35 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQMA35 -# endif -# define machine_is_tqma35() (machine_arch_type == MACH_TYPE_TQMA35) -#else -# define machine_is_tqma35() (0) -#endif - -#ifdef CONFIG_MACH_MARVEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVEL -# endif -# define machine_is_marvel() (machine_arch_type == MACH_TYPE_MARVEL) -#else -# define machine_is_marvel() (0) -#endif - -#ifdef CONFIG_MACH_MANUAE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MANUAE -# endif -# define machine_is_manuae() (machine_arch_type == MACH_TYPE_MANUAE) -#else -# define machine_is_manuae() (0) -#endif - -#ifdef CONFIG_MACH_CHACHA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHACHA -# endif -# define machine_is_chacha() (machine_arch_type == MACH_TYPE_CHACHA) -#else -# define machine_is_chacha() (0) -#endif - -#ifdef CONFIG_MACH_LEMON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEMON -# endif -# define machine_is_lemon() (machine_arch_type == MACH_TYPE_LEMON) -#else -# define machine_is_lemon() (0) -#endif - -#ifdef CONFIG_MACH_CSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CSC -# endif -# define machine_is_csc() (machine_arch_type == MACH_TYPE_CSC) -#else -# define machine_is_csc() (0) -#endif - -#ifdef CONFIG_MACH_GIRA_KNXIP_ROUTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GIRA_KNXIP_ROUTER -# endif -# define machine_is_gira_knxip_router() (machine_arch_type == MACH_TYPE_GIRA_KNXIP_ROUTER) -#else -# define machine_is_gira_knxip_router() (0) -#endif - -#ifdef CONFIG_MACH_T20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T20 -# endif -# define machine_is_t20() (machine_arch_type == MACH_TYPE_T20) -#else -# define machine_is_t20() (0) -#endif - -#ifdef CONFIG_MACH_HDMINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HDMINI -# endif -# define machine_is_hdmini() (machine_arch_type == MACH_TYPE_HDMINI) -#else -# define machine_is_hdmini() (0) -#endif - -#ifdef CONFIG_MACH_SCIPHONE_G2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SCIPHONE_G2 -# endif -# define machine_is_sciphone_g2() (machine_arch_type == MACH_TYPE_SCIPHONE_G2) -#else -# define machine_is_sciphone_g2() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESS -# endif -# define machine_is_express() (machine_arch_type == MACH_TYPE_EXPRESS) -#else -# define machine_is_express() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESS_KT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESS_KT -# endif -# define machine_is_express_kt() (machine_arch_type == MACH_TYPE_EXPRESS_KT) -#else -# define machine_is_express_kt() (0) -#endif - -#ifdef CONFIG_MACH_MAXIMASP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MAXIMASP -# endif -# define machine_is_maximasp() (machine_arch_type == MACH_TYPE_MAXIMASP) -#else -# define machine_is_maximasp() (0) -#endif - -#ifdef CONFIG_MACH_NITROGEN_IMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NITROGEN_IMX51 -# endif -# define machine_is_nitrogen_imx51() (machine_arch_type == MACH_TYPE_NITROGEN_IMX51) -#else -# define machine_is_nitrogen_imx51() (0) -#endif - -#ifdef CONFIG_MACH_NITROGEN_IMX53 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NITROGEN_IMX53 -# endif -# define machine_is_nitrogen_imx53() (machine_arch_type == MACH_TYPE_NITROGEN_IMX53) -#else -# define machine_is_nitrogen_imx53() (0) -#endif - -#ifdef CONFIG_MACH_SUNFIRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SUNFIRE -# endif -# define machine_is_sunfire() (machine_arch_type == MACH_TYPE_SUNFIRE) -#else -# define machine_is_sunfire() (0) -#endif - -#ifdef CONFIG_MACH_AROWANA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AROWANA -# endif -# define machine_is_arowana() (machine_arch_type == MACH_TYPE_AROWANA) -#else -# define machine_is_arowana() (0) -#endif - -#ifdef CONFIG_MACH_TEGRA_DAYTONA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEGRA_DAYTONA -# endif -# define machine_is_tegra_daytona() (machine_arch_type == MACH_TYPE_TEGRA_DAYTONA) -#else -# define machine_is_tegra_daytona() (0) -#endif - -#ifdef CONFIG_MACH_TEGRA_SWORDFISH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TEGRA_SWORDFISH -# endif -# define machine_is_tegra_swordfish() (machine_arch_type == MACH_TYPE_TEGRA_SWORDFISH) -#else -# define machine_is_tegra_swordfish() (0) -#endif - -#ifdef CONFIG_MACH_EDISON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EDISON -# endif -# define machine_is_edison() (machine_arch_type == MACH_TYPE_EDISON) -#else -# define machine_is_edison() (0) -#endif - -#ifdef CONFIG_MACH_SVP8500V1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVP8500V1 -# endif -# define machine_is_svp8500v1() (machine_arch_type == MACH_TYPE_SVP8500V1) -#else -# define machine_is_svp8500v1() (0) -#endif - -#ifdef CONFIG_MACH_SVP8500V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVP8500V2 -# endif -# define machine_is_svp8500v2() (machine_arch_type == MACH_TYPE_SVP8500V2) -#else -# define machine_is_svp8500v2() (0) -#endif - -#ifdef CONFIG_MACH_SVP5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVP5500 -# endif -# define machine_is_svp5500() (machine_arch_type == MACH_TYPE_SVP5500) -#else -# define machine_is_svp5500() (0) -#endif - -#ifdef CONFIG_MACH_B5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_B5500 -# endif -# define machine_is_b5500() (machine_arch_type == MACH_TYPE_B5500) -#else -# define machine_is_b5500() (0) -#endif - -#ifdef CONFIG_MACH_S5500 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_S5500 -# endif -# define machine_is_s5500() (machine_arch_type == MACH_TYPE_S5500) -#else -# define machine_is_s5500() (0) -#endif - -#ifdef CONFIG_MACH_ICON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICON -# endif -# define machine_is_icon() (machine_arch_type == MACH_TYPE_ICON) -#else -# define machine_is_icon() (0) -#endif - -#ifdef CONFIG_MACH_ELEPHANT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELEPHANT -# endif -# define machine_is_elephant() (machine_arch_type == MACH_TYPE_ELEPHANT) -#else -# define machine_is_elephant() (0) -#endif - -#ifdef CONFIG_MACH_SHOOTER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHOOTER -# endif -# define machine_is_shooter() (machine_arch_type == MACH_TYPE_SHOOTER) -#else -# define machine_is_shooter() (0) -#endif - -#ifdef CONFIG_MACH_SPADE_LTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPADE_LTE -# endif -# define machine_is_spade_lte() (machine_arch_type == MACH_TYPE_SPADE_LTE) -#else -# define machine_is_spade_lte() (0) -#endif - -#ifdef CONFIG_MACH_PHILHWANI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PHILHWANI -# endif -# define machine_is_philhwani() (machine_arch_type == MACH_TYPE_PHILHWANI) -#else -# define machine_is_philhwani() (0) -#endif - -#ifdef CONFIG_MACH_GSNCOMM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GSNCOMM -# endif -# define machine_is_gsncomm() (machine_arch_type == MACH_TYPE_GSNCOMM) -#else -# define machine_is_gsncomm() (0) -#endif - -#ifdef CONFIG_MACH_STRASBOURG_A2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STRASBOURG_A2 -# endif -# define machine_is_strasbourg_a2() (machine_arch_type == MACH_TYPE_STRASBOURG_A2) -#else -# define machine_is_strasbourg_a2() (0) -#endif - -#ifdef CONFIG_MACH_MMM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MMM -# endif -# define machine_is_mmm() (machine_arch_type == MACH_TYPE_MMM) -#else -# define machine_is_mmm() (0) -#endif - -#ifdef CONFIG_MACH_DAVINCI_DM365_BV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAVINCI_DM365_BV -# endif -# define machine_is_davinci_dm365_bv() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_BV) -#else -# define machine_is_davinci_dm365_bv() (0) -#endif - -#ifdef CONFIG_MACH_AG5EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AG5EVM -# endif -# define machine_is_ag5evm() (machine_arch_type == MACH_TYPE_AG5EVM) -#else -# define machine_is_ag5evm() (0) -#endif - -#ifdef CONFIG_MACH_SC575PLC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC575PLC -# endif -# define machine_is_sc575plc() (machine_arch_type == MACH_TYPE_SC575PLC) -#else -# define machine_is_sc575plc() (0) -#endif - -#ifdef CONFIG_MACH_SC575IPC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SC575IPC -# endif -# define machine_is_sc575hmi() (machine_arch_type == MACH_TYPE_SC575IPC) -#else -# define machine_is_sc575hmi() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_TDM3730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_TDM3730 -# endif -# define machine_is_omap3_tdm3730() (machine_arch_type == MACH_TYPE_OMAP3_TDM3730) -#else -# define machine_is_omap3_tdm3730() (0) -#endif - -#ifdef CONFIG_MACH_TOP9000_EVAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOP9000_EVAL -# endif -# define machine_is_top9000_eval() (machine_arch_type == MACH_TYPE_TOP9000_EVAL) -#else -# define machine_is_top9000_eval() (0) -#endif - -#ifdef CONFIG_MACH_TOP9000_SU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOP9000_SU -# endif -# define machine_is_top9000_su() (machine_arch_type == MACH_TYPE_TOP9000_SU) -#else -# define machine_is_top9000_su() (0) -#endif - -#ifdef CONFIG_MACH_UTM300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UTM300 -# endif -# define machine_is_utm300() (machine_arch_type == MACH_TYPE_UTM300) -#else -# define machine_is_utm300() (0) -#endif - -#ifdef CONFIG_MACH_TSUNAGI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TSUNAGI -# endif -# define machine_is_tsunagi() (machine_arch_type == MACH_TYPE_TSUNAGI) -#else -# define machine_is_tsunagi() (0) -#endif - -#ifdef CONFIG_MACH_TS75XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS75XX -# endif -# define machine_is_ts75xx() (machine_arch_type == MACH_TYPE_TS75XX) -#else -# define machine_is_ts75xx() (0) -#endif - -#ifdef CONFIG_MACH_TS47XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS47XX -# endif -# define machine_is_ts47xx() (machine_arch_type == MACH_TYPE_TS47XX) -#else -# define machine_is_ts47xx() (0) -#endif - -#ifdef CONFIG_MACH_DA850_K5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DA850_K5 -# endif -# define machine_is_da850_k5() (machine_arch_type == MACH_TYPE_DA850_K5) -#else -# define machine_is_da850_k5() (0) -#endif - -#ifdef CONFIG_MACH_AX502 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AX502 -# endif -# define machine_is_ax502() (machine_arch_type == MACH_TYPE_AX502) -#else -# define machine_is_ax502() (0) -#endif - -#ifdef CONFIG_MACH_IGEP0032 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IGEP0032 -# endif -# define machine_is_igep0032() (machine_arch_type == MACH_TYPE_IGEP0032) -#else -# define machine_is_igep0032() (0) -#endif - -#ifdef CONFIG_MACH_ANTERO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANTERO -# endif -# define machine_is_antero() (machine_arch_type == MACH_TYPE_ANTERO) -#else -# define machine_is_antero() (0) -#endif - -#ifdef CONFIG_MACH_SYNERGY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SYNERGY -# endif -# define machine_is_synergy() (machine_arch_type == MACH_TYPE_SYNERGY) -#else -# define machine_is_synergy() (0) -#endif - -#ifdef CONFIG_MACH_ICS_IF_VOIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICS_IF_VOIP -# endif -# define machine_is_ics_if_voip() (machine_arch_type == MACH_TYPE_ICS_IF_VOIP) -#else -# define machine_is_ics_if_voip() (0) -#endif - -#ifdef CONFIG_MACH_WLF_CRAGG_6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WLF_CRAGG_6410 -# endif -# define machine_is_wlf_cragg_6410() (machine_arch_type == MACH_TYPE_WLF_CRAGG_6410) -#else -# define machine_is_wlf_cragg_6410() (0) -#endif - -#ifdef CONFIG_MACH_PUNICA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PUNICA -# endif -# define machine_is_punica() (machine_arch_type == MACH_TYPE_PUNICA) -#else -# define machine_is_punica() (0) -#endif - -#ifdef CONFIG_MACH_TRIMSLICE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIMSLICE -# endif -# define machine_is_trimslice() (machine_arch_type == MACH_TYPE_TRIMSLICE) -#else -# define machine_is_trimslice() (0) -#endif - -#ifdef CONFIG_MACH_MX27_WMULTRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27_WMULTRA -# endif -# define machine_is_mx27_wmultra() (machine_arch_type == MACH_TYPE_MX27_WMULTRA) -#else -# define machine_is_mx27_wmultra() (0) -#endif - -#ifdef CONFIG_MACH_MACKEREL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACKEREL -# endif -# define machine_is_mackerel() (machine_arch_type == MACH_TYPE_MACKEREL) -#else -# define machine_is_mackerel() (0) -#endif - -#ifdef CONFIG_MACH_FA9X27 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FA9X27 -# endif -# define machine_is_fa9x27() (machine_arch_type == MACH_TYPE_FA9X27) -#else -# define machine_is_fa9x27() (0) -#endif - -#ifdef CONFIG_MACH_NS2816TB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS2816TB -# endif -# define machine_is_ns2816tb() (machine_arch_type == MACH_TYPE_NS2816TB) -#else -# define machine_is_ns2816tb() (0) -#endif - -#ifdef CONFIG_MACH_NS2816_NTPAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS2816_NTPAD -# endif -# define machine_is_ns2816_ntpad() (machine_arch_type == MACH_TYPE_NS2816_NTPAD) -#else -# define machine_is_ns2816_ntpad() (0) -#endif - -#ifdef CONFIG_MACH_NS2816_NTNB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NS2816_NTNB -# endif -# define machine_is_ns2816_ntnb() (machine_arch_type == MACH_TYPE_NS2816_NTNB) -#else -# define machine_is_ns2816_ntnb() (0) -#endif - -#ifdef CONFIG_MACH_KAEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KAEN -# endif -# define machine_is_kaen() (machine_arch_type == MACH_TYPE_KAEN) -#else -# define machine_is_kaen() (0) -#endif - -#ifdef CONFIG_MACH_NV1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NV1000 -# endif -# define machine_is_nv1000() (machine_arch_type == MACH_TYPE_NV1000) -#else -# define machine_is_nv1000() (0) -#endif - -#ifdef CONFIG_MACH_NUC950TS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC950TS -# endif -# define machine_is_nuc950ts() (machine_arch_type == MACH_TYPE_NUC950TS) -#else -# define machine_is_nuc950ts() (0) -#endif - -#ifdef CONFIG_MACH_NOKIA_RM680 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOKIA_RM680 -# endif -# define machine_is_nokia_rm680() (machine_arch_type == MACH_TYPE_NOKIA_RM680) -#else -# define machine_is_nokia_rm680() (0) -#endif - -#ifdef CONFIG_MACH_AST2200 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AST2200 -# endif -# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200) -#else -# define machine_is_ast2200() (0) -#endif - -#ifdef CONFIG_MACH_LEAD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEAD -# endif -# define machine_is_lead() (machine_arch_type == MACH_TYPE_LEAD) -#else -# define machine_is_lead() (0) -#endif - -#ifdef CONFIG_MACH_UNINO1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UNINO1 -# endif -# define machine_is_unino1() (machine_arch_type == MACH_TYPE_UNINO1) -#else -# define machine_is_unino1() (0) -#endif - -#ifdef CONFIG_MACH_GREECO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GREECO -# endif -# define machine_is_greeco() (machine_arch_type == MACH_TYPE_GREECO) -#else -# define machine_is_greeco() (0) -#endif - -#ifdef CONFIG_MACH_VERDI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERDI -# endif -# define machine_is_verdi() (machine_arch_type == MACH_TYPE_VERDI) -#else -# define machine_is_verdi() (0) -#endif - -#ifdef CONFIG_MACH_DM6446_ADBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM6446_ADBOX -# endif -# define machine_is_dm6446_adbox() (machine_arch_type == MACH_TYPE_DM6446_ADBOX) -#else -# define machine_is_dm6446_adbox() (0) -#endif - -#ifdef CONFIG_MACH_QUAD_SALSA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_QUAD_SALSA -# endif -# define machine_is_quad_salsa() (machine_arch_type == MACH_TYPE_QUAD_SALSA) -#else -# define machine_is_quad_salsa() (0) -#endif - -#ifdef CONFIG_MACH_ABB_GMA_1_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABB_GMA_1_1 -# endif -# define machine_is_abb_gma_1_1() (machine_arch_type == MACH_TYPE_ABB_GMA_1_1) -#else -# define machine_is_abb_gma_1_1() (0) -#endif - -#ifdef CONFIG_MACH_SVCID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SVCID -# endif -# define machine_is_svcid() (machine_arch_type == MACH_TYPE_SVCID) -#else -# define machine_is_svcid() (0) -#endif - -#ifdef CONFIG_MACH_MSM8960_SIM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8960_SIM -# endif -# define machine_is_msm8960_sim() (machine_arch_type == MACH_TYPE_MSM8960_SIM) -#else -# define machine_is_msm8960_sim() (0) -#endif - -#ifdef CONFIG_MACH_MSM8960_RUMI3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8960_RUMI3 -# endif -# define machine_is_msm8960_rumi3() (machine_arch_type == MACH_TYPE_MSM8960_RUMI3) -#else -# define machine_is_msm8960_rumi3() (0) -#endif - -#ifdef CONFIG_MACH_ICON_G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICON_G -# endif -# define machine_is_icon_g() (machine_arch_type == MACH_TYPE_ICON_G) -#else -# define machine_is_icon_g() (0) -#endif - -#ifdef CONFIG_MACH_MB3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MB3 -# endif -# define machine_is_mb3() (machine_arch_type == MACH_TYPE_MB3) -#else -# define machine_is_mb3() (0) -#endif - -#ifdef CONFIG_MACH_GSIA18S -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GSIA18S -# endif -# define machine_is_gsia18s() (machine_arch_type == MACH_TYPE_GSIA18S) -#else -# define machine_is_gsia18s() (0) -#endif - -#ifdef CONFIG_MACH_PIVICC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PIVICC -# endif -# define machine_is_pivicc() (machine_arch_type == MACH_TYPE_PIVICC) -#else -# define machine_is_pivicc() (0) -#endif - -#ifdef CONFIG_MACH_PCM048 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM048 -# endif -# define machine_is_pcm048() (machine_arch_type == MACH_TYPE_PCM048) -#else -# define machine_is_pcm048() (0) -#endif - -#ifdef CONFIG_MACH_DDS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DDS -# endif -# define machine_is_dds() (machine_arch_type == MACH_TYPE_DDS) -#else -# define machine_is_dds() (0) -#endif - -#ifdef CONFIG_MACH_CHALTEN_XA1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CHALTEN_XA1 -# endif -# define machine_is_chalten_xa1() (machine_arch_type == MACH_TYPE_CHALTEN_XA1) -#else -# define machine_is_chalten_xa1() (0) -#endif - -#ifdef CONFIG_MACH_TS48XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS48XX -# endif -# define machine_is_ts48xx() (machine_arch_type == MACH_TYPE_TS48XX) -#else -# define machine_is_ts48xx() (0) -#endif - -#ifdef CONFIG_MACH_TONGA2_TFTTIMER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TONGA2_TFTTIMER -# endif -# define machine_is_tonga2_tfttimer() (machine_arch_type == MACH_TYPE_TONGA2_TFTTIMER) -#else -# define machine_is_tonga2_tfttimer() (0) -#endif - -#ifdef CONFIG_MACH_WHISTLER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WHISTLER -# endif -# define machine_is_whistler() (machine_arch_type == MACH_TYPE_WHISTLER) -#else -# define machine_is_whistler() (0) -#endif - -#ifdef CONFIG_MACH_ASL_PHOENIX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ASL_PHOENIX -# endif -# define machine_is_asl_phoenix() (machine_arch_type == MACH_TYPE_ASL_PHOENIX) -#else -# define machine_is_asl_phoenix() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263OTLITE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263OTLITE -# endif -# define machine_is_at91sam9263otlite() (machine_arch_type == MACH_TYPE_AT91SAM9263OTLITE) -#else -# define machine_is_at91sam9263otlite() (0) -#endif - -#ifdef CONFIG_MACH_DDPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DDPLUG -# endif -# define machine_is_ddplug() (machine_arch_type == MACH_TYPE_DDPLUG) -#else -# define machine_is_ddplug() (0) -#endif - -#ifdef CONFIG_MACH_D2PLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_D2PLUG -# endif -# define machine_is_d2plug() (machine_arch_type == MACH_TYPE_D2PLUG) -#else -# define machine_is_d2plug() (0) -#endif - -#ifdef CONFIG_MACH_KZM9D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KZM9D -# endif -# define machine_is_kzm9d() (machine_arch_type == MACH_TYPE_KZM9D) -#else -# define machine_is_kzm9d() (0) -#endif - -#ifdef CONFIG_MACH_VERDI_LTE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERDI_LTE -# endif -# define machine_is_verdi_lte() (machine_arch_type == MACH_TYPE_VERDI_LTE) -#else -# define machine_is_verdi_lte() (0) -#endif - -#ifdef CONFIG_MACH_NANOZOOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NANOZOOM -# endif -# define machine_is_nanozoom() (machine_arch_type == MACH_TYPE_NANOZOOM) -#else -# define machine_is_nanozoom() (0) -#endif - -#ifdef CONFIG_MACH_DM3730_SOM_LV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM3730_SOM_LV -# endif -# define machine_is_dm3730_som_lv() (machine_arch_type == MACH_TYPE_DM3730_SOM_LV) -#else -# define machine_is_dm3730_som_lv() (0) -#endif - -#ifdef CONFIG_MACH_DM3730_TORPEDO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM3730_TORPEDO -# endif -# define machine_is_dm3730_torpedo() (machine_arch_type == MACH_TYPE_DM3730_TORPEDO) -#else -# define machine_is_dm3730_torpedo() (0) -#endif - -#ifdef CONFIG_MACH_ANCHOVY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ANCHOVY -# endif -# define machine_is_anchovy() (machine_arch_type == MACH_TYPE_ANCHOVY) -#else -# define machine_is_anchovy() (0) -#endif - -#ifdef CONFIG_MACH_RE2REV20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RE2REV20 -# endif -# define machine_is_re2rev20() (machine_arch_type == MACH_TYPE_RE2REV20) -#else -# define machine_is_re2rev20() (0) -#endif - -#ifdef CONFIG_MACH_RE2REV21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RE2REV21 -# endif -# define machine_is_re2rev21() (machine_arch_type == MACH_TYPE_RE2REV21) -#else -# define machine_is_re2rev21() (0) -#endif - -#ifdef CONFIG_MACH_CNS21XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNS21XX -# endif -# define machine_is_cns21xx() (machine_arch_type == MACH_TYPE_CNS21XX) -#else -# define machine_is_cns21xx() (0) -#endif - -#ifdef CONFIG_MACH_RIDER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RIDER -# endif -# define machine_is_rider() (machine_arch_type == MACH_TYPE_RIDER) -#else -# define machine_is_rider() (0) -#endif - -#ifdef CONFIG_MACH_NSK330 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSK330 -# endif -# define machine_is_nsk330() (machine_arch_type == MACH_TYPE_NSK330) -#else -# define machine_is_nsk330() (0) -#endif - -#ifdef CONFIG_MACH_CNS2133EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CNS2133EVB -# endif -# define machine_is_cns2133evb() (machine_arch_type == MACH_TYPE_CNS2133EVB) -#else -# define machine_is_cns2133evb() (0) -#endif - -#ifdef CONFIG_MACH_Z3_816X_MOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_816X_MOD -# endif -# define machine_is_z3_816x_mod() (machine_arch_type == MACH_TYPE_Z3_816X_MOD) -#else -# define machine_is_z3_816x_mod() (0) -#endif - -#ifdef CONFIG_MACH_Z3_814X_MOD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_Z3_814X_MOD -# endif -# define machine_is_z3_814x_mod() (machine_arch_type == MACH_TYPE_Z3_814X_MOD) -#else -# define machine_is_z3_814x_mod() (0) -#endif - -#ifdef CONFIG_MACH_BEECT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BEECT -# endif -# define machine_is_beect() (machine_arch_type == MACH_TYPE_BEECT) -#else -# define machine_is_beect() (0) -#endif - -#ifdef CONFIG_MACH_DMA_THUNDERBUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DMA_THUNDERBUG -# endif -# define machine_is_dma_thunderbug() (machine_arch_type == MACH_TYPE_DMA_THUNDERBUG) -#else -# define machine_is_dma_thunderbug() (0) -#endif - -#ifdef CONFIG_MACH_OMN_AT91SAM9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMN_AT91SAM9G20 -# endif -# define machine_is_omn_at91sam9g20() (machine_arch_type == MACH_TYPE_OMN_AT91SAM9G20) -#else -# define machine_is_omn_at91sam9g20() (0) -#endif - -#ifdef CONFIG_MACH_MX25_E2S_UC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX25_E2S_UC -# endif -# define machine_is_mx25_e2s_uc() (machine_arch_type == MACH_TYPE_MX25_E2S_UC) -#else -# define machine_is_mx25_e2s_uc() (0) -#endif - -#ifdef CONFIG_MACH_MIONE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIONE -# endif -# define machine_is_mione() (machine_arch_type == MACH_TYPE_MIONE) -#else -# define machine_is_mione() (0) -#endif - -#ifdef CONFIG_MACH_TOP9000_TCU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOP9000_TCU -# endif -# define machine_is_top9000_tcu() (machine_arch_type == MACH_TYPE_TOP9000_TCU) -#else -# define machine_is_top9000_tcu() (0) -#endif - -#ifdef CONFIG_MACH_TOP9000_BSL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TOP9000_BSL -# endif -# define machine_is_top9000_bsl() (machine_arch_type == MACH_TYPE_TOP9000_BSL) -#else -# define machine_is_top9000_bsl() (0) -#endif - -#ifdef CONFIG_MACH_KINGDOM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KINGDOM -# endif -# define machine_is_kingdom() (machine_arch_type == MACH_TYPE_KINGDOM) -#else -# define machine_is_kingdom() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO460 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO460 -# endif -# define machine_is_armadillo460() (machine_arch_type == MACH_TYPE_ARMADILLO460) -#else -# define machine_is_armadillo460() (0) -#endif - -#ifdef CONFIG_MACH_LQ2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LQ2 -# endif -# define machine_is_lq2() (machine_arch_type == MACH_TYPE_LQ2) -#else -# define machine_is_lq2() (0) -#endif - -#ifdef CONFIG_MACH_SWEDA_TMS2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWEDA_TMS2 -# endif -# define machine_is_sweda_tms2() (machine_arch_type == MACH_TYPE_SWEDA_TMS2) -#else -# define machine_is_sweda_tms2() (0) -#endif - -#ifdef CONFIG_MACH_MX53_LOCO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX53_LOCO -# endif -# define machine_is_mx53_loco() (machine_arch_type == MACH_TYPE_MX53_LOCO) -#else -# define machine_is_mx53_loco() (0) -#endif - -#ifdef CONFIG_MACH_ACER_A8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_A8 -# endif -# define machine_is_acer_a8() (machine_arch_type == MACH_TYPE_ACER_A8) -#else -# define machine_is_acer_a8() (0) -#endif - -#ifdef CONFIG_MACH_ACER_GAUGUIN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_GAUGUIN -# endif -# define machine_is_acer_gauguin() (machine_arch_type == MACH_TYPE_ACER_GAUGUIN) -#else -# define machine_is_acer_gauguin() (0) -#endif - -#ifdef CONFIG_MACH_GUPPY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GUPPY -# endif -# define machine_is_guppy() (machine_arch_type == MACH_TYPE_GUPPY) -#else -# define machine_is_guppy() (0) -#endif - -#ifdef CONFIG_MACH_MX61_ARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX61_ARD -# endif -# define machine_is_mx61_ard() (machine_arch_type == MACH_TYPE_MX61_ARD) -#else -# define machine_is_mx61_ard() (0) -#endif - -#ifdef CONFIG_MACH_TX53 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TX53 -# endif -# define machine_is_tx53() (machine_arch_type == MACH_TYPE_TX53) -#else -# define machine_is_tx53() (0) -#endif - -#ifdef CONFIG_MACH_OMAPL138_CASE_A3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAPL138_CASE_A3 -# endif -# define machine_is_omapl138_case_a3() (machine_arch_type == MACH_TYPE_OMAPL138_CASE_A3) -#else -# define machine_is_omapl138_case_a3() (0) -#endif - -#ifdef CONFIG_MACH_UEMD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UEMD -# endif -# define machine_is_uemd() (machine_arch_type == MACH_TYPE_UEMD) -#else -# define machine_is_uemd() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX51MUT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX51MUT -# endif -# define machine_is_ccwmx51mut() (machine_arch_type == MACH_TYPE_CCWMX51MUT) -#else -# define machine_is_ccwmx51mut() (0) -#endif - -#ifdef CONFIG_MACH_ROCKHOPPER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROCKHOPPER -# endif -# define machine_is_rockhopper() (machine_arch_type == MACH_TYPE_ROCKHOPPER) -#else -# define machine_is_rockhopper() (0) -#endif - -#ifdef CONFIG_MACH_ENCORE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENCORE -# endif -# define machine_is_encore() (machine_arch_type == MACH_TYPE_ENCORE) -#else -# define machine_is_encore() (0) -#endif - -#ifdef CONFIG_MACH_HKDKC100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HKDKC100 -# endif -# define machine_is_hkdkc100() (machine_arch_type == MACH_TYPE_HKDKC100) -#else -# define machine_is_hkdkc100() (0) -#endif - -#ifdef CONFIG_MACH_TS42XX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS42XX -# endif -# define machine_is_ts42xx() (machine_arch_type == MACH_TYPE_TS42XX) -#else -# define machine_is_ts42xx() (0) -#endif - -#ifdef CONFIG_MACH_AEBL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AEBL -# endif -# define machine_is_aebl() (machine_arch_type == MACH_TYPE_AEBL) -#else -# define machine_is_aebl() (0) -#endif - -#ifdef CONFIG_MACH_WARIO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WARIO -# endif -# define machine_is_wario() (machine_arch_type == MACH_TYPE_WARIO) -#else -# define machine_is_wario() (0) -#endif - -#ifdef CONFIG_MACH_GFS_SPM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GFS_SPM -# endif -# define machine_is_gfs_spm() (machine_arch_type == MACH_TYPE_GFS_SPM) -#else -# define machine_is_gfs_spm() (0) -#endif - -#ifdef CONFIG_MACH_CM_T3730 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CM_T3730 -# endif -# define machine_is_cm_t3730() (machine_arch_type == MACH_TYPE_CM_T3730) -#else -# define machine_is_cm_t3730() (0) -#endif - -#ifdef CONFIG_MACH_ISC3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ISC3 -# endif -# define machine_is_isc3() (machine_arch_type == MACH_TYPE_ISC3) -#else -# define machine_is_isc3() (0) -#endif - -#ifdef CONFIG_MACH_RASCAL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RASCAL -# endif -# define machine_is_rascal() (machine_arch_type == MACH_TYPE_RASCAL) -#else -# define machine_is_rascal() (0) -#endif - -#ifdef CONFIG_MACH_HREFV60 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HREFV60 -# endif -# define machine_is_hrefv60() (machine_arch_type == MACH_TYPE_HREFV60) -#else -# define machine_is_hrefv60() (0) -#endif - -#ifdef CONFIG_MACH_TPT_2_0 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TPT_2_0 -# endif -# define machine_is_tpt_2_0() (machine_arch_type == MACH_TYPE_TPT_2_0) -#else -# define machine_is_tpt_2_0() (0) -#endif - -#ifdef CONFIG_MACH_SPLENDOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPLENDOR -# endif -# define machine_is_splendor() (machine_arch_type == MACH_TYPE_SPLENDOR) -#else -# define machine_is_splendor() (0) -#endif - -#ifdef CONFIG_MACH_MSM8X60_QT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8X60_QT -# endif -# define machine_is_msm8x60_qt() (machine_arch_type == MACH_TYPE_MSM8X60_QT) -#else -# define machine_is_msm8x60_qt() (0) -#endif - -#ifdef CONFIG_MACH_HTC_HD_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HTC_HD_MINI -# endif -# define machine_is_htc_hd_mini() (machine_arch_type == MACH_TYPE_HTC_HD_MINI) -#else -# define machine_is_htc_hd_mini() (0) -#endif - -#ifdef CONFIG_MACH_ATHENE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATHENE -# endif -# define machine_is_athene() (machine_arch_type == MACH_TYPE_ATHENE) -#else -# define machine_is_athene() (0) -#endif - -#ifdef CONFIG_MACH_DEEP_R_EK_1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DEEP_R_EK_1 -# endif -# define machine_is_deep_r_ek_1() (machine_arch_type == MACH_TYPE_DEEP_R_EK_1) -#else -# define machine_is_deep_r_ek_1() (0) -#endif - -#ifdef CONFIG_MACH_VIVOW_CT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIVOW_CT -# endif -# define machine_is_vivow_ct() (machine_arch_type == MACH_TYPE_VIVOW_CT) -#else -# define machine_is_vivow_ct() (0) -#endif - -#ifdef CONFIG_MACH_NERY_1000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NERY_1000 -# endif -# define machine_is_nery_1000() (machine_arch_type == MACH_TYPE_NERY_1000) -#else -# define machine_is_nery_1000() (0) -#endif - -#ifdef CONFIG_MACH_RFL109145_SSRV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RFL109145_SSRV -# endif -# define machine_is_rfl109145_ssrv() (machine_arch_type == MACH_TYPE_RFL109145_SSRV) -#else -# define machine_is_rfl109145_ssrv() (0) -#endif - -#ifdef CONFIG_MACH_NMH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NMH -# endif -# define machine_is_nmh() (machine_arch_type == MACH_TYPE_NMH) -#else -# define machine_is_nmh() (0) -#endif - -#ifdef CONFIG_MACH_WN802T -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WN802T -# endif -# define machine_is_wn802t() (machine_arch_type == MACH_TYPE_WN802T) -#else -# define machine_is_wn802t() (0) -#endif - -#ifdef CONFIG_MACH_DRAGONET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DRAGONET -# endif -# define machine_is_dragonet() (machine_arch_type == MACH_TYPE_DRAGONET) -#else -# define machine_is_dragonet() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9263DESK16L -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9263DESK16L -# endif -# define machine_is_at91sam9263desk16l() (machine_arch_type == MACH_TYPE_AT91SAM9263DESK16L) -#else -# define machine_is_at91sam9263desk16l() (0) -#endif - -#ifdef CONFIG_MACH_BCMHANA_SV -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMHANA_SV -# endif -# define machine_is_bcmhana_sv() (machine_arch_type == MACH_TYPE_BCMHANA_SV) -#else -# define machine_is_bcmhana_sv() (0) -#endif - -#ifdef CONFIG_MACH_BCMHANA_TABLET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BCMHANA_TABLET -# endif -# define machine_is_bcmhana_tablet() (machine_arch_type == MACH_TYPE_BCMHANA_TABLET) -#else -# define machine_is_bcmhana_tablet() (0) -#endif - -#ifdef CONFIG_MACH_KOI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KOI -# endif -# define machine_is_koi() (machine_arch_type == MACH_TYPE_KOI) -#else -# define machine_is_koi() (0) -#endif - -#ifdef CONFIG_MACH_TS4800 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TS4800 -# endif -# define machine_is_ts4800() (machine_arch_type == MACH_TYPE_TS4800) -#else -# define machine_is_ts4800() (0) -#endif - -#ifdef CONFIG_MACH_TQMA9263 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TQMA9263 -# endif -# define machine_is_tqma9263() (machine_arch_type == MACH_TYPE_TQMA9263) -#else -# define machine_is_tqma9263() (0) -#endif - -#ifdef CONFIG_MACH_HOLIDAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HOLIDAY -# endif -# define machine_is_holiday() (machine_arch_type == MACH_TYPE_HOLIDAY) -#else -# define machine_is_holiday() (0) -#endif - -#ifdef CONFIG_MACH_DMA6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DMA6410 -# endif -# define machine_is_dma_6410() (machine_arch_type == MACH_TYPE_DMA6410) -#else -# define machine_is_dma_6410() (0) -#endif - -#ifdef CONFIG_MACH_PCATS_OVERLAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCATS_OVERLAY -# endif -# define machine_is_pcats_overlay() (machine_arch_type == MACH_TYPE_PCATS_OVERLAY) -#else -# define machine_is_pcats_overlay() (0) -#endif - -#ifdef CONFIG_MACH_HWGW6410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HWGW6410 -# endif -# define machine_is_hwgw6410() (machine_arch_type == MACH_TYPE_HWGW6410) -#else -# define machine_is_hwgw6410() (0) -#endif - -#ifdef CONFIG_MACH_SHENZHOU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHENZHOU -# endif -# define machine_is_shenzhou() (machine_arch_type == MACH_TYPE_SHENZHOU) -#else -# define machine_is_shenzhou() (0) -#endif - -#ifdef CONFIG_MACH_CWME9210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWME9210 -# endif -# define machine_is_cwme9210() (machine_arch_type == MACH_TYPE_CWME9210) -#else -# define machine_is_cwme9210() (0) -#endif - -#ifdef CONFIG_MACH_CWME9210JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWME9210JS -# endif -# define machine_is_cwme9210js() (machine_arch_type == MACH_TYPE_CWME9210JS) -#else -# define machine_is_cwme9210js() (0) -#endif - -#ifdef CONFIG_MACH_PGS_SITARA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PGS_SITARA -# endif -# define machine_is_pgs_v1() (machine_arch_type == MACH_TYPE_PGS_SITARA) -#else -# define machine_is_pgs_v1() (0) -#endif - -#ifdef CONFIG_MACH_COLIBRI_TEGRA2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2 -# endif -# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2) -#else -# define machine_is_colibri_tegra2() (0) -#endif - -#ifdef CONFIG_MACH_W21 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_W21 -# endif -# define machine_is_w21() (machine_arch_type == MACH_TYPE_W21) -#else -# define machine_is_w21() (0) -#endif - -#ifdef CONFIG_MACH_POLYSAT1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_POLYSAT1 -# endif -# define machine_is_polysat1() (machine_arch_type == MACH_TYPE_POLYSAT1) -#else -# define machine_is_polysat1() (0) -#endif - -#ifdef CONFIG_MACH_DATAWAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DATAWAY -# endif -# define machine_is_dataway() (machine_arch_type == MACH_TYPE_DATAWAY) -#else -# define machine_is_dataway() (0) -#endif - -#ifdef CONFIG_MACH_COBRAL138 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_COBRAL138 -# endif -# define machine_is_cobral138() (machine_arch_type == MACH_TYPE_COBRAL138) -#else -# define machine_is_cobral138() (0) -#endif - -#ifdef CONFIG_MACH_ROVERPCS8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERPCS8 -# endif -# define machine_is_roverpcs8() (machine_arch_type == MACH_TYPE_ROVERPCS8) -#else -# define machine_is_roverpcs8() (0) -#endif - -#ifdef CONFIG_MACH_MARVELC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELC -# endif -# define machine_is_marvelc() (machine_arch_type == MACH_TYPE_MARVELC) -#else -# define machine_is_marvelc() (0) -#endif - -#ifdef CONFIG_MACH_NAVEFIHID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NAVEFIHID -# endif -# define machine_is_navefihid() (machine_arch_type == MACH_TYPE_NAVEFIHID) -#else -# define machine_is_navefihid() (0) -#endif - -#ifdef CONFIG_MACH_DM365_CV100 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM365_CV100 -# endif -# define machine_is_dm365_cv100() (machine_arch_type == MACH_TYPE_DM365_CV100) -#else -# define machine_is_dm365_cv100() (0) -#endif - -#ifdef CONFIG_MACH_ABLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ABLE -# endif -# define machine_is_able() (machine_arch_type == MACH_TYPE_ABLE) -#else -# define machine_is_able() (0) -#endif - -#ifdef CONFIG_MACH_LEGACY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LEGACY -# endif -# define machine_is_legacy() (machine_arch_type == MACH_TYPE_LEGACY) -#else -# define machine_is_legacy() (0) -#endif - -#ifdef CONFIG_MACH_ICONG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ICONG -# endif -# define machine_is_icong() (machine_arch_type == MACH_TYPE_ICONG) -#else -# define machine_is_icong() (0) -#endif - -#ifdef CONFIG_MACH_ROVER_G8 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVER_G8 -# endif -# define machine_is_rover_g8() (machine_arch_type == MACH_TYPE_ROVER_G8) -#else -# define machine_is_rover_g8() (0) -#endif - -#ifdef CONFIG_MACH_T5388P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T5388P -# endif -# define machine_is_t5388p() (machine_arch_type == MACH_TYPE_T5388P) -#else -# define machine_is_t5388p() (0) -#endif - -#ifdef CONFIG_MACH_DINGO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DINGO -# endif -# define machine_is_dingo() (machine_arch_type == MACH_TYPE_DINGO) -#else -# define machine_is_dingo() (0) -#endif - -#ifdef CONFIG_MACH_GOFLEXHOME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOFLEXHOME -# endif -# define machine_is_goflexhome() (machine_arch_type == MACH_TYPE_GOFLEXHOME) -#else -# define machine_is_goflexhome() (0) -#endif - -#ifdef CONFIG_MACH_LANREADYFN511 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LANREADYFN511 -# endif -# define machine_is_lanreadyfn511() (machine_arch_type == MACH_TYPE_LANREADYFN511) -#else -# define machine_is_lanreadyfn511() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3_BAIA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3_BAIA -# endif -# define machine_is_omap3_baia() (machine_arch_type == MACH_TYPE_OMAP3_BAIA) -#else -# define machine_is_omap3_baia() (0) -#endif - -#ifdef CONFIG_MACH_OMAP3SMARTDISPLAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP3SMARTDISPLAY -# endif -# define machine_is_omap3smartdisplay() (machine_arch_type == MACH_TYPE_OMAP3SMARTDISPLAY) -#else -# define machine_is_omap3smartdisplay() (0) -#endif - -#ifdef CONFIG_MACH_XILINX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XILINX -# endif -# define machine_is_xilinx() (machine_arch_type == MACH_TYPE_XILINX) -#else -# define machine_is_xilinx() (0) -#endif - -#ifdef CONFIG_MACH_A2F -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_A2F -# endif -# define machine_is_a2f() (machine_arch_type == MACH_TYPE_A2F) -#else -# define machine_is_a2f() (0) -#endif - -#ifdef CONFIG_MACH_SKY25 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SKY25 -# endif -# define machine_is_sky25() (machine_arch_type == MACH_TYPE_SKY25) -#else -# define machine_is_sky25() (0) -#endif - -#ifdef CONFIG_MACH_CCMX53 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCMX53 -# endif -# define machine_is_ccmx53() (machine_arch_type == MACH_TYPE_CCMX53) -#else -# define machine_is_ccmx53() (0) -#endif - -#ifdef CONFIG_MACH_CCMX53JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCMX53JS -# endif -# define machine_is_ccmx53js() (machine_arch_type == MACH_TYPE_CCMX53JS) -#else -# define machine_is_ccmx53js() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX53 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX53 -# endif -# define machine_is_ccwmx53() (machine_arch_type == MACH_TYPE_CCWMX53) -#else -# define machine_is_ccwmx53() (0) -#endif - -#ifdef CONFIG_MACH_CCWMX53JS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CCWMX53JS -# endif -# define machine_is_ccwmx53js() (machine_arch_type == MACH_TYPE_CCWMX53JS) -#else -# define machine_is_ccwmx53js() (0) -#endif - -#ifdef CONFIG_MACH_FRISMS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_FRISMS -# endif -# define machine_is_frisms() (machine_arch_type == MACH_TYPE_FRISMS) -#else -# define machine_is_frisms() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27A_FFA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27A_FFA -# endif -# define machine_is_msm7x27a_ffa() (machine_arch_type == MACH_TYPE_MSM7X27A_FFA) -#else -# define machine_is_msm7x27a_ffa() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27A_SURF -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27A_SURF -# endif -# define machine_is_msm7x27a_surf() (machine_arch_type == MACH_TYPE_MSM7X27A_SURF) -#else -# define machine_is_msm7x27a_surf() (0) -#endif - -#ifdef CONFIG_MACH_MSM7X27A_RUMI3 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM7X27A_RUMI3 -# endif -# define machine_is_msm7x27a_rumi3() (machine_arch_type == MACH_TYPE_MSM7X27A_RUMI3) -#else -# define machine_is_msm7x27a_rumi3() (0) -#endif - -#ifdef CONFIG_MACH_DIMMSAM9G20 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIMMSAM9G20 -# endif -# define machine_is_dimmsam9g20() (machine_arch_type == MACH_TYPE_DIMMSAM9G20) -#else -# define machine_is_dimmsam9g20() (0) -#endif - -#ifdef CONFIG_MACH_DIMM_IMX28 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIMM_IMX28 -# endif -# define machine_is_dimm_imx28() (machine_arch_type == MACH_TYPE_DIMM_IMX28) -#else -# define machine_is_dimm_imx28() (0) -#endif - -#ifdef CONFIG_MACH_AMK_A4 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AMK_A4 -# endif -# define machine_is_amk_a4() (machine_arch_type == MACH_TYPE_AMK_A4) -#else -# define machine_is_amk_a4() (0) -#endif - -#ifdef CONFIG_MACH_GNET_SGME -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GNET_SGME -# endif -# define machine_is_gnet_sgme() (machine_arch_type == MACH_TYPE_GNET_SGME) -#else -# define machine_is_gnet_sgme() (0) -#endif - -#ifdef CONFIG_MACH_SHOOTER_U -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHOOTER_U -# endif -# define machine_is_shooter_u() (machine_arch_type == MACH_TYPE_SHOOTER_U) -#else -# define machine_is_shooter_u() (0) -#endif - -#ifdef CONFIG_MACH_VMX53 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VMX53 -# endif -# define machine_is_vmx53() (machine_arch_type == MACH_TYPE_VMX53) -#else -# define machine_is_vmx53() (0) -#endif - -#ifdef CONFIG_MACH_RHINO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RHINO -# endif -# define machine_is_rhino() (machine_arch_type == MACH_TYPE_RHINO) -#else -# define machine_is_rhino() (0) -#endif - -#ifdef CONFIG_MACH_ARMLEX4210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMLEX4210 -# endif -# define machine_is_armlex4210() (machine_arch_type == MACH_TYPE_ARMLEX4210) -#else -# define machine_is_armlex4210() (0) -#endif - -#ifdef CONFIG_MACH_SWARCOEXTMODEM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SWARCOEXTMODEM -# endif -# define machine_is_swarcoextmodem() (machine_arch_type == MACH_TYPE_SWARCOEXTMODEM) -#else -# define machine_is_swarcoextmodem() (0) -#endif - -#ifdef CONFIG_MACH_SNOWBALL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SNOWBALL -# endif -# define machine_is_snowball() (machine_arch_type == MACH_TYPE_SNOWBALL) -#else -# define machine_is_snowball() (0) -#endif - -#ifdef CONFIG_MACH_PCM049 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PCM049 -# endif -# define machine_is_pcm049() (machine_arch_type == MACH_TYPE_PCM049) -#else -# define machine_is_pcm049() (0) -#endif - -#ifdef CONFIG_MACH_VIGOR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIGOR -# endif -# define machine_is_vigor() (machine_arch_type == MACH_TYPE_VIGOR) -#else -# define machine_is_vigor() (0) -#endif - -#ifdef CONFIG_MACH_OSLO_AMUNDSEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OSLO_AMUNDSEN -# endif -# define machine_is_oslo_amundsen() (machine_arch_type == MACH_TYPE_OSLO_AMUNDSEN) -#else -# define machine_is_oslo_amundsen() (0) -#endif - -#ifdef CONFIG_MACH_GSL_DIAMOND -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GSL_DIAMOND -# endif -# define machine_is_gsl_diamond() (machine_arch_type == MACH_TYPE_GSL_DIAMOND) -#else -# define machine_is_gsl_diamond() (0) -#endif - -#ifdef CONFIG_MACH_CV2201 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CV2201 -# endif -# define machine_is_cv2201() (machine_arch_type == MACH_TYPE_CV2201) -#else -# define machine_is_cv2201() (0) -#endif - -#ifdef CONFIG_MACH_CV2202 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CV2202 -# endif -# define machine_is_cv2202() (machine_arch_type == MACH_TYPE_CV2202) -#else -# define machine_is_cv2202() (0) -#endif - -#ifdef CONFIG_MACH_CV2203 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CV2203 -# endif -# define machine_is_cv2203() (machine_arch_type == MACH_TYPE_CV2203) -#else -# define machine_is_cv2203() (0) -#endif - -#ifdef CONFIG_MACH_VIT_IBOX -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIT_IBOX -# endif -# define machine_is_vit_ibox() (machine_arch_type == MACH_TYPE_VIT_IBOX) -#else -# define machine_is_vit_ibox() (0) -#endif - -#ifdef CONFIG_MACH_DM6441_ESP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM6441_ESP -# endif -# define machine_is_dm6441_esp() (machine_arch_type == MACH_TYPE_DM6441_ESP) -#else -# define machine_is_dm6441_esp() (0) -#endif - -#ifdef CONFIG_MACH_AT91SAM9X5EK -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AT91SAM9X5EK -# endif -# define machine_is_at91sam9x5ek() (machine_arch_type == MACH_TYPE_AT91SAM9X5EK) -#else -# define machine_is_at91sam9x5ek() (0) -#endif - -#ifdef CONFIG_MACH_LIBRA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_LIBRA -# endif -# define machine_is_libra() (machine_arch_type == MACH_TYPE_LIBRA) -#else -# define machine_is_libra() (0) -#endif - -#ifdef CONFIG_MACH_EASYCRRH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EASYCRRH -# endif -# define machine_is_easycrrh() (machine_arch_type == MACH_TYPE_EASYCRRH) -#else -# define machine_is_easycrrh() (0) -#endif - -#ifdef CONFIG_MACH_TRIPEL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRIPEL -# endif -# define machine_is_tripel() (machine_arch_type == MACH_TYPE_TRIPEL) -#else -# define machine_is_tripel() (0) -#endif - -#ifdef CONFIG_MACH_ENDIAN_MINI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ENDIAN_MINI -# endif -# define machine_is_endian_mini() (machine_arch_type == MACH_TYPE_ENDIAN_MINI) -#else -# define machine_is_endian_mini() (0) -#endif - -#ifdef CONFIG_MACH_XILINX_EP107 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XILINX_EP107 -# endif -# define machine_is_xilinx_ep107() (machine_arch_type == MACH_TYPE_XILINX_EP107) -#else -# define machine_is_xilinx_ep107() (0) -#endif - -#ifdef CONFIG_MACH_NURI -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NURI -# endif -# define machine_is_nuri() (machine_arch_type == MACH_TYPE_NURI) -#else -# define machine_is_nuri() (0) -#endif - -#ifdef CONFIG_MACH_JANUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_JANUS -# endif -# define machine_is_janus() (machine_arch_type == MACH_TYPE_JANUS) -#else -# define machine_is_janus() (0) -#endif - -#ifdef CONFIG_MACH_DDNAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DDNAS -# endif -# define machine_is_ddnas() (machine_arch_type == MACH_TYPE_DDNAS) -#else -# define machine_is_ddnas() (0) -#endif - -#ifdef CONFIG_MACH_TAG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAG -# endif -# define machine_is_tag() (machine_arch_type == MACH_TYPE_TAG) -#else -# define machine_is_tag() (0) -#endif - -#ifdef CONFIG_MACH_TAGW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TAGW -# endif -# define machine_is_tagw() (machine_arch_type == MACH_TYPE_TAGW) -#else -# define machine_is_tagw() (0) -#endif - -#ifdef CONFIG_MACH_NITROGEN_VM_IMX51 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NITROGEN_VM_IMX51 -# endif -# define machine_is_nitrogen_vm_imx51() (machine_arch_type == MACH_TYPE_NITROGEN_VM_IMX51) -#else -# define machine_is_nitrogen_vm_imx51() (0) -#endif - -#ifdef CONFIG_MACH_VIPRINET -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VIPRINET -# endif -# define machine_is_viprinet() (machine_arch_type == MACH_TYPE_VIPRINET) -#else -# define machine_is_viprinet() (0) -#endif - -#ifdef CONFIG_MACH_BOCKW -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BOCKW -# endif -# define machine_is_bockw() (machine_arch_type == MACH_TYPE_BOCKW) -#else -# define machine_is_bockw() (0) -#endif - -#ifdef CONFIG_MACH_EVA2000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EVA2000 -# endif -# define machine_is_eva2000() (machine_arch_type == MACH_TYPE_EVA2000) -#else -# define machine_is_eva2000() (0) -#endif - -#ifdef CONFIG_MACH_STEELYARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_STEELYARD -# endif -# define machine_is_steelyard() (machine_arch_type == MACH_TYPE_STEELYARD) -#else -# define machine_is_steelyard() (0) -#endif - -#ifdef CONFIG_MACH_MACH_SDH001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_SDH001 -# endif -# define machine_is_sdh001() (machine_arch_type == MACH_TYPE_MACH_SDH001) -#else -# define machine_is_sdh001() (0) -#endif - -#ifdef CONFIG_MACH_NSSLSBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NSSLSBOARD -# endif -# define machine_is_nsslsboard() (machine_arch_type == MACH_TYPE_NSSLSBOARD) -#else -# define machine_is_nsslsboard() (0) -#endif - -#ifdef CONFIG_MACH_GENEVA_B5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GENEVA_B5 -# endif -# define machine_is_geneva_b5() (machine_arch_type == MACH_TYPE_GENEVA_B5) -#else -# define machine_is_geneva_b5() (0) -#endif - -#ifdef CONFIG_MACH_SPEAR1340 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SPEAR1340 -# endif -# define machine_is_spear1340() (machine_arch_type == MACH_TYPE_SPEAR1340) -#else -# define machine_is_spear1340() (0) -#endif - -#ifdef CONFIG_MACH_REXMAS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_REXMAS -# endif -# define machine_is_rexmas() (machine_arch_type == MACH_TYPE_REXMAS) -#else -# define machine_is_rexmas() (0) -#endif - -#ifdef CONFIG_MACH_MSM8960_CDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8960_CDP -# endif -# define machine_is_msm8960_cdp() (machine_arch_type == MACH_TYPE_MSM8960_CDP) -#else -# define machine_is_msm8960_cdp() (0) -#endif - -#ifdef CONFIG_MACH_MSM8960_MDP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8960_MDP -# endif -# define machine_is_msm8960_mdp() (machine_arch_type == MACH_TYPE_MSM8960_MDP) -#else -# define machine_is_msm8960_mdp() (0) -#endif - -#ifdef CONFIG_MACH_MSM8960_FLUID -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8960_FLUID -# endif -# define machine_is_msm8960_fluid() (machine_arch_type == MACH_TYPE_MSM8960_FLUID) -#else -# define machine_is_msm8960_fluid() (0) -#endif - -#ifdef CONFIG_MACH_MSM8960_APQ -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MSM8960_APQ -# endif -# define machine_is_msm8960_apq() (machine_arch_type == MACH_TYPE_MSM8960_APQ) -#else -# define machine_is_msm8960_apq() (0) -#endif - -#ifdef CONFIG_MACH_HELIOS_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HELIOS_V2 -# endif -# define machine_is_helios_v2() (machine_arch_type == MACH_TYPE_HELIOS_V2) -#else -# define machine_is_helios_v2() (0) -#endif - -#ifdef CONFIG_MACH_MIF10P -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MIF10P -# endif -# define machine_is_mif10p() (machine_arch_type == MACH_TYPE_MIF10P) -#else -# define machine_is_mif10p() (0) -#endif - -#ifdef CONFIG_MACH_IAM28 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_IAM28 -# endif -# define machine_is_iam28() (machine_arch_type == MACH_TYPE_IAM28) -#else -# define machine_is_iam28() (0) -#endif - -#ifdef CONFIG_MACH_PICASSO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICASSO -# endif -# define machine_is_picasso() (machine_arch_type == MACH_TYPE_PICASSO) -#else -# define machine_is_picasso() (0) -#endif - -#ifdef CONFIG_MACH_MR301A -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MR301A -# endif -# define machine_is_mr301a() (machine_arch_type == MACH_TYPE_MR301A) -#else -# define machine_is_mr301a() (0) -#endif - -#ifdef CONFIG_MACH_NOTLE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NOTLE -# endif -# define machine_is_notle() (machine_arch_type == MACH_TYPE_NOTLE) -#else -# define machine_is_notle() (0) -#endif - -#ifdef CONFIG_MACH_EELX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EELX2 -# endif -# define machine_is_eelx2() (machine_arch_type == MACH_TYPE_EELX2) -#else -# define machine_is_eelx2() (0) -#endif - -#ifdef CONFIG_MACH_MOON -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MOON -# endif -# define machine_is_moon() (machine_arch_type == MACH_TYPE_MOON) -#else -# define machine_is_moon() (0) -#endif - -#ifdef CONFIG_MACH_RUBY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_RUBY -# endif -# define machine_is_ruby() (machine_arch_type == MACH_TYPE_RUBY) -#else -# define machine_is_ruby() (0) -#endif - -#ifdef CONFIG_MACH_GOLDENGATE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GOLDENGATE -# endif -# define machine_is_goldengate() (machine_arch_type == MACH_TYPE_GOLDENGATE) -#else -# define machine_is_goldengate() (0) -#endif - -#ifdef CONFIG_MACH_CTBU_GEN2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTBU_GEN2 -# endif -# define machine_is_ctbu_gen2() (machine_arch_type == MACH_TYPE_CTBU_GEN2) -#else -# define machine_is_ctbu_gen2() (0) -#endif - -#ifdef CONFIG_MACH_KMP_AM17_01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KMP_AM17_01 -# endif -# define machine_is_kmp_am17_01() (machine_arch_type == MACH_TYPE_KMP_AM17_01) -#else -# define machine_is_kmp_am17_01() (0) -#endif - -#ifdef CONFIG_MACH_WTPLUG -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WTPLUG -# endif -# define machine_is_wtplug() (machine_arch_type == MACH_TYPE_WTPLUG) -#else -# define machine_is_wtplug() (0) -#endif - -#ifdef CONFIG_MACH_MX27SU2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX27SU2 -# endif -# define machine_is_mx27su2() (machine_arch_type == MACH_TYPE_MX27SU2) -#else -# define machine_is_mx27su2() (0) -#endif - -#ifdef CONFIG_MACH_NB31 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NB31 -# endif -# define machine_is_nb31() (machine_arch_type == MACH_TYPE_NB31) -#else -# define machine_is_nb31() (0) -#endif - -#ifdef CONFIG_MACH_HJSDU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HJSDU -# endif -# define machine_is_hjsdu() (machine_arch_type == MACH_TYPE_HJSDU) -#else -# define machine_is_hjsdu() (0) -#endif - -#ifdef CONFIG_MACH_TD3_REV1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TD3_REV1 -# endif -# define machine_is_td3_rev1() (machine_arch_type == MACH_TYPE_TD3_REV1) -#else -# define machine_is_td3_rev1() (0) -#endif - -#ifdef CONFIG_MACH_EAG_CI4000 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EAG_CI4000 -# endif -# define machine_is_eag_ci4000() (machine_arch_type == MACH_TYPE_EAG_CI4000) -#else -# define machine_is_eag_ci4000() (0) -#endif - -#ifdef CONFIG_MACH_NET5BIG_NAND_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET5BIG_NAND_V2 -# endif -# define machine_is_net5big_nand_v2() (machine_arch_type == MACH_TYPE_NET5BIG_NAND_V2) -#else -# define machine_is_net5big_nand_v2() (0) -#endif - -#ifdef CONFIG_MACH_CPX2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CPX2 -# endif -# define machine_is_cpx2() (machine_arch_type == MACH_TYPE_CPX2) -#else -# define machine_is_cpx2() (0) -#endif - -#ifdef CONFIG_MACH_NET2BIG_NAND_V2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NET2BIG_NAND_V2 -# endif -# define machine_is_net2big_nand_v2() (machine_arch_type == MACH_TYPE_NET2BIG_NAND_V2) -#else -# define machine_is_net2big_nand_v2() (0) -#endif - -#ifdef CONFIG_MACH_ECUV5 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ECUV5 -# endif -# define machine_is_ecuv5() (machine_arch_type == MACH_TYPE_ECUV5) -#else -# define machine_is_ecuv5() (0) -#endif - -#ifdef CONFIG_MACH_HSGX6D -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_HSGX6D -# endif -# define machine_is_hsgx6d() (machine_arch_type == MACH_TYPE_HSGX6D) -#else -# define machine_is_hsgx6d() (0) -#endif - -#ifdef CONFIG_MACH_DAWAD7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DAWAD7 -# endif -# define machine_is_dawad7() (machine_arch_type == MACH_TYPE_DAWAD7) -#else -# define machine_is_dawad7() (0) -#endif - -#ifdef CONFIG_MACH_SAM9REPEATER -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SAM9REPEATER -# endif -# define machine_is_sam9repeater() (machine_arch_type == MACH_TYPE_SAM9REPEATER) -#else -# define machine_is_sam9repeater() (0) -#endif - -#ifdef CONFIG_MACH_GT_I5700 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_GT_I5700 -# endif -# define machine_is_gt_i5700() (machine_arch_type == MACH_TYPE_GT_I5700) -#else -# define machine_is_gt_i5700() (0) -#endif - -#ifdef CONFIG_MACH_CTERA_PLUG_C2 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CTERA_PLUG_C2 -# endif -# define machine_is_ctera_plug_c2() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C2) -#else -# define machine_is_ctera_plug_c2() (0) -#endif - -#ifdef CONFIG_MACH_MARVELCT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MARVELCT -# endif -# define machine_is_marvelct() (machine_arch_type == MACH_TYPE_MARVELCT) -#else -# define machine_is_marvelct() (0) -#endif - -#ifdef CONFIG_MACH_AG11005 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AG11005 -# endif -# define machine_is_ag11005() (machine_arch_type == MACH_TYPE_AG11005) -#else -# define machine_is_ag11005() (0) -#endif - -#ifdef CONFIG_MACH_VANGOGH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VANGOGH -# endif -# define machine_is_vangogh() (machine_arch_type == MACH_TYPE_VANGOGH) -#else -# define machine_is_vangogh() (0) -#endif - -#ifdef CONFIG_MACH_MATRIX505 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MATRIX505 -# endif -# define machine_is_matrix505() (machine_arch_type == MACH_TYPE_MATRIX505) -#else -# define machine_is_matrix505() (0) -#endif - -#ifdef CONFIG_MACH_OCE_NIGMA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OCE_NIGMA -# endif -# define machine_is_oce_nigma() (machine_arch_type == MACH_TYPE_OCE_NIGMA) -#else -# define machine_is_oce_nigma() (0) -#endif - -#ifdef CONFIG_MACH_T55 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_T55 -# endif -# define machine_is_t55() (machine_arch_type == MACH_TYPE_T55) -#else -# define machine_is_t55() (0) -#endif - -#ifdef CONFIG_MACH_BIO3K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BIO3K -# endif -# define machine_is_bio3k() (machine_arch_type == MACH_TYPE_BIO3K) -#else -# define machine_is_bio3k() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESSCT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESSCT -# endif -# define machine_is_expressct() (machine_arch_type == MACH_TYPE_EXPRESSCT) -#else -# define machine_is_expressct() (0) -#endif - -#ifdef CONFIG_MACH_CARDHU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CARDHU -# endif -# define machine_is_cardhu() (machine_arch_type == MACH_TYPE_CARDHU) -#else -# define machine_is_cardhu() (0) -#endif - -#ifdef CONFIG_MACH_ARUBA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARUBA -# endif -# define machine_is_aruba() (machine_arch_type == MACH_TYPE_ARUBA) -#else -# define machine_is_aruba() (0) -#endif - -#ifdef CONFIG_MACH_BONAIRE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BONAIRE -# endif -# define machine_is_bonaire() (machine_arch_type == MACH_TYPE_BONAIRE) -#else -# define machine_is_bonaire() (0) -#endif - -#ifdef CONFIG_MACH_NUC700EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC700EVB -# endif -# define machine_is_nuc700evb() (machine_arch_type == MACH_TYPE_NUC700EVB) -#else -# define machine_is_nuc700evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC710EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC710EVB -# endif -# define machine_is_nuc710evb() (machine_arch_type == MACH_TYPE_NUC710EVB) -#else -# define machine_is_nuc710evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC740EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC740EVB -# endif -# define machine_is_nuc740evb() (machine_arch_type == MACH_TYPE_NUC740EVB) -#else -# define machine_is_nuc740evb() (0) -#endif - -#ifdef CONFIG_MACH_NUC745EVB -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NUC745EVB -# endif -# define machine_is_nuc745evb() (machine_arch_type == MACH_TYPE_NUC745EVB) -#else -# define machine_is_nuc745evb() (0) -#endif - -#ifdef CONFIG_MACH_TRANSCEDE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRANSCEDE -# endif -# define machine_is_transcede() (machine_arch_type == MACH_TYPE_TRANSCEDE) -#else -# define machine_is_transcede() (0) -#endif - -#ifdef CONFIG_MACH_MORA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MORA -# endif -# define machine_is_mora() (machine_arch_type == MACH_TYPE_MORA) -#else -# define machine_is_mora() (0) -#endif - -#ifdef CONFIG_MACH_NDA_EVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_NDA_EVM -# endif -# define machine_is_nda_evm() (machine_arch_type == MACH_TYPE_NDA_EVM) -#else -# define machine_is_nda_evm() (0) -#endif - -#ifdef CONFIG_MACH_TIMU -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TIMU -# endif -# define machine_is_timu() (machine_arch_type == MACH_TYPE_TIMU) -#else -# define machine_is_timu() (0) -#endif - -#ifdef CONFIG_MACH_EXPRESSH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EXPRESSH -# endif -# define machine_is_expressh() (machine_arch_type == MACH_TYPE_EXPRESSH) -#else -# define machine_is_expressh() (0) -#endif - -#ifdef CONFIG_MACH_VERIDIS_A300 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_VERIDIS_A300 -# endif -# define machine_is_veridis_a300() (machine_arch_type == MACH_TYPE_VERIDIS_A300) -#else -# define machine_is_veridis_a300() (0) -#endif - -#ifdef CONFIG_MACH_DM368_LEOPARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DM368_LEOPARD -# endif -# define machine_is_dm368_leopard() (machine_arch_type == MACH_TYPE_DM368_LEOPARD) -#else -# define machine_is_dm368_leopard() (0) -#endif - -#ifdef CONFIG_MACH_OMAP_MCOP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP_MCOP -# endif -# define machine_is_omap_mcop() (machine_arch_type == MACH_TYPE_OMAP_MCOP) -#else -# define machine_is_omap_mcop() (0) -#endif - -#ifdef CONFIG_MACH_TRITIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TRITIP -# endif -# define machine_is_tritip() (machine_arch_type == MACH_TYPE_TRITIP) -#else -# define machine_is_tritip() (0) -#endif - -#ifdef CONFIG_MACH_SM1K -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SM1K -# endif -# define machine_is_sm1k() (machine_arch_type == MACH_TYPE_SM1K) -#else -# define machine_is_sm1k() (0) -#endif - -#ifdef CONFIG_MACH_MONCH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MONCH -# endif -# define machine_is_monch() (machine_arch_type == MACH_TYPE_MONCH) -#else -# define machine_is_monch() (0) -#endif - -#ifdef CONFIG_MACH_CURACAO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CURACAO -# endif -# define machine_is_curacao() (machine_arch_type == MACH_TYPE_CURACAO) -#else -# define machine_is_curacao() (0) -#endif - -#ifdef CONFIG_MACH_ORIGEN -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ORIGEN -# endif -# define machine_is_origen() (machine_arch_type == MACH_TYPE_ORIGEN) -#else -# define machine_is_origen() (0) -#endif - -#ifdef CONFIG_MACH_EPC10 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_EPC10 -# endif -# define machine_is_epc10() (machine_arch_type == MACH_TYPE_EPC10) -#else -# define machine_is_epc10() (0) -#endif - -#ifdef CONFIG_MACH_SGH_I740 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SGH_I740 -# endif -# define machine_is_sgh_i740() (machine_arch_type == MACH_TYPE_SGH_I740) -#else -# define machine_is_sgh_i740() (0) -#endif - -#ifdef CONFIG_MACH_TUNA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TUNA -# endif -# define machine_is_tuna() (machine_arch_type == MACH_TYPE_TUNA) -#else -# define machine_is_tuna() (0) -#endif - -#ifdef CONFIG_MACH_MX51_TULIP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_TULIP -# endif -# define machine_is_mx51_tulip() (machine_arch_type == MACH_TYPE_MX51_TULIP) -#else -# define machine_is_mx51_tulip() (0) -#endif - -#ifdef CONFIG_MACH_MX51_ASTER7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_ASTER7 -# endif -# define machine_is_mx51_aster7() (machine_arch_type == MACH_TYPE_MX51_ASTER7) -#else -# define machine_is_mx51_aster7() (0) -#endif - -#ifdef CONFIG_MACH_ACRO37XBRD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACRO37XBRD -# endif -# define machine_is_acro37xbrd() (machine_arch_type == MACH_TYPE_ACRO37XBRD) -#else -# define machine_is_acro37xbrd() (0) -#endif - -#ifdef CONFIG_MACH_ELKE -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ELKE -# endif -# define machine_is_elke() (machine_arch_type == MACH_TYPE_ELKE) -#else -# define machine_is_elke() (0) -#endif - -#ifdef CONFIG_MACH_SBC6000X -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SBC6000X -# endif -# define machine_is_sbc6000x() (machine_arch_type == MACH_TYPE_SBC6000X) -#else -# define machine_is_sbc6000x() (0) -#endif - -#ifdef CONFIG_MACH_R1801E -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_R1801E -# endif -# define machine_is_r1801e() (machine_arch_type == MACH_TYPE_R1801E) -#else -# define machine_is_r1801e() (0) -#endif - -#ifdef CONFIG_MACH_H1600 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_H1600 -# endif -# define machine_is_h1600() (machine_arch_type == MACH_TYPE_H1600) -#else -# define machine_is_h1600() (0) -#endif - -#ifdef CONFIG_MACH_MINI210 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI210 -# endif -# define machine_is_mini210() (machine_arch_type == MACH_TYPE_MINI210) -#else -# define machine_is_mini210() (0) -#endif - -#ifdef CONFIG_MACH_MINI8168 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MINI8168 -# endif -# define machine_is_mini8168() (machine_arch_type == MACH_TYPE_MINI8168) -#else -# define machine_is_mini8168() (0) -#endif - -#ifdef CONFIG_MACH_PC7308 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PC7308 -# endif -# define machine_is_pc7308() (machine_arch_type == MACH_TYPE_PC7308) -#else -# define machine_is_pc7308() (0) -#endif - -#ifdef CONFIG_MACH_KMM2M01 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KMM2M01 -# endif -# define machine_is_kmm2m01() (machine_arch_type == MACH_TYPE_KMM2M01) -#else -# define machine_is_kmm2m01() (0) -#endif - -#ifdef CONFIG_MACH_MX51EREBUS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51EREBUS -# endif -# define machine_is_mx51erebus() (machine_arch_type == MACH_TYPE_MX51EREBUS) -#else -# define machine_is_mx51erebus() (0) -#endif - -#ifdef CONFIG_MACH_WM8650REFBOARD -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_WM8650REFBOARD -# endif -# define machine_is_wm8650refboard() (machine_arch_type == MACH_TYPE_WM8650REFBOARD) -#else -# define machine_is_wm8650refboard() (0) -#endif - -#ifdef CONFIG_MACH_TUXRAIL -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_TUXRAIL -# endif -# define machine_is_tuxrail() (machine_arch_type == MACH_TYPE_TUXRAIL) -#else -# define machine_is_tuxrail() (0) -#endif - -#ifdef CONFIG_MACH_ARTHUR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARTHUR -# endif -# define machine_is_arthur() (machine_arch_type == MACH_TYPE_ARTHUR) -#else -# define machine_is_arthur() (0) -#endif - -#ifdef CONFIG_MACH_DOORBOY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DOORBOY -# endif -# define machine_is_doorboy() (machine_arch_type == MACH_TYPE_DOORBOY) -#else -# define machine_is_doorboy() (0) -#endif - -#ifdef CONFIG_MACH_XARINA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_XARINA -# endif -# define machine_is_xarina() (machine_arch_type == MACH_TYPE_XARINA) -#else -# define machine_is_xarina() (0) -#endif - -#ifdef CONFIG_MACH_ROVERX7 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ROVERX7 -# endif -# define machine_is_roverx7() (machine_arch_type == MACH_TYPE_ROVERX7) -#else -# define machine_is_roverx7() (0) -#endif - -#ifdef CONFIG_MACH_SDVR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SDVR -# endif -# define machine_is_sdvr() (machine_arch_type == MACH_TYPE_SDVR) -#else -# define machine_is_sdvr() (0) -#endif - -#ifdef CONFIG_MACH_ACER_MAYA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACER_MAYA -# endif -# define machine_is_acer_maya() (machine_arch_type == MACH_TYPE_ACER_MAYA) -#else -# define machine_is_acer_maya() (0) -#endif - -#ifdef CONFIG_MACH_PICO -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_PICO -# endif -# define machine_is_pico() (machine_arch_type == MACH_TYPE_PICO) -#else -# define machine_is_pico() (0) -#endif - -#ifdef CONFIG_MACH_CWMX233 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWMX233 -# endif -# define machine_is_cwmx233() (machine_arch_type == MACH_TYPE_CWMX233) -#else -# define machine_is_cwmx233() (0) -#endif - -#ifdef CONFIG_MACH_CWAM1808 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWAM1808 -# endif -# define machine_is_cwam1808() (machine_arch_type == MACH_TYPE_CWAM1808) -#else -# define machine_is_cwam1808() (0) -#endif - -#ifdef CONFIG_MACH_CWDM365 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_CWDM365 -# endif -# define machine_is_cwdm365() (machine_arch_type == MACH_TYPE_CWDM365) -#else -# define machine_is_cwdm365() (0) -#endif - -#ifdef CONFIG_MACH_MX51_MORAY -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MX51_MORAY -# endif -# define machine_is_mx51_moray() (machine_arch_type == MACH_TYPE_MX51_MORAY) -#else -# define machine_is_mx51_moray() (0) -#endif - -#ifdef CONFIG_MACH_THALES_CBC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_THALES_CBC -# endif -# define machine_is_thales_cbc() (machine_arch_type == MACH_TYPE_THALES_CBC) -#else -# define machine_is_thales_cbc() (0) -#endif - -#ifdef CONFIG_MACH_BLUEPOINT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLUEPOINT -# endif -# define machine_is_bluepoint() (machine_arch_type == MACH_TYPE_BLUEPOINT) -#else -# define machine_is_bluepoint() (0) -#endif - -#ifdef CONFIG_MACH_DIR665 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_DIR665 -# endif -# define machine_is_dir665() (machine_arch_type == MACH_TYPE_DIR665) -#else -# define machine_is_dir665() (0) -#endif - -#ifdef CONFIG_MACH_ACMEROVER1 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ACMEROVER1 -# endif -# define machine_is_acmerover1() (machine_arch_type == MACH_TYPE_ACMEROVER1) -#else -# define machine_is_acmerover1() (0) -#endif - -#ifdef CONFIG_MACH_SHOOTER_CT -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SHOOTER_CT -# endif -# define machine_is_shooter_ct() (machine_arch_type == MACH_TYPE_SHOOTER_CT) -#else -# define machine_is_shooter_ct() (0) -#endif - -#ifdef CONFIG_MACH_BLISS -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLISS -# endif -# define machine_is_bliss() (machine_arch_type == MACH_TYPE_BLISS) -#else -# define machine_is_bliss() (0) -#endif - -#ifdef CONFIG_MACH_BLISSC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_BLISSC -# endif -# define machine_is_blissc() (machine_arch_type == MACH_TYPE_BLISSC) -#else -# define machine_is_blissc() (0) -#endif - -#ifdef CONFIG_MACH_THALES_ADC -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_THALES_ADC -# endif -# define machine_is_thales_adc() (machine_arch_type == MACH_TYPE_THALES_ADC) -#else -# define machine_is_thales_adc() (0) -#endif - -#ifdef CONFIG_MACH_UBISYS_P9D_EVP -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_UBISYS_P9D_EVP -# endif -# define machine_is_ubisys_p9d_evp() (machine_arch_type == MACH_TYPE_UBISYS_P9D_EVP) -#else -# define machine_is_ubisys_p9d_evp() (0) -#endif - -#ifdef CONFIG_MACH_ATDGP318 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ATDGP318 -# endif -# define machine_is_atdgp318() (machine_arch_type == MACH_TYPE_ATDGP318) -#else -# define machine_is_atdgp318() (0) -#endif - -#ifdef CONFIG_MACH_OMAP5_SEVM -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_OMAP5_SEVM -# endif -# define machine_is_omap5_sevm() (machine_arch_type == MACH_TYPE_OMAP5_SEVM) -#else -# define machine_is_omap5_sevm() (0) -#endif - -#ifdef CONFIG_MACH_ARMADILLO800EVA -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ARMADILLO800EVA -# endif -# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA) -#else -# define machine_is_armadillo800eva() (0) -#endif - -#ifdef CONFIG_MACH_KZM9G -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_KZM9G -# endif -# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G) -#else -# define machine_is_kzm9g() (0) -#endif - -/* - * These have not yet been registered - */ - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/macro.h b/qemu/roms/u-boot/arch/arm/include/asm/macro.h deleted file mode 100644 index f77e4b880..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/macro.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * include/asm-arm/macro.h - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_MACRO_H__ -#define __ASM_ARM_MACRO_H__ -#ifdef __ASSEMBLY__ - -/* - * These macros provide a convenient way to write 8, 16 and 32 bit data - * to any address. - * Registers r4 and r5 are used, any data in these registers are - * overwritten by the macros. - * The macros are valid for any ARM architecture, they do not implement - * any memory barriers so caution is recommended when using these when the - * caches are enabled or on a multi-core system. - */ - -.macro write32, addr, data - ldr r4, =\addr - ldr r5, =\data - str r5, [r4] -.endm - -.macro write16, addr, data - ldr r4, =\addr - ldrh r5, =\data - strh r5, [r4] -.endm - -.macro write8, addr, data - ldr r4, =\addr - ldrb r5, =\data - strb r5, [r4] -.endm - -/* - * This macro generates a loop that can be used for delays in the code. - * Register r4 is used, any data in this register is overwritten by the - * macro. - * The macro is valid for any ARM architeture. The actual time spent in the - * loop will vary from CPU to CPU though. - */ - -.macro wait_timer, time - ldr r4, =\time -1: - nop - subs r4, r4, #1 - bcs 1b -.endm - -#ifdef CONFIG_ARM64 -/* - * Register aliases. - */ -lr .req x30 - -/* - * Branch according to exception level - */ -.macro switch_el, xreg, el3_label, el2_label, el1_label - mrs \xreg, CurrentEL - cmp \xreg, 0xc - b.eq \el3_label - cmp \xreg, 0x8 - b.eq \el2_label - cmp \xreg, 0x4 - b.eq \el1_label -.endm - -/* - * Branch if current processor is a slave, - * choose processor with all zero affinity value as the master. - */ -.macro branch_if_slave, xreg, slave_label - mrs \xreg, mpidr_el1 - tst \xreg, #0xff /* Test Affinity 0 */ - b.ne \slave_label - lsr \xreg, \xreg, #8 - tst \xreg, #0xff /* Test Affinity 1 */ - b.ne \slave_label - lsr \xreg, \xreg, #8 - tst \xreg, #0xff /* Test Affinity 2 */ - b.ne \slave_label - lsr \xreg, \xreg, #16 - tst \xreg, #0xff /* Test Affinity 3 */ - b.ne \slave_label -.endm - -/* - * Branch if current processor is a master, - * choose processor with all zero affinity value as the master. - */ -.macro branch_if_master, xreg1, xreg2, master_label - mrs \xreg1, mpidr_el1 - lsr \xreg2, \xreg1, #32 - lsl \xreg1, \xreg1, #40 - lsr \xreg1, \xreg1, #40 - orr \xreg1, \xreg1, \xreg2 - cbz \xreg1, \master_label -.endm - -#endif /* CONFIG_ARM64 */ - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARM_MACRO_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/memory.h b/qemu/roms/u-boot/arch/arm/include/asm/memory.h deleted file mode 100644 index 1864ab9fb..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/memory.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * linux/include/asm-arm/memory.h - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_ARM_MEMORY_H -#define __ASM_ARM_MEMORY_H - -#if 0 /* XXX###XXX */ - -#include <asm/arch/memory.h> - -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) - -/* - * These are *only* valid on the kernel direct mapped RAM memory. - */ -static inline unsigned long virt_to_phys(void *x) -{ - return __virt_to_phys((unsigned long)(x)); -} - -static inline void *phys_to_virt(unsigned long x) -{ - return (void *)(__phys_to_virt((unsigned long)(x))); -} - -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) - -/* - * Virtual <-> DMA view memory address translations - * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. - */ -#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) -#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) - -/* - * Conversion between a struct page and a physical address. - * - * Note: when converting an unknown physical address to a - * struct page, the resulting pointer must be validated - * using VALID_PAGE(). It must return an invalid struct page - * for any physical address not corresponding to a system - * RAM address. - * - * page_to_pfn(page) convert a struct page * to a PFN number - * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * - * pfn_valid(pfn) indicates whether a PFN number is valid - * - * virt_to_page(k) convert a _valid_ virtual address to struct page * - * virt_addr_valid(k) indicates whether a virtual address is valid - */ -#ifndef CONFIG_DISCONTIGMEM - -#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) -#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) -#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) - -#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) - -#define PHYS_TO_NID(addr) (0) - -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#else - -/* - * This is more complex. We have a set of mem_map arrays spread - * around in memory. - */ -#define page_to_pfn(page) \ - (((page) - page_zone(page)->zone_mem_map) \ - + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) - -#define pfn_to_page(pfn) \ - (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) - -#define pfn_valid(pfn) \ - ({ \ - unsigned int node = PFN_TO_NID(pfn); \ - struct pglist_data *nd = NODE_DATA(node); \ - ((node < NR_NODES) && \ - ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ - }) - -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) - -/* - * Common discontigmem stuff. - * PHYS_TO_NID is used by the ARM kernel/setup.c - */ -#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) - -/* - * 2.4 compatibility - * - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they - * refer to. This is actually inherently buggy. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ((node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ -}) - -#endif - -/* - * We should really eliminate virt_to_bus() here - it's depreciated. - */ -#define page_to_bus(page) (virt_to_bus(page_address(page))) - -#endif /* XXX###XXX */ - -#endif /* __ASM_ARM_MEMORY_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_boot.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_boot.h deleted file mode 100644 index f77f9d6b7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/omap_boot.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * Sricharan R <r.sricharan@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ROM code defines */ -/* Boot device */ -#define BOOT_DEVICE_MASK 0xFF -#define BOOT_DEVICE_OFFSET 0x8 -#define DEV_DESC_PTR_OFFSET 0x4 -#define DEV_DATA_PTR_OFFSET 0x18 -#define BOOT_MODE_OFFSET 0x8 -#define RESET_REASON_OFFSET 0x9 -#define CH_FLAGS_OFFSET 0xA - -#define CH_FLAGS_CHSETTINGS (0x1 << 0) -#define CH_FLAGS_CHRAM (0x1 << 1) -#define CH_FLAGS_CHFLASH (0x1 << 2) -#define CH_FLAGS_CHMMCSD (0x1 << 3) - -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - char *boot_message; - unsigned int mem_boot_descriptor; - unsigned char omap_bootdevice; - unsigned char reset_reason; - unsigned char ch_flags; - unsigned long omap_bootmode; -}; -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_common.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_common.h deleted file mode 100644 index 729723afe..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/omap_common.h +++ /dev/null @@ -1,663 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _OMAP_COMMON_H_ -#define _OMAP_COMMON_H_ - -#ifndef __ASSEMBLY__ - -#include <common.h> - -#define NUM_SYS_CLKS 7 - -struct prcm_regs { - /* cm1.ckgen */ - u32 cm_clksel_core; - u32 cm_clksel_abe; - u32 cm_dll_ctrl; - u32 cm_clkmode_dpll_core; - u32 cm_idlest_dpll_core; - u32 cm_autoidle_dpll_core; - u32 cm_clksel_dpll_core; - u32 cm_div_m2_dpll_core; - u32 cm_div_m3_dpll_core; - u32 cm_div_h11_dpll_core; - u32 cm_div_h12_dpll_core; - u32 cm_div_h13_dpll_core; - u32 cm_div_h14_dpll_core; - u32 cm_div_h21_dpll_core; - u32 cm_div_h24_dpll_core; - u32 cm_ssc_deltamstep_dpll_core; - u32 cm_ssc_modfreqdiv_dpll_core; - u32 cm_emu_override_dpll_core; - u32 cm_div_h22_dpllcore; - u32 cm_div_h23_dpll_core; - u32 cm_clkmode_dpll_mpu; - u32 cm_idlest_dpll_mpu; - u32 cm_autoidle_dpll_mpu; - u32 cm_clksel_dpll_mpu; - u32 cm_div_m2_dpll_mpu; - u32 cm_ssc_deltamstep_dpll_mpu; - u32 cm_ssc_modfreqdiv_dpll_mpu; - u32 cm_bypclk_dpll_mpu; - u32 cm_clkmode_dpll_iva; - u32 cm_idlest_dpll_iva; - u32 cm_autoidle_dpll_iva; - u32 cm_clksel_dpll_iva; - u32 cm_div_h11_dpll_iva; - u32 cm_div_h12_dpll_iva; - u32 cm_ssc_deltamstep_dpll_iva; - u32 cm_ssc_modfreqdiv_dpll_iva; - u32 cm_bypclk_dpll_iva; - u32 cm_clkmode_dpll_abe; - u32 cm_idlest_dpll_abe; - u32 cm_autoidle_dpll_abe; - u32 cm_clksel_dpll_abe; - u32 cm_div_m2_dpll_abe; - u32 cm_div_m3_dpll_abe; - u32 cm_ssc_deltamstep_dpll_abe; - u32 cm_ssc_modfreqdiv_dpll_abe; - u32 cm_clkmode_dpll_ddrphy; - u32 cm_idlest_dpll_ddrphy; - u32 cm_autoidle_dpll_ddrphy; - u32 cm_clksel_dpll_ddrphy; - u32 cm_div_m2_dpll_ddrphy; - u32 cm_div_h11_dpll_ddrphy; - u32 cm_div_h12_dpll_ddrphy; - u32 cm_div_h13_dpll_ddrphy; - u32 cm_ssc_deltamstep_dpll_ddrphy; - u32 cm_clkmode_dpll_dsp; - u32 cm_shadow_freq_config1; - u32 cm_clkmode_dpll_gmac; - u32 cm_mpu_mpu_clkctrl; - - /* cm1.dsp */ - u32 cm_dsp_clkstctrl; - u32 cm_dsp_dsp_clkctrl; - - /* cm1.abe */ - u32 cm1_abe_clkstctrl; - u32 cm1_abe_l4abe_clkctrl; - u32 cm1_abe_aess_clkctrl; - u32 cm1_abe_pdm_clkctrl; - u32 cm1_abe_dmic_clkctrl; - u32 cm1_abe_mcasp_clkctrl; - u32 cm1_abe_mcbsp1_clkctrl; - u32 cm1_abe_mcbsp2_clkctrl; - u32 cm1_abe_mcbsp3_clkctrl; - u32 cm1_abe_slimbus_clkctrl; - u32 cm1_abe_timer5_clkctrl; - u32 cm1_abe_timer6_clkctrl; - u32 cm1_abe_timer7_clkctrl; - u32 cm1_abe_timer8_clkctrl; - u32 cm1_abe_wdt3_clkctrl; - - /* cm2.ckgen */ - u32 cm_clksel_mpu_m3_iss_root; - u32 cm_clksel_usb_60mhz; - u32 cm_scale_fclk; - u32 cm_core_dvfs_perf1; - u32 cm_core_dvfs_perf2; - u32 cm_core_dvfs_perf3; - u32 cm_core_dvfs_perf4; - u32 cm_core_dvfs_current; - u32 cm_iva_dvfs_perf_tesla; - u32 cm_iva_dvfs_perf_ivahd; - u32 cm_iva_dvfs_perf_abe; - u32 cm_iva_dvfs_current; - u32 cm_clkmode_dpll_per; - u32 cm_idlest_dpll_per; - u32 cm_autoidle_dpll_per; - u32 cm_clksel_dpll_per; - u32 cm_div_m2_dpll_per; - u32 cm_div_m3_dpll_per; - u32 cm_div_h11_dpll_per; - u32 cm_div_h12_dpll_per; - u32 cm_div_h13_dpll_per; - u32 cm_div_h14_dpll_per; - u32 cm_ssc_deltamstep_dpll_per; - u32 cm_ssc_modfreqdiv_dpll_per; - u32 cm_emu_override_dpll_per; - u32 cm_clkmode_dpll_usb; - u32 cm_idlest_dpll_usb; - u32 cm_autoidle_dpll_usb; - u32 cm_clksel_dpll_usb; - u32 cm_div_m2_dpll_usb; - u32 cm_ssc_deltamstep_dpll_usb; - u32 cm_ssc_modfreqdiv_dpll_usb; - u32 cm_clkdcoldo_dpll_usb; - u32 cm_clkmode_dpll_pcie_ref; - u32 cm_clkmode_apll_pcie; - u32 cm_idlest_apll_pcie; - u32 cm_div_m2_apll_pcie; - u32 cm_clkvcoldo_apll_pcie; - u32 cm_clkmode_dpll_unipro; - u32 cm_idlest_dpll_unipro; - u32 cm_autoidle_dpll_unipro; - u32 cm_clksel_dpll_unipro; - u32 cm_div_m2_dpll_unipro; - u32 cm_ssc_deltamstep_dpll_unipro; - u32 cm_ssc_modfreqdiv_dpll_unipro; - u32 cm_coreaon_usb_phy_core_clkctrl; - u32 cm_coreaon_usb_phy2_core_clkctrl; - - /* cm2.core */ - u32 cm_coreaon_bandgap_clkctrl; - u32 cm_coreaon_io_srcomp_clkctrl; - u32 cm_l3_1_clkstctrl; - u32 cm_l3_1_dynamicdep; - u32 cm_l3_1_l3_1_clkctrl; - u32 cm_l3_2_clkstctrl; - u32 cm_l3_2_dynamicdep; - u32 cm_l3_2_l3_2_clkctrl; - u32 cm_l3_gpmc_clkctrl; - u32 cm_l3_2_ocmc_ram_clkctrl; - u32 cm_mpu_m3_clkstctrl; - u32 cm_mpu_m3_staticdep; - u32 cm_mpu_m3_dynamicdep; - u32 cm_mpu_m3_mpu_m3_clkctrl; - u32 cm_sdma_clkstctrl; - u32 cm_sdma_staticdep; - u32 cm_sdma_dynamicdep; - u32 cm_sdma_sdma_clkctrl; - u32 cm_memif_clkstctrl; - u32 cm_memif_dmm_clkctrl; - u32 cm_memif_emif_fw_clkctrl; - u32 cm_memif_emif_1_clkctrl; - u32 cm_memif_emif_2_clkctrl; - u32 cm_memif_dll_clkctrl; - u32 cm_memif_emif_h1_clkctrl; - u32 cm_memif_emif_h2_clkctrl; - u32 cm_memif_dll_h_clkctrl; - u32 cm_c2c_clkstctrl; - u32 cm_c2c_staticdep; - u32 cm_c2c_dynamicdep; - u32 cm_c2c_sad2d_clkctrl; - u32 cm_c2c_modem_icr_clkctrl; - u32 cm_c2c_sad2d_fw_clkctrl; - u32 cm_l4cfg_clkstctrl; - u32 cm_l4cfg_dynamicdep; - u32 cm_l4cfg_l4_cfg_clkctrl; - u32 cm_l4cfg_hw_sem_clkctrl; - u32 cm_l4cfg_mailbox_clkctrl; - u32 cm_l4cfg_sar_rom_clkctrl; - u32 cm_l3instr_clkstctrl; - u32 cm_l3instr_l3_3_clkctrl; - u32 cm_l3instr_l3_instr_clkctrl; - u32 cm_l3instr_intrconn_wp1_clkctrl; - - /* cm2.ivahd */ - u32 cm_ivahd_clkstctrl; - u32 cm_ivahd_ivahd_clkctrl; - u32 cm_ivahd_sl2_clkctrl; - - /* cm2.cam */ - u32 cm_cam_clkstctrl; - u32 cm_cam_iss_clkctrl; - u32 cm_cam_fdif_clkctrl; - u32 cm_cam_vip1_clkctrl; - u32 cm_cam_vip2_clkctrl; - u32 cm_cam_vip3_clkctrl; - u32 cm_cam_lvdsrx_clkctrl; - u32 cm_cam_csi1_clkctrl; - u32 cm_cam_csi2_clkctrl; - - /* cm2.dss */ - u32 cm_dss_clkstctrl; - u32 cm_dss_dss_clkctrl; - - /* cm2.sgx */ - u32 cm_sgx_clkstctrl; - u32 cm_sgx_sgx_clkctrl; - - /* cm2.l3init */ - u32 cm_l3init_clkstctrl; - - /* cm2.l3init */ - u32 cm_l3init_hsmmc1_clkctrl; - u32 cm_l3init_hsmmc2_clkctrl; - u32 cm_l3init_hsi_clkctrl; - u32 cm_l3init_hsusbhost_clkctrl; - u32 cm_l3init_hsusbotg_clkctrl; - u32 cm_l3init_hsusbtll_clkctrl; - u32 cm_l3init_p1500_clkctrl; - u32 cm_l3init_sata_clkctrl; - u32 cm_l3init_fsusb_clkctrl; - u32 cm_l3init_ocp2scp1_clkctrl; - u32 cm_l3init_ocp2scp3_clkctrl; - u32 cm_l3init_usb_otg_ss_clkctrl; - - u32 prm_irqstatus_mpu_2; - - /* cm2.l4per */ - u32 cm_l4per_clkstctrl; - u32 cm_l4per_dynamicdep; - u32 cm_l4per_adc_clkctrl; - u32 cm_l4per_gptimer10_clkctrl; - u32 cm_l4per_gptimer11_clkctrl; - u32 cm_l4per_gptimer2_clkctrl; - u32 cm_l4per_gptimer3_clkctrl; - u32 cm_l4per_gptimer4_clkctrl; - u32 cm_l4per_gptimer9_clkctrl; - u32 cm_l4per_elm_clkctrl; - u32 cm_l4per_gpio2_clkctrl; - u32 cm_l4per_gpio3_clkctrl; - u32 cm_l4per_gpio4_clkctrl; - u32 cm_l4per_gpio5_clkctrl; - u32 cm_l4per_gpio6_clkctrl; - u32 cm_l4per_hdq1w_clkctrl; - u32 cm_l4per_hecc1_clkctrl; - u32 cm_l4per_hecc2_clkctrl; - u32 cm_l4per_i2c1_clkctrl; - u32 cm_l4per_i2c2_clkctrl; - u32 cm_l4per_i2c3_clkctrl; - u32 cm_l4per_i2c4_clkctrl; - u32 cm_l4per_l4per_clkctrl; - u32 cm_l4per_mcasp2_clkctrl; - u32 cm_l4per_mcasp3_clkctrl; - u32 cm_l4per_mgate_clkctrl; - u32 cm_l4per_mcspi1_clkctrl; - u32 cm_l4per_mcspi2_clkctrl; - u32 cm_l4per_mcspi3_clkctrl; - u32 cm_l4per_mcspi4_clkctrl; - u32 cm_l4per_gpio7_clkctrl; - u32 cm_l4per_gpio8_clkctrl; - u32 cm_l4per_mmcsd3_clkctrl; - u32 cm_l4per_mmcsd4_clkctrl; - u32 cm_l4per_msprohg_clkctrl; - u32 cm_l4per_slimbus2_clkctrl; - u32 cm_l4per_qspi_clkctrl; - u32 cm_l4per_uart1_clkctrl; - u32 cm_l4per_uart2_clkctrl; - u32 cm_l4per_uart3_clkctrl; - u32 cm_l4per_uart4_clkctrl; - u32 cm_l4per_mmcsd5_clkctrl; - u32 cm_l4per_i2c5_clkctrl; - u32 cm_l4per_uart5_clkctrl; - u32 cm_l4per_uart6_clkctrl; - u32 cm_l4sec_clkstctrl; - u32 cm_l4sec_staticdep; - u32 cm_l4sec_dynamicdep; - u32 cm_l4sec_aes1_clkctrl; - u32 cm_l4sec_aes2_clkctrl; - u32 cm_l4sec_des3des_clkctrl; - u32 cm_l4sec_pkaeip29_clkctrl; - u32 cm_l4sec_rng_clkctrl; - u32 cm_l4sec_sha2md51_clkctrl; - u32 cm_l4sec_cryptodma_clkctrl; - - /* l4 wkup regs */ - u32 cm_abe_pll_ref_clksel; - u32 cm_sys_clksel; - u32 cm_abe_pll_sys_clksel; - u32 cm_wkup_clkstctrl; - u32 cm_wkup_l4wkup_clkctrl; - u32 cm_wkup_wdtimer1_clkctrl; - u32 cm_wkup_wdtimer2_clkctrl; - u32 cm_wkup_gpio1_clkctrl; - u32 cm_wkup_gptimer1_clkctrl; - u32 cm_wkup_gptimer12_clkctrl; - u32 cm_wkup_synctimer_clkctrl; - u32 cm_wkup_usim_clkctrl; - u32 cm_wkup_sarram_clkctrl; - u32 cm_wkup_keyboard_clkctrl; - u32 cm_wkup_rtc_clkctrl; - u32 cm_wkup_bandgap_clkctrl; - u32 cm_wkupaon_scrm_clkctrl; - u32 cm_wkupaon_io_srcomp_clkctrl; - u32 prm_rstctrl; - u32 prm_rstst; - u32 prm_rsttime; - u32 prm_vc_val_bypass; - u32 prm_vc_cfg_i2c_mode; - u32 prm_vc_cfg_i2c_clk; - u32 prm_abbldo_mpu_setup; - u32 prm_abbldo_mpu_ctrl; - - u32 cm_div_m4_dpll_core; - u32 cm_div_m5_dpll_core; - u32 cm_div_m6_dpll_core; - u32 cm_div_m7_dpll_core; - u32 cm_div_m4_dpll_iva; - u32 cm_div_m5_dpll_iva; - u32 cm_div_m4_dpll_ddrphy; - u32 cm_div_m5_dpll_ddrphy; - u32 cm_div_m6_dpll_ddrphy; - u32 cm_div_m4_dpll_per; - u32 cm_div_m5_dpll_per; - u32 cm_div_m6_dpll_per; - u32 cm_div_m7_dpll_per; - u32 cm_l3instr_intrconn_wp1_clkct; - u32 cm_l3init_usbphy_clkctrl; - u32 cm_l4per_mcbsp4_clkctrl; - u32 prm_vc_cfg_channel; - - /* SCRM stuff, used by some boards */ - u32 scrm_auxclk0; - u32 scrm_auxclk1; - - /* GMAC Clk Ctrl */ - u32 cm_gmac_gmac_clkctrl; - u32 cm_gmac_clkstctrl; -}; - -struct omap_sys_ctrl_regs { - u32 control_status; - u32 control_core_mac_id_0_lo; - u32 control_core_mac_id_0_hi; - u32 control_core_mac_id_1_lo; - u32 control_core_mac_id_1_hi; - u32 control_std_fuse_opp_vdd_mpu_2; - u32 control_phy_power_usb; - u32 control_core_mmr_lock1; - u32 control_core_mmr_lock2; - u32 control_core_mmr_lock3; - u32 control_core_mmr_lock4; - u32 control_core_mmr_lock5; - u32 control_core_control_io1; - u32 control_core_control_io2; - u32 control_id_code; - u32 control_std_fuse_opp_bgap; - u32 control_ldosram_iva_voltage_ctrl; - u32 control_ldosram_mpu_voltage_ctrl; - u32 control_ldosram_core_voltage_ctrl; - u32 control_usbotghs_ctrl; - u32 control_phy_power_sata; - u32 control_padconf_core_base; - u32 control_paconf_global; - u32 control_paconf_mode; - u32 control_smart1io_padconf_0; - u32 control_smart1io_padconf_1; - u32 control_smart1io_padconf_2; - u32 control_smart2io_padconf_0; - u32 control_smart2io_padconf_1; - u32 control_smart2io_padconf_2; - u32 control_smart3io_padconf_0; - u32 control_smart3io_padconf_1; - u32 control_pbias; - u32 control_i2c_0; - u32 control_camera_rx; - u32 control_hdmi_tx_phy; - u32 control_uniportm; - u32 control_dsiphy; - u32 control_mcbsplp; - u32 control_usb2phycore; - u32 control_hdmi_1; - u32 control_hsi; - u32 control_ddr3ch1_0; - u32 control_ddr3ch2_0; - u32 control_ddrch1_0; - u32 control_ddrch1_1; - u32 control_ddrch2_0; - u32 control_ddrch2_1; - u32 control_lpddr2ch1_0; - u32 control_lpddr2ch1_1; - u32 control_ddrio_0; - u32 control_ddrio_1; - u32 control_ddrio_2; - u32 control_ddr_control_ext_0; - u32 control_lpddr2io1_0; - u32 control_lpddr2io1_1; - u32 control_lpddr2io1_2; - u32 control_lpddr2io1_3; - u32 control_lpddr2io2_0; - u32 control_lpddr2io2_1; - u32 control_lpddr2io2_2; - u32 control_lpddr2io2_3; - u32 control_hyst_1; - u32 control_usbb_hsic_control; - u32 control_c2c; - u32 control_core_control_spare_rw; - u32 control_core_control_spare_r; - u32 control_core_control_spare_r_c0; - u32 control_srcomp_north_side; - u32 control_srcomp_south_side; - u32 control_srcomp_east_side; - u32 control_srcomp_west_side; - u32 control_srcomp_code_latch; - u32 control_pbiaslite; - u32 control_port_emif1_sdram_config; - u32 control_port_emif1_lpddr2_nvm_config; - u32 control_port_emif2_sdram_config; - u32 control_emif1_sdram_config_ext; - u32 control_emif2_sdram_config_ext; - u32 control_wkup_ldovbb_mpu_voltage_ctrl; - u32 control_smart1nopmio_padconf_0; - u32 control_smart1nopmio_padconf_1; - u32 control_padconf_mode; - u32 control_xtal_oscillator; - u32 control_i2c_2; - u32 control_ckobuffer; - u32 control_wkup_control_spare_rw; - u32 control_wkup_control_spare_r; - u32 control_wkup_control_spare_r_c0; - u32 control_srcomp_east_side_wkup; - u32 control_efuse_1; - u32 control_efuse_2; - u32 control_efuse_3; - u32 control_efuse_4; - u32 control_efuse_5; - u32 control_efuse_6; - u32 control_efuse_7; - u32 control_efuse_8; - u32 control_efuse_9; - u32 control_efuse_10; - u32 control_efuse_11; - u32 control_efuse_12; - u32 control_efuse_13; - u32 control_padconf_wkup_base; -}; - -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 m4_h11; - s8 m5_h12; - s8 m6_h13; - s8 m7_h14; - s8 h21; - s8 h22; - s8 h23; - s8 h24; -}; - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_m4_h11_dpll; - u32 cm_div_m5_h12_dpll; - u32 cm_div_m6_h13_dpll; - u32 cm_div_m7_h14_dpll; - u32 reserved[2]; - u32 cm_div_h21_dpll; - u32 cm_div_h22_dpll; - u32 cm_div_h23_dpll; - u32 cm_div_h24_dpll; -}; - -struct dplls { - const struct dpll_params *mpu; - const struct dpll_params *core; - const struct dpll_params *per; - const struct dpll_params *abe; - const struct dpll_params *iva; - const struct dpll_params *usb; - const struct dpll_params *ddr; - const struct dpll_params *gmac; -}; - -struct pmic_data { - u32 base_offset; - u32 step; - u32 start_code; - unsigned gpio; - int gpio_en; - u32 i2c_slave_addr; - void (*pmic_bus_init)(void); - int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); -}; - -/** - * struct volts_efuse_data - efuse definition for voltage - * @reg: register address for efuse - * @reg_bits: Number of bits in a register address, mandatory. - */ -struct volts_efuse_data { - u32 reg; - u8 reg_bits; -}; - -struct volts { - u32 value; - u32 addr; - struct volts_efuse_data efuse; - struct pmic_data *pmic; -}; - -struct vcores_data { - struct volts mpu; - struct volts core; - struct volts mm; - struct volts gpu; - struct volts eve; - struct volts iva; -}; - -extern struct prcm_regs const **prcm; -extern struct prcm_regs const omap5_es1_prcm; -extern struct prcm_regs const omap5_es2_prcm; -extern struct prcm_regs const omap4_prcm; -extern struct prcm_regs const dra7xx_prcm; -extern struct dplls const **dplls_data; -extern struct vcores_data const **omap_vcores; -extern const u32 sys_clk_array[8]; -extern struct omap_sys_ctrl_regs const **ctrl; -extern struct omap_sys_ctrl_regs const omap4_ctrl; -extern struct omap_sys_ctrl_regs const omap5_ctrl; -extern struct omap_sys_ctrl_regs const dra7xx_ctrl; - -void hw_data_init(void); - -const struct dpll_params *get_mpu_dpll_params(struct dplls const *); -const struct dpll_params *get_core_dpll_params(struct dplls const *); -const struct dpll_params *get_per_dpll_params(struct dplls const *); -const struct dpll_params *get_iva_dpll_params(struct dplls const *); -const struct dpll_params *get_usb_dpll_params(struct dplls const *); -const struct dpll_params *get_abe_dpll_params(struct dplls const *); - -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable); - -void setup_post_dividers(u32 const base, - const struct dpll_params *params); -u32 omap_ddr_clk(void); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_basic_uboot_clocks(void); -void scale_vcores(struct vcores_data const *); -u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); -void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); -void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, - u32 txdone, u32 txdone_mask, u32 opp); -s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); - -void usb_fake_mac_from_die_id(u32 *id); - -/* HW Init Context */ -#define OMAP_INIT_CONTEXT_SPL 0 -#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 - -/* ABB */ -#define OMAP_ABB_NOMINAL_OPP 0 -#define OMAP_ABB_FAST_OPP 1 -#define OMAP_ABB_SLOW_OPP 3 -#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) -#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) -#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) -#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) -#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) -#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) -#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) -#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) - -static inline u32 omap_revision(void) -{ - extern u32 *const omap_si_rev; - return *omap_si_rev; -} - -#define OMAP54xx 0x54000000 - -static inline u8 is_omap54xx(void) -{ - extern u32 *const omap_si_rev; - return ((*omap_si_rev & 0xFF000000) == OMAP54xx); -} - -#define DRA7XX 0x07000000 - -static inline u8 is_dra7xx(void) -{ - extern u32 *const omap_si_rev; - return ((*omap_si_rev & 0xFF000000) == DRA7XX); -} -#endif - -/* - * silicon revisions. - * Moving this to common, so that most of code can be moved to common, - * directories. - */ - -/* omap4 */ -#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF -#define OMAP4430_ES1_0 0x44300100 -#define OMAP4430_ES2_0 0x44300200 -#define OMAP4430_ES2_1 0x44300210 -#define OMAP4430_ES2_2 0x44300220 -#define OMAP4430_ES2_3 0x44300230 -#define OMAP4460_ES1_0 0x44600100 -#define OMAP4460_ES1_1 0x44600110 -#define OMAP4470_ES1_0 0x44700100 - -/* omap5 */ -#define OMAP5430_SILICON_ID_INVALID 0 -#define OMAP5430_ES1_0 0x54300100 -#define OMAP5432_ES1_0 0x54320100 -#define OMAP5430_ES2_0 0x54300200 -#define OMAP5432_ES2_0 0x54320200 - -/* DRA7XX */ -#define DRA752_ES1_0 0x07520100 -#define DRA752_ES1_1 0x07520110 - -/* - * SRAM scratch space entries - */ -#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) -#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) -#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) -#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) -#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) -#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) - -#endif /* _OMAP_COMMON_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_gpio.h deleted file mode 100644 index 5d25d04c3..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/omap_gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * SPDX-License-Identifier: GPL-2.0 - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_H -#define _GPIO_H - -#include <asm/arch/cpu.h> - -struct gpio_bank { - void *base; - int method; -}; - -extern const struct gpio_bank *const omap_gpio_bank; - -#define METHOD_GPIO_24XX 4 - -/** - * Check if gpio is valid. - * - * @param gpio GPIO number - * @return 1 if ok, 0 on error - */ -int gpio_is_valid(int gpio); -#endif /* _GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_mmc.h deleted file mode 100644 index 617e22fa5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/omap_mmc.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef OMAP_MMC_H_ -#define OMAP_MMC_H_ - -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, - int wp_gpio); - - -#endif /* OMAP_MMC_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_musb.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_musb.h deleted file mode 100644 index 8b9cb0eb8..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/omap_musb.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Board data structure for musb gadget on OMAPs - * - * Copyright (C) 2012, Ilya Yanok <ilya.yanok@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_OMAP_MUSB_H -#define __ASM_ARM_OMAP_MUSB_H - -extern struct musb_platform_ops musb_dsps_ops; -extern const struct musb_platform_ops am35x_ops; -extern const struct musb_platform_ops omap2430_ops; - -struct omap_musb_board_data { - u8 interface_type; - void (*set_phy_power)(u8 on); - void (*clear_irq)(void); - void (*reset)(void); -}; - -enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; -#endif /* __ASM_ARM_OMAP_MUSB_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/pl310.h b/qemu/roms/u-boot/arch/arm/include/asm/pl310.h deleted file mode 100644 index ddc245bfd..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/pl310.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _PL310_H_ -#define _PL310_H_ - -#include <linux/types.h> - -/* Register bit fields */ -#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) -#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) -#define L2X0_STNDBY_MODE_EN (1 << 0) -#define L2X0_CTRL_EN 1 - -struct pl310_regs { - u32 pl310_cache_id; - u32 pl310_cache_type; - u32 pad1[62]; - u32 pl310_ctrl; - u32 pl310_aux_ctrl; - u32 pl310_tag_latency_ctrl; - u32 pl310_data_latency_ctrl; - u32 pad2[60]; - u32 pl310_event_cnt_ctrl; - u32 pl310_event_cnt1_cfg; - u32 pl310_event_cnt0_cfg; - u32 pl310_event_cnt1_val; - u32 pl310_event_cnt0_val; - u32 pl310_intr_mask; - u32 pl310_masked_intr_stat; - u32 pl310_raw_intr_stat; - u32 pl310_intr_clear; - u32 pad3[323]; - u32 pl310_cache_sync; - u32 pad4[15]; - u32 pl310_inv_line_pa; - u32 pad5[2]; - u32 pl310_inv_way; - u32 pad6[12]; - u32 pl310_clean_line_pa; - u32 pad7[1]; - u32 pl310_clean_line_idx; - u32 pl310_clean_way; - u32 pad8[12]; - u32 pl310_clean_inv_line_pa; - u32 pad9[1]; - u32 pl310_clean_inv_line_idx; - u32 pl310_clean_inv_way; - u32 pad10[64]; - u32 pl310_lockdown_dbase; - u32 pl310_lockdown_ibase; - u32 pad11[190]; - u32 pl310_addr_filter_start; - u32 pl310_addr_filter_end; - u32 pad12[190]; - u32 pl310_test_operation; - u32 pad13[3]; - u32 pl310_line_data; - u32 pad14[7]; - u32 pl310_line_tag; - u32 pad15[3]; - u32 pl310_debug_ctrl; - u32 pad16[7]; - u32 pl310_prefetch_ctrl; - u32 pad17[7]; - u32 pl310_power_ctrl; -}; - -void pl310_inval_all(void); -void pl310_clean_inval_all(void); -void pl310_inval_range(u32 start, u32 end); -void pl310_clean_inval_range(u32 start, u32 end); - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/posix_types.h b/qemu/roms/u-boot/arch/arm/include/asm/posix_types.h deleted file mode 100644 index d254b95b2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/posix_types.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * linux/include/asm-arm/posix_types.h - * - * Copyright (C) 1996-1998 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; - -#ifdef __aarch64__ -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef long __kernel_ptrdiff_t; -#else -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -#endif - -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h deleted file mode 100644 index aadc83187..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/domain.h - * - * Copyright (C) 1999 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_DOMAIN_H -#define __ASM_PROC_DOMAIN_H - -/* - * Domain numbers - * - * DOMAIN_IO - domain 2 includes all IO only - * DOMAIN_KERNEL - domain 1 includes all kernel memory only - * DOMAIN_USER - domain 0 includes all user memory only - */ -#define DOMAIN_USER 0 -#define DOMAIN_KERNEL 1 -#define DOMAIN_TABLE 1 -#define DOMAIN_IO 2 - -/* - * Domain types - */ -#define DOMAIN_NOACCESS 0 -#define DOMAIN_CLIENT 1 -#define DOMAIN_MANAGER 3 - -#define domain_val(dom,type) ((type) << 2*(dom)) - -#define set_domain(x) \ - do { \ - __asm__ __volatile__( \ - "mcr p15, 0, %0, c3, c0 @ set domain" \ - : : "r" (x)); \ - } while (0) - -#define modify_domain(dom,type) \ - do { \ - unsigned int domain = current->thread.domain; \ - domain &= ~domain_val(dom, DOMAIN_MANAGER); \ - domain |= domain_val(dom, type); \ - current->thread.domain = domain; \ - set_domain(current->thread.domain); \ - } while (0) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h deleted file mode 100644 index 5bfab7fb9..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/processor.h - * - * Copyright (C) 1996-1999 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 20-09-1996 RMK Created - * 26-09-1996 RMK Added 'EXTRA_THREAD_STRUCT*' - * 28-09-1996 RMK Moved start_thread into the processor dependencies - * 09-09-1998 PJB Delete redundant `wp_works_ok' - * 30-05-1999 PJB Save sl across context switches - * 31-07-1999 RMK Added 'domain' stuff - */ -#ifndef __ASM_PROC_PROCESSOR_H -#define __ASM_PROC_PROCESSOR_H - -#include <asm/proc/domain.h> - -#define KERNEL_STACK_SIZE PAGE_SIZE - -struct context_save_struct { - unsigned long cpsr; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long sl; - unsigned long fp; - unsigned long pc; -}; - -#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } - -#define EXTRA_THREAD_STRUCT \ - unsigned int domain; - -#define EXTRA_THREAD_STRUCT_INIT \ - domain: domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \ - domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_IO, DOMAIN_CLIENT) - -#define start_thread(regs,pc,sp) \ -({ \ - unsigned long *stack = (unsigned long *)sp; \ - set_fs(USER_DS); \ - memzero(regs->uregs, sizeof(regs->uregs)); \ - if (current->personality & ADDR_LIMIT_32BIT) \ - regs->ARM_cpsr = USR_MODE; \ - else \ - regs->ARM_cpsr = USR26_MODE; \ - regs->ARM_pc = pc; /* pc */ \ - regs->ARM_sp = sp; /* sp */ \ - regs->ARM_r2 = stack[2]; /* r2 (envp) */ \ - regs->ARM_r1 = stack[1]; /* r1 (argv) */ \ - regs->ARM_r0 = stack[0]; /* r0 (argc) */ \ -}) - -#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019]) -#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1017]) - -/* Allocation and freeing of basic task resources. */ -/* - * NOTE! The task struct and the stack go together - */ -#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define ll_free_task_struct(p) free_pages((unsigned long)(p),1) - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h deleted file mode 100644 index 21aef58b7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/ptrace.h - * - * Copyright (C) 1996-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_PTRACE_H -#define __ASM_PROC_PTRACE_H - -#ifdef CONFIG_ARM64 - -#define PCMASK 0 - -#ifndef __ASSEMBLY__ - -/* - * This struct defines the way the registers are stored - * on the stack during an exception. - */ -struct pt_regs { - unsigned long elr; - unsigned long regs[31]; -}; - -#endif /* __ASSEMBLY__ */ - -#else /* CONFIG_ARM64 */ - -#define USR26_MODE 0x00 -#define FIQ26_MODE 0x01 -#define IRQ26_MODE 0x02 -#define SVC26_MODE 0x03 -#define USR_MODE 0x10 -#define FIQ_MODE 0x11 -#define IRQ_MODE 0x12 -#define SVC_MODE 0x13 -#define ABT_MODE 0x17 -#define UND_MODE 0x1b -#define SYSTEM_MODE 0x1f -#define MODE_MASK 0x1f -#define T_BIT 0x20 -#define F_BIT 0x40 -#define I_BIT 0x80 -#define CC_V_BIT (1 << 28) -#define CC_C_BIT (1 << 29) -#define CC_Z_BIT (1 << 30) -#define CC_N_BIT (1 << 31) -#define PCMASK 0 - -#ifndef __ASSEMBLY__ - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long uregs[18]; -}; - -#define ARM_cpsr uregs[16] -#define ARM_pc uregs[15] -#define ARM_lr uregs[14] -#define ARM_sp uregs[13] -#define ARM_ip uregs[12] -#define ARM_fp uregs[11] -#define ARM_r10 uregs[10] -#define ARM_r9 uregs[9] -#define ARM_r8 uregs[8] -#define ARM_r7 uregs[7] -#define ARM_r6 uregs[6] -#define ARM_r5 uregs[5] -#define ARM_r4 uregs[4] -#define ARM_r3 uregs[3] -#define ARM_r2 uregs[2] -#define ARM_r1 uregs[1] -#define ARM_r0 uregs[0] -#define ARM_ORIG_r0 uregs[17] - -#ifdef __KERNEL__ - -#define user_mode(regs) \ - (((regs)->ARM_cpsr & 0xf) == 0) - -#ifdef CONFIG_ARM_THUMB -#define thumb_mode(regs) \ - (((regs)->ARM_cpsr & T_BIT)) -#else -#define thumb_mode(regs) (0) -#endif - -#define processor_mode(regs) \ - ((regs)->ARM_cpsr & MODE_MASK) - -#define interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & I_BIT)) - -#define fast_interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & F_BIT)) - -#define condition_codes(regs) \ - ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) - -/* Are the current registers suitable for user mode? - * (used to maintain security in signal handlers) - */ -static inline int valid_user_regs(struct pt_regs *regs) -{ - if ((regs->ARM_cpsr & 0xf) == 0 && - (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) - return 1; - - /* - * Force CPSR to something logical... - */ - regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); - - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_ARM64 */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/system.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/system.h deleted file mode 100644 index 693d1f492..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/system.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * linux/include/asm-arm/proc-armv/system.h - * - * Copyright (C) 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_PROC_SYSTEM_H -#define __ASM_PROC_SYSTEM_H - -/* - * Save the current interrupt enable state & disable IRQs - */ -#ifdef CONFIG_ARM64 - -/* - * Save the current interrupt enable state - * and disable IRQs/FIQs - */ -#define local_irq_save(flags) \ - ({ \ - asm volatile( \ - "mrs %0, daif" \ - "msr daifset, #3" \ - : "=r" (flags) \ - : \ - : "memory"); \ - }) - -/* - * restore saved IRQ & FIQ state - */ -#define local_irq_restore(flags) \ - ({ \ - asm volatile( \ - "msr daif, %0" \ - : \ - : "r" (flags) \ - : "memory"); \ - }) - -/* - * Enable IRQs/FIQs - */ -#define local_irq_enable() \ - ({ \ - asm volatile( \ - "msr daifclr, #3" \ - : \ - : \ - : "memory"); \ - }) - -/* - * Disable IRQs/FIQs - */ -#define local_irq_disable() \ - ({ \ - asm volatile( \ - "msr daifset, #3" \ - : \ - : \ - : "memory"); \ - }) - -#else /* CONFIG_ARM64 */ - -#define local_irq_save(x) \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ -" orr %1, %0, #128\n" \ -" msr cpsr_c, %1" \ - : "=r" (x), "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Enable IRQs - */ -#define local_irq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_enable\n" \ -" bic %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Disable IRQs - */ -#define local_irq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_disable\n" \ -" orr %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Enable FIQs - */ -#define __stf() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ stf\n" \ -" bic %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Disable FIQs - */ -#define __clf() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ clf\n" \ -" orr %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory"); \ - }) - -/* - * Save the current interrupt enable state. - */ -#define local_save_flags(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_save_flags\n" \ - : "=r" (x) \ - : \ - : "memory"); \ - }) - -/* - * restore saved IRQ & FIQ state - */ -#define local_irq_restore(x) \ - __asm__ __volatile__( \ - "msr cpsr_c, %0 @ local_irq_restore\n" \ - : \ - : "r" (x) \ - : "memory") - -#endif /* CONFIG_ARM64 */ - -#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \ - defined(CONFIG_ARM64) -/* - * On the StrongARM, "swp" is terminally broken since it bypasses the - * cache totally. This means that the cache becomes inconsistent, and, - * since we use normal loads/stores as well, this is really bad. - * Typically, this causes oopsen in filp_close, but could have other, - * more disasterous effects. There are two work-arounds: - * 1. Disable interrupts and emulate the atomic swap - * 2. Clean the cache, perform atomic swap, flush the cache - * - * We choose (1) since its the "easiest" to achieve here and is not - * dependent on the processor type. - */ -#define swp_is_buggy -#endif - -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) -{ - extern void __bad_xchg(volatile void *, int); - unsigned long ret; -#ifdef swp_is_buggy - unsigned long flags; -#endif - - switch (size) { -#ifdef swp_is_buggy - case 1: - local_irq_save(flags); - ret = *(volatile unsigned char *)ptr; - *(volatile unsigned char *)ptr = x; - local_irq_restore(flags); - break; - - case 4: - local_irq_save(flags); - ret = *(volatile unsigned long *)ptr; - *(volatile unsigned long *)ptr = x; - local_irq_restore(flags); - break; -#else - case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" - : "=&r" (ret) - : "r" (x), "r" (ptr) - : "memory"); - break; - case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" - : "=&r" (ret) - : "r" (x), "r" (ptr) - : "memory"); - break; -#endif - default: __bad_xchg(ptr, size), ret = 0; - } - - return ret; -} - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/processor.h b/qemu/roms/u-boot/arch/arm/include/asm/processor.h deleted file mode 100644 index 445d4495b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/processor.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * linux/include/asm-arm/processor.h - * - * Copyright (C) 1995-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_PROCESSOR_H -#define __ASM_ARM_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#define FP_SIZE 35 - -struct fp_hard_struct { - unsigned int save[FP_SIZE]; /* as yet undefined */ -}; - -struct fp_soft_struct { - unsigned int save[FP_SIZE]; /* undefined information */ -}; - -union fp_state { - struct fp_hard_struct hard; - struct fp_soft_struct soft; -}; - -typedef unsigned long mm_segment_t; /* domain register */ - -#ifdef __KERNEL__ - -#define EISA_bus 0 -#define MCA_bus 0 -#define MCA_bus__is_a_macro - -#include <asm/atomic.h> -#include <asm/ptrace.h> -#if 0 /* XXX###XXX */ -#include <asm/arch/memory.h> -#endif /* XXX###XXX */ -#include <asm/proc/processor.h> -#include <asm/types.h> - -union debug_insn { - u32 arm; - u16 thumb; -}; - -struct debug_entry { - u32 address; - union debug_insn insn; -}; - -struct debug_info { - int nsaved; - struct debug_entry bp[2]; -}; - -struct thread_struct { - atomic_t refcount; - /* fault info */ - unsigned long address; - unsigned long trap_no; - unsigned long error_code; - /* floating point */ - union fp_state fpstate; - /* debugging */ - struct debug_info debug; - /* context info */ - struct context_save_struct *save; - EXTRA_THREAD_STRUCT -}; - -#define INIT_THREAD { \ - refcount: ATOMIC_INIT(1), \ - EXTRA_THREAD_STRUCT_INIT \ -} - -/* - * Return saved PC of a blocked thread. - */ -static inline unsigned long thread_saved_pc(struct thread_struct *t) -{ - return t->save ? pc_pointer(t->save->pc) : 0; -} - -static inline unsigned long thread_saved_fp(struct thread_struct *t) -{ - return t->save ? t->save->fp : 0; -} - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); - -/* Copy and release all segment info associated with a VM */ -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) - -unsigned long get_wchan(struct task_struct *p); - -#define THREAD_SIZE (8192) - -extern struct task_struct *alloc_task_struct(void); -extern void __free_task_struct(struct task_struct *); -#define get_task_struct(p) atomic_inc(&(p)->thread.refcount) -#define free_task_struct(p) \ - do { \ - if (atomic_dec_and_test(&(p)->thread.refcount)) \ - __free_task_struct((p)); \ - } while (0) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - -#define cpu_relax() barrier() - -/* - * Create a new kernel thread - */ -extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -#endif - -#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/ptrace.h b/qemu/roms/u-boot/arch/arm/include/asm/ptrace.h deleted file mode 100644 index 73c9087b5..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/ptrace.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARM_PTRACE_H -#define __ASM_ARM_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#define PTRACE_SETOPTIONS 21 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -#include <asm/proc/ptrace.h> - -#ifndef __ASSEMBLY__ -#define pc_pointer(v) \ - ((v) & ~PCMASK) - -#define instruction_pointer(regs) \ - (pc_pointer((regs)->ARM_pc)) - -#ifdef __KERNEL__ -extern void show_regs(struct pt_regs *); - -#define predicate(x) (x & 0xf0000000) -#define PREDICATE_ALWAYS 0xe0000000 - -#endif - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/sections.h b/qemu/roms/u-boot/arch/arm/include/asm/sections.h deleted file mode 100644 index f7a7f4c41..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/sections.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARM_SECTIONS_H -#define __ASM_ARM_SECTIONS_H - -#include <asm-generic/sections.h> - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/setup.h b/qemu/roms/u-boot/arch/arm/include/asm/setup.h deleted file mode 100644 index 78a7facfc..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/setup.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See linux/Documentation/arm/Setup - * for more info. - * - * NOTE: - * This file contains two ways to pass information from the boot - * loader to the kernel. The old struct param_struct is deprecated, - * but it will be kept in the kernel for 5 years from now - * (2001). This will allow boot loaders to convert to the new struct - * tag way. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -/* - * Usage: - * - do not go blindly adding fields, add them at the end - * - when adding fields, don't rely on the address until - * a patch from me has been released - * - unused fields should be zero (for future expansion) - * - this structure is relatively short-lived - only - * guaranteed to contain useful data in setup_arch() - */ -#define COMMAND_LINE_SIZE 1024 - -/* This is the old deprecated way to pass parameters to the kernel */ -struct param_struct { - union { - struct { - unsigned long page_size; /* 0 */ - unsigned long nr_pages; /* 4 */ - unsigned long ramdisk_size; /* 8 */ - unsigned long flags; /* 12 */ -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - unsigned long rootdev; /* 16 */ - unsigned long video_num_cols; /* 20 */ - unsigned long video_num_rows; /* 24 */ - unsigned long video_x; /* 28 */ - unsigned long video_y; /* 32 */ - unsigned long memc_control_reg; /* 36 */ - unsigned char sounddefault; /* 40 */ - unsigned char adfsdrives; /* 41 */ - unsigned char bytes_per_char_h; /* 42 */ - unsigned char bytes_per_char_v; /* 43 */ - unsigned long pages_in_bank[4]; /* 44 */ - unsigned long pages_in_vram; /* 60 */ - unsigned long initrd_start; /* 64 */ - unsigned long initrd_size; /* 68 */ - unsigned long rd_start; /* 72 */ - unsigned long system_rev; /* 76 */ - unsigned long system_serial_low; /* 80 */ - unsigned long system_serial_high; /* 84 */ - unsigned long mem_fclk_21285; /* 88 */ - } s; - char unused[256]; - } u1; - union { - char paths[8][128]; - struct { - unsigned long magic; - char n[1024 - sizeof(unsigned long)]; - } s; - } u2; - char commandline[COMMAND_LINE_SIZE]; -}; - - -/* - * The new way of passing information: a list of tagged entries - */ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * its depreciated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __attribute__((unused, __section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif - -/* - * Board specified tags - */ -void setup_board_tags(struct tag **in_params); diff --git a/qemu/roms/u-boot/arch/arm/include/asm/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/spl.h deleted file mode 100644 index 90e5a9dde..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/spl.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_SPL_H_ -#define _ASM_SPL_H_ - -/* Platform-specific defines */ -#include <asm/arch/spl.h> - -/* Linker symbols. */ -extern char __bss_start[], __bss_end[]; - -extern gd_t gdata; - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/string.h b/qemu/roms/u-boot/arch/arm/include/asm/string.h deleted file mode 100644 index c6dfb254b..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/string.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __ASM_ARM_STRING_H -#define __ASM_ARM_STRING_H - -#include <config.h> - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#ifdef CONFIG_USE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMCPY -#endif -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -#ifdef CONFIG_USE_ARCH_MEMSET -#define __HAVE_ARCH_MEMSET -#endif -extern void * memset(void *, int, __kernel_size_t); - -#if 0 -extern void __memzero(void *ptr, __kernel_size_t n); - -#define memset(p,v,n) \ - ({ \ - if ((n) != 0) { \ - if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ - else \ - memset((p),(v),(n)); \ - } \ - (p); \ - }) - -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) -#else -extern void memzero(void *ptr, __kernel_size_t n); -#endif - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/system.h b/qemu/roms/u-boot/arch/arm/include/asm/system.h deleted file mode 100644 index 74ee9a4df..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/system.h +++ /dev/null @@ -1,220 +0,0 @@ -#ifndef __ASM_ARM_SYSTEM_H -#define __ASM_ARM_SYSTEM_H - -#ifdef CONFIG_ARM64 - -/* - * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions - */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_WXN (1 << 19) /* Write Permision Imply XN */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ - -#define PGTABLE_SIZE (0x10000) - -#ifndef __ASSEMBLY__ - -#define isb() \ - ({asm volatile( \ - "isb" : : : "memory"); \ - }) - -#define wfi() \ - ({asm volatile( \ - "wfi" : : : "memory"); \ - }) - -static inline unsigned int current_el(void) -{ - unsigned int el; - asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); - return el >> 2; -} - -static inline unsigned int get_sctlr(void) -{ - unsigned int el, val; - - el = current_el(); - if (el == 1) - asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); - else if (el == 2) - asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); - else - asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); - - return val; -} - -static inline void set_sctlr(unsigned int val) -{ - unsigned int el; - - el = current_el(); - if (el == 1) - asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); - else if (el == 2) - asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); - else - asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); - - asm volatile("isb"); -} - -void __asm_flush_dcache_all(void); -void __asm_invalidate_dcache_all(void); -void __asm_flush_dcache_range(u64 start, u64 end); -void __asm_invalidate_tlb_all(void); -void __asm_invalidate_icache_all(void); - -void armv8_switch_to_el2(void); -void armv8_switch_to_el1(void); -void gic_init(void); -void gic_send_sgi(unsigned long sgino); -void wait_for_wakeup(void); -void smp_kick_all_cpus(void); - -#endif /* __ASSEMBLY__ */ - -#else /* CONFIG_ARM64 */ - -#ifdef __KERNEL__ - -#define CPU_ARCH_UNKNOWN 0 -#define CPU_ARCH_ARMv3 1 -#define CPU_ARCH_ARMv4 2 -#define CPU_ARCH_ARMv4T 3 -#define CPU_ARCH_ARMv5 4 -#define CPU_ARCH_ARMv5T 5 -#define CPU_ARCH_ARMv5TE 6 -#define CPU_ARCH_ARMv5TEJ 7 -#define CPU_ARCH_ARMv6 8 -#define CPU_ARCH_ARMv7 9 - -/* - * CR1 bits (CP#15 CR1) - */ -#define CR_M (1 << 0) /* MMU enable */ -#define CR_A (1 << 1) /* Alignment abort enable */ -#define CR_C (1 << 2) /* Dcache enable */ -#define CR_W (1 << 3) /* Write buffer enable */ -#define CR_P (1 << 4) /* 32-bit exception handler */ -#define CR_D (1 << 5) /* 32-bit data address range */ -#define CR_L (1 << 6) /* Implementation defined */ -#define CR_B (1 << 7) /* Big endian */ -#define CR_S (1 << 8) /* System MMU protection */ -#define CR_R (1 << 9) /* ROM MMU protection */ -#define CR_F (1 << 10) /* Implementation defined */ -#define CR_Z (1 << 11) /* Implementation defined */ -#define CR_I (1 << 12) /* Icache enable */ -#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ -#define CR_RR (1 << 14) /* Round Robin cache replacement */ -#define CR_L4 (1 << 15) /* LDR pc can set T bit */ -#define CR_DT (1 << 16) -#define CR_IT (1 << 18) -#define CR_ST (1 << 19) -#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ -#define CR_U (1 << 22) /* Unaligned access operation */ -#define CR_XP (1 << 23) /* Extended page tables */ -#define CR_VE (1 << 24) /* Vectored interrupts */ -#define CR_EE (1 << 25) /* Exception (Big) Endian */ -#define CR_TRE (1 << 28) /* TEX remap enable */ -#define CR_AFE (1 << 29) /* Access flag enable */ -#define CR_TE (1 << 30) /* Thumb exception enable */ - -#define PGTABLE_SIZE (4096 * 4) - -/* - * This is used to ensure the compiler did actually allocate the register we - * asked it for some inline assembly sequences. Apparently we can't trust - * the compiler from one version to another so a bit of paranoia won't hurt. - * This string is meant to be concatenated with the inline asm string and - * will cause compilation to stop on mismatch. - * (for details, see gcc PR 15089) - */ -#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" - -#ifndef __ASSEMBLY__ - -#define isb() __asm__ __volatile__ ("" : : : "memory") - -#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); - -#ifdef __ARM_ARCH_7A__ -#define wfi() __asm__ __volatile__ ("wfi" : : : "memory") -#else -#define wfi() -#endif - -static inline unsigned int get_cr(void) -{ - unsigned int val; - asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); - return val; -} - -static inline void set_cr(unsigned int val) -{ - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" - : : "r" (val) : "cc"); - isb(); -} - -static inline unsigned int get_dacr(void) -{ - unsigned int val; - asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); - return val; -} - -static inline void set_dacr(unsigned int val) -{ - asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" - : : "r" (val) : "cc"); - isb(); -} - -/* options available for data cache on each page */ -enum dcache_option { - DCACHE_OFF = 0x12, - DCACHE_WRITETHROUGH = 0x1a, - DCACHE_WRITEBACK = 0x1e, -}; - -/* Size of an MMU section */ -enum { - MMU_SECTION_SHIFT = 20, - MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, -}; - -/** - * Change the cache settings for a region. - * - * \param start start address of memory region to change - * \param size size of memory region to change - * \param option dcache option to select - */ -void mmu_set_region_dcache_behaviour(u32 start, int size, - enum dcache_option option); - -/** - * Register an update to the page tables, and flush the TLB - * - * \param start start address of update in page table - * \param stop stop address of update in page table - */ -void mmu_page_table_flush(unsigned long start, unsigned long stop); - -#endif /* __ASSEMBLY__ */ - -#define arch_align_stack(x) (x) - -#endif /* __KERNEL__ */ - -#endif /* CONFIG_ARM64 */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/types.h b/qemu/roms/u-boot/arch/arm/include/asm/types.h deleted file mode 100644 index 2326420a7..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/types.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#ifdef CONFIG_ARM64 -#define BITS_PER_LONG 64 -#else /* CONFIG_ARM64 */ -#define BITS_PER_LONG 32 -#endif /* CONFIG_ARM64 */ - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __KERNEL__ */ - -#endif diff --git a/qemu/roms/u-boot/arch/arm/include/asm/u-boot-arm.h b/qemu/roms/u-boot/arch/arm/include/asm/u-boot-arm.h deleted file mode 100644 index b16694c72..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/u-boot-arm.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _U_BOOT_ARM_H_ -#define _U_BOOT_ARM_H_ 1 - -/* for the following variables, see start.S */ -extern ulong IRQ_STACK_START; /* top of IRQ stack */ -extern ulong FIQ_STACK_START; /* top of FIQ stack */ -extern ulong _datarel_start_ofs; -extern ulong _datarelrolocal_start_ofs; -extern ulong _datarellocal_start_ofs; -extern ulong _datarelro_start_ofs; -extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */ - -/* cpu/.../cpu.c */ -int cpu_init(void); -int cleanup_before_linux(void); - -/* Set up ARMv7 MMU, caches and TLBs */ -void cpu_init_cp15(void); - -/* cpu/.../arch/cpu.c */ -int arch_cpu_init(void); -int arch_misc_init(void); -int arch_early_init_r(void); - -/* board/.../... */ -int board_init(void); -int dram_init (void); -void dram_init_banksize (void); - -/* cpu/.../interrupt.c */ -int arch_interrupt_init (void); -void reset_timer_masked (void); -ulong get_timer_masked (void); -void udelay_masked (unsigned long usec); - -#endif /* _U_BOOT_ARM_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/u-boot.h b/qemu/roms/u-boot/arch/arm/include/asm/u-boot.h deleted file mode 100644 index 43cc49468..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/u-boot.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef _U_BOOT_H_ -#define _U_BOOT_H_ 1 - -#ifdef CONFIG_SYS_GENERIC_BOARD -/* Use the generic board which requires a unified bd_info */ -#include <asm-generic/u-boot.h> -#else - -#ifndef __ASSEMBLY__ -typedef struct bd_info { - ulong bi_arch_number; /* unique id for this board */ - ulong bi_boot_params; /* where this board expects params */ - unsigned long bi_arm_freq; /* arm frequency */ - unsigned long bi_dsp_freq; /* dsp core frequency */ - unsigned long bi_ddr_freq; /* ddr frequency */ - struct /* RAM configuration */ - { - ulong start; - ulong size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; -} bd_t; -#endif - -#endif /* !CONFIG_SYS_GENERIC_BOARD */ - -/* For image.h:image_check_target_arch() */ -#ifndef CONFIG_ARM64 -#define IH_ARCH_DEFAULT IH_ARCH_ARM -#else -#define IH_ARCH_DEFAULT IH_ARCH_ARM64 -#endif - -#endif /* _U_BOOT_H_ */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/unaligned.h b/qemu/roms/u-boot/arch/arm/include/asm/unaligned.h deleted file mode 100644 index 0a228fb8e..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/unaligned.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _ASM_ARM_UNALIGNED_H -#define _ASM_ARM_UNALIGNED_H - -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -/* - * Select endianness - */ -#if __BYTE_ORDER == __LITTLE_ENDIAN -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#endif - -#endif /* _ASM_ARM_UNALIGNED_H */ diff --git a/qemu/roms/u-boot/arch/arm/include/asm/utils.h b/qemu/roms/u-boot/arch/arm/include/asm/utils.h deleted file mode 100644 index 1b3f1a0c2..000000000 --- a/qemu/roms/u-boot/arch/arm/include/asm/utils.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _UTILS_H_ -#define _UTILS_H_ - -static inline s32 log_2_n_round_up(u32 n) -{ - s32 log2n = -1; - u32 temp = n; - - while (temp) { - log2n++; - temp >>= 1; - } - - if (n & (n - 1)) - return log2n + 1; /* not power of 2 - round up */ - else - return log2n; /* power of 2 */ -} - -static inline s32 log_2_n_round_down(u32 n) -{ - s32 log2n = -1; - u32 temp = n; - - while (temp) { - log2n++; - temp >>= 1; - } - - return log2n; -} - -#endif |