diff options
author | 2015-08-28 09:58:54 +0800 | |
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committer | 2015-09-01 12:44:00 +0800 | |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts')
-rw-r--r-- | qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts new file mode 100644 index 000000000..4c1b08d76 --- /dev/null +++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +#include "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "ad,tec", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + host1x { + status = "okay"; + + dc@54200000 { + status = "okay"; + + rgb { + nvidia,panel = <&lcd_panel>; + status = "okay"; + }; + }; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; + + lcd_panel: panel { + clock = <33260000>; + xres = <800>; + yres = <480>; + left-margin = <120>; + right-margin = <120>; + hsync-len = <16>; + lower-margin = <15>; + upper-margin = <15>; + vsync-len = <15>; + + nvidia,bits-per-pixel = <16>; + nvidia,pwm = <&pwm 0 500000>; + nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */ + nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */ + nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */ + nvidia,panel-timings = <0 0 0 0>; + }; +}; |