Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
author: RajithaY <rajithax.yerrumsetty@intel.com> 2017-04-25 03:31:15 -0700
committer: Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> 2017-05-22 06:48:08 +0000
commit: bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
tree: ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/qemu-palcode
parent: a14b48d18a9ed03ec191cf16b162206998a895ce (diff)
38 files changed, 0 insertions, 11777 deletions
diff --git a/qemu/roms/qemu-palcode/.gitignore b/qemu/roms/qemu-palcode/.gitignore
deleted file mode 100644
index ec54fa7db..000000000
--- a/qemu/roms/qemu-palcode/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-*.o
-palcode-*
diff --git a/qemu/roms/qemu-palcode/COPYING b/qemu/roms/qemu-palcode/COPYING
deleted file mode 100644
index 00ccfbb62..000000000
--- a/qemu/roms/qemu-palcode/COPYING
+++ /dev/null
@@ -1,339 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-			    Preamble
-
-  The licenses for most software are designed to take away your
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diff --git a/qemu/roms/qemu-palcode/HEADER b/qemu/roms/qemu-palcode/HEADER
deleted file mode 100644
index 9a0dd3293..000000000
--- a/qemu/roms/qemu-palcode/HEADER
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Short Description
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
diff --git a/qemu/roms/qemu-palcode/Makefile b/qemu/roms/qemu-palcode/Makefile
deleted file mode 100644
index 202559931..000000000
--- a/qemu/roms/qemu-palcode/Makefile
+++ /dev/null
@@ -1,35 +0,0 @@
-CROSS = alphaev67-linux-
-CC = $(CROSS)gcc
-LD = $(CROSS)ld
-
-CORE = typhoon
-SYSTEM = clipper
-
-ASFLAGS = -Wa,-m21264 -Wa,--noexecstack
-OPT= -O2
-CFLAGS = $(OPT) -g1 -Wall -fvisibility=hidden -fno-strict-aliasing \
-  -msmall-text -msmall-data -mno-fp-regs -mbuild-constants
-CPPFLAGS = -DSYSTEM_H='"sys-$(SYSTEM).h"'
-
-CFLAGS += -mcpu=ev67
-
-OBJS = pal.o sys-$(SYSTEM).o init.o crb.o uart.o console.o console-low.o \
-	ps2port.o pci.o vgaio.o vgatables.o vgafonts.o \
-	printf.o util.o memset.o memcpy.o strlen.o
-
-all: palcode-$(SYSTEM)
-
-palcode-$(SYSTEM): palcode.ld $(OBJS)
-	$(LD) -relax -o $@ -T palcode.ld -Map $@.map $(OBJS)
-
-clean:
-	rm -f *.o
-	rm -f palcode-*
-
-pal.o: pal.S osf.h sys-$(SYSTEM).h core-$(CORE).h
-init.o: init.c hwrpb.h osf.h uart.h sys-$(SYSTEM).h core-$(CORE).h
-printf.o: printf.c uart.h
-uart.o: uart.c uart.h protos.h
-crb.o: crb.c hwrpb.h protos.h console.h uart.h
-console.o: console.c console.h protos.h
-pci.o: pci.c protos.h pci.h pci_regs.h
diff --git a/qemu/roms/qemu-palcode/console-low.S b/qemu/roms/qemu-palcode/console-low.S
deleted file mode 100644
index a03f4edab..000000000
--- a/qemu/roms/qemu-palcode/console-low.S
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Assembly helper routines for the emulation SRM console.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-	.set nomacro
-	.set noat
-	.text
-	.cfi_sections .debug_frame
-
-#define SAVE_ALL_SIZE	(18*8)
-
-	.globl	entInt
-	.type	entInt, @function
-	.cfi_startproc simple
-entInt:
-	.cfi_return_column 64
-	.cfi_def_cfa	$sp, 48
-	.cfi_rel_offset	64, 8
-	.cfi_rel_offset	$gp, 16
-	.cfi_rel_offset	$16, 24
-	.cfi_rel_offset	$17, 32
-	.cfi_rel_offset	$18, 40
-	lda	$sp, -SAVE_ALL_SIZE($sp)
-	.cfi_adjust_cfa_offset SAVE_ALL_SIZE
-	stq	$0, 0*8($sp)
-	stq	$1, 1*8($sp)
-	stq	$2, 2*8($sp)
-	stq	$3, 3*8($sp)
-	stq	$4, 4*8($sp)
-	stq	$5, 5*8($sp)
-	stq	$6, 6*8($sp)
-	stq	$7, 7*8($sp)
-	stq	$8, 9*8($sp)
-	stq	$19, 9*8($sp)
-	stq	$20, 10*8($sp)
-	stq	$21, 11*8($sp)
-	stq	$22, 12*8($sp)
-	stq	$23, 13*8($sp)
-	stq	$24, 14*8($sp)
-	stq	$25, 15*8($sp)
-	stq	$26, 16*8($sp)
-	stq	$27, 17*8($sp)
-	stq	$28, 18*8($sp)
-	.cfi_rel_offset $0, 0*8
-	.cfi_rel_offset $1, 1*8
-	.cfi_rel_offset $2, 2*8
-	.cfi_rel_offset $3, 3*8
-	.cfi_rel_offset $4, 4*8
-	.cfi_rel_offset $5, 5*8
-	.cfi_rel_offset $6, 6*8
-	.cfi_rel_offset $7, 7*8
-	.cfi_rel_offset $8, 8*8
-	.cfi_rel_offset $19, 9*8
-	.cfi_rel_offset $20, 10*8
-	.cfi_rel_offset $21, 11*8
-	.cfi_rel_offset $22, 12*8
-	.cfi_rel_offset $23, 13*8
-	.cfi_rel_offset $24, 14*8
-	.cfi_rel_offset $25, 15*8
-	.cfi_rel_offset $26, 16*8
-	.cfi_rel_offset $27, 17*8
-	.cfi_rel_offset $28, 18*8
-
-	bsr	$26, do_entInt	!samegp
-
-	ldq	$0, 0*8($sp)
-	ldq	$1, 1*8($sp)
-	ldq	$2, 2*8($sp)
-	ldq	$3, 3*8($sp)
-	ldq	$4, 4*8($sp)
-	ldq	$5, 5*8($sp)
-	ldq	$6, 6*8($sp)
-	ldq	$7, 7*8($sp)
-	ldq	$8, 9*8($sp)
-	ldq	$19, 9*8($sp)
-	ldq	$20, 10*8($sp)
-	ldq	$21, 11*8($sp)
-	ldq	$22, 12*8($sp)
-	ldq	$23, 13*8($sp)
-	ldq	$24, 14*8($sp)
-	ldq	$25, 15*8($sp)
-	ldq	$26, 16*8($sp)
-	ldq	$27, 17*8($sp)
-	ldq	$28, 18*8($sp)
-	lda	$sp, SAVE_ALL_SIZE($sp)
-	.cfi_adjust_cfa_offset -SAVE_ALL_SIZE
-	.cfi_restore	$0
-	.cfi_restore	$1
-	.cfi_restore	$2
-	.cfi_restore	$3
-	.cfi_restore	$4
-	.cfi_restore	$5
-	.cfi_restore	$6
-	.cfi_restore	$7
-	.cfi_restore	$8
-	.cfi_restore	$19
-	.cfi_restore	$20
-	.cfi_restore	$21
-	.cfi_restore	$22
-	.cfi_restore	$23
-	.cfi_restore	$24
-	.cfi_restore	$25
-	.cfi_restore	$26
-	.cfi_restore	$27
-	.cfi_restore	$28
-
-	call_pal 0x3f // rti
-
-	.cfi_endproc
-	.size	entInt, . - entInt
diff --git a/qemu/roms/qemu-palcode/console.c b/qemu/roms/qemu-palcode/console.c
deleted file mode 100644
index 382cf54d4..000000000
--- a/qemu/roms/qemu-palcode/console.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* The SRM console prompt.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include "protos.h"
-#include "console.h"
-#include "vgatables.h"
-
-
-static void
-output_crnl(void)
-{
-  crb_puts(0, "\r\n", 2);
-}
-
-static void
-output_bell(void)
-{
-  crb_puts(0, "\a", 1);
-}
-
-static void
-backspace_and_erase(void)
-{
-  crb_puts(0, "\b \b", 3);
-}
-
-static unsigned long
-getline(char *buf, unsigned long bufsize)
-{
-  unsigned long len = 0;
-  long c;
-
-  while (1)
-    {
-      c = crb_getc(0);
-      if (c < 0)
-	continue;
-      switch ((int)c)
-	{
-	case '\r':
-	case '\n':
-	  output_crnl();
-	  buf[len] = 0;
-	  return len;
-
-        case '\b':
-	case 0x7f: /* Delete */
-          if (len > 0)
-	    {
-	      backspace_and_erase();
-              len--;
-            }
-	  else
-	    output_bell();
-          break;
-
-        default:
-	  if (len + 1 < bufsize)
-	    {
-	      buf[len] = c;
-              crb_puts(0, buf+len, 1);
-	      len++;
-	    }
-	  else
-	    output_bell();
-	  break;
-        }
-    }
-}
-
-static inline void set_console_alarm(void)
-{
-  /* Just set a new timeout for 10ms = 10M ns.  */
-  set_alarm_rel(10 * 1000 * 1000);
-}
-
-void
-do_entInt(unsigned long type, unsigned long vector)
-{
-  switch (type)
-    {
-    case 0:
-      /* ??? SMP interrupt.  We're going to need this for starting up
-         secondary cpus.  */
-      break;
-    case 1:
-      /* Timer interrupt.  */
-      set_console_alarm();
-      break;
-    case 2:
-      /* ??? Device interrupt.  We're going to need this for virtio disk
-         operations at minimum.  */
-      break;
-    }
-}
-
-void
-do_console(void)
-{
-  char line[256];
-  unsigned long len;
-
-  wrkgp();
-  wrent(entInt, 0);
-  set_console_alarm();
-  swpipl(0);
-
-  if (have_vga)
-  {
-    unsigned short *vga, attr;
-    vga = pci_mem_base + SEG_CTEXT *16;
-    attr = 0x2000;
-    vga[0] = 'H' + attr;
-    vga[1] = 'e' + attr;
-    vga[2] = 'l' + attr;
-    vga[3] = 'l' + attr;
-    vga[4] = 'o' + attr;
-  }
-
-  while (1)
-    {
-      crb_puts(0, ">>> ", 4);
-      len = getline(line, sizeof(line));
-      crb_puts(0, "got: ", 5);
-      crb_puts(0, line, len);
-      output_crnl();
-    }
-}
diff --git a/qemu/roms/qemu-palcode/console.h b/qemu/roms/qemu-palcode/console.h
deleted file mode 100644
index 98ac0156b..000000000
--- a/qemu/roms/qemu-palcode/console.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Console Callback Routines.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef CONSOLE_H
-#define CONSOLE_H 1
-
-#define CRB_GETC		0x01
-#define CRB_PUTS		0x02
-#define CRB_RESET_TERM		0x03
-#define CRB_SET_TERM_INT	0x04
-#define CRB_SET_TERM_CTL	0x05
-#define CRB_PROCESS_KEYCODE	0x06
-
-#define CRB_OPEN		0x10
-#define CRB_CLOSE		0x11
-#define CRB_IOCTL		0x12
-#define CRB_READ		0x13
-#define CRB_WRITE		0x14
-
-#define CRB_SET_ENV		0x20
-#define CRB_RESET_ENV		0x21
-#define CRB_GET_ENV		0x22
-#define CRB_SAVE_ENV		0x23
-
-#define CRB_PSWITCH		0x30
-
-extern unsigned long crb_getc(long unit);
-extern unsigned long crb_process_keycode(long unit, long keycode, long again);
-extern unsigned long crb_puts(long unit, const char *buf, unsigned long length);
-extern unsigned long crb_reset_term(long unit);
-
-extern unsigned long crb_open(const char *devstr,  unsigned long length);
-extern unsigned long crb_close(long channel);
-extern unsigned long crb_read(long channel, unsigned long length,
-                              char *buf, unsigned long block);
-extern unsigned long crb_write(long channel, unsigned long length,
-                               const char *buf, unsigned long block);
-
-extern unsigned long crb_get_env(unsigned long id, char *buf,
-                                 unsigned long length);
-extern unsigned long crb_set_env(unsigned long id, const char *buf,
-                                 unsigned long length);
-
-#endif /* CONSOLE_H */
diff --git a/qemu/roms/qemu-palcode/core-cia.h b/qemu/roms/qemu-palcode/core-cia.h
deleted file mode 100644
index 644fbd760..000000000
--- a/qemu/roms/qemu-palcode/core-cia.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* Memory layout and register descriptions for the CIA/PYXIS chipset.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef CIA_H
-#define CIA_H
-
-#define IDENT_ADDR 0xfffffc0000000000UL
-
-#define CIA_MEM_R1_MASK 0x1fffffff  /* SPARSE Mem region 1 mask is 29 bits */
-#define CIA_MEM_R2_MASK 0x07ffffff  /* SPARSE Mem region 2 mask is 27 bits */
-#define CIA_MEM_R3_MASK 0x03ffffff  /* SPARSE Mem region 3 mask is 26 bits */
-
-/*
- * 21171-CA Control and Status Registers
- */
-#define CIA_IOC_CIA_REV			(IDENT_ADDR + 0x8740000080UL)
-#  define CIA_REV_MASK			0xff
-#define CIA_IOC_PCI_LAT			(IDENT_ADDR + 0x87400000C0UL)
-#define CIA_IOC_CIA_CTRL		(IDENT_ADDR + 0x8740000100UL)
-#  define CIA_CTRL_PCI_EN		(1 << 0)
-#  define CIA_CTRL_PCI_LOCK_EN		(1 << 1)
-#  define CIA_CTRL_PCI_LOOP_EN		(1 << 2)
-#  define CIA_CTRL_FST_BB_EN		(1 << 3)
-#  define CIA_CTRL_PCI_MST_EN		(1 << 4)
-#  define CIA_CTRL_PCI_MEM_EN		(1 << 5)
-#  define CIA_CTRL_PCI_REQ64_EN		(1 << 6)
-#  define CIA_CTRL_PCI_ACK64_EN		(1 << 7)
-#  define CIA_CTRL_ADDR_PE_EN		(1 << 8)
-#  define CIA_CTRL_PERR_EN		(1 << 9)
-#  define CIA_CTRL_FILL_ERR_EN		(1 << 10)
-#  define CIA_CTRL_MCHK_ERR_EN		(1 << 11)
-#  define CIA_CTRL_ECC_CHK_EN		(1 << 12)
-#  define CIA_CTRL_ASSERT_IDLE_BC	(1 << 13)
-#  define CIA_CTRL_COM_IDLE_BC		(1 << 14)
-#  define CIA_CTRL_CSR_IOA_BYPASS	(1 << 15)
-#  define CIA_CTRL_IO_FLUSHREQ_EN	(1 << 16)
-#  define CIA_CTRL_CPU_FLUSHREQ_EN	(1 << 17)
-#  define CIA_CTRL_ARB_CPU_EN		(1 << 18)
-#  define CIA_CTRL_EN_ARB_LINK		(1 << 19)
-#  define CIA_CTRL_RD_TYPE_SHIFT	20
-#  define CIA_CTRL_RL_TYPE_SHIFT	24
-#  define CIA_CTRL_RM_TYPE_SHIFT	28
-#  define CIA_CTRL_EN_DMA_RD_PERF	(1 << 31)
-#define CIA_IOC_CIA_CNFG		(IDENT_ADDR + 0x8740000140UL)
-#  define CIA_CNFG_IOA_BWEN		(1 << 0)
-#  define CIA_CNFG_PCI_MWEN		(1 << 4)
-#  define CIA_CNFG_PCI_DWEN		(1 << 5)
-#  define CIA_CNFG_PCI_WLEN		(1 << 8)
-#define CIA_IOC_FLASH_CTRL		(IDENT_ADDR + 0x8740000200UL)
-#define CIA_IOC_HAE_MEM			(IDENT_ADDR + 0x8740000400UL)
-#define CIA_IOC_HAE_IO			(IDENT_ADDR + 0x8740000440UL)
-#define CIA_IOC_CFG			(IDENT_ADDR + 0x8740000480UL)
-#define CIA_IOC_CACK_EN			(IDENT_ADDR + 0x8740000600UL)
-#  define CIA_CACK_EN_LOCK_EN		(1 << 0)
-#  define CIA_CACK_EN_MB_EN		(1 << 1)
-#  define CIA_CACK_EN_SET_DIRTY_EN	(1 << 2)
-#  define CIA_CACK_EN_BC_VICTIM_EN	(1 << 3)
-
-
-/*
- * 21171-CA Diagnostic Registers
- */
-#define CIA_IOC_CIA_DIAG		(IDENT_ADDR + 0x8740002000UL)
-#define CIA_IOC_DIAG_CHECK		(IDENT_ADDR + 0x8740003000UL)
-
-/*
- * 21171-CA Performance Monitor registers
- */
-#define CIA_IOC_PERF_MONITOR		(IDENT_ADDR + 0x8740004000UL)
-#define CIA_IOC_PERF_CONTROL		(IDENT_ADDR + 0x8740004040UL)
-
-/*
- * 21171-CA Error registers
- */
-#define CIA_IOC_CPU_ERR0		(IDENT_ADDR + 0x8740008000UL)
-#define CIA_IOC_CPU_ERR1		(IDENT_ADDR + 0x8740008040UL)
-#define CIA_IOC_CIA_ERR			(IDENT_ADDR + 0x8740008200UL)
-#  define CIA_ERR_COR_ERR		(1 << 0)
-#  define CIA_ERR_UN_COR_ERR		(1 << 1)
-#  define CIA_ERR_CPU_PE		(1 << 2)
-#  define CIA_ERR_MEM_NEM		(1 << 3)
-#  define CIA_ERR_PCI_SERR		(1 << 4)
-#  define CIA_ERR_PERR			(1 << 5)
-#  define CIA_ERR_PCI_ADDR_PE		(1 << 6)
-#  define CIA_ERR_RCVD_MAS_ABT		(1 << 7)
-#  define CIA_ERR_RCVD_TAR_ABT		(1 << 8)
-#  define CIA_ERR_PA_PTE_INV		(1 << 9)
-#  define CIA_ERR_FROM_WRT_ERR		(1 << 10)
-#  define CIA_ERR_IOA_TIMEOUT		(1 << 11)
-#  define CIA_ERR_LOST_CORR_ERR		(1 << 16)
-#  define CIA_ERR_LOST_UN_CORR_ERR	(1 << 17)
-#  define CIA_ERR_LOST_CPU_PE		(1 << 18)
-#  define CIA_ERR_LOST_MEM_NEM		(1 << 19)
-#  define CIA_ERR_LOST_PERR		(1 << 21)
-#  define CIA_ERR_LOST_PCI_ADDR_PE	(1 << 22)
-#  define CIA_ERR_LOST_RCVD_MAS_ABT	(1 << 23)
-#  define CIA_ERR_LOST_RCVD_TAR_ABT	(1 << 24)
-#  define CIA_ERR_LOST_PA_PTE_INV	(1 << 25)
-#  define CIA_ERR_LOST_FROM_WRT_ERR	(1 << 26)
-#  define CIA_ERR_LOST_IOA_TIMEOUT	(1 << 27)
-#  define CIA_ERR_VALID			(1 << 31)
-#define CIA_IOC_CIA_STAT		(IDENT_ADDR + 0x8740008240UL)
-#define CIA_IOC_ERR_MASK		(IDENT_ADDR + 0x8740008280UL)
-#define CIA_IOC_CIA_SYN			(IDENT_ADDR + 0x8740008300UL)
-#define CIA_IOC_MEM_ERR0		(IDENT_ADDR + 0x8740008400UL)
-#define CIA_IOC_MEM_ERR1		(IDENT_ADDR + 0x8740008440UL)
-#define CIA_IOC_PCI_ERR0		(IDENT_ADDR + 0x8740008800UL)
-#define CIA_IOC_PCI_ERR1		(IDENT_ADDR + 0x8740008840UL)
-#define CIA_IOC_PCI_ERR3		(IDENT_ADDR + 0x8740008880UL)
-
-/*
- * 21171-CA System configuration registers
- */
-#define CIA_IOC_MCR			(IDENT_ADDR + 0x8750000000UL)
-#define CIA_IOC_MBA0			(IDENT_ADDR + 0x8750000600UL)
-#define CIA_IOC_MBA2			(IDENT_ADDR + 0x8750000680UL)
-#define CIA_IOC_MBA4			(IDENT_ADDR + 0x8750000700UL)
-#define CIA_IOC_MBA6			(IDENT_ADDR + 0x8750000780UL)
-#define CIA_IOC_MBA8			(IDENT_ADDR + 0x8750000800UL)
-#define CIA_IOC_MBAA			(IDENT_ADDR + 0x8750000880UL)
-#define CIA_IOC_MBAC			(IDENT_ADDR + 0x8750000900UL)
-#define CIA_IOC_MBAE			(IDENT_ADDR + 0x8750000980UL)
-#define CIA_IOC_TMG0			(IDENT_ADDR + 0x8750000B00UL)
-#define CIA_IOC_TMG1			(IDENT_ADDR + 0x8750000B40UL)
-#define CIA_IOC_TMG2			(IDENT_ADDR + 0x8750000B80UL)
-
-/*
- * 2117A-CA PCI Address and Scatter-Gather Registers.
- */
-#define CIA_IOC_PCI_TBIA		(IDENT_ADDR + 0x8760000100UL)
-
-#define CIA_IOC_PCI_W0_BASE		(IDENT_ADDR + 0x8760000400UL)
-#define CIA_IOC_PCI_W0_MASK		(IDENT_ADDR + 0x8760000440UL)
-#define CIA_IOC_PCI_T0_BASE		(IDENT_ADDR + 0x8760000480UL)
-
-#define CIA_IOC_PCI_W1_BASE		(IDENT_ADDR + 0x8760000500UL)
-#define CIA_IOC_PCI_W1_MASK		(IDENT_ADDR + 0x8760000540UL)
-#define CIA_IOC_PCI_T1_BASE		(IDENT_ADDR + 0x8760000580UL)
-
-#define CIA_IOC_PCI_W2_BASE		(IDENT_ADDR + 0x8760000600UL)
-#define CIA_IOC_PCI_W2_MASK		(IDENT_ADDR + 0x8760000640UL)
-#define CIA_IOC_PCI_T2_BASE		(IDENT_ADDR + 0x8760000680UL)
-
-#define CIA_IOC_PCI_W3_BASE		(IDENT_ADDR + 0x8760000700UL)
-#define CIA_IOC_PCI_W3_MASK		(IDENT_ADDR + 0x8760000740UL)
-#define CIA_IOC_PCI_T3_BASE		(IDENT_ADDR + 0x8760000780UL)
-
-#define CIA_IOC_PCI_Wn_BASE(N)	(IDENT_ADDR + 0x8760000400UL + (N)*0x100) 
-#define CIA_IOC_PCI_Wn_MASK(N)	(IDENT_ADDR + 0x8760000440UL + (N)*0x100) 
-#define CIA_IOC_PCI_Tn_BASE(N)	(IDENT_ADDR + 0x8760000480UL + (N)*0x100) 
-
-#define CIA_IOC_PCI_W_DAC		(IDENT_ADDR + 0x87600007C0UL)
-
-/*
- * 2117A-CA Address Translation Registers.
- */
-
-/* 8 tag registers, the first 4 of which are lockable.  */
-#define CIA_IOC_TB_TAGn(n) \
-	(IDENT_ADDR + 0x8760000800UL + (n)*0x40)
-
-/* 4 page registers per tag register.  */
-#define CIA_IOC_TBn_PAGEm(n,m) \
-	(IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
-
-/*
- * Memory spaces:
- */
-#define CIA_IACK_SC			(IDENT_ADDR + 0x8720000000UL)
-#define CIA_CONF			(IDENT_ADDR + 0x8700000000UL)
-#define CIA_IO				(IDENT_ADDR + 0x8580000000UL)
-#define CIA_SPARSE_MEM			(IDENT_ADDR + 0x8000000000UL)
-#define CIA_SPARSE_MEM_R2		(IDENT_ADDR + 0x8400000000UL)
-#define CIA_SPARSE_MEM_R3		(IDENT_ADDR + 0x8500000000UL)
-#define CIA_DENSE_MEM		        (IDENT_ADDR + 0x8600000000UL)
-#define CIA_BW_MEM			(IDENT_ADDR + 0x8800000000UL)
-#define CIA_BW_IO			(IDENT_ADDR + 0x8900000000UL)
-#define CIA_BW_CFG_0			(IDENT_ADDR + 0x8a00000000UL)
-#define CIA_BW_CFG_1			(IDENT_ADDR + 0x8b00000000UL)
-
-/*
- * ALCOR's GRU ASIC registers
- */
-#define GRU_INT_REQ			(IDENT_ADDR + 0x8780000000UL)
-#define GRU_INT_MASK			(IDENT_ADDR + 0x8780000040UL)
-#define GRU_INT_EDGE			(IDENT_ADDR + 0x8780000080UL)
-#define GRU_INT_HILO			(IDENT_ADDR + 0x87800000C0UL)
-#define GRU_INT_CLEAR			(IDENT_ADDR + 0x8780000100UL)
-
-#define GRU_CACHE_CNFG			(IDENT_ADDR + 0x8780000200UL)
-#define GRU_SCR				(IDENT_ADDR + 0x8780000300UL)
-#define GRU_LED				(IDENT_ADDR + 0x8780000800UL)
-#define GRU_RESET			(IDENT_ADDR + 0x8780000900UL)
-
-#define ALCOR_GRU_INT_REQ_BITS		0x800fffffUL
-#define XLT_GRU_INT_REQ_BITS		0x80003fffUL
-#define GRU_INT_REQ_BITS		(alpha_mv.sys.cia.gru_int_req_bits+0)
-
-/*
- * PYXIS interrupt control registers
- */
-#define PYXIS_INT_REQ			(IDENT_ADDR + 0x87A0000000UL)
-#define PYXIS_INT_MASK			(IDENT_ADDR + 0x87A0000040UL)
-#define PYXIS_INT_HILO			(IDENT_ADDR + 0x87A00000C0UL)
-#define PYXIS_INT_ROUTE			(IDENT_ADDR + 0x87A0000140UL)
-#define PYXIS_GPO			(IDENT_ADDR + 0x87A0000180UL)
-#define PYXIS_INT_CNFG			(IDENT_ADDR + 0x87A00001C0UL)
-#define PYXIS_RT_COUNT			(IDENT_ADDR + 0x87A0000200UL)
-#define PYXIS_INT_TIME			(IDENT_ADDR + 0x87A0000240UL)
-#define PYXIS_IIC_CTRL			(IDENT_ADDR + 0x87A00002C0UL)
-#define PYXIS_RESET			(IDENT_ADDR + 0x8780000900UL)
-
-/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
-#define PYXIS_DAC_OFFSET		(1UL << 40)
-
-#ifdef __ASSEMBLER__
-
-/* Unfortunately, GAS doesn't attempt any interesting constructions of
-   64-bit constants, dropping them all into the .lit8 section.  It is
-   better for us to build these by hand.  */
-.macro	LOAD_PHYS_PYXIS_INT ret
-	lda	\ret, 0x87a
-	sll	\ret, 28, \ret
-.endm
-
-.macro	LOAD_KSEG_PCI_IO ret
-	lda	\ret, -887
-	sll	\ret, 32, \ret
-.endm
-
-.macro	SYS_WHAMI	ret
-	mov	0, \ret
-.endm
-
-.macro	SYS_ACK_SMP	t0, t1, t2
-	br	MchkBugCheck
-.endm
-
-#else
-
-static inline unsigned long inb(unsigned long port)
-{
-  return *(volatile unsigned char *)(CIA_BW_IO + port);
-}
-
-static inline void outb(unsigned long port, unsigned char val)
-{
-  *(volatile unsigned char *)(CIA_BW_IO + port) = val;
-}
-
-
-#endif
-
-#endif /* CIA_H */
diff --git a/qemu/roms/qemu-palcode/core-typhoon.h b/qemu/roms/qemu-palcode/core-typhoon.h
deleted file mode 100644
index 96a0a9007..000000000
--- a/qemu/roms/qemu-palcode/core-typhoon.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Memory layout and register descriptions for the TSUNAMI/TYPHOON chipset.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef TYPHOON_H
-#define TYPHOON_H 1
-
-/* Assume a 43-bit KSEG for now.  */
-#define PIO_PHYS_ADDR   0x80000000000
-#define PIO_KSEG_ADDR   (0xfffffc0000000000 + 0x10000000000)
-
-/* CCHIP REGISTERS */
-
-#define TYPHOON_CCHIP		0x1a0000000
-
-#define TYPHOON_CCHIP_CSC	0x0000
-#define TYPHOON_CCHIP_MTR	0x0040
-#define TYPHOON_CCHIP_MISC	0x0080
-#define TYPHOON_CCHIP_MPD	0x00c0
-#define TYPHOON_CCHIP_AAR0	0x0100
-#define TYPHOON_CCHIP_AAR1	0x0140
-#define TYPHOON_CCHIP_AAR2	0x0180
-#define TYPHOON_CCHIP_AAR3	0x01c0
-#define TYPHOON_CCHIP_DIM0	0x0200
-#define TYPHOON_CCHIP_DIM1	0x0240
-#define TYPHOON_CCHIP_DIR0	0x0280
-#define TYPHOON_CCHIP_DIR1	0x02c0
-#define TYPHOON_CCHIP_DRIR	0x0300
-#define TYPHOON_CCHIP_PRBEN	0x0340
-#define TYPHOON_CCHIP_IIC0	0x0380
-#define TYPHOON_CCHIP_IIC1	0x03c0
-#define TYPHOON_CCHIP_MPR0	0x0400
-#define TYPHOON_CCHIP_MPR1	0x0440
-#define TYPHOON_CCHIP_MPR2	0x0480
-#define TYPHOON_CCHIP_MPR3	0x04c0
-#define TYPHOON_CCHIP_TTR	0x0580
-#define TYPHOON_CCHIP_TDR	0x05c0
-#define TYPHOON_CCHIP_DIM2	0x0600
-#define TYPHOON_CCHIP_DIM3	0x0640
-#define TYPHOON_CCHIP_DIR2	0x0680
-#define TYPHOON_CCHIP_DIR3	0x06c0
-#define TYPHOON_CCHIP_IIC2	0x0700
-#define TYPHOON_CCHIP_IIC3	0x0740
-#define TYPHOON_CCHIP_PWR	0x0780
-#define TYPHOON_CCHIP_CMONCTLA	0x0c00
-#define TYPHOON_CCHIP_CMONCTLB	0x0c40
-#define TYPHOON_CCHIP_CMONCNT01	0x0c80
-#define TYPHOON_CCHIP_CMONCNT23	0x0cc0
-
-/* DCHIP REGISTERS */
-
-#define TYPHOON_DCHIP		0x1b0000000
-
-#define TYPHOON_DCHIP_DSC	0x0800
-#define TYPHOON_DCHIP_STR	0x0840
-#define TYPHOON_DCHIP_DREV	0x0880
-#define TYPHOON_DCHIP_DSC2	0x08c0
-
-/* PCHIP REGISTERS */
-
-#define TYPHOON_PCHIP0		0x180000000
-#define TYPHOON_PCHIP1		0x380000000
-
-#define TYPHOON_PCHIP_WSBA0	0x0000
-#define TYPHOON_PCHIP_WSBA1	0x0040
-#define TYPHOON_PCHIP_WSBA2	0x0080
-#define TYPHOON_PCHIP_WSBA3	0x00c0
-#define TYPHOON_PCHIP_WSM0	0x0100
-#define TYPHOON_PCHIP_WSM1	0x0140
-#define TYPHOON_PCHIP_WSM2	0x0180
-#define TYPHOON_PCHIP_WSM3	0x01c0
-#define TYPHOON_PCHIP_TBA0	0x0200
-#define TYPHOON_PCHIP_TBA1	0x0240
-#define TYPHOON_PCHIP_TBA2	0x0280
-#define TYPHOON_PCHIP_TBA3	0x02c0
-#define TYPHOON_PCHIP_PCTL	0x0300
-#define TYPHOON_PCHIP_PLAT	0x0340
-#define TYPHOON_PCHIP_PERROR	0x03c0
-#define TYPHOON_PCHIP_PERRMASK	0x0400
-#define TYPHOON_PCHIP_PERRSET	0x0440
-#define TYPHOON_PCHIP_TLBIV	0x0480
-#define TYPHOON_PCHIP_TLBIA	0x04c0
-#define TYPHOON_PCHIP_PMONCTL	0x0500
-#define TYPHOON_PCHIP_PMONCNT	0x0540
-#define TYPHOON_PCHIP_SPRST	0x0800
-
-/* PCI ADDRESSES */
-
-#define TYPHOON_PCHIP0_PCI_MEM	0
-#define TYPHOON_PCHIP0_PCI_IO	0x1fc000000
-#define TYPHOON_PCHIP0_PCI_CONF	0x1fe000000
-#define TYPHOON_PCHIP0_PCI_IACK	0x1f8000000
-
-#ifdef __ASSEMBLER__
-
-#include "pal.h"
-
-#define	ptCpuDIR	ptSys0
-#define	ptCpuIIC	ptSys1
-
-/* Unfortunately, GAS doesn't attempt any interesting constructions of
-   64-bit constants, dropping them all into the .lit8 section.  It is
-   better for us to build these by hand.  */
-.macro	LOAD_PHYS_CCHIP ret
-	lda	\ret, (PIO_PHYS_ADDR + TYPHOON_CCHIP) >> 29
-	sll	\ret, 29, \ret
-.endm
-
-.macro	LOAD_PHYS_PCHIP0 ret
-	lda	\ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0) >> 29
-	sll	\ret, 29, \ret
-.endm
-
-.macro	LOAD_PHYS_PCHIP0_IACK ret
-	.set	macro
-	lda	\ret, (PIO_PHYS_ADDR + TYPHOON_PCHIP0_PCI_IACK) >> 24
-	.set	nomacro
-	sll	\ret, 24, \ret
-.endm
-
-.macro	LOAD_KSEG_PCI_IO ret
-	.set	macro
-	// Note that GAS shifts are logical.  Force arithmetic shift style
-	// results by negating before and after the shift.
-	lda	\ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO) >> 20)
-	.set	nomacro
-	sll	\ret, 20, \ret
-.endm
-
-.macro	LOAD_KSEG_PCI_CONF ret
-	.set	macro
-	// Note that GAS shifts are logical.  Force arithmetic shift style
-	// results by negating before and after the shift.
-	lda	\ret, -(-(PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_CONF) >> 20)
-	.set	nomacro
-	sll	\ret, 20, \ret
-.endm
-
-.macro	SYS_WHAMI	ret
-	LOAD_PHYS_CCHIP	\ret
-	ldq_p		\ret, TYPHOON_CCHIP_MISC(\ret)
-	and		\ret, 3, \ret
-.endm
-
-/* ACK the Interprocessor Interrupt.  */
-.macro	SYS_ACK_SMP	t0, t1, t2
-	LOAD_PHYS_CCHIP	\t0
-	ldq_p		\t1, TYPHOON_CCHIP_MISC(\t0)
-	and		\t1, 3, \t1
-	addq		\t1, 8, \t1
-	lda		\t2, 1
-	sll		\t2, \t1, \t2
-	stq_p		\t2, TYPHOON_CCHIP_MISC(\t0)
-.endm
-
-/* ACK the Clock Interrupt.  */
-.macro	SYS_ACK_CLK	t0, t1, t2
-	LOAD_PHYS_CCHIP	\t0
-	ldq_p		\t1, TYPHOON_CCHIP_MISC(\t0)
-	and		\t1, 3, \t1
-	addq		\t1, 4, \t1
-	lda		\t2, 1
-	sll		\t2, \t1, \t2
-	stq_p		\t2, TYPHOON_CCHIP_MISC(\t0)
-.endm
-
-/* Interrupt another CPU.  */
-.macro SYS_WRIPIR	target, t0, t1, t2
-	LOAD_PHYS_CCHIP	\t0
-	mov		1, \t1
-	and		\target, 3, \t2
-	addq		\t2, 12, \t2
-	sll		\t1, \t2, \t1
-	stq_p		\t1, TYPHOON_CCHIP_MISC(\t0)
-.endm
-
-#endif /* ASSEMBLER */
-#endif /* TYPHOON_H */
diff --git a/qemu/roms/qemu-palcode/crb.c b/qemu/roms/qemu-palcode/crb.c
deleted file mode 100644
index c79d4b2ac..000000000
--- a/qemu/roms/qemu-palcode/crb.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Console Callback Routines.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include "hwrpb.h"
-#include "protos.h"
-#include "console.h"
-#include "uart.h"
-
-
-/* All routines use the high bit to signal error.  */
-#define ERR	0x8000000000000000ul
-
-
-unsigned long
-crb_getc(long unit)
-{
-  /* Multiple consoles not yet supported.  */
-  if (unit != 0)
-    return ERR;
-
-  return uart_getchar(COM1);
-}
-
-unsigned long
-crb_process_keycode(long unit, long keycode, long again)
-{
-  /* This routine might be needed for real keyboards, and mostly for
-     internationalization stuff.  */
-  /* Return Failure: routine not supported.  */
-  return 0xc000000000000000ul;
-}
-
-unsigned long
-crb_puts(long unit, const char *buf, unsigned long length)
-{
-  unsigned int orig_length = length;
-
-  /* Multiple consoles not yet supported.  */
-  if (unit != 0)
-    return ERR;
-
-  for (; length != 0; --length, ++buf)
-    uart_putchar_raw(COM1, (unsigned char)*buf);
-
-  /* Bits <31:0> of the return value are the number of bytes written.
-     To me that implies that the input value must be 32-bit, but v2
-     of the ARM doesn't explicitly say.  */
-  return orig_length;
-}
-
-unsigned long
-crb_reset_term(long unit)
-{
-  /* Multiple consoles not yet supported.  */
-  if (unit != 0)
-    return ERR;
-
-  uart_init_line(COM1, 9600);
-  return 0;
-}
-
-static unsigned long
-crb_set_term_ctl(long unit, long ctb)
-{
-  /* ??? The contents of the CTB do not seem to be defined anywhere.
-     How, therefore, can the user set new contents?  */
-  return ERR;
-}
-
-static unsigned long
-crb_set_term_int(long unit, long mask)
-{
-  /* We do no buffering, therefore we don't need to support interrupts.  */
-  if (unit != 0 || (mask & 0x22) != 0)
-    return ERR;
-  return 0;
-}
-
-unsigned long
-crb_open(const char *devstr,  unsigned long length)
-{
-  /* FIXME */
-  return ERR;
-}
-
-unsigned long
-crb_close(long channel)
-{
-  /* FIXME */
-  return 0;
-}
-
-static unsigned long
-crb_ioctl(long channel)
-{
-  /* We do not, nor will not, support virtual tapes.  */
-  return ERR;
-}
-
-unsigned long
-crb_read(long channel, unsigned long length, char *buf, unsigned long block)
-{
-  /* FIXME */
-  return ERR;
-}
-
-unsigned long
-crb_write(long channel, unsigned long length, const char *buf,
-          unsigned long block)
-{
-  /* FIXME */
-  return ERR;
-}
-
-unsigned long
-crb_get_env(unsigned long id, char *buf, unsigned long length)
-{
-  /* FIXME */
-  return 0xc000000000000000ul;
-}
-
-unsigned long
-crb_set_env(unsigned long id, const char *buf, unsigned long length)
-{
-  /* FIXME */
-  return 0xc000000000000000ul;
-}
-
-static unsigned long
-crb_reset_env(unsigned long id, char *buf, unsigned long length)
-{
-  /* FIXME */
-  return 0xc000000000000000ul;
-}
-
-static unsigned long
-crb_save_env(void)
-{
-  /* FIXME */
-  return 0xc000000000000000ul;
-}
-
-static unsigned long
-crb_pswitch(long action, long cpu_id)
-{
-  /* Why would we ever need to support switching primary processor?  */
-  return ERR;
-}
-
-static unsigned long __attribute__((used))
-int_crb_dispatch(long select, long a1, long a2, long a3, long a4)
-{
-  switch (select)
-    {
-    case CRB_GETC:
-      return crb_getc(a1);
-    case CRB_PUTS:
-      return crb_puts(a1, (const char *)a2, a3);
-    case CRB_RESET_TERM:
-      return crb_reset_term(a1);
-    case CRB_SET_TERM_INT:
-      return crb_set_term_int(a1, a2);
-    case CRB_SET_TERM_CTL:
-      return crb_set_term_ctl(a1, a2);
-    case CRB_PROCESS_KEYCODE:
-      return crb_process_keycode(a1, a2, a3);
-
-    case CRB_OPEN:
-      return crb_open((const char*)a1, a2);
-    case CRB_CLOSE:
-      return crb_close(a1);
-    case CRB_IOCTL:
-      return crb_ioctl(a1);
-    case CRB_READ:
-      return crb_read(a1, a2, (char *)a3, a4);
-    case CRB_WRITE:
-      return crb_write(a1, a2, (const char *)a3, a4);
-
-    case CRB_SET_ENV:
-      return crb_set_env(a1, (const char *)a2, a3);
-    case CRB_RESET_ENV:
-      return crb_reset_env(a1, (char *)a2, a3);
-    case CRB_GET_ENV:
-      return crb_get_env(a1, (char *)a2, a3);
-    case CRB_SAVE_ENV:
-      return crb_save_env();
-
-    case CRB_PSWITCH:
-      return crb_pswitch(a1, a2);
-    }
-  return ERR;
-}
-
-static unsigned long __attribute__((used))
-int_crb_fixup(unsigned long vptptr, unsigned long hwrpb)
-{
-  /* Given that this console is written to use the KSEG, and not be
-     mapped into any page-table address space, it doesn't seem like
-     we need to do anything at all here.  */
-  return 0;
-}
-
-/* The CRB DISPATCH and FIXUP functions are defined to use the VMS
-   calling convention.  This has several effects: 
-     (1) The set of call-saved registers is different.
-     (2) $27 contains the procdesc_struct, not the called function.
-   Map between the two calling conventions here.  */
-
-asm(".macro	VMStoUNIX name\n"
-"	.globl	\\name\n"
-"	.ent	\\name\n"
-"\\name:\n"
-"	.frame	$sp, 64, $26, 0\n"
-"	subq	$sp, 64, $sp\n"
-"	stq	$26, 0($sp)\n"
-"	stq	$2, 8($sp)\n"
-"	stq	$3, 16($sp)\n"
-"	stq	$4, 24($sp)\n"
-"	stq	$5, 32($sp)\n"
-"	stq	$6, 40($sp)\n"
-"	stq	$7, 48($sp)\n"
-"	stq	$8, 56($sp)\n"
-"	.mask	0x40001fc, 0\n"
-"	.prologue 2\n"
-"	br	$gp, .+4\n"
-"	ldgp	$gp, 0($gp)\n"
-"	bsr	$26, int_\\name !samegp\n"
-"	ldq	$26, 0($sp)\n"
-"	ldq	$2, 8($sp)\n"
-"	ldq	$3, 16($sp)\n"
-"	ldq	$4, 24($sp)\n"
-"	ldq	$5, 32($sp)\n"
-"	ldq	$6, 40($sp)\n"
-"	ldq	$7, 48($sp)\n"
-"	ldq	$8, 56($sp)\n"
-"	addq	$sp, 64, $sp\n"
-"	ret\n"
-"	.end	\\name\n"
-".endm\n"
-"	VMStoUNIX	crb_dispatch\n"
-"	VMStoUNIX	crb_fixup\n"
-);
diff --git a/qemu/roms/qemu-palcode/hwrpb.h b/qemu/roms/qemu-palcode/hwrpb.h
deleted file mode 100644
index 2166bad7d..000000000
--- a/qemu/roms/qemu-palcode/hwrpb.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* Layout and contents of the HardWare Resource Parameter Block (HWRPB).
-
-   This file is copied intact from the Linux kernel.  As such, it is
-   covered by the GNU General Public License, v2.0.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef __ALPHA_HWRPB_H
-#define __ALPHA_HWRPB_H
-
-#define INIT_HWRPB ((struct hwrpb_struct *) 0x10000000)
-
-/*
- * DEC processor types for Alpha systems.  Found in HWRPB.
- * These values are architected.
- */
-
-#define EV3_CPU                 1       /* EV3                  */
-#define EV4_CPU                 2       /* EV4 (21064)          */
-#define LCA4_CPU                4       /* LCA4 (21066/21068)   */
-#define EV5_CPU                 5       /* EV5 (21164)          */
-#define EV45_CPU                6       /* EV4.5 (21064/xxx)    */
-#define EV56_CPU		7	/* EV5.6 (21164)	*/
-#define EV6_CPU			8	/* EV6 (21264)		*/
-#define PCA56_CPU		9	/* PCA56 (21164PC)	*/
-#define PCA57_CPU		10	/* PCA57 (notyet)	*/
-#define EV67_CPU		11	/* EV67 (21264A)	*/
-#define EV68CB_CPU		12	/* EV68CB (21264C)	*/
-#define EV68AL_CPU		13	/* EV68AL (21264B)	*/
-#define EV68CX_CPU		14	/* EV68CX (21264D)	*/
-#define EV7_CPU			15	/* EV7 (21364)		*/
-#define EV79_CPU		16	/* EV79 (21364??)	*/
-#define EV69_CPU		17	/* EV69 (21264/EV69A)	*/
-
-/*
- * DEC system types for Alpha systems.  Found in HWRPB.
- * These values are architected.
- */
-
-#define ST_ADU			  1	/* Alpha ADU systype	*/
-#define ST_DEC_4000		  2	/* Cobra systype	*/
-#define ST_DEC_7000		  3	/* Ruby systype		*/
-#define ST_DEC_3000_500		  4	/* Flamingo systype	*/
-#define ST_DEC_2000_300		  6	/* Jensen systype	*/
-#define ST_DEC_3000_300		  7	/* Pelican systype	*/
-#define ST_DEC_2100_A500	  9	/* Sable systype	*/
-#define ST_DEC_AXPVME_64	 10	/* AXPvme system type	*/
-#define ST_DEC_AXPPCI_33	 11	/* NoName system type	*/
-#define ST_DEC_TLASER		 12	/* Turbolaser systype	*/
-#define ST_DEC_2100_A50		 13	/* Avanti systype	*/
-#define ST_DEC_MUSTANG		 14	/* Mustang systype	*/
-#define ST_DEC_ALCOR		 15	/* Alcor (EV5) systype	*/
-#define ST_DEC_1000		 17	/* Mikasa systype	*/
-#define ST_DEC_EB64		 18	/* EB64 systype		*/
-#define ST_DEC_EB66		 19	/* EB66 systype		*/
-#define ST_DEC_EB64P		 20	/* EB64+ systype	*/
-#define ST_DEC_BURNS		 21	/* laptop systype	*/
-#define ST_DEC_RAWHIDE		 22	/* Rawhide systype	*/
-#define ST_DEC_K2		 23	/* K2 systype		*/
-#define ST_DEC_LYNX		 24	/* Lynx systype		*/
-#define ST_DEC_XL		 25	/* Alpha XL systype	*/
-#define ST_DEC_EB164		 26	/* EB164 systype	*/
-#define ST_DEC_NORITAKE		 27	/* Noritake systype	*/
-#define ST_DEC_CORTEX		 28	/* Cortex systype	*/
-#define ST_DEC_MIATA		 30	/* Miata systype        */
-#define ST_DEC_XXM		 31	/* XXM systype		*/
-#define ST_DEC_TAKARA		 32	/* Takara systype	*/
-#define ST_DEC_YUKON		 33	/* Yukon systype	*/
-#define ST_DEC_TSUNAMI		 34	/* Tsunami systype	*/
-#define ST_DEC_WILDFIRE		 35	/* Wildfire systype	*/
-#define ST_DEC_CUSCO		 36	/* CUSCO systype	*/
-#define ST_DEC_EIGER		 37	/* Eiger systype	*/
-#define ST_DEC_TITAN		 38	/* Titan systype	*/
-#define ST_DEC_MARVEL		 39	/* Marvel systype	*/
-
-/* UNOFFICIAL!!! */
-#define ST_UNOFFICIAL_BIAS	100
-#define ST_DTI_RUFFIAN		101	/* RUFFIAN systype	*/
-
-/* Alpha Processor, Inc. systems */
-#define ST_API_BIAS		200
-#define ST_API_NAUTILUS		201	/* UP1000 systype	*/
-
-struct pcb_struct {
-	unsigned long ksp;
-	unsigned long usp;
-	unsigned long ptbr;
-	unsigned int pcc;
-	unsigned int asn;
-	unsigned long unique;
-	unsigned long flags;
-	unsigned long res1, res2;
-};
-
-struct percpu_struct {
-	unsigned long hwpcb[16];
-	unsigned long flags;
-	unsigned long pal_mem_size;
-	unsigned long pal_scratch_size;
-	unsigned long pal_mem_pa;
-	unsigned long pal_scratch_pa;
-	unsigned long pal_revision;
-	unsigned long type;
-	unsigned long variation;
-	unsigned long revision;
-	unsigned long serial_no[2];
-	unsigned long logout_area_pa;
-	unsigned long logout_area_len;
-	unsigned long halt_PCBB;
-	unsigned long halt_PC;
-	unsigned long halt_PS;
-	unsigned long halt_arg;
-	unsigned long halt_ra;
-	unsigned long halt_pv;
-	unsigned long halt_reason;
-	unsigned long res;
-	unsigned long ipc_buffer[21];
-	unsigned long palcode_avail[16];
-	unsigned long compatibility;
-	unsigned long console_data_log_pa;
-	unsigned long console_data_log_length;
-	unsigned long bcache_info;
-};
-
-struct procdesc_struct {
-	unsigned long weird_vms_stuff;
-	unsigned long address;
-};
-
-struct vf_map_struct {
-	void *va;
-	unsigned long pa;
-	unsigned long count;
-};
-
-struct crb_struct {
-	struct procdesc_struct * dispatch_va;
-	unsigned long dispatch_pa;
-	struct procdesc_struct * fixup_va;
-	unsigned long fixup_pa;
-	/* virtual->physical map */
-	unsigned long map_entries;
-	unsigned long map_pages;
-	struct vf_map_struct map[1];
-};
-
-struct memclust_struct {
-	unsigned long start_pfn;
-	unsigned long numpages;
-	unsigned long numtested;
-	unsigned long bitmap_va;
-	unsigned long bitmap_pa;
-	unsigned long bitmap_chksum;
-	unsigned long usage;
-};
-
-struct memdesc_struct {
-	unsigned long chksum;
-	unsigned long optional_pa;
-	unsigned long numclusters;
-	struct memclust_struct cluster[0];
-};
-
-struct dsr_struct {
-	long smm;			/* SMM nubber used by LMF       */
-	unsigned long  lurt_off;	/* offset to LURT table         */
-	unsigned long  sysname_off;	/* offset to sysname char count */
-};
-
-struct hwrpb_struct {
-	unsigned long phys_addr;	/* check: physical address of the hwrpb */
-	unsigned long id;		/* check: "HWRPB\0\0\0" */
-	unsigned long revision;	
-	unsigned long size;		/* size of hwrpb */
-	unsigned long cpuid;
-	unsigned long pagesize;		/* 8192, I hope */
-	unsigned long pa_bits;		/* number of physical address bits */
-	unsigned long max_asn;
-	unsigned char ssn[16];		/* system serial number: big bother is watching */
-	unsigned long sys_type;
-	unsigned long sys_variation;
-	unsigned long sys_revision;
-	unsigned long intr_freq;	/* interval clock frequency * 4096 */
-	unsigned long cycle_freq;	/* cycle counter frequency */
-	unsigned long vptb;		/* Virtual Page Table Base address */
-	unsigned long res1;
-	unsigned long tbhb_offset;	/* Translation Buffer Hint Block */
-	unsigned long nr_processors;
-	unsigned long processor_size;
-	unsigned long processor_offset;
-	unsigned long ctb_nr;
-	unsigned long ctb_size;		/* console terminal block size */
-	unsigned long ctbt_offset;	/* console terminal block table offset */
-	unsigned long crb_offset;	/* console callback routine block */
-	unsigned long mddt_offset;	/* memory data descriptor table */
-	unsigned long cdb_offset;	/* configuration data block (or NULL) */
-	unsigned long frut_offset;	/* FRU table (or NULL) */
-	void (*save_terminal)(unsigned long);
-	unsigned long save_terminal_data;
-	void (*restore_terminal)(unsigned long);
-	unsigned long restore_terminal_data;
-	void (*CPU_restart)(unsigned long);
-	unsigned long CPU_restart_data;
-	unsigned long res2;
-	unsigned long res3;
-	unsigned long chksum;
-	unsigned long rxrdy;
-	unsigned long txrdy;
-	unsigned long dsr_offset;	/* "Dynamic System Recognition Data Block Table" */
-};
-
-
-static inline void
-hwrpb_update_checksum(struct hwrpb_struct *h)
-{
-	unsigned long sum = 0, *l;
-        for (l = (unsigned long *) h; l < (unsigned long *) &h->chksum; ++l)
-                sum += *l;
-        h->chksum = sum;
-}
-
-#endif /* __ALPHA_HWRPB_H */
diff --git a/qemu/roms/qemu-palcode/init.c b/qemu/roms/qemu-palcode/init.c
deleted file mode 100644
index 324bc911a..000000000
--- a/qemu/roms/qemu-palcode/init.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/* Initialization of the system and the HWRPB.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include <string.h>
-#include <stddef.h>
-#include "hwrpb.h"
-#include "osf.h"
-#include "ioport.h"
-#include "uart.h"
-#include "protos.h"
-#include SYSTEM_H
-
-#define PAGE_SHIFT	13
-#define PAGE_SIZE	(1ul << PAGE_SHIFT)
-#define PAGE_OFFSET	0xfffffc0000000000UL
-
-#define VPTPTR		0xfffffffe00000000UL
-
-#define PA(VA)		((unsigned long)(VA) & 0xfffffffffful)
-#define VA(PA)		((void *)(PA) + PAGE_OFFSET)
-
-#define HZ	1024
-
-struct hwrpb_combine {
-  struct hwrpb_struct hwrpb;
-  struct percpu_struct processor;
-  struct memdesc_struct md;
-  struct memclust_struct mc[2];
-  struct crb_struct crb;
-  struct procdesc_struct proc_dispatch;
-  struct procdesc_struct proc_fixup;
-};
-
-extern char stack[PAGE_SIZE] __attribute__((section(".sbss")));
-extern char _end[] __attribute__((visibility("hidden"), nocommon));
-
-struct pcb_struct pcb __attribute__((section(".sbss")));
-
-static unsigned long page_dir[1024]
-  __attribute__((aligned(PAGE_SIZE), section(".bss.page_dir")));
-
-/* The HWRPB must be aligned because it is exported at INIT_HWRPB.  */
-struct hwrpb_combine hwrpb __attribute__((aligned(PAGE_SIZE)));
-
-void *last_alloc;
-bool have_vga;
-
-static void *
-alloc (unsigned long size, unsigned long align)
-{
-  void *p = (void *)(((unsigned long)last_alloc + align - 1) & ~(align - 1));
-  last_alloc = p + size;
-  return memset (p, 0, size);
-}
-
-static inline unsigned long
-pt_index(unsigned long addr, int level)
-{
-  return (addr >> (PAGE_SHIFT + (10 * level))) & 0x3ff;
-}
-
-static inline unsigned long
-build_pte (void *page)
-{
-  unsigned long bits;
-
-  bits = PA((unsigned long)page) << (32 - PAGE_SHIFT);
-  bits += _PAGE_VALID | _PAGE_KRE | _PAGE_KWE;
-
-  return bits;
-}
-
-static inline void *
-pte_page (unsigned long pte)
-{
-  return VA(pte >> 32 << PAGE_SHIFT);
-}
-
-static void
-set_pte (unsigned long addr, void *page)
-{
-  unsigned long *pt = page_dir;
-  unsigned long index;
-
-  index = pt_index(addr, 2);
-  if (pt[index] != 0)
-    pt = pte_page (pt[index]);
-  else
-    {
-      unsigned long *npt = alloc(PAGE_SIZE, PAGE_SIZE);
-      pt[index] = build_pte (npt);
-      pt = npt;
-    }
-
-  index = pt_index(addr, 1);
-  if (pt[index] != 0)
-    pt = pte_page (pt[index]);
-  else
-    {
-      unsigned long *npt = alloc(PAGE_SIZE, PAGE_SIZE);
-      pt[index] = build_pte (npt);
-      pt = npt;
-    }
-
-  index = pt_index(addr, 0);
-  pt[index] = build_pte (page);
-}
-
-static void
-init_page_table(void)
-{
-  /* Install the self-reference for the virtual page table base register.  */
-  page_dir[pt_index(VPTPTR, 2)] = build_pte(page_dir);
-
-  set_pte ((unsigned long)INIT_HWRPB, &hwrpb);
-  
-  /* ??? SRM maps some amount of memory at 0x20000000 for use by programs
-     started from the console prompt.  Including the bootloader.  While
-     we're emulating MILO, don't bother as we jump straight to the kernel
-     loaded into KSEG.  */
-}
-
-static void
-init_hwrpb (unsigned long memsize)
-{
-  unsigned long pal_pages;
-  unsigned long amask;
-  
-  hwrpb.hwrpb.phys_addr = PA(&hwrpb);
-
-  /* Yes, the 'HWRPB' magic is in big-endian byte ordering.  */
-  hwrpb.hwrpb.id = ( (long)'H' << 56
-		   | (long)'W' << 48
-		   | (long)'R' << 40
-		   | (long)'P' << 32
-		   | (long)'B' << 24);
-
-  hwrpb.hwrpb.size = sizeof(struct hwrpb_struct);
-
-  ((int *)hwrpb.hwrpb.ssn)[0] = ( 'Q' << 0
-				| 'E' << 8
-				| 'M' << 16
-				| 'U' << 24);
-
-  amask = ~__builtin_alpha_amask(-1);
-  switch (__builtin_alpha_implver())
-    {
-    case 0: /* EV4 */
-      hwrpb.hwrpb.cpuid = EV4_CPU;
-      hwrpb.hwrpb.max_asn = 63;
-      break;
-
-    case 1: /* EV5 */
-      hwrpb.hwrpb.cpuid
-	= ((amask & 0x101) == 0x101 ? PCA56_CPU		/* MAX+BWX */
-	   : amask & 1 ? EV56_CPU			/* BWX */
-	   : EV5_CPU);
-      hwrpb.hwrpb.max_asn = 127;
-      break;
-
-    case 2: /* EV6 */
-      hwrpb.hwrpb.cpuid = (amask & 4 ? EV67_CPU : EV6_CPU);  /* CIX */
-      hwrpb.hwrpb.max_asn = 255;
-      break;
-    }
-
-  hwrpb.hwrpb.pagesize = PAGE_SIZE;
-  hwrpb.hwrpb.pa_bits = 40;
-  hwrpb.hwrpb.sys_type = SYS_TYPE;
-  hwrpb.hwrpb.sys_variation = SYS_VARIATION;
-  hwrpb.hwrpb.sys_revision = SYS_REVISION;
-  hwrpb.processor.type = hwrpb.hwrpb.cpuid;
-
-  hwrpb.hwrpb.intr_freq = HZ * 4096;
-  hwrpb.hwrpb.cycle_freq = 250000000;	/* QEMU architects 250MHz.  */
-
-  hwrpb.hwrpb.vptb = VPTPTR;
-
-  hwrpb.hwrpb.nr_processors = 1;
-  hwrpb.hwrpb.processor_size = sizeof(struct percpu_struct);
-  hwrpb.hwrpb.processor_offset = offsetof(struct hwrpb_combine, processor);
-
-  hwrpb.hwrpb.mddt_offset = offsetof(struct hwrpb_combine, md);
-  hwrpb.md.numclusters = 2;
-
-  pal_pages = (PA(last_alloc) + PAGE_SIZE - 1) >> PAGE_SHIFT;
-
-  hwrpb.mc[0].numpages = pal_pages;
-  hwrpb.mc[0].usage = 1;
-  hwrpb.mc[1].start_pfn = pal_pages;
-  hwrpb.mc[1].numpages = (memsize >> PAGE_SHIFT) - pal_pages;
-
-  hwrpb.hwrpb.crb_offset = offsetof(struct hwrpb_combine, crb);
-  hwrpb.crb.dispatch_va = &hwrpb.proc_dispatch;
-  hwrpb.crb.dispatch_pa = PA(&hwrpb.proc_dispatch);
-  hwrpb.crb.fixup_va = &hwrpb.proc_fixup;
-  hwrpb.crb.fixup_pa = PA(&hwrpb.proc_fixup);
-  hwrpb.crb.map_entries = 1;
-  hwrpb.crb.map_pages = 1;
-  hwrpb.crb.map[0].va = &hwrpb;
-  hwrpb.crb.map[0].pa = PA(&hwrpb);
-  hwrpb.crb.map[0].count = 1;
-
-  /* See crb.c for how we match the VMS calling conventions to Unix.  */
-  hwrpb.proc_dispatch.address = (unsigned long)crb_dispatch;
-  hwrpb.proc_fixup.address = (unsigned long)crb_fixup;
-
-  hwrpb_update_checksum(&hwrpb.hwrpb);
-}
-
-static void
-init_pcb (void)
-{
-  pcb.ksp = (unsigned long)stack + sizeof(stack);
-  pcb.ptbr = PA(page_dir) >> PAGE_SHIFT;
-  pcb.flags = 1; /* FEN */
-}
-
-static void
-init_i8259 (void)
-{
-  /* ??? MILO initializes the PIC as edge triggered; I do not know how SRM
-     initializes them.  However, Linux seems to expect that these are level
-     triggered.  That may be a kernel bug, but level triggers are more
-     reliable anyway so lets go with that.  */
-
-  /* Initialize the slave PIC.  */
-  outb(0x11, PORT_PIC2_CMD);	/* ICW1: edge trigger, cascade, ICW4 req */
-  outb(0x08, PORT_PIC2_DATA);	/* ICW2: irq offset = 8 */
-  outb(0x02, PORT_PIC2_DATA);	/* ICW3: slave ID 2 */
-  outb(0x01, PORT_PIC2_DATA);	/* ICW4: not special nested, normal eoi */
-
-  /* Initialize the master PIC.  */
-  outb(0x11, PORT_PIC1_CMD);	/* ICW1 */
-  outb(0x00, PORT_PIC1_DATA);	/* ICW2: irq offset = 0 */
-  outb(0x04, PORT_PIC1_DATA);	/* ICW3: slave control INTC2 */
-  outb(0x01, PORT_PIC1_DATA);	/* ICW4 */
-
-  /* Initialize level triggers.  The CY82C693UB that's on real alpha
-     hardware doesn't have this; this is a PIIX extension.  However,
-     QEMU doesn't implement regular level triggers.  */
-  outb(0xff, PORT_PIC2_ELCR);
-  outb(0xff, PORT_PIC1_ELCR);
-
-  /* Disable all interrupts.  */
-  outb(0xff, PORT_PIC2_DATA);
-  outb(0xff, PORT_PIC1_DATA);
-
-  /* Non-specific EOI, clearing anything the might be pending.  */
-  outb(0x20, PORT_PIC2_CMD);
-  outb(0x20, PORT_PIC1_CMD);
-}
-
-void
-do_start(unsigned long memsize, void (*kernel_entry)(void), long cpus)
-{
-  last_alloc = _end;
-
-  init_page_table();
-  init_hwrpb(memsize);
-  init_pcb();
-  init_i8259();
-  uart_init();
-  ps2port_setup();
-  pci_setup();
-  vgahw_init();
-
-  {
-    register int variant __asm__("$16") = 2;	/* OSF/1 PALcode */
-    register void (*pc)(void) __asm__("$17");
-    register unsigned long pa_pcb __asm__("$18");
-    register unsigned long vptptr __asm__("$19");
-
-    pc = (kernel_entry ? kernel_entry : do_console);
-    pa_pcb = PA(&pcb);
-    vptptr = VPTPTR;
-    asm("call_pal 0x0a" : : "r"(variant), "r"(pc), "r"(pa_pcb), "r"(vptptr));
-  }
-  __builtin_unreachable ();
-}
-
-void
-do_start_wait(void)
-{
-  while (1)
-    {
-      // WtInt with interrupts off.  Rely on the fact that QEMU will
-      // un-halt the CPU when an interrupt arrives.
-      asm("lda $16,-1\n\tcall_pal 0x3e" : : : "$0", "$16");
-
-      // FIXME do something with the IPI.
-    }
-}
diff --git a/qemu/roms/qemu-palcode/ioport.h b/qemu/roms/qemu-palcode/ioport.h
deleted file mode 100644
index b1bb4b395..000000000
--- a/qemu/roms/qemu-palcode/ioport.h
+++ /dev/null
@@ -1,84 +0,0 @@
-// Definitions for X86 IO port access.
-//
-// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
-//
-// This file may be distributed under the terms of the GNU LGPLv3 license.
-//
-// This file copied (somewhat) intact from SeaBIOS.
-
-#ifndef IOPORT_H
-#define IOPORT_H
-
-#define PORT_DMA_ADDR_2        0x0004
-#define PORT_DMA_CNT_2         0x0005
-#define PORT_DMA1_MASK_REG     0x000a
-#define PORT_DMA1_MODE_REG     0x000b
-#define PORT_DMA1_CLEAR_FF_REG 0x000c
-#define PORT_DMA1_MASTER_CLEAR 0x000d
-#define PORT_PIC1_CMD          0x0020
-#define PORT_PIC1_DATA         0x0021
-#define PORT_PIT_COUNTER0      0x0040
-#define PORT_PIT_COUNTER1      0x0041
-#define PORT_PIT_COUNTER2      0x0042
-#define PORT_PIT_MODE          0x0043
-#define PORT_PS2_DATA          0x0060
-#define PORT_PS2_CTRLB         0x0061
-#define PORT_PS2_STATUS        0x0064
-#define PORT_CMOS_INDEX        0x0070
-#define PORT_CMOS_DATA         0x0071
-#define PORT_DIAG              0x0080
-#define PORT_DMA_PAGE_2        0x0081
-#define PORT_A20               0x0092
-#define PORT_PIC2_CMD          0x00a0
-#define PORT_PIC2_DATA         0x00a1
-#define PORT_SMI_CMD           0x00b2
-#define PORT_SMI_STATUS        0x00b3
-#define PORT_DMA2_MASK_REG     0x00d4
-#define PORT_DMA2_MODE_REG     0x00d6
-#define PORT_DMA2_MASTER_CLEAR 0x00da
-#define PORT_MATH_CLEAR        0x00f0
-#define PORT_ATA2_CMD_BASE     0x0170
-#define PORT_ATA1_CMD_BASE     0x01f0
-#define PORT_LPT2              0x0278
-#define PORT_SERIAL4           0x02e8
-#define PORT_SERIAL2           0x02f8
-#define PORT_ATA2_CTRL_BASE    0x0374
-#define PORT_LPT1              0x0378
-#define PORT_SERIAL3           0x03e8
-#define PORT_ATA1_CTRL_BASE    0x03f4
-#define PORT_FD_BASE           0x03f0
-#define PORT_FD_DOR            0x03f2
-#define PORT_FD_STATUS         0x03f4
-#define PORT_FD_DATA           0x03f5
-#define PORT_HD_DATA           0x03f6
-#define PORT_FD_DIR            0x03f7
-#define PORT_SERIAL1           0x03f8
-#define PORT_PIC1_ELCR         0x04d0
-#define PORT_PIC2_ELCR         0x04d1
-#define PORT_PCI_CMD           0x0cf8
-#define PORT_PCI_REBOOT        0x0cf9
-#define PORT_PCI_DATA          0x0cfc
-#define PORT_BIOS_DEBUG        0x0402
-#define PORT_QEMU_CFG_CTL      0x0510
-#define PORT_QEMU_CFG_DATA     0x0511
-#define PORT_ACPI_PM_BASE      0xb000
-#define PORT_SMB_BASE          0xb100
-#define PORT_BIOS_APM          0x8900
-
-// Serial port offsets
-#define SEROFF_DATA    0
-#define SEROFF_DLL     0
-#define SEROFF_IER     1
-#define SEROFF_DLH     1
-#define SEROFF_IIR     2
-#define SEROFF_LCR     3
-#define SEROFF_LSR     5
-#define SEROFF_MSR     6
-
-// PORT_A20 bitdefs
-#define A20_ENABLE_BIT 0x02
-
-// PORT_CMOS_INDEX nmi disable bit
-#define NMI_DISABLE_BIT 0x80
-
-#endif // ioport.h
diff --git a/qemu/roms/qemu-palcode/memcpy.c b/qemu/roms/qemu-palcode/memcpy.c
deleted file mode 100644
index b6bbb7434..000000000
--- a/qemu/roms/qemu-palcode/memcpy.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- *  linux/arch/alpha/lib/memcpy.c
- *
- *  Copyright (C) 1995  Linus Torvalds
- */
-
-/*
- * This is a reasonably optimized memcpy() routine.
- */
-
-#include <string.h>
-
-/*
- * Note that the C code is written to be optimized into good assembly. However,
- * at this point gcc is unable to sanely compile "if (n >= 0)", resulting in a
- * explicit compare against 0 (instead of just using the proper "blt reg, xx" or
- * "bge reg, xx"). I hope alpha-gcc will be fixed to notice this eventually..
- */
-
-/*
- * This should be done in one go with ldq_u*2/mask/stq_u. Do it
- * with a macro so that we can fix it up later..
- */
-#define ALIGN_DEST_TO8_UP(d,s,n) \
-	while (d & 7) { \
-		if (n <= 0) return; \
-		n--; \
-		*(char *) d = *(char *) s; \
-		d++; s++; \
-	}
-#define ALIGN_DEST_TO8_DN(d,s,n) \
-	while (d & 7) { \
-		if (n <= 0) return; \
-		n--; \
-		d--; s--; \
-		*(char *) d = *(char *) s; \
-	}
-
-/*
- * This should similarly be done with ldq_u*2/mask/stq. The destination
- * is aligned, but we don't fill in a full quad-word
- */
-#define DO_REST_UP(d,s,n) \
-	while (n > 0) { \
-		n--; \
-		*(char *) d = *(char *) s; \
-		d++; s++; \
-	}
-#define DO_REST_DN(d,s,n) \
-	while (n > 0) { \
-		n--; \
-		d--; s--; \
-		*(char *) d = *(char *) s; \
-	}
-
-/*
- * This should be done with ldq/mask/stq. The source and destination are
- * aligned, but we don't fill in a full quad-word
- */
-#define DO_REST_ALIGNED_UP(d,s,n) DO_REST_UP(d,s,n)
-#define DO_REST_ALIGNED_DN(d,s,n) DO_REST_DN(d,s,n)
-
-/*
- * This does unaligned memory copies. We want to avoid storing to
- * an unaligned address, as that would do a read-modify-write cycle.
- * We also want to avoid double-reading the unaligned reads.
- *
- * Note the ordering to try to avoid load (and address generation) latencies.
- */
-static inline void __memcpy_unaligned_up (unsigned long d, unsigned long s,
-					  long n)
-{
-	ALIGN_DEST_TO8_UP(d,s,n);
-	n -= 8;			/* to avoid compare against 8 in the loop */
-	if (n >= 0) {
-		unsigned long low_word, high_word;
-		__asm__("ldq_u %0,%1":"=r" (low_word):"m" (*(unsigned long *) s));
-		do {
-			unsigned long tmp;
-			__asm__("ldq_u %0,%1":"=r" (high_word):"m" (*(unsigned long *)(s+8)));
-			n -= 8;
-			__asm__("extql %1,%2,%0"
-				:"=r" (low_word)
-				:"r" (low_word), "r" (s));
-			__asm__("extqh %1,%2,%0"
-				:"=r" (tmp)
-				:"r" (high_word), "r" (s));
-			s += 8;
-			*(unsigned long *) d = low_word | tmp;
-			d += 8;
-			low_word = high_word;
-		} while (n >= 0);
-	}
-	n += 8;
-	DO_REST_UP(d,s,n);
-}
-
-static inline void __memcpy_unaligned_dn (unsigned long d, unsigned long s,
-					  long n)
-{
-	/* I don't understand AXP assembler well enough for this. -Tim */
-	s += n;
-	d += n;
-	while (n--)
-		* (char *) --d = * (char *) --s;
-}
-
-/*
- * Hmm.. Strange. The __asm__ here is there to make gcc use an integer register
- * for the load-store. I don't know why, but it would seem that using a floating
- * point register for the move seems to slow things down (very small difference,
- * though).
- *
- * Note the ordering to try to avoid load (and address generation) latencies.
- */
-static inline void __memcpy_aligned_up (unsigned long d, unsigned long s,
-					long n)
-{
-	ALIGN_DEST_TO8_UP(d,s,n);
-	n -= 8;
-	while (n >= 0) {
-		unsigned long tmp;
-		__asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s));
-		n -= 8;
-		s += 8;
-		*(unsigned long *) d = tmp;
-		d += 8;
-	}
-	n += 8;
-	DO_REST_ALIGNED_UP(d,s,n);
-}
-static inline void __memcpy_aligned_dn (unsigned long d, unsigned long s,
-					long n)
-{
-	s += n;
-	d += n;
-	ALIGN_DEST_TO8_DN(d,s,n);
-	n -= 8;
-	while (n >= 0) {
-		unsigned long tmp;
-		s -= 8;
-		__asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s));
-		n -= 8;
-		d -= 8;
-		*(unsigned long *) d = tmp;
-	}
-	n += 8;
-	DO_REST_ALIGNED_DN(d,s,n);
-}
-
-void * memcpy(void * dest, const void *src, size_t n)
-{
-	if (!(((unsigned long) dest ^ (unsigned long) src) & 7)) {
-		__memcpy_aligned_up ((unsigned long) dest, (unsigned long) src,
-				     n);
-		return dest;
-	}
-	__memcpy_unaligned_up ((unsigned long) dest, (unsigned long) src, n);
-	return dest;
-}
diff --git a/qemu/roms/qemu-palcode/memset.c b/qemu/roms/qemu-palcode/memset.c
deleted file mode 100644
index e8481dc9c..000000000
--- a/qemu/roms/qemu-palcode/memset.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* The standard memset function.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-
-#include <string.h>
-
-void *memset(void *optr, int ival, unsigned long size)
-{
-  unsigned long val = ival;
-  void *ptr = optr;
-
-  if (__builtin_expect (size == 0, 0))
-    return optr;
-
-  if (__builtin_expect (val != 0, 0))
-    {
-      val = val & 0xff;
-      val |= val << 8;
-      val |= val << 16;
-      val |= val << 32;
-    }
-
-  if (__builtin_expect ((unsigned long)ptr & 1, 0))
-    {
-      *(char *)ptr = val;
-      ptr += 1;
-      size -= 1;
-    }
-
-  if (__builtin_expect ((unsigned long)ptr & 2, 0))
-    {
-      if (size < 2)
-	goto tail_1;
-      *(short *)ptr = val;
-      ptr += 2;
-      size -= 2;
-    }
-
-  if (__builtin_expect ((unsigned long)ptr & 4, 0))
-    {
-      if (size < 4)
-	goto tail_3;
-      *(int *)ptr = val;
-      ptr += 4;
-      size -= 4;
-    }
-  
-  while (size >= 8)
-    {
-      *(long *)ptr = val;
-      ptr += 8;
-      size -= 8;
-    }
-
-  if (size >= 4)
-    {
-      *(int *)ptr = val;
-      ptr += 4;
-      size -= 4;
-    }
-
- tail_3:
-  if (size >= 2)
-    {
-      *(short *)ptr = val;
-      ptr += 2;
-      size -= 2;
-    }
-
- tail_1:
-  if (size > 0)
-    {
-      *(char *)ptr = val;
-      ptr += 1;
-      size -= 1;
-    }
-
-  return optr;
-}
diff --git a/qemu/roms/qemu-palcode/osf.h b/qemu/roms/qemu-palcode/osf.h
deleted file mode 100644
index 2794cd769..000000000
--- a/qemu/roms/qemu-palcode/osf.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
-*****************************************************************************
-**                                                                          *
-**  Copyright � 1993, 1994						    *
-**  by Digital Equipment Corporation, Maynard, Massachusetts.		    *
-**                                                                          *
-**  All Rights Reserved							    *
-**                                                                          *
-**  Permission  is  hereby  granted  to  use, copy, modify and distribute   *
-**  this  software  and  its  documentation,  in  both  source  code  and   *
-**  object  code  form,  and without fee, for the purpose of distribution   *
-**  of this software  or  modifications  of this software within products   *
-**  incorporating  an  integrated   circuit  implementing  Digital's  AXP   *
-**  architecture,  regardless  of the  source of such integrated circuit,   *
-**  provided that the  above copyright  notice and this permission notice   *
-**  appear  in  all copies,  and  that  the  name  of  Digital  Equipment   *
-**  Corporation  not  be  used  in advertising or publicity pertaining to   *
-**  distribution of the  document  or  software without specific, written   *
-**  prior permission.							    *
-**                                                                          *
-**  Digital  Equipment  Corporation   disclaims  all   warranties  and/or   *
-**  guarantees  with  regard  to  this  software,  including  all implied   *
-**  warranties of fitness for  a  particular purpose and merchantability,   *
-**  and makes  no  representations  regarding  the use of, or the results   *
-**  of the use of, the software and documentation in terms of correctness,  *
-**  accuracy,  reliability,  currentness  or  otherwise;  and you rely on   *
-**  the software, documentation and results solely at your own risk.	    *
-**                                                                          *
-**  AXP is a trademark of Digital Equipment Corporation.		    *
-**                                                                          *
-*****************************************************************************
-*/
-
-/*
-**  Seg0 and Seg1 Virtual Address (VA) Format
-**
-**	  Loc	Size	Name	Function
-**	 -----	----	----	---------------------------------
-**	<42:33>  10	SEG1	First level page table offset
-**	<32:23>  10	SEG2	Second level page table offset
-**	<22:13>  10	SEG3	Third level page table offset
-**	<12:00>  13	OFFSET	Byte within page offset
-*/
-
-#define VA_V_SEG1	33
-#define	VA_M_SEG1	(0x3FF<<VA_V_SEG1)
-#define VA_V_SEG2	23
-#define VA_M_SEG2	(0x3FF<<VA_V_SEG2)
-#define VA_V_SEG3	13
-#define VA_M_SEG3	(0x3FF<<VA_V_SEG3)
-#define VA_V_OFFSET	0
-#define VA_M_OFFSET	0x1FFF
-
-/*
-**  Virtual Address Options: 8K byte page size
-*/
-
-#define	VA_S_SIZE	43
-#define	VA_S_OFF	13
-#define VA_S_SEG	10
-#define VA_S_PAGE_SIZE	8192
-
-/*
-**  Page Table Entry (PTE) Format
-**
-**	 Extent	Size	Name	Function
-**	 ------	----	----	---------------------------------
-**	<63:32>	  32	PFN	Page Frame Number
-**	<31:16>	  16	SW	Reserved for software
-**	<15:14>	   2	RSV0	Reserved for hardware SBZ
-**	   <13>	   1	UWE	User Write Enable
-**	   <12>	   1	KWE	Kernel Write Enable
-**	<11:10>	   2	RSV1	Reserved for hardware SBZ
-**	    <9>	   1	URE	User Read Enable
-**	    <8>	   1	KRE	Kernel Read Enable
-**	    <7>	   1	RSV2	Reserved for hardware SBZ
-**	  <6:5>	   2	GH	Granularity Hint
-**	    <4>	   1	ASM	Address Space Match
-**	    <3>	   1	FOE	Fault On Execute
-**	    <2>	   1	FOW	Fault On Write
-**	    <1>	   1	FOR	Fault On Read
-**	    <0>	   1	V	Valid
-*/
-
-#define	PTE_V_PFN	32
-#define PTE_M_PFN	0xFFFFFFFF00000000
-#define PTE_V_SW	16
-#define PTE_M_SW	0x00000000FFFF0000
-#define PTE_V_UWE	13
-#define PTE_M_UWE	(1<<PTE_V_UWE)
-#define PTE_V_KWE	12
-#define PTE_M_KWE	(1<<PTE_V_KWE)
-#define PTE_V_URE	9
-#define PTE_M_URE	(1<<PTE_V_URE)
-#define PTE_V_KRE	8
-#define PTE_M_KRE	(1<<PTE_V_KRE)
-#define PTE_V_GH	5
-#define PTE_M_GH	(3<<PTE_V_GH)
-#define PTE_V_ASM	4
-#define PTE_M_ASM	(1<<PTE_V_ASM)
-#define PTE_V_FOE	3
-#define PTE_M_FOE	(1<<PTE_V_FOE)
-#define PTE_V_FOW	2
-#define PTE_M_FOW	(1<<PTE_V_FOW)
-#define PTE_V_FOR	1
-#define PTE_M_FOR	(1<<PTE_V_FOR)
-#define PTE_V_VALID	0
-#define PTE_M_VALID	(1<<PTE_V_VALID)
-
-#define PTE_M_KSEG	0x1111
-#define PTE_M_PROT	0x3300
-
-/*
-**  System Entry Instruction Fault (entIF) Constants:
-*/
-
-#define IF_K_BPT        0x0
-#define IF_K_BUGCHK     0x1
-#define IF_K_GENTRAP    0x2
-#define IF_K_FEN        0x3
-#define IF_K_OPCDEC     0x4
-
-/*
-**  System Entry Hardware Interrupt (entInt) Constants:
-*/
-
-#define INT_K_IP	0x0
-#define INT_K_CLK	0x1
-#define INT_K_MCHK	0x2
-#define INT_K_DEV	0x3
-#define INT_K_PERF	0x4
-
-/*
-**  System Entry MM Fault (entMM) Constants:
-*/
-
-#define	MM_K_TNV	0x0
-#define MM_K_ACV	0x1
-#define MM_K_FOR	0x2
-#define MM_K_FOE	0x3
-#define MM_K_FOW	0x4
-
-/*
-**  Process Control Block (PCB) Offsets:
-*/
-
-#define PCB_Q_KSP	0x0000
-#define PCB_Q_USP	0x0008
-#define PCB_Q_PTBR	0x0010
-#define PCB_L_PCC	0x0018
-#define PCB_L_ASN	0x001C
-#define PCB_Q_UNIQUE	0x0020
-#define PCB_Q_FEN	0x0028
-#define PCB_Q_RSV0	0x0030
-#define PCB_Q_RSV1	0x0038
-
-/*
-**  Processor Status Register (PS) Bit Summary
-**
-**	Extent	Size	Name	Function
-**	------	----	----	---------------------------------
-**	  <3>	 1	CM	Current Mode
-**	<2:0>	 3	IPL	Interrupt Priority Level
-**/
-
-#define	PS_V_CM		3
-#define PS_M_CM		(1<<PS_V_CM)
-#define	PS_V_IPL	0
-#define	PS_M_IPL	(7<<PS_V_IPL)
-
-#define	PS_K_KERN	(0<<PS_V_CM)
-#define PS_K_USER	(1<<PS_V_CM)
-
-#define	IPL_K_ZERO	0x0
-#define IPL_K_SW0	0x1
-#define IPL_K_SW1	0x2
-#define IPL_K_DEV0	0x3
-#define IPL_K_DEV1	0x4
-#define IPL_K_CLK	0x5
-#define IPL_K_IP	0x6
-#define IPL_K_RT	0x6
-#define IPL_K_PERF      0x6
-#define IPL_K_PFAIL     0x6
-#define IPL_K_MCHK	0x7
-
-#define IPL_K_LOW	0x0
-#define IPL_K_HIGH	0x7
-
-/*
-**  SCB Offset Definitions:
-*/
-
-#define SCB_Q_FEN	    	0x0010
-#define SCB_Q_ACV		0x0080
-#define SCB_Q_TNV		0x0090
-#define SCB_Q_FOR		0x00A0
-#define SCB_Q_FOW		0x00B0
-#define SCB_Q_FOE		0x00C0
-#define SCB_Q_ARITH		0x0200
-#define SCB_Q_KAST		0x0240
-#define SCB_Q_EAST		0x0250
-#define SCB_Q_SAST		0x0260
-#define SCB_Q_UAST		0x0270
-#define SCB_Q_UNALIGN		0x0280
-#define SCB_Q_BPT		0x0400
-#define SCB_Q_BUGCHK		0x0410
-#define SCB_Q_OPCDEC		0x0420
-#define SCB_Q_ILLPAL		0x0430
-#define SCB_Q_TRAP		0x0440
-#define SCB_Q_CHMK		0x0480
-#define SCB_Q_CHME		0x0490
-#define SCB_Q_CHMS		0x04A0
-#define SCB_Q_CHMU		0x04B0
-#define SCB_Q_SW0		0x0500
-#define SCB_Q_SW1		0x0510
-#define SCB_Q_SW2		0x0520
-#define SCB_Q_SW3		0x0530
-#define	SCB_Q_SW4		0x0540
-#define SCB_Q_SW5		0x0550
-#define SCB_Q_SW6		0x0560
-#define SCB_Q_SW7		0x0570
-#define SCB_Q_SW8		0x0580
-#define SCB_Q_SW9		0x0590
-#define SCB_Q_SW10		0x05A0
-#define SCB_Q_SW11		0x05B0
-#define SCB_Q_SW12		0x05C0
-#define SCB_Q_SW13		0x05D0
-#define SCB_Q_SW14		0x05E0
-#define SCB_Q_SW15		0x05F0
-#define SCB_Q_CLOCK		0x0600
-#define SCB_Q_INTER		0x0610
-#define SCB_Q_SYSERR        	0x0620
-#define SCB_Q_PROCERR		0x0630
-#define SCB_Q_PWRFAIL		0x0640
-#define SCB_Q_PERFMON		0x0650
-#define SCB_Q_SYSMCHK		0x0660
-#define SCB_Q_PROCMCHK      	0x0670
-#define SCB_Q_PASSREL		0x0680
-
-/*
-**  Stack Frame (FRM) Offsets:
-**
-**  There are two types of system entries for OSF/1 - those for the
-**  callsys CALL_PAL function and those for exceptions and interrupts.
-**  Both entry types use the same stack frame layout.  The stack frame
-**  contains space for the PC, the PS, the saved GP, and the saved
-**  argument registers a0, a1, and a2.  On entry, SP points to the
-**  saved PS.
-*/
-
-#define	FRM_Q_PS	0x0000
-#define FRM_Q_PC	0x0008
-#define FRM_Q_GP	0x0010
-#define FRM_Q_A0	0x0018
-#define FRM_Q_A1	0x0020
-#define FRM_Q_A2	0x0028
-
-#define FRM_K_SIZE	48
-
-/*
-**  Halt Codes:
-*/
-
-#define HLT_K_RESET	    0x0000
-#define HLT_K_HW_HALT	    0x0001
-#define HLT_K_KSP_INVAL	    0x0002
-#define HLT_K_SCBB_INVAL    0x0003
-#define HLT_K_PTBR_INVAL    0x0004
-#define HLT_K_SW_HALT	    0x0005
-#define HLT_K_DBL_MCHK	    0x0006
-#define HLT_K_MCHK_FROM_PAL 0x0007
-
-/*
-**  Machine Check Codes:
-*/
-
-#define MCHK_K_TPERR	    0x0080
-#define MCHK_K_TCPERR	    0x0082
-#define MCHK_K_HERR	    0x0084
-#define MCHK_K_ECC_C	    0x0086
-#define MCHK_K_ECC_NC	    0x0088
-#define MCHK_K_UNKNOWN	    0x008A
-#define MCHK_K_CACKSOFT	    0x008C
-#define MCHK_K_BUGCHECK	    0x008E
-#define MCHK_K_OS_BUGCHECK  0x0090
-#define MCHK_K_DCPERR	    0x0092
-#define MCHK_K_ICPERR	    0x0094
-#define MCHK_K_RETRY_IRD    0x0096
-#define MCHK_K_PROC_HERR    0x0098
-
-/*
-** System Machine Check Codes:
-*/
-
-#define MCHK_K_READ_NXM     0x0200
-#define MCHK_K_SYS_HERR     0x0202
-
-/*
-**  Machine Check Error Status Summary (MCES) Register Format
-**
-**	 Extent	Size	Name	Function
-**	 ------	----	----	---------------------------------
-**	  <0>	  1	MIP	Machine check in progress
-**	  <1>	  1	SCE	System correctable error in progress
-**	  <2>	  1	PCE	Processor correctable error in progress
-**	  <3>	  1	DPC	Disable PCE error reporting
-**	  <4>	  1	DSC	Disable SCE error reporting
-*/
-
-#define MCES_V_MIP	0
-#define MCES_M_MIP	(1<<MCES_V_MIP)
-#define MCES_V_SCE	1
-#define MCES_M_SCE	(1<<MCES_V_SCE)
-#define MCES_V_PCE	2
-#define MCES_M_PCE	(1<<MCES_V_PCE)
-#define MCES_V_DPC	3
-#define MCES_M_DPC	(1<<MCES_V_DPC)
-#define MCES_V_DSC	4
-#define MCES_M_DSC	(1<<MCES_V_DSC)
-
-#define MCES_M_ALL      (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
-                         | MCES_M_DSC)
-
-/*
-**  Who-Am-I (WHAMI) Register Format
-**
-**	 Extent	Size	Name	Function
-**	 ------	----	----	---------------------------------
-**	  <7:0>	  8	ID	Who-Am-I identifier
-**	  <15:8>   1	SWAP	Swap PALcode flag - character 'S'
-*/
-
-#define WHAMI_V_SWAP	8
-#define WHAMI_M_SWAP	(1<<WHAMI_V_SWAP)
-#define WHAMI_V_ID	0
-#define WHAMI_M_ID	0xFF
-
-#define WHAMI_K_SWAP    0x53    /* Character 'S' */
-
-/*
- * OSF/1 PAL-code-imposed page table bits
- */
-#define _PAGE_VALID     0x0001
-#define _PAGE_FOR       0x0002  /* used for page protection (fault on read) */
-#define _PAGE_FOW       0x0004  /* used for page protection (fault on write) */
-#define _PAGE_FOE       0x0008  /* used for page protection (fault on exec) */
-#define _PAGE_ASM       0x0010
-#define _PAGE_KRE       0x0100  /* xxx - see below on the "accessed" bit */
-#define _PAGE_URE       0x0200  /* xxx */
-#define _PAGE_KWE       0x1000  /* used to do the dirty bit in software */
-#define _PAGE_UWE       0x2000  /* used to do the dirty bit in software */
diff --git a/qemu/roms/qemu-palcode/pal.S b/qemu/roms/qemu-palcode/pal.S
deleted file mode 100644
index 1befc9f4a..000000000
--- a/qemu/roms/qemu-palcode/pal.S
+++ /dev/null
@@ -1,1918 +0,0 @@
-/* QEMU Emulation PALcode.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-	.set		noat
-	.set		nomacro
-	.text
-
-#include "pal.h"
-#include "osf.h"
-#include SYSTEM_H
-
-/*
- * Create a standard kernel entry stack frame.
- */
-
-.macro	STACK_FRAME save_ps, save_pc, temp, do_ps
-	// Test if we're currently in user mode
-	and	\save_ps, PS_M_CM, \temp
-	beq	\temp, 0f
-	// Switch to kernel mode
-.ifne \do_ps
-	mtpr	$31, qemu_ps
-.endif
-	mtpr	$sp, qemu_usp
-	mfpr	$sp, ptKsp
-	// Allocate the stack frame
-0:	lda	$sp, -FRM_K_SIZE($sp)
-	stq	\save_ps, FRM_Q_PS($sp)
-	stq	\save_pc, FRM_Q_PC($sp)
-	stq	$gp, FRM_Q_GP($sp)
-	stq	a0, FRM_Q_A0($sp)
-	stq	a1, FRM_Q_A1($sp)
-	stq	a2, FRM_Q_A2($sp)
-.endm
-
-/*
- * Allocate a 1 page stack for use by the console.
- */
-#define STACK_SIZE	8192
-
-/*
- * QEMU emulator "hardware" entry points.
- */
-
-/*
- * Reset
- * 
- * INPUT PARAMETERS:
- * 
- *	trap_arg0 = Memory size
- *	trap_arg1 = Kernel entry (if loaded)
- */ 
-        .org	0x0000
-	.globl	__start
-__start:
-	// Initialize GP.
-	br	$gp, .+4
-	ldah	$gp, 0($gp)			!gpdisp!1
-	lda	$gp, 0($gp)			!gpdisp!1
-	mtpr	$gp, ptPgp
-
-	// Disable interrupts; kernel mode
-	lda	t0, IPL_K_HIGH
-	mtpr	t0, qemu_ps
-
-	// Initialize Stack.
-	SYS_WHAMI a0
-	lda	t0, STACK_SIZE
-	addq	a0, 1, t1
-	mull	t0, t1, t0
-	ldah	t1, stack($gp)			!gprelhigh
-	lda	t1, stack(t1)			!gprellow
-	addq	t0, t1, $sp
-
-	// Do any necessary system setup required for PALmode,
-	// e.g. setting up ptSys[01].
-	bsr	$26, Sys_Setup
-
-	// Non-boot CPUs can go wait now.
-	bne	a0, 1f
-
-	// Load boot arguments
-	mfpr	a0, qemu_trap_arg0
-	mfpr	a1, qemu_trap_arg1
-	mfpr	a2, qemu_trap_arg2
-
-	// Continue in do_start, outside PALmode.
-	ldah	$27, do_start($gp)		!gprelhigh
-	lda	$27, do_start($27)		!gprellow
-	hw_ret	($27)
-
-1:	ldah	$27, do_start_wait($gp)		!gprelhigh
-	lda	$27, do_start_wait($27)		!gprellow
-	hw_ret	($27)
-ENDFN	__start
-
-/*
- * Machine Check
- *
- * INPUT PARAMETERS:
- * 
- *	trap_arg0 = 
- *	trap_arg1 = 
- *	trap_arg2 = 
- */
-	.org	0x0080
-Pal_Mchk:
-	halt
-ENDFN	Pal_Mchk
-
-/*
- * Interprocessor Interrupt
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = 
- *	trap_arg1 =
- *	trap_arg2 =
- *
- * The interprocessor interrupt is special, in that PALcode is supposed
- * to clear the interupt and not wait for the OS to do it.
- */
-	.org	0x0100
-Pal_Smp_Interrupt:
-	mfpr	p6, qemu_exc_addr
-
-	SYS_ACK_SMP p0, p1, p2
-
-	mfpr	p0, qemu_ps
-
-	STACK_FRAME p0, p6, p2, 0
-
-	mov	IPL_K_IP, p0		// Raise IPL
-	mtpr	p0, qemu_ps
-
-	mfpr	p6, ptEntInt
-	mfpr	$gp, ptKgp
-	lda	a0, INT_K_IP
-	lda	a1, 0
-	lda	a2, 0
-
-	hw_ret	(p6)
-ENDFN	Pal_Smp_Interrupt
-
-/*
- * Clock Interrupt
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = 
- *	trap_arg1 =
- *	trap_arg2 =
- *
- * The clock interrupt is special, in that PALcode is supposed
- * to clear the interupt and not wait for the OS to do it.
- */
-	.org	0x0180
-Pal_Clk_Interrupt:
-	mfpr	p6, qemu_exc_addr
-
-	SYS_ACK_CLK p0, p1, p2
-
-	mfpr	p0, qemu_ps
-
-	STACK_FRAME p0, p6, p2, 0
-
-	mov	IPL_K_CLK, p0		// Raise IPL
-	mtpr	p0, qemu_ps
-
-	mfpr	p6, ptEntInt
-	mfpr	$gp, ptKgp
-	lda	a0, INT_K_CLK
-	lda	a1, 0
-	lda	a2, 0
-
-9:	hw_ret	(p6)
-ENDFN	Pal_Clk_Interrupt
-
-/*
- * Device Interrupt
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = 
- *	trap_arg1 =
- *	trap_arg2 =
- */ 
-	.org	0x0200
-Pal_Dev_Interrupt:
-	mfpr	p6, qemu_exc_addr
-	mfpr	p0, qemu_ps
-
-	STACK_FRAME p0, p6, p2, 0
-
-	mov	IPL_K_DEV1, p0		// Raise IPL
-	mtpr	p0, qemu_ps
-
-	bsr	p7, Sys_Dev_Vector
-
-	mfpr	p7, ptEntInt
-	mfpr	$gp, ptKgp
-	lda	a0, INT_K_DEV
-	lda	a2, 0
-	hw_ret	(p7)
-ENDFN	Pal_Dev_Interrupt
-
-/*
- * Memory Fault
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = faulting address
- *	trap_arg1 = fault type (TNV, ACV, FOR, FOW, FOE)
- *	trap_arg2 = access type (exec=-1, read=0, write=1)
- */ 
-	.org	0x0280
-Pal_MMFault:
-	mfpr	p0, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	blbs	p6, MchkBugCheck
-
-	STACK_FRAME p0, p6, p2, 1
-
-	mfpr	p0, ptEntMM
-	mfpr	$gp, ptKgp
-	mfpr	a0, qemu_trap_arg0
-	mfpr	a1, qemu_trap_arg1
-	mfpr	a2, qemu_trap_arg2
-	hw_ret	(p0)
-ENDFN	Pal_MMFault
-
-/*
- * Unaligned Data
- * 
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = faulting address
- *	trap_arg1 = opcode of faulting insn
- *	trap_arg2 = src/dst register number
- */ 
-	.org	0x0300
-Pal_Unalign:
-	mfpr	p0, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	addq	p6, 4, p1		// increment past the faulting insn
-	blbs	p6, MchkBugCheck
-
-	STACK_FRAME p0, p1, p2, 1
-
-	mfpr	p0, ptEntUna
-	mfpr	$gp, ptKgp
-	mfpr	a0, qemu_trap_arg0
-	mfpr	a1, qemu_trap_arg1
-	mfpr	a2, qemu_trap_arg2
-	hw_ret	(p0)
-ENDFN	Pal_Unalign
-
-/*
- * Illegal Opcode
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = UNDEFINED
- *	trap_arg1 = UNDEFINED
- *	trap_arg2 = UNDEFINED
- *
- * OUTPUT PARAMETERS:
- *
- *	r16 (a0) = Instruction fault code
- *	r17 (a1) = UNPREDICTABLE
- *	r18 (a2) = UNPREDICTABLE
- */ 
-	.org	0x0380
-Pal_OpcDec:
-	mfpr	p0, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	addq	p6, 4, p1		// increment past the faulting insn
-	blbs	p6, MchkBugCheck
-
-	STACK_FRAME p0, p1, p2, 1
-
-	mfpr	p0, ptEntIF
-	mfpr	$gp, ptKgp
-	mov	IF_K_OPCDEC, a0
-	hw_ret	(p0)
-ENDFN	Pal_OpcDec
-
-/*
- * Arithmetic Trap
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = exception type
- *	trap_arg1 = register modification mask
- *	trap_arg2 = UNDEFINED
- */
-	.org	0x0400
-Pal_Arith:
-	mfpr	p0, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	blbs	p6, MchkBugCheck
-
-	STACK_FRAME p0, p6, p2, 1
-
-	mfpr	p0, ptEntArith
-	mfpr	$gp, ptKgp
-	mfpr	a0, qemu_trap_arg0
-	mfpr	a1, qemu_trap_arg1
-	hw_ret	(p0)
-ENDFN	Pal_Arith
-
-/*
- * Floating Point Disabled
- *
- * INPUT PARAMETERS:
- *
- *	trap_arg0 = UNDEFINED
- *	trap_arg1 = UNDEFINED
- *	trap_arg2 = UNDEFINED
- *
- * OUTPUT PARAMETERS:
- *
- *	r16 (a0) = Instruction fault code
- *	r17 (a1) = UNPREDICTABLE
- *	r18 (a2) = UNPREDICTABLE
- */ 
-	.org	0x0480
-Pal_Fen:
-	mfpr	p0, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	blbs	p6, MchkBugCheck
-
-	STACK_FRAME p0, p6, p2, 1
-
-	mfpr	p0, ptEntIF
-	mfpr	$gp, ptKgp
-	mov	IF_K_FEN, a0
-	hw_ret	(p0)
-ENDFN	Pal_Fen
-
-/*
- * OSF/1 Privileged CALL_PAL Entry Points
- */
-
-#define ORG_CALL_PAL_PRIV(X)	.org	0x1000+64*X
-
-/*
- * Halt
- *
- * SIDE EFFECTS:
- *
- *	We either power down the system or re-enter the console.
- *	But given that we're not returning to the kernel, there's
- *	no reason to continue processing in assembler.  Go to C.
- */
-	ORG_CALL_PAL_PRIV(0x00)
-CallPal_Halt:
-	bsr	p7, UpdatePCB		// Save kernel data
-	lda	v0, HLT_K_SW_HALT	// FIXME store this somewhere.
-
-	mtpr	$31, qemu_halt
-
-	br	Sys_EnterConsole
-ENDFN	CallPal_Halt
-
-/*
- * Cache Flush
- *
- * For QEMU, this is of course a no-op.
- */
-	ORG_CALL_PAL_PRIV(0x01)
-CallPal_Cflush:
-	hw_rei
-ENDFN	CallPal_Cflush
-
-/*
- * Drain Aborts
- *
- * For QEMU, this is of course a no-op.
- */
-        ORG_CALL_PAL_PRIV(0x02)
-CallPal_Draina:
-	hw_rei
-ENDFN	CallPal_Draina
-
-	ORG_CALL_PAL_PRIV(0x03)
-CallPal_OpcDec03:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec03
-
-	ORG_CALL_PAL_PRIV(0x04)
-CallPal_OpcDec04:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec04
-
-	ORG_CALL_PAL_PRIV(0x05)
-CallPal_OpcDec05:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec05
-
-	ORG_CALL_PAL_PRIV(0x06)
-CallPal_OpcDec06:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec06
-
-	ORG_CALL_PAL_PRIV(0x07)
-CallPal_OpcDec07:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec07
-
-	ORG_CALL_PAL_PRIV(0x08)
-CallPal_OpcDec08:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec08
-
-/*
- * Console Service
- * 
- * INPUT PARAMETERS:
- * 
- *	r16 (a0)          = Option selector
- *	r17..r21 (a1..a5) = Implementation specific entry parameters
- *
- * SIDE EFFECTS:
- *
- *	Registers a0..a5, and v0 are UNPREDICTABLE upon return.
- */ 
-	ORG_CALL_PAL_PRIV(0x09)
-CallPal_Cserve:
-	// Most of the entries are densely clustered around 0.
-	mov	0, v0
-	cmpule	a0, 7, p0
-	cmovne	p0, a0, v0
-	br	p0, 1f
-1:	lda	p0, Cserve_Table-1b(p0)
-	s8addq	v0, p0, p0
-	jmp	$31, (p0), 0
-ENDFN	CallPal_Cserve
-
-	.text	1
-	.align	3
-/* Note that the entries in the following table are all 2 insns.
-   The first entry is unused, and is also where all out-of-range
-   commands are vectored.  */
-Cserve_Table:
-	br	CallPal_Cserve_Cont
-	nop
-Cserve_Ldqp:
-	ldq_p	v0, 0(a1)
-	hw_rei
-ENDFN	Cserve_Ldqp
-Cserve_Stqp:
-	stq_p	a2, 0(a1)
-	hw_rei
-ENDFN	Cserve_Stqp
-Cserve_Get_Wall_Time:
-	mfpr	v0, qemu_walltime
-	hw_rei
-ENDFN	Cserve_Get_Wall_Time
-Cserve_Get_Alarm:
-	mfpr	v0, qemu_alarm
-	hw_rei
-ENDFN	Cserve_Get_Alarm
-Cserve_Set_Alarm_Rel:
-	// Cheating here: create the absolute time and fall thru.
-	mfpr	p0, qemu_vmtime
-	addq	p0, a1, a1
-ENDFN	Cserve_Set_Alarm_Rel
-Cserve_Set_Alarm_Abs:
-	mtpr	a1, qemu_alarm
-	hw_rei
-ENDFN	Cserve_Set_Alarm_Abs
-Cserve_Get_VM_Time:
-	mfpr	v0, qemu_vmtime
-	hw_rei
-ENDFN	Cserve_Get_VM_Time
-
-
-CallPal_Cserve_Cont:
-	// ??? For SRM compatibility and their use within Linux, use 52/53
-	// for these.  Anyone know what other "standard" SRM Cserve entry
-	// points are?  Certainly we don't want to be compatible with MILO,
-	// which puts the selector at A2.
-	cmpeq	a0, 52, v0
-	bne	v0, Cserve_Ena
-	cmpeq	a0, 53, v0
-	bne	v0, Cserve_Dis
-	hw_rei
-ENDFN	CallPal_Cserve_Cont
-	.previous
-
-/*
- * Swap PALcode
- *
- * FUNCTIONAL DESCRIPTION:
- *
- *	The swap PALcode (swppal) function replaces the current 
- *	(active) PALcode by the specified new PALcode image.  
- *	This function is intended for use by operating systems 
- *	only during bootstraps and restarts, or during transitions 
- *	to console I/O mode.
- * 
- *	The PALcode descriptor passed in a0 is interpreted as
- *	either a PALcode variant or the base physical address
- *	of the new PALcode image.  If a variant, the PALcode
- *	image must have been previously loaded.  No PALcode
- *	loading occurs as a result of this function. 
- *
- *	NOTE:
- *	This implementation of SWPPAL does not support PALcode
- *	variants.  If a variant is specified in a0, a check is
- *	performed to determine whether the variant is OSF/1 or
- *	not and the returned status is either unknown variant
- *	(if not OSF/1) or variant not loaded.
- *
- * INPUT PARAMETERS:
- *
- *	r16 (a0) = New PALcode variant or base physical address
- *	r17 (a1) = New PC
- *	r18 (a2) = New PCB
- *	r19 (a3) = New VptPtr
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = Returned status indicating:
- *			0 - Success (PALcode was switched)
- *			1 - Unknown PALcode variant
- *			2 - Known PALcode variant, but PALcode not loaded
- *
- *	r26 (ra) = r27 (pv) = New PC
- *		Note that this is non-architected, but is relied on by
- *		the usage of SwpPal within our own console code in order
- *		to simplify its use within C code.
- *
- */
-	ORG_CALL_PAL_PRIV(0x0A)
-CallPal_SwpPal:
-	// Save a copy of the return address in case of machine check.
-	mfpr	p6, qemu_exc_addr
-
-	// Accept swapping to OSF PALcode.  The side effect here is to
-	// load the other parameters for the kernel.
-	cmpeq	a0, 2, v0
-	bne	v0, CallPal_SwpPal_Cont
-
-	// Return as an unknown PALcode variant
-	mov	1, v0
-	hw_rei
-ENDFN	CallPal_SwpPal
-
-	.text	1
-CallPal_SwpPal_Cont:
-	rpcc	p0
-	mtpr	a2, ptPcbb
-	mtpr	a3, qemu_vptptr
-
-	ldq_p	$sp, PCB_Q_KSP(a2)
-	ldq_p	t0, PCB_Q_USP(a2)
-	ldq_p	t1, PCB_Q_PTBR(a2)
-	ldl_p	t2, PCB_L_PCC(a2)
-	ldq_p	t3, PCB_Q_UNIQUE(a2)
-	ldq_p	t4, PCB_Q_FEN(a2)
-
-	mtpr	t0, qemu_usp
-
-	sll	t1, VA_S_OFF, t1
-	mtpr	t1, qemu_ptbr
-
-	subl	t2, p0, t2
-	mtpr	t2, qemu_pcc_ofs
-
-	mtpr	t3, qemu_unique
-
-	and	t4, 1, t4
-	mtpr	t4, qemu_fen
-
-	mtpr	$31, qemu_tbia		// Flush TLB for new PTBR
-
-	mov	a1, $26
-	mov	a1, $27
-	hw_ret	(a1)
-ENDFN	CallPal_SwpPal_Cont
-	.previous
-
-	ORG_CALL_PAL_PRIV(0x0B)
-CallPal_OpcDec0B:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec0B
-
-	ORG_CALL_PAL_PRIV(0x0C)
-CallPal_OpcDec0C:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec0C
-
-/*
- * Write Interprocessor Interrupt Request
- *
- * INPUT PARAMETERS:
- *
- *	r16 (a0) = target processor number 
- * 
- * OUTPUT PARAMETERS:
- *
- * SIDE EFFECTS:
- * 
- */ 
-        ORG_CALL_PAL_PRIV(0x0D)
-CallPal_WrIpir:
-	// Save a copy of the return address in case of machine check.
-	mfpr	p6, qemu_exc_addr
-
-	SYS_WRIPIR	a0, p0, p1, p2
-
-	hw_rei
-ENDFN	CallPal_WrIpir
-
-	ORG_CALL_PAL_PRIV(0x0E)
-CallPal_OpcDec0E:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec0E
-
-	ORG_CALL_PAL_PRIV(0x0F)
-CallPal_OpcDec0F:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec0F
-
-/*
- * Read Machine Check Error Summary
- *
- * INPUT PARAMETERS:
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = returned MCES value
- * 
- * SIDE EFFECTS:
- *
- */ 
-        ORG_CALL_PAL_PRIV(0x10)
-CallPal_RdMces:
-	mfpr	v0, ptMces		// Get current MCES value
-	and	v0, MCES_M_ALL, v0	// Clear all other bits
-	hw_rei
-ENDFN	CallPal_RdMces
-
-/*
- * Write Machine Check Error Summary
- *
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = MCES<DPC> <- a0<3>,  MCES<DSC> <- a0<4>
- * 
- * OUTPUT PARAMETERS:
- *
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x11)
-CallPal_WrMces:
-	// Clear MIP, SCE, PCE
-	and	a0, (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE), p0
-	mfpr	p1, ptMces
-	bic	p1, p0, p1
-
-	// Copy DPC and DSC
-	and	a0, (MCES_M_DPC | MCES_M_DSC), p0
-	bic	p1, (MCES_M_DPC | MCES_M_DSC), p1
-	or	p1, p0, p1
-
-	mtpr	p1, ptMces
-	hw_rei
-ENDFN	CallPal_WrMces
-
-	ORG_CALL_PAL_PRIV(0x12)
-CallPal_OpcDec12:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec12
-
-	ORG_CALL_PAL_PRIV(0x13)
-CallPal_OpcDec13:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec13
-
-	ORG_CALL_PAL_PRIV(0x14)
-CallPal_OpcDec14:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec14
-
-	ORG_CALL_PAL_PRIV(0x15)
-CallPal_OpcDec15:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec15
-
-	ORG_CALL_PAL_PRIV(0x16)
-CallPal_OpcDec16:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec16
-
-	ORG_CALL_PAL_PRIV(0x17)
-CallPal_OpcDec17:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec17
-
-	ORG_CALL_PAL_PRIV(0x18)
-CallPal_OpcDec18:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec18
-
-	ORG_CALL_PAL_PRIV(0x19)
-CallPal_OpcDec19:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec19
-
-	ORG_CALL_PAL_PRIV(0x1A)
-CallPal_OpcDec1A:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec1A
-
-	ORG_CALL_PAL_PRIV(0x1B)
-CallPal_OpcDec1B:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec1B
-
-	ORG_CALL_PAL_PRIV(0x1C)
-CallPal_OpcDec1C:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec1C
-
-	ORG_CALL_PAL_PRIV(0x1D)
-CallPal_OpcDec1D:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec1D
-
-	ORG_CALL_PAL_PRIV(0x1E)
-CallPal_OpcDec1E:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec1E
-
-	ORG_CALL_PAL_PRIV(0x1F)
-CallPal_OpcDec1F:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec1F
-
-	ORG_CALL_PAL_PRIV(0x20)
-CallPal_OpcDec20:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec20
-
-	ORG_CALL_PAL_PRIV(0x21)
-CallPal_OpcDec21:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec21
-
-	ORG_CALL_PAL_PRIV(0x22)
-CallPal_OpcDec22:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec22
-
-	ORG_CALL_PAL_PRIV(0x23)
-CallPal_OpcDec23:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec23
-
-	ORG_CALL_PAL_PRIV(0x24)
-CallPal_OpcDec24:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec24
-
-	ORG_CALL_PAL_PRIV(0x25)
-CallPal_OpcDec25:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec25
-
-	ORG_CALL_PAL_PRIV(0x26)
-CallPal_OpcDec26:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec26
-
-	ORG_CALL_PAL_PRIV(0x27)
-CallPal_OpcDec27:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec27
-
-	ORG_CALL_PAL_PRIV(0x28)
-CallPal_OpcDec28:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec28
-
-	ORG_CALL_PAL_PRIV(0x29)
-CallPal_OpcDec29:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec29
-
-	ORG_CALL_PAL_PRIV(0x2A)
-CallPal_OpcDec2A:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec2A
-
-/*
- * Write Floating Point Enable
- *
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = ICSR<FPE> <- a0<0>
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x2B)
-CallPal_WrFen:
-	mfpr	p0, ptPcbb		// Get PCBB
-	and	a0, 1, a0		// Clean new FEN value to single bit
-	mtpr	a0, qemu_fen
-	stl_p	a0, PCB_Q_FEN(p0)	// Write new PCB<FEN>
-	hw_rei
-ENDFN	CallPal_WrFen
-
-	ORG_CALL_PAL_PRIV(0x2C)
-CallPal_OpcDec2C:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec2C
-
-/*
- * Write Virtual Page Table Pointer
- *
- * INPUT PARAMETERS:
- *
- *	r16 (a0) = New virtual page table pointer 
- *
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x2D)
-CallPal_WrVptPtr:
-	mtpr	a0, qemu_vptptr
-	hw_rei
-ENDFN	CallPal_WrVptPtr
-
-	ORG_CALL_PAL_PRIV(0x2E)
-CallPal_OpcDec2E:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec2E
-
-	ORG_CALL_PAL_PRIV(0x2F)
-CallPal_OpcDec2F:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec2F
-
-/*
- * Swap Process Context
- *
- * FUNCTIONAL DESCRIPTION:
- *
- *	The swap process context (swpctx) function saves 
- *	the current process data in the current PCB, then 
- *	switches to the PCB passed in a0 and loads the
- *	new process context.  The old PCB is returned in v0.	
- * 
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = New PCBB 
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0  (v0) = Old PCBB
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-	ORG_CALL_PAL_PRIV(0x30)
-CallPal_SwpCtx:
-	rpcc	p5			// Get cycle counter
-	mfpr	p6, qemu_exc_addr	// Save exc_addr for machine check
-
-	mfpr	v0, ptPcbb		// Get current PCBB
-	mtpr	a0, ptPcbb		// Save new PCBB
-	srl	p5, 32, p7		// Move CC<OFFSET> to low longword
-
-	addl	p5, p7, p7		// Accumulate time for old pcb
-	stl_p	p7, PCB_L_PCC(v0)
-
-	ldl_p	t9, PCB_L_PCC(a0)	// Get new PCC
-	subl	t9, p5, p5		// Generate and ...
-	mtpr	p5, qemu_pcc_ofs	// .. set new CC<OFFSET> bits
-
-	stq_p	$sp, PCB_Q_KSP(v0)	// Store old kernel stack pointer
-	mfpr	t10, qemu_usp		// Save old user stack pointer
-	stq_p	t10, PCB_Q_USP(v0)
-
-	br	CallPal_SwpCtx_Cont
-ENDFN	CallPal_SwpCtx
-
-	.text	1
-CallPal_SwpCtx_Cont:
-	ldq_p	$sp, PCB_Q_KSP(a0)	// Install new stack pointers
-	ldq_p	t10, PCB_Q_USP(a0)
-	mtpr	t10, qemu_usp
-
-	mfpr	t10, qemu_unique	// Save old unique value
-	stq_p	t10, PCB_Q_UNIQUE(v0)
-	ldq_p	t10, PCB_Q_UNIQUE(a0)	// Install new unique value
-	mtpr	t10, qemu_unique
-
-	ldq_p	t8, PCB_Q_FEN(a0)	// Install new FEN
-	and	t8, 1, t8
-	mtpr	t8, qemu_fen
-
-	// QEMU does not implement an ASN; skip that.
-
-	ldq_p	t10, PCB_Q_PTBR(a0)	// Install new page tables
-	sll	t10, VA_S_OFF, t10
-	mtpr	t10, qemu_ptbr
-	mtpr	$31, qemu_tbia		// Flush TLB, since we don't do ASNs
-
-	hw_rei
-ENDFN	CallPal_SwpCtx_Cont
-	.previous
-
-/*
- * Write System Value
- *
- * INPUT PARAMETERS:
- *
- *	r16 (a0) = New system value 
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x31)
-CallPal_WrVal:
-	mtpr	a0, qemu_sysval
-	hw_rei
-ENDFN	CallPal_WrVal
-
-/*
- * Read System Value
- *
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = Returned system value
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0 and t8..t11 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x32)
-CallPal_RdVal:
-	mfpr	v0, qemu_sysval
-	hw_rei
-ENDFN	CallPal_RdVal
-
-/*
- * Translation Buffer Invalidate
- * 
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = tbi selector type:
- *
- *		-2 - Flush all TB entries (tbia)
- *		-1 - Invalidate all TB entries with ASM=0 (tbiap)
- *		 1 - Invalidate ITB entry for va=a1 (tbisi)
- *		 2 - Invalidate DTB entry for va=a1 (tbisd)
- *		 3 - Invalidate both ITB and DTB entry for va=a1 (tbis)
- *
- *	r17 (a1) = VA for TBISx types
- *
- * Qemu does not implement ASNs or split I/D tlbs.  Therefore these
- * collapse to tbia and tbis.
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x33)
-CallPal_Tbi:
-	bge	a0, 1f
-
-	mtpr	$31, qemu_tbia
-	hw_rei
-
-1:	mtpr	a1, qemu_tbis
-	hw_rei
-ENDFN	CallPal_Tbi
-
-/*
- * Write System Entry Address
- *
- * INPUT PARAMETERS:
- *
- *	r16 (a0) = VA of system entry point
- *	r17 (a1) = System entry point selector 
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0..a1 are UNPREDICTABLE
- *	upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x34)
-CallPal_WrEnt:
-	andnot	a0, 3, a0		// Clean PC<1:0>
-
-	cmpult	a1, 6, t8		// Bound the input
-	cmoveq	t8, 6, a1
-
-	br	t0, 1f
-1:	lda	t0, WrEnt_Table-1b(t0)
-	s8addq	a1, t0, t0
-	jmp	$31, (t0), 0
-ENDFN	CallPal_WrEnt
-
-	.text	1
-WrEnt_Table:
-0:	mtpr	a0, ptEntInt
-	hw_rei
-1:	mtpr	a0, ptEntArith
-	hw_rei
-2:	mtpr	a0, ptEntMM
-	hw_rei
-3:	mtpr	a0, ptEntIF
-	hw_rei
-4:	mtpr	a0, ptEntUna
-	hw_rei
-5:	mtpr	a0, ptEntSys
-	hw_rei
-6:	nop
-	hw_rei
-ENDFN	WrEnt_Table
-	.previous
-
-/*
- * Swap Interrupt Priority Level
- * 
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = New IPL
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0  (v0) = Old IPL
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x35)
-CallPal_SwpIpl:
-	mfpr	v0, qemu_ps
-	and	a0, PS_M_IPL, a0
-	and	v0, PS_M_IPL, v0
-	mtpr	a0, qemu_ps
-	hw_rei
-ENDFN	CallPal_SwpIpl
-
-/*
- * Read Processor Status
- *
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = Current PS
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x36)
-CallPal_RdPs:
-	mfpr	v0, qemu_ps
-	hw_rei
-ENDFN	CallPal_RdPs
-
-/*
- * Write Kernel Global Pointer
- *
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = New KGP value
- *
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x37)
-CallPal_WrKgp:
-	mtpr	a0, ptKgp
-	hw_rei
-ENDFN	CallPal_WrKgp
-
-/*
- * Write User Stack Pointer
- * 
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = New user stack pointer value
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x38)
-CallPal_WrUsp:
-	mtpr	a0, qemu_usp
-	hw_rei
-ENDFN	CallPal_WrUsp
-
-/*
- * Write Performance Monitor
- *
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = New user stack pointer value
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, t8..t11, and a0 are UNPREDICTABLE upon return.
- */
-	ORG_CALL_PAL_PRIV(0x39)
-CallPal_WrPerfMon:
-	// Not implemented
-	hw_rei
-ENDFN	CallPal_WrPerfMon
-
-/*
- * Read User Stack Pointer
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = User stack pointer value
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0, and t8..t11 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x3A)
-CallPal_RdUsp:
-	mfpr	v0, qemu_usp
-	hw_rei
-ENDFN	CallPal_RdUsp
-
-	ORG_CALL_PAL_PRIV(0x3B)
-CallPal_OpcDec3B:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec3B
-
-/*
- * Who Am I
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = Current processor number
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0 and t8..t11 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x3C)
-CallPal_Whami:
-	SYS_WHAMI v0
-	hw_rei
-ENDFN	CallPal_Whami
-
-/*
- * Return From System Call
- *
- * INPUT PARAMETERS:
- * 
- *	r30 (sp) = Pointer to the top of the kernel stack
- * 
- * OUTPUT PARAMETERS:
- *
- *	r29 (gp) = Restored user mode global pointer
- *	r30 (sp) = User stack pointer
- * 
- * SIDE EFFECTS:
- *
- *	Registers t0 and t8..t11 are UNPREDICTABLE upon return.
- */ 
-        ORG_CALL_PAL_PRIV(0x3D)
-CallPal_RetSys:
-	ldq	t9, FRM_Q_PC($sp)	// Pop the return address
-	ldq	$gp, FRM_Q_GP($sp)	// Get the user mode global pointer
-	lda	t8, FRM_K_SIZE($sp)
-	mtpr	t8, ptKsp
-
-	mov	PS_K_USER, t8		// Set new mode to user
-	mtpr	t8, qemu_ps
-
-	mfpr	$sp, qemu_usp		// Get the user stack pointer
-
-	andnot	t9, 3, t9		// Clean return PC<1:0>
-	hw_ret	(t9)
-ENDFN	CallPal_RetSys
-
-/*
- * Wait For Interrupt
- *
- * FUNCTIONAL DESCRIPTION:
- *
- *	If possible, wait for the first of either of the following
- *	conditions before returning: any interrupt other than a clock
- *	tick; or the first clock tick after a specified number of clock
- *	ticks have bbeen skipped.
- *
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = Maximum number of clock ticks to skip
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = Number of clock ticks actually skipped.
- */
-	ORG_CALL_PAL_PRIV(0x3E)
-CallPal_WtInt:
-	mtpr	$31, qemu_wait
-	mov	0, v0
-	hw_rei
-ENDFN	CallPal_WtInt
-
-/*
- * Return From Trap, Fault, or Interrupt
- *
- * INPUT PARAMETERS:
- * 
- *	r30 (sp) = Pointer to the top of the kernel stack
- * 
- * OUTPUT PARAMETERS:
- *
- *	ps       <- (sp+00)
- *	pc       <- (sp+08)
- *	r29 (gp) <- (sp+16)
- *	r16 (a0) <- (sp+24)
- *	r17 (a1) <- (sp+32)
- *	r18 (a2) <- (sp+40)
- */ 
-        ORG_CALL_PAL_PRIV(0x3F)
-	.globl	CallPal_Rti
-CallPal_Rti:
-	mfpr	p6, qemu_exc_addr	// Save exc_addr for machine check
-
-	ldq	p4, FRM_Q_PS($sp)	// Get the PS
-	ldq	p5, FRM_Q_PC($sp)	// Get the return PC
-	ldq	$gp, FRM_Q_GP($sp)	// Get gp
-	ldq	a0, FRM_Q_A0($sp)	// Get a0
-	ldq	a1, FRM_Q_A1($sp)	// Get a1
-	ldq	a2, FRM_Q_A2($sp)	// Get a2
-	lda	$sp, FRM_K_SIZE($sp)	// Pop the stack
-
-	andnot	p5, 3, p5		// Clean return PC<1:0>
-
-	and	p4, PS_M_CM, p3
-	bne	p3, CallPal_Rti_ToUser
-
-	and	p4, PS_M_IPL, p4
-	mtpr	p4, qemu_ps
-	hw_ret	(p5)
-ENDFN	CallPal_Rti
-
-	.text	1
-CallPal_Rti_ToUser:
-	mtpr	p3, qemu_ps
-	mtpr	$sp, ptKsp
-	mfpr	$sp, qemu_usp
-	hw_ret	(p5)
-ENDFN	CallPal_Rti_ToUser
-	.previous
-
-/*
- * OSF/1 Unprivileged CALL_PAL Entry Points
- */
-
-#define ORG_CALL_PAL_UNPRIV(X)	.org	0x2000+64*(X-0x80)
-
-/*
- * A helper routine for the unprivaledged kernel entry points, since the
- * actual stack frame setup code is just a tad too large to fit inline.
- *
- * INPUT PARAMETERS:
- *
- *	p5 = ps
- *	p6 = exc_addr
- *	p7 = return address
- *
- * SIDE EFFECTS:
- *
- *	p0 is clobbered
- *
- */
-	.text	1
-CallPal_Stack_Frame:
-	// Test if we're currently in user mode
-	and	p5, PS_M_CM, p0
-	beq	p0, 0f
-CallPal_Stack_Frame_FromUser:
-	// Switch to kernel mode
-	mtpr	$31, qemu_ps
-	mtpr	$sp, qemu_usp
-	mfpr	$sp, ptKsp
-0:
-	// Allocate the stack frame
-	lda	$sp, -FRM_K_SIZE($sp)
-	stq	p5, FRM_Q_PS($sp)
-	stq	p6, FRM_Q_PC($sp)
-	stq	$gp, FRM_Q_GP($sp)
-	stq	a0, FRM_Q_A0($sp)
-	stq	a1, FRM_Q_A1($sp)
-	stq	a2, FRM_Q_A2($sp)
-	ret	$31, (p7), 0
-ENDFN	CallPal_Stack_Frame
-	.previous
-
-/*
- * Breakpoint Trap
- *
- * OUTPUT PARAMETERS:
- *
- *	r16 (a0) = Code for bpt (0)
- *	r17 (a1) = UNPREDICTABLE
- *	r18 (a2) = UNPREDICTABLE
- */ 
-        ORG_CALL_PAL_UNPRIV(0x80)
-CallPal_Bpt:
-	mfpr	p5, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	bsr	p7, CallPal_Stack_Frame
-
-	mfpr	p0, ptEntIF
-	mfpr	$gp, ptKgp
-	mov	IF_K_BPT, a0
-	hw_ret	(p0)
-ENDFN	CallPal_Bpt
-
-/*
- * Bugcheck Trap
- * 
- * OUTPUT PARAMETERS:
- *
- *	r16 (a0) = Code for bugchk (1)
- *	r17 (a1) = UNPREDICTABLE
- *	r18 (a2) = UNPREDICTABLE
- */ 
-        ORG_CALL_PAL_UNPRIV(0x81)
-CallPal_BugChk:
-	mfpr	p5, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	bsr	p7, CallPal_Stack_Frame
-
-	mfpr	p0, ptEntIF
-	mfpr	$gp, ptKgp
-	mov	IF_K_BUGCHK, a0
-	hw_ret	(p0)
-ENDFN	CallPal_BugChk
-
-
-	ORG_CALL_PAL_UNPRIV(0x82)
-CallPal_OpcDec82:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec82
-
-/*
- * System Call
- */ 
-        ORG_CALL_PAL_UNPRIV(0x83)
-CallPal_CallSys:
-	mfpr	p5, qemu_ps
-	mfpr	p6, qemu_exc_addr
-
-	and	p5, PS_M_CM, p0
-	beq	p0, 0f
-
-	bsr	p7, CallPal_Stack_Frame_FromUser
-
-	mfpr	p0, ptEntSys
-	mfpr	$gp, ptKgp
-	hw_ret	(p0)
-
-0:	subq	p6, 4, p6		// Get PC of CALL_PAL insn
-	br	MchkOSBugCheck
-ENDFN	CallPal_CallSys
-
-	ORG_CALL_PAL_UNPRIV(0x84)
-CallPal_OpcDec84:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec84
-
-	ORG_CALL_PAL_UNPRIV(0x85)
-CallPal_OpcDec85:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec85
-
-
-/*
- * I-Stream Memory Barrier
- *
- * For QEMU, this is of course a no-op.
- */ 
-        ORG_CALL_PAL_UNPRIV(0x86)
-CallPal_Imb:
-	hw_rei
-ENDFN	CallPal_Imb
-
-
-	ORG_CALL_PAL_UNPRIV(0x87)
-CallPal_OpcDec87:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec87
-
-	ORG_CALL_PAL_UNPRIV(0x88)
-CallPal_OpcDec88:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec88
-
-	ORG_CALL_PAL_UNPRIV(0x89)
-CallPal_OpcDec89:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec89
-
-	ORG_CALL_PAL_UNPRIV(0x8A)
-CallPal_OpcDec8A:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec8A
-
-	ORG_CALL_PAL_UNPRIV(0x8B)
-CallPal_OpcDec8B:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec8B
-
-	ORG_CALL_PAL_UNPRIV(0x8C)
-CallPal_OpcDec8C:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec8C
-
-	ORG_CALL_PAL_UNPRIV(0x8D)
-CallPal_OpcDec8D:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec8D
-
-	ORG_CALL_PAL_UNPRIV(0x8E)
-CallPal_OpcDec8E:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec8E
-
-	ORG_CALL_PAL_UNPRIV(0x8F)
-CallPal_OpcDec8F:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec8F
-
-	ORG_CALL_PAL_UNPRIV(0x90)
-CallPal_OpcDec90:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec90
-
-	ORG_CALL_PAL_UNPRIV(0x91)
-CallPal_OpcDec91:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec91
-
-	ORG_CALL_PAL_UNPRIV(0x92)
-CallPal_OpcDec92:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec92
-
-	ORG_CALL_PAL_UNPRIV(0x93)
-CallPal_OpcDec93:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec93
-
-	ORG_CALL_PAL_UNPRIV(0x94)
-CallPal_OpcDec94:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec94
-
-	ORG_CALL_PAL_UNPRIV(0x95)
-CallPal_OpcDec95:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec95
-
-	ORG_CALL_PAL_UNPRIV(0x96)
-CallPal_OpcDec96:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec96
-
-	ORG_CALL_PAL_UNPRIV(0x97)
-CallPal_OpcDec97:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec97
-
-	ORG_CALL_PAL_UNPRIV(0x98)
-CallPal_OpcDec98:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec98
-
-	ORG_CALL_PAL_UNPRIV(0x99)
-CallPal_OpcDec99:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec99
-
-	ORG_CALL_PAL_UNPRIV(0x9A)
-CallPal_OpcDec9A:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec9A
-
-	ORG_CALL_PAL_UNPRIV(0x9B)
-CallPal_OpcDec9B:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec9B
-
-	ORG_CALL_PAL_UNPRIV(0x9C)
-CallPal_OpcDec9C:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec9C
-
-	ORG_CALL_PAL_UNPRIV(0x9D)
-CallPal_OpcDec9D:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDec9D
-
-/*
- * Read Unique Value
- * 
- * OUTPUT PARAMETERS:
- *
- *	r0 (v0) = Returned process unique value
-*/ 
-        ORG_CALL_PAL_UNPRIV(0x9E)
-CallPal_RdUnique:
-	mfpr	v0, qemu_unique
-	hw_rei
-ENDFN	CallPal_RdUnique
-
-/*
- * Write Unique Value
- * 
- * INPUT PARAMETERS:
- * 
- *	r16 (a0) = New process unique value
- */ 
-        ORG_CALL_PAL_UNPRIV(0x9F)
-CallPal_WrUnique:
-	mtpr	a0, qemu_unique
-	hw_rei
-ENDFN	CallPal_WrUnique
-
-	ORG_CALL_PAL_UNPRIV(0xA0)
-CallPal_OpcDecA0:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA0
-
-	ORG_CALL_PAL_UNPRIV(0xA1)
-CallPal_OpcDecA1:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA1
-
-	ORG_CALL_PAL_UNPRIV(0xA2)
-CallPal_OpcDecA2:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA2
-
-	ORG_CALL_PAL_UNPRIV(0xA3)
-CallPal_OpcDecA3:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA3
-
-	ORG_CALL_PAL_UNPRIV(0xA4)
-CallPal_OpcDecA4:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA4
-
-	ORG_CALL_PAL_UNPRIV(0xA5)
-CallPal_OpcDecA5:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA5
-
-	ORG_CALL_PAL_UNPRIV(0xA6)
-CallPal_OpcDecA6:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA6
-
-	ORG_CALL_PAL_UNPRIV(0xA7)
-CallPal_OpcDecA7:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA7
-
-	ORG_CALL_PAL_UNPRIV(0xA8)
-CallPal_OpcDecA8:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA8
-
-	ORG_CALL_PAL_UNPRIV(0xA9)
-CallPal_OpcDecA9:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecA9
-
-/*
- * Generate Trap
- *
- * OUTPUT PARAMETERS:
- *
- *	r16 (a0) = Code for gentrap (2)
- *	r17 (a1) = UNPREDICTABLE
- *	r18 (a2) = UNPREDICTABLE
- */ 
-        ORG_CALL_PAL_UNPRIV(0xAA)
-CallPal_GenTrap:
-	mfpr	p5, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	bsr	p7, CallPal_Stack_Frame
-
-	mfpr	p0, ptEntIF
-	mfpr	$gp, ptKgp
-	mov	IF_K_GENTRAP, a0
-	hw_ret	(p0)
-ENDFN	CallPal_GenTrap
-
-	ORG_CALL_PAL_UNPRIV(0xAB)
-CallPal_OpcDecAB:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecAB
-
-	ORG_CALL_PAL_UNPRIV(0xAC)
-CallPal_OpcDecAC:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecAC
-
-	ORG_CALL_PAL_UNPRIV(0xAD)
-CallPal_OpcDecAD:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecAD
-
-	ORG_CALL_PAL_UNPRIV(0xAE)
-CallPal_OpcDecAE:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecAE
-
-	ORG_CALL_PAL_UNPRIV(0xAF)
-CallPal_OpcDecAF:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecAF
-
-	ORG_CALL_PAL_UNPRIV(0xB0)
-CallPal_OpcDecB0:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB0
-
-	ORG_CALL_PAL_UNPRIV(0xB1)
-CallPal_OpcDecB1:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB1
-
-	ORG_CALL_PAL_UNPRIV(0xB2)
-CallPal_OpcDecB2:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB2
-
-	ORG_CALL_PAL_UNPRIV(0xB3)
-CallPal_OpcDecB3:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB3
-
-	ORG_CALL_PAL_UNPRIV(0xB4)
-CallPal_OpcDecB4:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB4
-
-	ORG_CALL_PAL_UNPRIV(0xB5)
-CallPal_OpcDecB5:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB5
-
-	ORG_CALL_PAL_UNPRIV(0xB6)
-CallPal_OpcDecB6:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB6
-
-	ORG_CALL_PAL_UNPRIV(0xB7)
-CallPal_OpcDecB7:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB7
-
-	ORG_CALL_PAL_UNPRIV(0xB8)
-CallPal_OpcDecB8:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB8
-
-	ORG_CALL_PAL_UNPRIV(0xB9)
-CallPal_OpcDecB9:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecB9
-
-	ORG_CALL_PAL_UNPRIV(0xBA)
-CallPal_OpcDecBA:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecBA
-
-	ORG_CALL_PAL_UNPRIV(0xBB)
-CallPal_OpcDecBB:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecBB
-
-	ORG_CALL_PAL_UNPRIV(0xBC)
-CallPal_OpcDecBC:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecBC
-
-	ORG_CALL_PAL_UNPRIV(0xBD)
-CallPal_OpcDecBD:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecBD
-
-	ORG_CALL_PAL_UNPRIV(0xBE)
-CallPal_OpcDecBE:
-	br	CallPal_OpcDec
-ENDFN	CallPal_OpcDecBE
-
-	ORG_CALL_PAL_UNPRIV(0xBF)
-CallPal_OpcDec:
-	mfpr	p5, qemu_ps
-	mfpr	p6, qemu_exc_addr
-	bsr	p7, CallPal_Stack_Frame
-
-	mfpr	p0, ptEntIF
-	mfpr	$gp, ptKgp
-	mov	IF_K_OPCDEC, a0
-	hw_ret	(p0)
-ENDFN	CallPal_OpcDec
-
-	.org	0x3000
-	.text	1
-/*
- * PALcode detected processor machine check handler.
- *
- *      The PALcode-detected machine check handler loads a code
- *      indicating the type of machine check error, loads 
- *      the System Control Block (SCB) vector for the 
- *      processor machine check service routine, sets the 
- *      Machine-Check-In-Progress (MIP) flag in the Machine
- *      Check Error Summary register (MCES), and merges
- *      with the common machine check flow.
- *
- *      If a second processor machine check error condition 
- *      is detected while the MIP flag is set, the processor 
- *      is forced into console I/O mode indicating "double 
- *      error abort encountered" as the reason for the halt. 
- * 
- * CALLING SEQUENCE:
- * 
- *      Called when an internal processor error is detected
- *      that cannot be successfully corrected by hardware or
- *      PALcode.
- * 
- * INPUT PARAMETERS:
- *
- *      r14 (p6) = Exception address 
- * 
- * OUTPUT PARAMETERS:
- *
- *      ptMchk0         = saved v0
- *      ptMchk1         = saved t0
- *      ptMchk2         = saved t3
- *      ptMchk3         = saved t4
- *      ptMchk4         = saved t5
- *	ptMchk5		= saved exc_addr
- *      ptMisc<47:32>   = MCHK code
- *      ptMisc<31:16>   = SCB vector
- *      ptMces<MIP>     = Set
- * 
- * SIDE EFFECTS:
- *
- *      r0 (v0), r1 (t0), and r4..r6 (t3..t5) are saved in
- *      PAL temporaries and are available for use as scratch
- *      registers by the system specific machine check 
- *      handler.
- */
-
-MchkBugCheck:
-MchkOSBugCheck:
-	halt
-ENDFN	MchkBugCheck
-
-/*
- * Common Machine Check Handler
- *
- * INPUT STATE:
- *
- *      ptMchk0		Saved v0
- *      ptMchk1		Saved t0
- *      ptMchk2		Saved t3
- *      ptMchk3		Saved t4
- *      ptMchk4		Saved t5
- *      ptMchk5		Saved exc_addr
- *      ptMisc<47:32>	MCHK code
- *      ptMisc<31:16>	SCB vector
- *      ptMces<MIP>	Set
- *
- * Registers v0, t0, and t3 .. t5 are available for use, in
- * addition to the shadow registers.
- */
-
-MchkCommon:
-	halt
-ENDFN	MchkCommon
-
-/*
- * Build Machine Check Logout Frame
- *
- *      This portion of the  machine check handler builds a logout frame
- *      in the PAL impure scratch area, builds a stack frame on the kernel
- *      stack (already built if there was an interrupt machine check),
- *      loads the GP with the KGP, loads the machine check entry 
- *      code in a0, loads a platform-specific interrupt vector 
- *      (typically the same value as the SCB offset) in a1, loads 
- *      the kseg address of the logout area in a2, and dispatches 
- *      to the kernel interrupt handler pointed to by the entInt 
- *      operating system entry point.
- *
- * OUTPUT PARAMETERS:
- * 
- *      a0 (r16) = Machine check entry type
- *      a1 (r17) = Platform-specific interrupt vector
- *      a2 (r18) = Pointer to logout area
- */
-
-.macro	STORE_IPR	which, offset, base
-	mfpr	v0, \which
-	stq_p	v0, \offset(\base)
-.endm
-
-MchkLogOut:
-	halt
-ENDFN	MchkLogOut
-
-MchkDouble:
-	bsr	p7, UpdatePCB
-	lda	v0, HLT_K_DBL_MCHK
-	br	Sys_EnterConsole
-ENDFN	MchkDouble
-
-MchkFromPal:
-	bsr	p7, UpdatePCB
-	lda	v0, HLT_K_MCHK_FROM_PAL
-	br	Sys_EnterConsole
-ENDFN	MchkFromPal
-
-MchkKspInvalid:
-	bsr	p7, UpdatePCB
-	lda	v0, HLT_K_KSP_INVAL
-	br	Sys_EnterConsole
-ENDFN	MchkKspInvalid
-
-/*
- * Update the current PCB with new SP and CC info.
- *
- * INPUT PARAMETERS:
- *
- *	p7	= return linkage
- */
-
-UpdatePCB:
-	rpcc	p5
-	mfpr	p4, ptPcbb
-
-	mfpr	p3, qemu_ps		// Check current mode
-	and	p3, PS_M_CM, p3
-	beq	p3, 1f
-
-	mtpr	$sp, qemu_usp		// Save user stack pointer
-	stq_p	$sp, PCB_Q_USP(p4)
-	br	2f
-
-1:	mtpr	$sp, ptKsp		// Save kernel stack pointer
-	stq_p	$sp, PCB_Q_KSP(p4)
-
-2:	srl	p5, 32, p3		// Merge for new time
-	addl	p5, p3, p3
-	stl_p	p3, PCB_L_PCC(p4)	// Store new time
-
-	mfpr	p5, qemu_unique		// Save unique
-	stq_p	p5, PCB_Q_UNIQUE(p4)
-
-	ret	$31, (p7), 0
-ENDFN	UpdatePCB
-
-/*
- * FIXME
- */
-Sys_EnterConsole:
-	halt
-
-/*
- * Allocate the initial bootup stack.
- */
-
-	.section .bss.stack
-	.align 3
-	.globl	stack
-	.type	stack,@object
-	.size	stack,STACK_SIZE
-stack:	.skip	STACK_SIZE
diff --git a/qemu/roms/qemu-palcode/pal.h b/qemu/roms/qemu-palcode/pal.h
deleted file mode 100644
index c89a18c39..000000000
--- a/qemu/roms/qemu-palcode/pal.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Common definitions for QEMU Emulation PALcode
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef PAL_H
-#define PAL_H 1
-
-/* General Purpose Registers.  */
-#define	v0	$0
-#define t0	$1
-#define t1	$2
-#define t2	$3
-#define t3	$4
-#define t4	$5
-#define t5	$6
-#define a0	$16
-#define a1	$17
-#define a2	$18
-#define a3	$19
-#define a4	$20
-#define a5	$21
-#define t8	$22
-#define t9	$23
-#define t10	$24
-
-/* PALcode Shadow Registers.  These registers are swapped out when
-   QEMU is in PALmode.  Unlike real hardware, there is no enable bit.
-   However, also unlike real hardware, the originals can be accessed
-   via MTPR/MFPR.  */
-#define p0	$8
-#define p1	$9
-#define p2	$10
-#define p3	$11
-#define p4	$12
-#define p5	$13
-#define p6	$14		// Used to save exc_addr for machine check
-#define p7	$25
-
-/* QEMU Processor Registers.  */
-#define	qemu_ps		0
-#define qemu_fen	1
-#define qemu_pcc_ofs	2
-#define qemu_trap_arg0	3
-#define qemu_trap_arg1	4
-#define qemu_trap_arg2	5
-#define qemu_exc_addr	6
-#define qemu_palbr	7
-#define qemu_ptbr	8
-#define qemu_vptptr	9
-#define qemu_unique	10
-#define qemu_sysval	11
-#define qemu_usp	12
-
-#define qemu_shadow0	32
-#define qemu_shadow1	33
-#define qemu_shadow2	34
-#define qemu_shadow3	35
-#define qemu_shadow4	36
-#define qemu_shadow5	37
-#define qemu_shadow6	38
-#define qemu_shadow7	39
-
-/* PALcode Processor Register Private Storage.  */
-#define pt0		40
-#define pt1		41
-#define pt2		42
-#define pt3		43
-#define pt4		44
-#define pt5		45
-#define pt6		46
-#define pt7		47
-#define pt8		48
-#define pt9		49
-#define pt10		50
-#define pt11		51
-#define pt12		52
-#define pt13		53
-#define pt14		54
-#define pt15		55
-#define pt16		56
-#define pt17		57
-#define pt18		58
-#define pt19		59
-#define pt20		60
-#define pt21		61
-#define pt22		62
-#define pt23		63
-
-/* QEMU function calls, via mtpr.  */
-#define qemu_tbia	255
-#define qemu_tbis	254
-#define qemu_wait	253
-#define qemu_halt	252
-#define qemu_alarm	251
-#define qemu_walltime	250
-#define qemu_vmtime	249
-
-/* PALcode uses of the private storage slots.  */
-#define ptEntUna	pt0
-#define ptEntIF		pt1
-#define ptEntSys	pt2
-#define ptEntInt	pt3
-#define ptEntArith	pt4
-#define ptEntMM		pt5
-#define ptMces		pt6
-#define ptKsp		pt7
-#define ptKgp		pt8
-#define ptPcbb		pt9
-#define ptPgp		pt10
-#define ptMisc		pt11
-#define ptMchk0		pt12
-#define ptMchk1		pt13
-#define ptMchk2		pt14
-#define ptMchk3		pt15
-#define ptMchk4		pt16
-#define ptMchk5		pt17
-#define ptSys0		pt18
-#define ptSys1		pt19
-
-/*
- * Shortcuts for various PALmode instructions.
- */
-#define mtpr	hw_mtpr
-#define mfpr	hw_mfpr
-#define stq_p	hw_stq/p
-#define stl_p	hw_stl/p
-#define ldl_p	hw_ldl/p
-#define ldq_p	hw_ldq/p
-
-/* QEMU recognizes the EV4/EV5 HW_REI instruction as a special case of
-   the EV6 HW_RET instruction.  This pulls the destination address from
-   the EXC_ADDR processor register.  */
-#define hw_rei	hw_ret ($31)
-
-
-.macro	ENDFN	function
-	.type	\function, @function
-	.size	\function, . - \function
-.endm
-
-#endif /* PAL_H */
diff --git a/qemu/roms/qemu-palcode/palcode.ld b/qemu/roms/qemu-palcode/palcode.ld
deleted file mode 100644
index b525cbd20..000000000
--- a/qemu/roms/qemu-palcode/palcode.ld
+++ /dev/null
@@ -1,53 +0,0 @@
-OUTPUT_FORMAT("elf64-alpha")
-ENTRY(__start)
-
-SECTIONS
-{
-  . = 0xfffffc0000000000;
-  .text : { *(.text*) }
-  .rodata : { *(.rodata*) }
-  .data ALIGN(8192) : { *(.data*) }
-  .got : { *(.got.plt) *(.got) }
-  .sdata : { *(.sdata*) }
-  .sbss : { *(.sbss) *(.scommon) }
-  .bss : {
-    *(.bss.page_dir)
-    *(.bss.stack)
-    *(COMMON)
-    *(.bss)
-    PROVIDE (_end = .);
-  }
-
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* DWARF 3 */
-  .debug_pubtypes 0 : { *(.debug_pubtypes) }
-  .debug_ranges   0 : { *(.debug_ranges) }
-  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
-
-  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-  /DISCARD/ : { *(.eh_frame) }
-}
diff --git a/qemu/roms/qemu-palcode/pci.c b/qemu/roms/qemu-palcode/pci.c
deleted file mode 100644
index 87a101cc4..000000000
--- a/qemu/roms/qemu-palcode/pci.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Simplistic PCI support.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-/* We don't bother supporting PCI bridges, because the device model we're
-   currently using for QEMU doesn't build any.
-
-   We don't bother to build real datastructures in memory, because it's
-   fairly quick under emulation simply to access configuration space again.
-   This helps when running kernels under the emulator that might have
-   re-organized the BARs out from under us.  */
-
-#include "protos.h"
-#include "pci.h"
-#include "pci_regs.h"
-
-
-#define PCI_DEVFN(slot, func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
-#define PCI_BUS(devfn)		((devfn) >> 8)
-#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
-#define PCI_FUNC(devfn)		((devfn) & 0x07)
-#define PCI_SLOT_MAX		32
-#define PCI_FUNC_MAX		8
-#define PCI_REGION_ROM		6
-#define PCI_REGIONS_MAX		7
-
-
-void
-pci_config_maskw(int bdf, int addr, uint16_t off, uint16_t on)
-{
-  uint16_t val = pci_config_readw(bdf, addr);
-  val = (val & ~off) | on;
-  pci_config_writew(bdf, addr, val);
-}
-
-int
-pci_next(int bdf, int *pmax)
-{
-  int max;
-
-  if (PCI_FUNC(bdf) == 1)
-    {
-      /* If the last device was not a multi-function device, skip to next.  */
-      if ((pci_config_readb(bdf-1, PCI_HEADER_TYPE) & 0x80) == 0)
-        bdf += 7;
-    }
-
-  max = *pmax;
-  while (1)
-    {
-      uint16_t vendor;
-
-      /* ??? Support multiple PCI busses here at some point.  */
-      if (bdf >= max)
-	return -1;
-
-      /* Check if there is a device present at the location.  */
-      vendor = pci_config_readw(bdf, PCI_VENDOR_ID);
-      if (vendor != 0x0000 && vendor != 0xffff)
-	return bdf;
-
-      bdf += (PCI_FUNC(bdf) == 0 ? 8 : 1);
-    }
-}
-
-static void
-pci_setup_device(int bdf, uint32_t *p_io_base, uint32_t *p_mem_base)
-{
-  int vendor_id, device_id, class_id, region;
-
-  vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
-  device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
-  class_id = pci_config_readw(bdf, PCI_CLASS_DEVICE);
-
-  printf("PCI: %02x:%02x:%x class %04x id %04x:%04x\r\n",
-	 PCI_BUS(bdf), PCI_SLOT(bdf), PCI_FUNC(bdf),
-         class_id, vendor_id, device_id);
-
-  for (region = 0; region < PCI_REGION_ROM; region++)
-    {
-      int ofs = PCI_BASE_ADDRESS_0 + region * 4;
-      uint32_t old, mask, val, size, align;
-      uint32_t *p_base;
-
-      old = pci_config_readl(bdf, ofs);
-      if (old & PCI_BASE_ADDRESS_SPACE_IO)
-	{
-	  mask = PCI_BASE_ADDRESS_IO_MASK;
-	  p_base = p_io_base;
-	}
-      else
-	{
-	  mask = PCI_BASE_ADDRESS_MEM_MASK;
-	  p_base = p_mem_base;
-	}
-
-      pci_config_writel(bdf, ofs, -1);
-      val = pci_config_readl(bdf, ofs);
-      pci_config_writel(bdf, ofs, old);
-
-      align = size = ~(val & mask) + 1;
-      if (val != 0)
-	{
-	  uint32_t addr = *p_base;
-	  addr = (addr + align - 1) & ~(align - 1);
-	  *p_base = addr + size;
-	  pci_config_writel(bdf, ofs, addr);
-
-	  printf("PCI:   region %d: %08x\r\n", region, addr);
-
-	  if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-	      == PCI_BASE_ADDRESS_MEM_TYPE_64)
-	    {
-	      pci_config_writel(bdf, ofs + 4, 0);
-	      region++;
-	    }
-	}
-    }
-
-  pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
-
-  /* Map the interrupt.  */
-}
-
-void
-pci_setup(void)
-{
-  uint32_t io_base = 0xc000;
-  uint32_t mem_base = 256 * 1024 * 1024;
-  int bdf, max;
-
-  foreachpci (bdf, max)
-    pci_setup_device(bdf, &io_base, &mem_base);
-}
diff --git a/qemu/roms/qemu-palcode/pci.h b/qemu/roms/qemu-palcode/pci.h
deleted file mode 100644
index b751c6f66..000000000
--- a/qemu/roms/qemu-palcode/pci.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Simplistic PCI support.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-/* This header is intended to be compatible with the pci.h from SeaBIOS.
-   Their header, however, is too PC specific to be of use.  */
-
-#ifndef PCI_H
-#define PCI_H 1
-
-extern void *pci_conf_base;
-
-static inline void pci_config_writel(int bdf, uint8_t addr, uint32_t val)
-{
-  *(volatile uint32_t *)(pci_conf_base + bdf * 256 + addr) = val;
-}
-
-static inline void pci_config_writew(int bdf, uint8_t addr, uint16_t val)
-{
-  *(volatile uint16_t *)(pci_conf_base + bdf * 256 + addr) = val;
-}
-
-static inline void pci_config_writeb(int bdf, uint8_t addr, uint8_t val)
-{
-  *(volatile uint8_t *)(pci_conf_base + bdf * 256 + addr) = val;
-}
-
-static inline uint32_t pci_config_readl(int bdf, uint8_t addr)
-{
-  return *(volatile uint32_t *)(pci_conf_base + bdf * 256 + addr);
-}
-
-static inline uint16_t pci_config_readw(int bdf, uint8_t addr)
-{
-  return *(volatile uint16_t *)(pci_conf_base + bdf * 256 + addr);
-}
-
-static inline uint8_t pci_config_readb(int bdf, uint8_t addr)
-{
-  return *(volatile uint8_t *)(pci_conf_base + bdf * 256 + addr);
-}
-
-extern void pci_config_maskw(int bdf, int addr, uint16_t off, uint16_t on);
-
-extern int pci_next(int bdf, int *pmax);
-
-#define foreachpci(BDF, MAX)				\
-	for (MAX = 0x0100, BDF = pci_next(0, &MAX);	\
-	     BDF >= 0;					\
-	     BDF = pci_next(BDF+1, &MAX))
-
-#endif /* PCI_H */
diff --git a/qemu/roms/qemu-palcode/pci_ids.h b/qemu/roms/qemu-palcode/pci_ids.h
deleted file mode 100644
index e1cded28c..000000000
--- a/qemu/roms/qemu-palcode/pci_ids.h
+++ /dev/null
@@ -1,2610 +0,0 @@
-/*
- *	PCI Class, Vendor and Device IDs
- *
- *	Please keep sorted.
- */
-
-/* Device classes and subclasses */
-
-#define PCI_CLASS_NOT_DEFINED		0x0000
-#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
-
-#define PCI_BASE_CLASS_STORAGE		0x01
-#define PCI_CLASS_STORAGE_SCSI		0x0100
-#define PCI_CLASS_STORAGE_IDE		0x0101
-#define PCI_CLASS_STORAGE_FLOPPY	0x0102
-#define PCI_CLASS_STORAGE_IPI		0x0103
-#define PCI_CLASS_STORAGE_RAID		0x0104
-#define PCI_CLASS_STORAGE_SATA		0x0106
-#define PCI_CLASS_STORAGE_SATA_AHCI	0x010601
-#define PCI_CLASS_STORAGE_SAS		0x0107
-#define PCI_CLASS_STORAGE_OTHER		0x0180
-
-#define PCI_BASE_CLASS_NETWORK		0x02
-#define PCI_CLASS_NETWORK_ETHERNET	0x0200
-#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
-#define PCI_CLASS_NETWORK_FDDI		0x0202
-#define PCI_CLASS_NETWORK_ATM		0x0203
-#define PCI_CLASS_NETWORK_OTHER		0x0280
-
-#define PCI_BASE_CLASS_DISPLAY		0x03
-#define PCI_CLASS_DISPLAY_VGA		0x0300
-#define PCI_CLASS_DISPLAY_XGA		0x0301
-#define PCI_CLASS_DISPLAY_3D		0x0302
-#define PCI_CLASS_DISPLAY_OTHER		0x0380
-
-#define PCI_BASE_CLASS_MULTIMEDIA	0x04
-#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
-#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
-#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
-#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
-
-#define PCI_BASE_CLASS_MEMORY		0x05
-#define PCI_CLASS_MEMORY_RAM		0x0500
-#define PCI_CLASS_MEMORY_FLASH		0x0501
-#define PCI_CLASS_MEMORY_OTHER		0x0580
-
-#define PCI_BASE_CLASS_BRIDGE		0x06
-#define PCI_CLASS_BRIDGE_HOST		0x0600
-#define PCI_CLASS_BRIDGE_ISA		0x0601
-#define PCI_CLASS_BRIDGE_EISA		0x0602
-#define PCI_CLASS_BRIDGE_MC		0x0603
-#define PCI_CLASS_BRIDGE_PCI		0x0604
-#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
-#define PCI_CLASS_BRIDGE_NUBUS		0x0606
-#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
-#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
-#define PCI_CLASS_BRIDGE_OTHER		0x0680
-
-#define PCI_BASE_CLASS_COMMUNICATION	0x07
-#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
-#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
-#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
-#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
-#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
-
-#define PCI_BASE_CLASS_SYSTEM		0x08
-#define PCI_CLASS_SYSTEM_PIC		0x0800
-#define PCI_CLASS_SYSTEM_PIC_IOAPIC	0x080010
-#define PCI_CLASS_SYSTEM_PIC_IOXAPIC	0x080020
-#define PCI_CLASS_SYSTEM_DMA		0x0801
-#define PCI_CLASS_SYSTEM_TIMER		0x0802
-#define PCI_CLASS_SYSTEM_RTC		0x0803
-#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
-#define PCI_CLASS_SYSTEM_SDHCI		0x0805
-#define PCI_CLASS_SYSTEM_OTHER		0x0880
-
-#define PCI_BASE_CLASS_INPUT		0x09
-#define PCI_CLASS_INPUT_KEYBOARD	0x0900
-#define PCI_CLASS_INPUT_PEN		0x0901
-#define PCI_CLASS_INPUT_MOUSE		0x0902
-#define PCI_CLASS_INPUT_SCANNER		0x0903
-#define PCI_CLASS_INPUT_GAMEPORT	0x0904
-#define PCI_CLASS_INPUT_OTHER		0x0980
-
-#define PCI_BASE_CLASS_DOCKING		0x0a
-#define PCI_CLASS_DOCKING_GENERIC	0x0a00
-#define PCI_CLASS_DOCKING_OTHER		0x0a80
-
-#define PCI_BASE_CLASS_PROCESSOR	0x0b
-#define PCI_CLASS_PROCESSOR_386		0x0b00
-#define PCI_CLASS_PROCESSOR_486		0x0b01
-#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
-#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
-#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
-#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
-#define PCI_CLASS_PROCESSOR_CO		0x0b40
-
-#define PCI_BASE_CLASS_SERIAL		0x0c
-#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
-#define PCI_CLASS_SERIAL_FIREWIRE_OHCI	0x0c0010
-#define PCI_CLASS_SERIAL_ACCESS		0x0c01
-#define PCI_CLASS_SERIAL_SSA		0x0c02
-#define PCI_CLASS_SERIAL_USB		0x0c03
-#define PCI_CLASS_SERIAL_USB_UHCI	0x0c0300
-#define PCI_CLASS_SERIAL_USB_OHCI	0x0c0310
-#define PCI_CLASS_SERIAL_USB_EHCI	0x0c0320
-#define PCI_CLASS_SERIAL_FIBER		0x0c04
-#define PCI_CLASS_SERIAL_SMBUS		0x0c05
-
-#define PCI_BASE_CLASS_WIRELESS			0x0d
-#define PCI_CLASS_WIRELESS_RF_CONTROLLER	0x0d10
-#define PCI_CLASS_WIRELESS_WHCI			0x0d1010
-
-#define PCI_BASE_CLASS_INTELLIGENT	0x0e
-#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
-
-#define PCI_BASE_CLASS_SATELLITE	0x0f
-#define PCI_CLASS_SATELLITE_TV		0x0f00
-#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
-#define PCI_CLASS_SATELLITE_VOICE	0x0f03
-#define PCI_CLASS_SATELLITE_DATA	0x0f04
-
-#define PCI_BASE_CLASS_CRYPT		0x10
-#define PCI_CLASS_CRYPT_NETWORK		0x1000
-#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
-#define PCI_CLASS_CRYPT_OTHER		0x1080
-
-#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
-#define PCI_CLASS_SP_DPIO		0x1100
-#define PCI_CLASS_SP_OTHER		0x1180
-
-#define PCI_CLASS_OTHERS		0xff
-
-/* Vendors and devices.  Sort key: vendor first, device next. */
-
-#define PCI_VENDOR_ID_TTTECH		0x0357
-#define PCI_DEVICE_ID_TTTECH_MC322	0x000a
-
-#define PCI_VENDOR_ID_DYNALINK		0x0675
-#define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
-
-#define PCI_VENDOR_ID_BERKOM			0x0871
-#define PCI_DEVICE_ID_BERKOM_A1T		0xffa1
-#define PCI_DEVICE_ID_BERKOM_T_CONCEPT		0xffa2
-#define PCI_DEVICE_ID_BERKOM_A4T		0xffa4
-#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO	0xffa8
-
-#define PCI_VENDOR_ID_COMPAQ		0x0e11
-#define PCI_DEVICE_ID_COMPAQ_TOKENRING	0x0508
-#define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
-#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
-#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
-#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
-#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
-#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
-#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
-#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
-#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
-#define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
-#define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
-#define PCI_DEVICE_ID_COMPAQ_CISSC	0x46
-#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
-#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
-
-#define PCI_VENDOR_ID_NCR		0x1000
-#define PCI_VENDOR_ID_LSI_LOGIC		0x1000
-#define PCI_DEVICE_ID_NCR_53C810	0x0001
-#define PCI_DEVICE_ID_NCR_53C820	0x0002
-#define PCI_DEVICE_ID_NCR_53C825	0x0003
-#define PCI_DEVICE_ID_NCR_53C815	0x0004
-#define PCI_DEVICE_ID_LSI_53C810AP	0x0005
-#define PCI_DEVICE_ID_NCR_53C860	0x0006
-#define PCI_DEVICE_ID_LSI_53C1510	0x000a
-#define PCI_DEVICE_ID_NCR_53C896	0x000b
-#define PCI_DEVICE_ID_NCR_53C895	0x000c
-#define PCI_DEVICE_ID_NCR_53C885	0x000d
-#define PCI_DEVICE_ID_NCR_53C875	0x000f
-#define PCI_DEVICE_ID_NCR_53C1510	0x0010
-#define PCI_DEVICE_ID_LSI_53C895A	0x0012
-#define PCI_DEVICE_ID_LSI_53C875A	0x0013
-#define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
-#define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
-#define PCI_DEVICE_ID_LSI_53C1030	0x0030
-#define PCI_DEVICE_ID_LSI_1030_53C1035	0x0032
-#define PCI_DEVICE_ID_LSI_53C1035	0x0040
-#define PCI_DEVICE_ID_NCR_53C875J	0x008f
-#define PCI_DEVICE_ID_LSI_FC909		0x0621
-#define PCI_DEVICE_ID_LSI_FC929		0x0622
-#define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
-#define PCI_DEVICE_ID_LSI_FC919		0x0624
-#define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
-#define PCI_DEVICE_ID_LSI_FC929X	0x0626
-#define PCI_DEVICE_ID_LSI_FC939X	0x0642
-#define PCI_DEVICE_ID_LSI_FC949X	0x0640
-#define PCI_DEVICE_ID_LSI_FC949ES	0x0646
-#define PCI_DEVICE_ID_LSI_FC919X	0x0628
-#define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
-#define PCI_DEVICE_ID_LSI_61C102	0x0901
-#define PCI_DEVICE_ID_LSI_63C815	0x1000
-#define PCI_DEVICE_ID_LSI_SAS1064	0x0050
-#define PCI_DEVICE_ID_LSI_SAS1064R	0x0411
-#define PCI_DEVICE_ID_LSI_SAS1066	0x005E
-#define PCI_DEVICE_ID_LSI_SAS1068	0x0054
-#define PCI_DEVICE_ID_LSI_SAS1064A	0x005C
-#define PCI_DEVICE_ID_LSI_SAS1064E	0x0056
-#define PCI_DEVICE_ID_LSI_SAS1066E	0x005A
-#define PCI_DEVICE_ID_LSI_SAS1068E	0x0058
-#define PCI_DEVICE_ID_LSI_SAS1078	0x0060
-
-#define PCI_VENDOR_ID_ATI		0x1002
-/* Mach64 */
-#define PCI_DEVICE_ID_ATI_68800		0x4158
-#define PCI_DEVICE_ID_ATI_215CT222	0x4354
-#define PCI_DEVICE_ID_ATI_210888CX	0x4358
-#define PCI_DEVICE_ID_ATI_215ET222	0x4554
-/* Mach64 / Rage */
-#define PCI_DEVICE_ID_ATI_215GB		0x4742
-#define PCI_DEVICE_ID_ATI_215GD		0x4744
-#define PCI_DEVICE_ID_ATI_215GI		0x4749
-#define PCI_DEVICE_ID_ATI_215GP		0x4750
-#define PCI_DEVICE_ID_ATI_215GQ		0x4751
-#define PCI_DEVICE_ID_ATI_215XL		0x4752
-#define PCI_DEVICE_ID_ATI_215GT		0x4754
-#define PCI_DEVICE_ID_ATI_215GTB	0x4755
-#define PCI_DEVICE_ID_ATI_215_IV	0x4756
-#define PCI_DEVICE_ID_ATI_215_IW	0x4757
-#define PCI_DEVICE_ID_ATI_215_IZ	0x475A
-#define PCI_DEVICE_ID_ATI_210888GX	0x4758
-#define PCI_DEVICE_ID_ATI_215_LB	0x4c42
-#define PCI_DEVICE_ID_ATI_215_LD	0x4c44
-#define PCI_DEVICE_ID_ATI_215_LG	0x4c47
-#define PCI_DEVICE_ID_ATI_215_LI	0x4c49
-#define PCI_DEVICE_ID_ATI_215_LM	0x4c4D
-#define PCI_DEVICE_ID_ATI_215_LN	0x4c4E
-#define PCI_DEVICE_ID_ATI_215_LR	0x4c52
-#define PCI_DEVICE_ID_ATI_215_LS	0x4c53
-#define PCI_DEVICE_ID_ATI_264_LT	0x4c54
-/* Mach64 VT */
-#define PCI_DEVICE_ID_ATI_264VT		0x5654
-#define PCI_DEVICE_ID_ATI_264VU		0x5655
-#define PCI_DEVICE_ID_ATI_264VV		0x5656
-/* Rage128 GL */
-#define PCI_DEVICE_ID_ATI_RAGE128_RE	0x5245
-#define PCI_DEVICE_ID_ATI_RAGE128_RF	0x5246
-#define PCI_DEVICE_ID_ATI_RAGE128_RG	0x5247
-/* Rage128 VR */
-#define PCI_DEVICE_ID_ATI_RAGE128_RK	0x524b
-#define PCI_DEVICE_ID_ATI_RAGE128_RL	0x524c
-#define PCI_DEVICE_ID_ATI_RAGE128_SE	0x5345
-#define PCI_DEVICE_ID_ATI_RAGE128_SF	0x5346
-#define PCI_DEVICE_ID_ATI_RAGE128_SG	0x5347
-#define PCI_DEVICE_ID_ATI_RAGE128_SH	0x5348
-#define PCI_DEVICE_ID_ATI_RAGE128_SK	0x534b
-#define PCI_DEVICE_ID_ATI_RAGE128_SL	0x534c
-#define PCI_DEVICE_ID_ATI_RAGE128_SM	0x534d
-#define PCI_DEVICE_ID_ATI_RAGE128_SN	0x534e
-/* Rage128 Ultra */
-#define PCI_DEVICE_ID_ATI_RAGE128_TF	0x5446
-#define PCI_DEVICE_ID_ATI_RAGE128_TL	0x544c
-#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
-#define PCI_DEVICE_ID_ATI_RAGE128_TS	0x5453
-#define PCI_DEVICE_ID_ATI_RAGE128_TT	0x5454
-#define PCI_DEVICE_ID_ATI_RAGE128_TU	0x5455
-/* Rage128 M3 */
-#define PCI_DEVICE_ID_ATI_RAGE128_LE	0x4c45
-#define PCI_DEVICE_ID_ATI_RAGE128_LF	0x4c46
-/* Rage128 M4 */
-#define PCI_DEVICE_ID_ATI_RAGE128_MF    0x4d46
-#define PCI_DEVICE_ID_ATI_RAGE128_ML    0x4d4c
-/* Rage128 Pro GL */
-#define PCI_DEVICE_ID_ATI_RAGE128_PA	0x5041
-#define PCI_DEVICE_ID_ATI_RAGE128_PB	0x5042
-#define PCI_DEVICE_ID_ATI_RAGE128_PC	0x5043
-#define PCI_DEVICE_ID_ATI_RAGE128_PD	0x5044
-#define PCI_DEVICE_ID_ATI_RAGE128_PE	0x5045
-#define PCI_DEVICE_ID_ATI_RAGE128_PF	0x5046
-/* Rage128 Pro VR */
-#define PCI_DEVICE_ID_ATI_RAGE128_PG	0x5047
-#define PCI_DEVICE_ID_ATI_RAGE128_PH	0x5048
-#define PCI_DEVICE_ID_ATI_RAGE128_PI	0x5049
-#define PCI_DEVICE_ID_ATI_RAGE128_PJ	0x504A
-#define PCI_DEVICE_ID_ATI_RAGE128_PK	0x504B
-#define PCI_DEVICE_ID_ATI_RAGE128_PL	0x504C
-#define PCI_DEVICE_ID_ATI_RAGE128_PM	0x504D
-#define PCI_DEVICE_ID_ATI_RAGE128_PN	0x504E
-#define PCI_DEVICE_ID_ATI_RAGE128_PO	0x504F
-#define PCI_DEVICE_ID_ATI_RAGE128_PP	0x5050
-#define PCI_DEVICE_ID_ATI_RAGE128_PQ	0x5051
-#define PCI_DEVICE_ID_ATI_RAGE128_PR	0x5052
-#define PCI_DEVICE_ID_ATI_RAGE128_PS	0x5053
-#define PCI_DEVICE_ID_ATI_RAGE128_PT	0x5054
-#define PCI_DEVICE_ID_ATI_RAGE128_PU	0x5055
-#define PCI_DEVICE_ID_ATI_RAGE128_PV	0x5056
-#define PCI_DEVICE_ID_ATI_RAGE128_PW	0x5057
-#define PCI_DEVICE_ID_ATI_RAGE128_PX	0x5058
-/* Rage128 M4 */
-/* Radeon R100 */
-#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
-#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
-#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
-#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
-/* Radeon RV100 (VE) */
-#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
-#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
-/* Radeon R200 (8500) */
-#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
-#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
-#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
-#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
-#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
-/* Radeon R200 (9100) */
-#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
-/* Radeon RV200 (7500) */
-#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
-#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
-/* Radeon NV-100 */
-/* Radeon RV250 (9000) */
-#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
-#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
-#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
-#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
-/* Radeon RV280 (9200) */
-#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
-#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
-/* Radeon R300 (9500) */
-/* Radeon R300 (9700) */
-#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
-#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
-#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
-#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
-/* Radeon R350 (9800) */
-/* Radeon RV350 (9600) */
-/* Radeon M6 */
-#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
-#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
-/* Radeon M7 */
-#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
-#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
-/* Radeon M9 */
-#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
-#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
-#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
-#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
-/* Radeon */
-/* RadeonIGP */
-#define PCI_DEVICE_ID_ATI_RS100		0xcab0
-#define PCI_DEVICE_ID_ATI_RS200		0xcab2
-#define PCI_DEVICE_ID_ATI_RS200_B	0xcbb2
-#define PCI_DEVICE_ID_ATI_RS250		0xcab3
-#define PCI_DEVICE_ID_ATI_RS300_100	0x5830
-#define PCI_DEVICE_ID_ATI_RS300_133	0x5831
-#define PCI_DEVICE_ID_ATI_RS300_166	0x5832
-#define PCI_DEVICE_ID_ATI_RS300_200	0x5833
-#define PCI_DEVICE_ID_ATI_RS350_100     0x7830
-#define PCI_DEVICE_ID_ATI_RS350_133     0x7831
-#define PCI_DEVICE_ID_ATI_RS350_166     0x7832
-#define PCI_DEVICE_ID_ATI_RS350_200     0x7833
-#define PCI_DEVICE_ID_ATI_RS400_100     0x5a30
-#define PCI_DEVICE_ID_ATI_RS400_133     0x5a31
-#define PCI_DEVICE_ID_ATI_RS400_166     0x5a32
-#define PCI_DEVICE_ID_ATI_RS400_200     0x5a33
-#define PCI_DEVICE_ID_ATI_RS480         0x5950
-/* ATI IXP Chipset */
-#define PCI_DEVICE_ID_ATI_IXP200_IDE	0x4349
-#define PCI_DEVICE_ID_ATI_IXP200_SMBUS	0x4353
-#define PCI_DEVICE_ID_ATI_IXP300_SMBUS	0x4363
-#define PCI_DEVICE_ID_ATI_IXP300_IDE	0x4369
-#define PCI_DEVICE_ID_ATI_IXP300_SATA   0x436e
-#define PCI_DEVICE_ID_ATI_IXP400_SMBUS	0x4372
-#define PCI_DEVICE_ID_ATI_IXP400_IDE	0x4376
-#define PCI_DEVICE_ID_ATI_IXP400_SATA   0x4379
-#define PCI_DEVICE_ID_ATI_IXP400_SATA2	0x437a
-#define PCI_DEVICE_ID_ATI_IXP600_SATA	0x4380
-#define PCI_DEVICE_ID_ATI_SBX00_SMBUS	0x4385
-#define PCI_DEVICE_ID_ATI_IXP600_IDE	0x438c
-#define PCI_DEVICE_ID_ATI_IXP700_SATA	0x4390
-#define PCI_DEVICE_ID_ATI_IXP700_IDE	0x439c
-
-#define PCI_VENDOR_ID_VLSI		0x1004
-#define PCI_DEVICE_ID_VLSI_82C592	0x0005
-#define PCI_DEVICE_ID_VLSI_82C593	0x0006
-#define PCI_DEVICE_ID_VLSI_82C594	0x0007
-#define PCI_DEVICE_ID_VLSI_82C597	0x0009
-#define PCI_DEVICE_ID_VLSI_82C541	0x000c
-#define PCI_DEVICE_ID_VLSI_82C543	0x000d
-#define PCI_DEVICE_ID_VLSI_82C532	0x0101
-#define PCI_DEVICE_ID_VLSI_82C534	0x0102
-#define PCI_DEVICE_ID_VLSI_82C535	0x0104
-#define PCI_DEVICE_ID_VLSI_82C147	0x0105
-#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
-
-#define PCI_VENDOR_ID_ADL		0x1005
-#define PCI_DEVICE_ID_ADL_2301		0x2301
-
-#define PCI_VENDOR_ID_NS		0x100b
-#define PCI_DEVICE_ID_NS_87415		0x0002
-#define PCI_DEVICE_ID_NS_87560_LIO	0x000e
-#define PCI_DEVICE_ID_NS_87560_USB	0x0012
-#define PCI_DEVICE_ID_NS_83815		0x0020
-#define PCI_DEVICE_ID_NS_83820		0x0022
-#define PCI_DEVICE_ID_NS_CS5535_ISA	0x002b
-#define PCI_DEVICE_ID_NS_CS5535_IDE	0x002d
-#define PCI_DEVICE_ID_NS_CS5535_AUDIO	0x002e
-#define PCI_DEVICE_ID_NS_CS5535_USB	0x002f
-#define PCI_DEVICE_ID_NS_GX_VIDEO	0x0030
-#define PCI_DEVICE_ID_NS_SATURN		0x0035
-#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
-#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
-#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
-#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
-#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
-#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
-#define PCI_DEVICE_ID_NS_SC1100_BRIDGE	0x0510
-#define PCI_DEVICE_ID_NS_SC1100_SMI	0x0511
-#define PCI_DEVICE_ID_NS_SC1100_XBUS	0x0515
-#define PCI_DEVICE_ID_NS_87410		0xd001
-
-#define PCI_DEVICE_ID_NS_GX_HOST_BRIDGE  0x0028
-
-#define PCI_VENDOR_ID_TSENG		0x100c
-#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
-#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
-#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
-#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
-#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
-
-#define PCI_VENDOR_ID_WEITEK		0x100e
-#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
-#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
-
-#define PCI_VENDOR_ID_DEC		0x1011
-#define PCI_DEVICE_ID_DEC_BRD		0x0001
-#define PCI_DEVICE_ID_DEC_TULIP		0x0002
-#define PCI_DEVICE_ID_DEC_TGA		0x0004
-#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
-#define PCI_DEVICE_ID_DEC_TGA2		0x000D
-#define PCI_DEVICE_ID_DEC_FDDI		0x000F
-#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
-#define PCI_DEVICE_ID_DEC_21142		0x0019
-#define PCI_DEVICE_ID_DEC_21052		0x0021
-#define PCI_DEVICE_ID_DEC_21150		0x0022
-#define PCI_DEVICE_ID_DEC_21152		0x0024
-#define PCI_DEVICE_ID_DEC_21153		0x0025
-#define PCI_DEVICE_ID_DEC_21154		0x0026
-#define PCI_DEVICE_ID_DEC_21285		0x1065
-#define PCI_DEVICE_ID_COMPAQ_42XX	0x0046
-
-#define PCI_VENDOR_ID_CIRRUS		0x1013
-#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
-#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
-#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
-#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
-#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
-#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
-#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
-#define PCI_DEVICE_ID_CIRRUS_5462	0x00d0
-#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
-#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
-#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
-#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
-#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
-#define PCI_DEVICE_ID_CIRRUS_4610	0x6001
-#define PCI_DEVICE_ID_CIRRUS_4612	0x6003
-#define PCI_DEVICE_ID_CIRRUS_4615	0x6004
-
-#define PCI_VENDOR_ID_IBM		0x1014
-#define PCI_DEVICE_ID_IBM_TR		0x0018
-#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
-#define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
-#define PCI_DEVICE_ID_IBM_SNIPE		0x0180
-#define PCI_DEVICE_ID_IBM_CITRINE		0x028C
-#define PCI_DEVICE_ID_IBM_GEMSTONE		0xB166
-#define PCI_DEVICE_ID_IBM_OBSIDIAN		0x02BD
-#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1	0x0031
-#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2	0x0219
-#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX		0x021A
-#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM	0x0251
-#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
-#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL	0x252
-
-#define PCI_VENDOR_ID_UNISYS		0x1018
-#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C
-
-#define PCI_VENDOR_ID_COMPEX2		0x101a /* pci.ids says "AT&T GIS (NCR)" */
-#define PCI_DEVICE_ID_COMPEX2_100VG	0x0005
-
-#define PCI_VENDOR_ID_WD		0x101c
-#define PCI_DEVICE_ID_WD_90C		0xc24a
-
-#define PCI_VENDOR_ID_AMI		0x101e
-#define PCI_DEVICE_ID_AMI_MEGARAID3	0x1960
-#define PCI_DEVICE_ID_AMI_MEGARAID	0x9010
-#define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
-
-#define PCI_VENDOR_ID_AMD		0x1022
-#define PCI_DEVICE_ID_AMD_K8_NB		0x1100
-#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP	0x1101
-#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL	0x1102
-#define PCI_DEVICE_ID_AMD_K8_NB_MISC	0x1103
-#define PCI_DEVICE_ID_AMD_10H_NB_HT	0x1200
-#define PCI_DEVICE_ID_AMD_10H_NB_MAP	0x1201
-#define PCI_DEVICE_ID_AMD_10H_NB_DRAM	0x1202
-#define PCI_DEVICE_ID_AMD_10H_NB_MISC	0x1203
-#define PCI_DEVICE_ID_AMD_10H_NB_LINK	0x1204
-#define PCI_DEVICE_ID_AMD_11H_NB_HT	0x1300
-#define PCI_DEVICE_ID_AMD_11H_NB_MAP	0x1301
-#define PCI_DEVICE_ID_AMD_11H_NB_DRAM	0x1302
-#define PCI_DEVICE_ID_AMD_11H_NB_MISC	0x1303
-#define PCI_DEVICE_ID_AMD_11H_NB_LINK	0x1304
-#define PCI_DEVICE_ID_AMD_LANCE		0x2000
-#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
-#define PCI_DEVICE_ID_AMD_SCSI		0x2020
-#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
-#define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
-#define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
-#define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
-#define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
-#define PCI_DEVICE_ID_AMD_COBRA_7401	0x7401
-#define PCI_DEVICE_ID_AMD_VIPER_7409	0x7409
-#define PCI_DEVICE_ID_AMD_VIPER_740B	0x740B
-#define PCI_DEVICE_ID_AMD_VIPER_7410	0x7410
-#define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
-#define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
-#define PCI_DEVICE_ID_AMD_VIPER_7440	0x7440
-#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
-#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
-#define PCI_DEVICE_ID_AMD_VIPER_7443	0x7443
-#define PCI_DEVICE_ID_AMD_OPUS_7445	0x7445
-#define PCI_DEVICE_ID_AMD_8111_LPC	0x7468
-#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
-#define PCI_DEVICE_ID_AMD_8111_SMBUS2	0x746a
-#define PCI_DEVICE_ID_AMD_8111_SMBUS	0x746b
-#define PCI_DEVICE_ID_AMD_8111_AUDIO	0x746d
-#define PCI_DEVICE_ID_AMD_8151_0	0x7454
-#define PCI_DEVICE_ID_AMD_8131_BRIDGE	0x7450
-#define PCI_DEVICE_ID_AMD_8131_APIC	0x7451
-#define PCI_DEVICE_ID_AMD_8132_BRIDGE	0x7458
-#define PCI_DEVICE_ID_AMD_CS5536_ISA    0x2090
-#define PCI_DEVICE_ID_AMD_CS5536_FLASH  0x2091
-#define PCI_DEVICE_ID_AMD_CS5536_AUDIO  0x2093
-#define PCI_DEVICE_ID_AMD_CS5536_OHC    0x2094
-#define PCI_DEVICE_ID_AMD_CS5536_EHC    0x2095
-#define PCI_DEVICE_ID_AMD_CS5536_UDC    0x2096
-#define PCI_DEVICE_ID_AMD_CS5536_UOC    0x2097
-#define PCI_DEVICE_ID_AMD_CS5536_IDE    0x209A
-
-#define PCI_DEVICE_ID_AMD_LX_VIDEO  0x2081
-#define PCI_DEVICE_ID_AMD_LX_AES    0x2082
-
-#define PCI_VENDOR_ID_TRIDENT		0x1023
-#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
-#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
-#define PCI_DEVICE_ID_TRIDENT_9320	0x9320
-#define PCI_DEVICE_ID_TRIDENT_9388	0x9388
-#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
-#define PCI_DEVICE_ID_TRIDENT_939A	0x939A
-#define PCI_DEVICE_ID_TRIDENT_9520	0x9520
-#define PCI_DEVICE_ID_TRIDENT_9525	0x9525
-#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
-#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
-#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
-#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
-#define PCI_DEVICE_ID_TRIDENT_9850	0x9850
-#define PCI_DEVICE_ID_TRIDENT_9880	0x9880
-#define PCI_DEVICE_ID_TRIDENT_8400	0x8400
-#define PCI_DEVICE_ID_TRIDENT_8420	0x8420
-#define PCI_DEVICE_ID_TRIDENT_8500	0x8500
-
-#define PCI_VENDOR_ID_AI		0x1025
-#define PCI_DEVICE_ID_AI_M1435		0x1435
-
-#define PCI_VENDOR_ID_DELL		0x1028
-#define PCI_DEVICE_ID_DELL_RACIII	0x0008
-#define PCI_DEVICE_ID_DELL_RAC4		0x0012
-#define PCI_DEVICE_ID_DELL_PERC5	0x0015
-
-#define PCI_VENDOR_ID_MATROX		0x102B
-#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
-#define PCI_DEVICE_ID_MATROX_MIL	0x0519
-#define PCI_DEVICE_ID_MATROX_MYS	0x051A
-#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
-#define PCI_DEVICE_ID_MATROX_MYS_AGP	0x051e
-#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
-#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
-#define PCI_DEVICE_ID_MATROX_G100_MM	0x1000
-#define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
-#define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
-#define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
-#define	PCI_DEVICE_ID_MATROX_G400	0x0525
-#define	PCI_DEVICE_ID_MATROX_G200EV_PCI	0x0530
-#define PCI_DEVICE_ID_MATROX_G550	0x2527
-#define PCI_DEVICE_ID_MATROX_VIA	0x4536
-
-#define PCI_VENDOR_ID_CT		0x102c
-#define PCI_DEVICE_ID_CT_69000		0x00c0
-#define PCI_DEVICE_ID_CT_65545		0x00d8
-#define PCI_DEVICE_ID_CT_65548		0x00dc
-#define PCI_DEVICE_ID_CT_65550		0x00e0
-#define PCI_DEVICE_ID_CT_65554		0x00e4
-#define PCI_DEVICE_ID_CT_65555		0x00e5
-
-#define PCI_VENDOR_ID_MIRO		0x1031
-#define PCI_DEVICE_ID_MIRO_36050	0x5601
-#define PCI_DEVICE_ID_MIRO_DC10PLUS	0x7efe
-#define PCI_DEVICE_ID_MIRO_DC30PLUS	0xd801
-
-#define PCI_VENDOR_ID_NEC		0x1033
-#define PCI_DEVICE_ID_NEC_CBUS_1	0x0001 /* PCI-Cbus Bridge */
-#define PCI_DEVICE_ID_NEC_LOCAL		0x0002 /* Local Bridge */
-#define PCI_DEVICE_ID_NEC_ATM		0x0003 /* ATM LAN Controller */
-#define PCI_DEVICE_ID_NEC_R4000		0x0004 /* R4000 Bridge */
-#define PCI_DEVICE_ID_NEC_486		0x0005 /* 486 Like Peripheral Bus Bridge */
-#define PCI_DEVICE_ID_NEC_ACCEL_1	0x0006 /* Graphic Accelerator */
-#define PCI_DEVICE_ID_NEC_UXBUS		0x0007 /* UX-Bus Bridge */
-#define PCI_DEVICE_ID_NEC_ACCEL_2	0x0008 /* Graphic Accelerator */
-#define PCI_DEVICE_ID_NEC_GRAPH		0x0009 /* PCI-CoreGraph Bridge */
-#define PCI_DEVICE_ID_NEC_VL		0x0016 /* PCI-VL Bridge */
-#define PCI_DEVICE_ID_NEC_STARALPHA2	0x002c /* STAR ALPHA2 */
-#define PCI_DEVICE_ID_NEC_CBUS_2	0x002d /* PCI-Cbus Bridge */
-#define PCI_DEVICE_ID_NEC_USB		0x0035 /* PCI-USB Host */
-#define PCI_DEVICE_ID_NEC_CBUS_3	0x003b
-#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
-#define PCI_DEVICE_ID_NEC_PCX2		0x0046 /* PowerVR */
-#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
-#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
-#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
-#define PCI_DEVICE_ID_NEC_PC9821CS01    0x800c /* PC-9821-CS01 */
-#define PCI_DEVICE_ID_NEC_PC9821NRB06   0x800d /* PC-9821NR-B06 */
-
-#define PCI_VENDOR_ID_FD		0x1036
-#define PCI_DEVICE_ID_FD_36C70		0x0000
-
-#define PCI_VENDOR_ID_SI		0x1039
-#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
-#define PCI_DEVICE_ID_SI_6202		0x0002
-#define PCI_DEVICE_ID_SI_503		0x0008
-#define PCI_DEVICE_ID_SI_ACPI		0x0009
-#define PCI_DEVICE_ID_SI_SMBUS		0x0016
-#define PCI_DEVICE_ID_SI_LPC		0x0018
-#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
-#define PCI_DEVICE_ID_SI_6205		0x0205
-#define PCI_DEVICE_ID_SI_501		0x0406
-#define PCI_DEVICE_ID_SI_496		0x0496
-#define PCI_DEVICE_ID_SI_300		0x0300
-#define PCI_DEVICE_ID_SI_315H		0x0310
-#define PCI_DEVICE_ID_SI_315		0x0315
-#define PCI_DEVICE_ID_SI_315PRO		0x0325
-#define PCI_DEVICE_ID_SI_530		0x0530
-#define PCI_DEVICE_ID_SI_540		0x0540
-#define PCI_DEVICE_ID_SI_550		0x0550
-#define PCI_DEVICE_ID_SI_540_VGA	0x5300
-#define PCI_DEVICE_ID_SI_550_VGA	0x5315
-#define PCI_DEVICE_ID_SI_620		0x0620
-#define PCI_DEVICE_ID_SI_630		0x0630
-#define PCI_DEVICE_ID_SI_633		0x0633
-#define PCI_DEVICE_ID_SI_635		0x0635
-#define PCI_DEVICE_ID_SI_640		0x0640
-#define PCI_DEVICE_ID_SI_645		0x0645
-#define PCI_DEVICE_ID_SI_646		0x0646
-#define PCI_DEVICE_ID_SI_648		0x0648
-#define PCI_DEVICE_ID_SI_650		0x0650
-#define PCI_DEVICE_ID_SI_651		0x0651
-#define PCI_DEVICE_ID_SI_655		0x0655
-#define PCI_DEVICE_ID_SI_661		0x0661
-#define PCI_DEVICE_ID_SI_730		0x0730
-#define PCI_DEVICE_ID_SI_733		0x0733
-#define PCI_DEVICE_ID_SI_630_VGA	0x6300
-#define PCI_DEVICE_ID_SI_735		0x0735
-#define PCI_DEVICE_ID_SI_740		0x0740
-#define PCI_DEVICE_ID_SI_741		0x0741
-#define PCI_DEVICE_ID_SI_745		0x0745
-#define PCI_DEVICE_ID_SI_746		0x0746
-#define PCI_DEVICE_ID_SI_755		0x0755
-#define PCI_DEVICE_ID_SI_760		0x0760
-#define PCI_DEVICE_ID_SI_900		0x0900
-#define PCI_DEVICE_ID_SI_961		0x0961
-#define PCI_DEVICE_ID_SI_962		0x0962
-#define PCI_DEVICE_ID_SI_963		0x0963
-#define PCI_DEVICE_ID_SI_965		0x0965
-#define PCI_DEVICE_ID_SI_966		0x0966
-#define PCI_DEVICE_ID_SI_968		0x0968
-#define PCI_DEVICE_ID_SI_1180		0x1180
-#define PCI_DEVICE_ID_SI_5511		0x5511
-#define PCI_DEVICE_ID_SI_5513		0x5513
-#define PCI_DEVICE_ID_SI_5517		0x5517
-#define PCI_DEVICE_ID_SI_5518		0x5518
-#define PCI_DEVICE_ID_SI_5571		0x5571
-#define PCI_DEVICE_ID_SI_5581		0x5581
-#define PCI_DEVICE_ID_SI_5582		0x5582
-#define PCI_DEVICE_ID_SI_5591		0x5591
-#define PCI_DEVICE_ID_SI_5596		0x5596
-#define PCI_DEVICE_ID_SI_5597		0x5597
-#define PCI_DEVICE_ID_SI_5598		0x5598
-#define PCI_DEVICE_ID_SI_5600		0x5600
-#define PCI_DEVICE_ID_SI_7012		0x7012
-#define PCI_DEVICE_ID_SI_7013		0x7013
-#define PCI_DEVICE_ID_SI_7016		0x7016
-#define PCI_DEVICE_ID_SI_7018		0x7018
-
-#define PCI_VENDOR_ID_HP		0x103c
-#define PCI_DEVICE_ID_HP_VISUALIZE_EG	0x1005
-#define PCI_DEVICE_ID_HP_VISUALIZE_FX6	0x1006
-#define PCI_DEVICE_ID_HP_VISUALIZE_FX4	0x1008
-#define PCI_DEVICE_ID_HP_VISUALIZE_FX2	0x100a
-#define PCI_DEVICE_ID_HP_TACHYON	0x1028
-#define PCI_DEVICE_ID_HP_TACHLITE	0x1029
-#define PCI_DEVICE_ID_HP_J2585A		0x1030
-#define PCI_DEVICE_ID_HP_J2585B		0x1031
-#define PCI_DEVICE_ID_HP_J2973A		0x1040
-#define PCI_DEVICE_ID_HP_J2970A		0x1042
-#define PCI_DEVICE_ID_HP_DIVA		0x1048
-#define PCI_DEVICE_ID_HP_DIVA_TOSCA1	0x1049
-#define PCI_DEVICE_ID_HP_DIVA_TOSCA2	0x104A
-#define PCI_DEVICE_ID_HP_DIVA_MAESTRO	0x104B
-#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
-#define PCI_DEVICE_ID_HP_VISUALIZE_FXE	0x108b
-#define PCI_DEVICE_ID_HP_DIVA_HALFDOME	0x1223
-#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE	0x1226
-#define PCI_DEVICE_ID_HP_DIVA_POWERBAR	0x1227
-#define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
-#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
-#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
-#define PCI_DEVICE_ID_HP_DIVA_EVEREST	0x1282
-#define PCI_DEVICE_ID_HP_DIVA_AUX	0x1290
-#define PCI_DEVICE_ID_HP_DIVA_RMP3	0x1301
-#define PCI_DEVICE_ID_HP_DIVA_HURRICANE	0x132a
-#define PCI_DEVICE_ID_HP_CISSA		0x3220
-#define PCI_DEVICE_ID_HP_CISSC		0x3230
-#define PCI_DEVICE_ID_HP_CISSD		0x3238
-#define PCI_DEVICE_ID_HP_CISSE		0x323a
-#define PCI_DEVICE_ID_HP_ZX2_IOC	0x4031
-
-#define PCI_VENDOR_ID_PCTECH		0x1042
-#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
-#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
-
-#define PCI_VENDOR_ID_ASUSTEK		0x1043
-#define PCI_DEVICE_ID_ASUSTEK_0675	0x0675
-
-#define PCI_VENDOR_ID_DPT		0x1044
-#define PCI_DEVICE_ID_DPT		0xa400
-
-#define PCI_VENDOR_ID_OPTI		0x1045
-#define PCI_DEVICE_ID_OPTI_82C558	0xc558
-#define PCI_DEVICE_ID_OPTI_82C621	0xc621
-#define PCI_DEVICE_ID_OPTI_82C700	0xc700
-#define PCI_DEVICE_ID_OPTI_82C825	0xd568
-
-#define PCI_VENDOR_ID_ELSA		0x1048
-#define PCI_DEVICE_ID_ELSA_MICROLINK	0x1000
-#define PCI_DEVICE_ID_ELSA_QS3000	0x3000
-
-#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
-#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
-
-#define PCI_VENDOR_ID_TI		0x104c
-#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
-#define PCI_DEVICE_ID_TI_4450		0x8011
-#define PCI_DEVICE_ID_TI_TSB43AB22	0x8023
-#define PCI_DEVICE_ID_TI_XX21_XX11	0x8031
-#define PCI_DEVICE_ID_TI_XX21_XX11_FM	0x8033
-#define PCI_DEVICE_ID_TI_XX21_XX11_SD	0x8034
-#define PCI_DEVICE_ID_TI_X515		0x8036
-#define PCI_DEVICE_ID_TI_XX12		0x8039
-#define PCI_DEVICE_ID_TI_XX12_FM	0x803b
-#define PCI_DEVICE_ID_TI_1130		0xac12
-#define PCI_DEVICE_ID_TI_1031		0xac13
-#define PCI_DEVICE_ID_TI_1131		0xac15
-#define PCI_DEVICE_ID_TI_1250		0xac16
-#define PCI_DEVICE_ID_TI_1220		0xac17
-#define PCI_DEVICE_ID_TI_1221		0xac19
-#define PCI_DEVICE_ID_TI_1210		0xac1a
-#define PCI_DEVICE_ID_TI_1450		0xac1b
-#define PCI_DEVICE_ID_TI_1225		0xac1c
-#define PCI_DEVICE_ID_TI_1251A		0xac1d
-#define PCI_DEVICE_ID_TI_1211		0xac1e
-#define PCI_DEVICE_ID_TI_1251B		0xac1f
-#define PCI_DEVICE_ID_TI_4410		0xac41
-#define PCI_DEVICE_ID_TI_4451		0xac42
-#define PCI_DEVICE_ID_TI_4510		0xac44
-#define PCI_DEVICE_ID_TI_4520		0xac46
-#define PCI_DEVICE_ID_TI_7510		0xac47
-#define PCI_DEVICE_ID_TI_7610		0xac48
-#define PCI_DEVICE_ID_TI_7410		0xac49
-#define PCI_DEVICE_ID_TI_1410		0xac50
-#define PCI_DEVICE_ID_TI_1420		0xac51
-#define PCI_DEVICE_ID_TI_1451A		0xac52
-#define PCI_DEVICE_ID_TI_1620		0xac54
-#define PCI_DEVICE_ID_TI_1520		0xac55
-#define PCI_DEVICE_ID_TI_1510		0xac56
-#define PCI_DEVICE_ID_TI_X620		0xac8d
-#define PCI_DEVICE_ID_TI_X420		0xac8e
-#define PCI_DEVICE_ID_TI_XX20_FM	0xac8f
-
-#define PCI_VENDOR_ID_SONY		0x104d
-
-/* Winbond have two vendor IDs! See 0x10ad as well */
-#define PCI_VENDOR_ID_WINBOND2		0x1050
-#define PCI_DEVICE_ID_WINBOND2_89C940F	0x5a5a
-#define PCI_DEVICE_ID_WINBOND2_6692	0x6692
-
-#define PCI_VENDOR_ID_ANIGMA		0x1051
-#define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
-  
-#define PCI_VENDOR_ID_EFAR		0x1055
-#define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
-#define PCI_DEVICE_ID_EFAR_SLC90E66_3	0x9463
-
-#define PCI_VENDOR_ID_MOTOROLA		0x1057
-#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
-#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
-#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
-#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
-#define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
-#define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
-#define PCI_DEVICE_ID_MOTOROLA_HARRIER	0x480b
-#define PCI_DEVICE_ID_MOTOROLA_MPC5200	0x5803
-#define PCI_DEVICE_ID_MOTOROLA_MPC5200B	0x5809
-
-#define PCI_VENDOR_ID_PROMISE		0x105a
-#define PCI_DEVICE_ID_PROMISE_20265	0x0d30
-#define PCI_DEVICE_ID_PROMISE_20267	0x4d30
-#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
-#define PCI_DEVICE_ID_PROMISE_20262	0x4d38
-#define PCI_DEVICE_ID_PROMISE_20263	0x0D38
-#define PCI_DEVICE_ID_PROMISE_20268	0x4d68
-#define PCI_DEVICE_ID_PROMISE_20269	0x4d69
-#define PCI_DEVICE_ID_PROMISE_20270	0x6268
-#define PCI_DEVICE_ID_PROMISE_20271	0x6269
-#define PCI_DEVICE_ID_PROMISE_20275	0x1275
-#define PCI_DEVICE_ID_PROMISE_20276	0x5275
-#define PCI_DEVICE_ID_PROMISE_20277	0x7275
-
-#define PCI_VENDOR_ID_UMC		0x1060
-#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
-#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
-#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
-
-#define PCI_VENDOR_ID_PICOPOWER		0x1066
-#define PCI_DEVICE_ID_PICOPOWER_PT86C523	0x0002
-#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP	0x8002
-
-#define PCI_VENDOR_ID_MYLEX		0x1069
-#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
-#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
-#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
-#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
-#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
-#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
-#define PCI_DEVICE_ID_MYLEX_DAC960_GEM	0xB166
-
-#define PCI_VENDOR_ID_APPLE		0x106b
-#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
-#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
-#define PCI_DEVICE_ID_APPLE_UNI_N_FW	0x0018
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
-#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
-#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP	0x0024
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
-#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15	0x002e
-#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2	0x0032
-#define PCI_DEVICE_ID_APPLE_UNI_N_ATA	0x0033
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2	0x0034
-#define PCI_DEVICE_ID_APPLE_IPID_ATA100	0x003b
-#define PCI_DEVICE_ID_APPLE_K2_ATA100	0x0043
-#define PCI_DEVICE_ID_APPLE_U3_AGP	0x004b
-#define PCI_DEVICE_ID_APPLE_K2_GMAC	0x004c
-#define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
-#define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
-#define PCI_DEVICE_ID_APPLE_U3L_AGP	0x0058
-#define PCI_DEVICE_ID_APPLE_U3H_AGP	0x0059
-#define PCI_DEVICE_ID_APPLE_IPID2_AGP	0x0066
-#define PCI_DEVICE_ID_APPLE_IPID2_ATA	0x0069
-#define PCI_DEVICE_ID_APPLE_IPID2_FW	0x006a
-#define PCI_DEVICE_ID_APPLE_IPID2_GMAC	0x006b
-#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
-
-#define PCI_VENDOR_ID_YAMAHA		0x1073
-#define PCI_DEVICE_ID_YAMAHA_724	0x0004
-#define PCI_DEVICE_ID_YAMAHA_724F	0x000d
-#define PCI_DEVICE_ID_YAMAHA_740	0x000a
-#define PCI_DEVICE_ID_YAMAHA_740C	0x000c
-#define PCI_DEVICE_ID_YAMAHA_744	0x0010
-#define PCI_DEVICE_ID_YAMAHA_754	0x0012
-
-#define PCI_VENDOR_ID_QLOGIC		0x1077
-#define PCI_DEVICE_ID_QLOGIC_ISP10160	0x1016
-#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
-#define PCI_DEVICE_ID_QLOGIC_ISP1080	0x1080
-#define PCI_DEVICE_ID_QLOGIC_ISP12160	0x1216
-#define PCI_DEVICE_ID_QLOGIC_ISP1240	0x1240
-#define PCI_DEVICE_ID_QLOGIC_ISP1280	0x1280
-#define PCI_DEVICE_ID_QLOGIC_ISP2100	0x2100
-#define PCI_DEVICE_ID_QLOGIC_ISP2200	0x2200
-#define PCI_DEVICE_ID_QLOGIC_ISP2300	0x2300
-#define PCI_DEVICE_ID_QLOGIC_ISP2312	0x2312
-#define PCI_DEVICE_ID_QLOGIC_ISP2322	0x2322
-#define PCI_DEVICE_ID_QLOGIC_ISP6312	0x6312
-#define PCI_DEVICE_ID_QLOGIC_ISP6322	0x6322
-#define PCI_DEVICE_ID_QLOGIC_ISP2422	0x2422
-#define PCI_DEVICE_ID_QLOGIC_ISP2432	0x2432
-#define PCI_DEVICE_ID_QLOGIC_ISP2512	0x2512
-#define PCI_DEVICE_ID_QLOGIC_ISP2522	0x2522
-#define PCI_DEVICE_ID_QLOGIC_ISP5422	0x5422
-#define PCI_DEVICE_ID_QLOGIC_ISP5432	0x5432
-
-#define PCI_VENDOR_ID_CYRIX		0x1078
-#define PCI_DEVICE_ID_CYRIX_5510	0x0000
-#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
-#define PCI_DEVICE_ID_CYRIX_5520	0x0002
-#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
-#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
-#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
-#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
-
-#define PCI_VENDOR_ID_CONTAQ		0x1080
-#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
-
-#define PCI_VENDOR_ID_OLICOM		0x108d
-#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
-#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
-#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
-
-#define PCI_VENDOR_ID_SUN		0x108e
-#define PCI_DEVICE_ID_SUN_EBUS		0x1000
-#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
-#define PCI_DEVICE_ID_SUN_RIO_EBUS	0x1100
-#define PCI_DEVICE_ID_SUN_RIO_GEM	0x1101
-#define PCI_DEVICE_ID_SUN_RIO_1394	0x1102
-#define PCI_DEVICE_ID_SUN_RIO_USB	0x1103
-#define PCI_DEVICE_ID_SUN_GEM		0x2bad
-#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
-#define PCI_DEVICE_ID_SUN_PBM		0x8000
-#define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
-#define PCI_DEVICE_ID_SUN_SABRE		0xa000
-#define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
-#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
-#define PCI_DEVICE_ID_SUN_CASSINI	0xabba
-
-#define PCI_VENDOR_ID_CMD		0x1095
-#define PCI_DEVICE_ID_CMD_643		0x0643
-#define PCI_DEVICE_ID_CMD_646		0x0646
-#define PCI_DEVICE_ID_CMD_648		0x0648
-#define PCI_DEVICE_ID_CMD_649		0x0649
-
-#define PCI_DEVICE_ID_SII_680		0x0680
-#define PCI_DEVICE_ID_SII_3112		0x3112
-#define PCI_DEVICE_ID_SII_1210SA	0x0240
-
-#define PCI_VENDOR_ID_BROOKTREE		0x109e
-#define PCI_DEVICE_ID_BROOKTREE_878	0x0878
-#define PCI_DEVICE_ID_BROOKTREE_879	0x0879
-
-#define PCI_VENDOR_ID_SGI		0x10a9
-#define PCI_DEVICE_ID_SGI_IOC3		0x0003
-#define PCI_DEVICE_ID_SGI_LITHIUM	0x1002
-#define PCI_DEVICE_ID_SGI_IOC4		0x100a
-
-#define PCI_VENDOR_ID_WINBOND		0x10ad
-#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
-#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
-
-#define PCI_VENDOR_ID_PLX		0x10b5
-#define PCI_DEVICE_ID_PLX_R685		0x1030
-#define PCI_DEVICE_ID_PLX_ROMULUS	0x106a
-#define PCI_DEVICE_ID_PLX_SPCOM800	0x1076
-#define PCI_DEVICE_ID_PLX_1077		0x1077
-#define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
-#define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
-#define PCI_DEVICE_ID_PLX_R753		0x1152
-#define PCI_DEVICE_ID_PLX_OLITEC	0x1187
-#define PCI_DEVICE_ID_PLX_PCI200SYN	0x3196
-#define PCI_DEVICE_ID_PLX_9030          0x9030
-#define PCI_DEVICE_ID_PLX_9050		0x9050
-#define PCI_DEVICE_ID_PLX_9080		0x9080
-#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2	0xa001
-
-#define PCI_VENDOR_ID_MADGE		0x10b6
-#define PCI_DEVICE_ID_MADGE_MK2		0x0002
-
-#define PCI_VENDOR_ID_3COM		0x10b7
-#define PCI_DEVICE_ID_3COM_3C985	0x0001
-#define PCI_DEVICE_ID_3COM_3C940	0x1700
-#define PCI_DEVICE_ID_3COM_3C339	0x3390
-#define PCI_DEVICE_ID_3COM_3C359	0x3590
-#define PCI_DEVICE_ID_3COM_3C940B	0x80eb
-#define PCI_DEVICE_ID_3COM_3CR990	0x9900
-#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
-#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
-#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
-#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
-#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
-#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
-#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
-
-#define PCI_VENDOR_ID_AL		0x10b9
-#define PCI_DEVICE_ID_AL_M1533		0x1533
-#define PCI_DEVICE_ID_AL_M1535 		0x1535
-#define PCI_DEVICE_ID_AL_M1541		0x1541
-#define PCI_DEVICE_ID_AL_M1563		0x1563
-#define PCI_DEVICE_ID_AL_M1621		0x1621
-#define PCI_DEVICE_ID_AL_M1631		0x1631
-#define PCI_DEVICE_ID_AL_M1632		0x1632
-#define PCI_DEVICE_ID_AL_M1641		0x1641
-#define PCI_DEVICE_ID_AL_M1644		0x1644
-#define PCI_DEVICE_ID_AL_M1647		0x1647
-#define PCI_DEVICE_ID_AL_M1651		0x1651
-#define PCI_DEVICE_ID_AL_M1671		0x1671
-#define PCI_DEVICE_ID_AL_M1681		0x1681
-#define PCI_DEVICE_ID_AL_M1683		0x1683
-#define PCI_DEVICE_ID_AL_M1689		0x1689
-#define PCI_DEVICE_ID_AL_M5219		0x5219
-#define PCI_DEVICE_ID_AL_M5228		0x5228
-#define PCI_DEVICE_ID_AL_M5229		0x5229
-#define PCI_DEVICE_ID_AL_M5451		0x5451
-#define PCI_DEVICE_ID_AL_M7101		0x7101
-
-#define PCI_VENDOR_ID_NEOMAGIC		0x10c8
-#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
-#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
-#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
-
-#define PCI_VENDOR_ID_TCONRAD		0x10da
-#define PCI_DEVICE_ID_TCONRAD_TOKENRING	0x0508
-
-#define PCI_VENDOR_ID_NVIDIA			0x10de
-#define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
-#define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
-#define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
-#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN        0x002a
-#define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
-#define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS	0x0034
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE	0x0035
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA	0x0036
-#define PCI_DEVICE_ID_NVIDIA_NVENET_10		0x0037
-#define PCI_DEVICE_ID_NVIDIA_NVENET_11		0x0038
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2	0x003e
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE    0x0042
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT    0x0045
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000     0x004E
-#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS	0x0052
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE	0x0053
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA	0x0054
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2	0x0055
-#define PCI_DEVICE_ID_NVIDIA_NVENET_8		0x0056
-#define PCI_DEVICE_ID_NVIDIA_NVENET_9		0x0057
-#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO	0x0059
-#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE		0x005d
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS	0x0064
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
-#define PCI_DEVICE_ID_NVIDIA_NVENET_2		0x0066
-#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM		0x0069
-#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO		0x006a
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS	0x0084
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
-#define PCI_DEVICE_ID_NVIDIA_NVENET_4		0x0086
-#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM	0x0089
-#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO		0x008a
-#define PCI_DEVICE_ID_NVIDIA_NVENET_5		0x008c
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT   0x0090
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX	0x0091
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800   0x0098
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099
-#define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
-#define PCI_DEVICE_ID_GEFORCE_6800A             0x00c1
-#define PCI_DEVICE_ID_GEFORCE_6800A_LE          0x00c2
-#define PCI_DEVICE_ID_GEFORCE_GO_6800           0x00c8
-#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA     0x00c9
-#define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
-#define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS	0x00d4
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
-#define PCI_DEVICE_ID_NVIDIA_NVENET_3		0x00d6
-#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM		0x00d9
-#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
-#define PCI_DEVICE_ID_NVIDIA_NVENET_7		0x00df
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS	0x00e4
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
-#define PCI_DEVICE_ID_NVIDIA_NVENET_6		0x00e6
-#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO		0x00ea
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
-#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0
-#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1
-#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2
-#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3
-#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT   0x00f9
-#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280	0x00fd
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
-#define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX	0x0110
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2	0x0111
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO	0x0112
-#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR	0x0113
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT	0x0140
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600	0x0141
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL	0x0145
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540	0x014E
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200	0x014F
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS	0x0150
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2	0x0151
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
-#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200    0x0164
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250    0x0166
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1  0x0167
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1  0x0168
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460	0x0170
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440	0x0171
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420	0x0172
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE	0x0173
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO	0x0174
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO	0x0175
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO    0x0177
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL	0x0178
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200	0x017A
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL	0x017B
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL	0x017C
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000   0x0185
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO    0x0186
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO    0x0187
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL    0x0188
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC    0x0189
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS    0x018A
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL    0x018B
-#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
-#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
-#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO		0x01b1
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS	0x01b4
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
-#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM		0x01c1
-#define PCI_DEVICE_ID_NVIDIA_NVENET_1		0x01c3
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B      0x0211
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE   0x0212
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT   0x0215
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600	0x0250
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400	0x0251
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200	0x0253
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL	0x0258
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL	0x0259
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL	0x025B
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS	0x0264
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE	0x0265
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA	0x0266
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2	0x0267
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS	0x0368
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE	0x036E
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA	0x037E
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2	0x037F
-#define PCI_DEVICE_ID_NVIDIA_NVENET_12		0x0268
-#define PCI_DEVICE_ID_NVIDIA_NVENET_13		0x0269
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800	0x0280
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO       0x0286
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL        0x0288
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL        0x0289
-#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL       0x028C
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA  0x0301
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800        0x0302
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000         0x0308
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000         0x0309
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA  0x0311
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600        0x0312
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE      0x0314
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600      0x031A
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650      0x031B
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700        0x031C
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200        0x0320
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA  0x0321
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1      0x0322
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE      0x0323
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200      0x0324
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250      0x0325
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500        0x0326
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100        0x0327
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32   0x0328
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200	    0x0329
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI     0x032A
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500          0x032B
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300      0x032C
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100      0x032D
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA  0x0330
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900        0x0331
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT      0x0332
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA  0x0333
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT      0x0334
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000         0x0338
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700          0x033F
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA  0x0341
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700        0x0342
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE      0x0343
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE      0x0344
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1    0x0347
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
-#define PCI_DEVICE_ID_NVIDIA_NVENET_14              0x0372
-#define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
-#define PCI_DEVICE_ID_NVIDIA_NVENET_16              0x03E5
-#define PCI_DEVICE_ID_NVIDIA_NVENET_17              0x03E6
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA      0x03E7
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS	    0x03EB
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE       0x03EC
-#define PCI_DEVICE_ID_NVIDIA_NVENET_18              0x03EE
-#define PCI_DEVICE_ID_NVIDIA_NVENET_19              0x03EF
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2     0x03F6
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3     0x03F7
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS	    0x0446
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE	    0x0448
-#define PCI_DEVICE_ID_NVIDIA_NVENET_20              0x0450
-#define PCI_DEVICE_ID_NVIDIA_NVENET_21              0x0451
-#define PCI_DEVICE_ID_NVIDIA_NVENET_22              0x0452
-#define PCI_DEVICE_ID_NVIDIA_NVENET_23              0x0453
-#define PCI_DEVICE_ID_NVIDIA_NVENET_24              0x054C
-#define PCI_DEVICE_ID_NVIDIA_NVENET_25              0x054D
-#define PCI_DEVICE_ID_NVIDIA_NVENET_26              0x054E
-#define PCI_DEVICE_ID_NVIDIA_NVENET_27              0x054F
-#define PCI_DEVICE_ID_NVIDIA_NVENET_28              0x07DC
-#define PCI_DEVICE_ID_NVIDIA_NVENET_29              0x07DD
-#define PCI_DEVICE_ID_NVIDIA_NVENET_30              0x07DE
-#define PCI_DEVICE_ID_NVIDIA_NVENET_31              0x07DF
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE       0x0560
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE       0x056C
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE       0x0759
-#define PCI_DEVICE_ID_NVIDIA_NVENET_32              0x0760
-#define PCI_DEVICE_ID_NVIDIA_NVENET_33              0x0761
-#define PCI_DEVICE_ID_NVIDIA_NVENET_34              0x0762
-#define PCI_DEVICE_ID_NVIDIA_NVENET_35              0x0763
-#define PCI_DEVICE_ID_NVIDIA_NVENET_36              0x0AB0
-#define PCI_DEVICE_ID_NVIDIA_NVENET_37              0x0AB1
-#define PCI_DEVICE_ID_NVIDIA_NVENET_38              0x0AB2
-#define PCI_DEVICE_ID_NVIDIA_NVENET_39              0x0AB3
-
-#define PCI_VENDOR_ID_IMS		0x10e0
-#define PCI_DEVICE_ID_IMS_TT128		0x9128
-#define PCI_DEVICE_ID_IMS_TT3D		0x9135
-
-#define PCI_VENDOR_ID_INTERG		0x10ea
-#define PCI_DEVICE_ID_INTERG_1682	0x1682
-#define PCI_DEVICE_ID_INTERG_2000	0x2000
-#define PCI_DEVICE_ID_INTERG_2010	0x2010
-#define PCI_DEVICE_ID_INTERG_5000	0x5000
-#define PCI_DEVICE_ID_INTERG_5050	0x5050
-
-#define PCI_VENDOR_ID_REALTEK		0x10ec
-#define PCI_DEVICE_ID_REALTEK_8139	0x8139
-
-#define PCI_VENDOR_ID_XILINX		0x10ee
-#define PCI_DEVICE_ID_RME_DIGI96	0x3fc0
-#define PCI_DEVICE_ID_RME_DIGI96_8	0x3fc1
-#define PCI_DEVICE_ID_RME_DIGI96_8_PRO	0x3fc2
-#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
-#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
-#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
-
-#define PCI_VENDOR_ID_INIT		0x1101
-
-#define PCI_VENDOR_ID_CREATIVE		0x1102 /* duplicate: ECTIVA */
-#define PCI_DEVICE_ID_CREATIVE_EMU10K1	0x0002
-
-#define PCI_VENDOR_ID_ECTIVA		0x1102 /* duplicate: CREATIVE */
-#define PCI_DEVICE_ID_ECTIVA_EV1938	0x8938
-
-#define PCI_VENDOR_ID_TTI		0x1103
-#define PCI_DEVICE_ID_TTI_HPT343	0x0003
-#define PCI_DEVICE_ID_TTI_HPT366	0x0004
-#define PCI_DEVICE_ID_TTI_HPT372	0x0005
-#define PCI_DEVICE_ID_TTI_HPT302	0x0006
-#define PCI_DEVICE_ID_TTI_HPT371	0x0007
-#define PCI_DEVICE_ID_TTI_HPT374	0x0008
-#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	/* apparently a 372N variant? */
-
-#define PCI_VENDOR_ID_VIA		0x1106
-#define PCI_DEVICE_ID_VIA_8763_0	0x0198
-#define PCI_DEVICE_ID_VIA_8380_0	0x0204
-#define PCI_DEVICE_ID_VIA_3238_0	0x0238
-#define PCI_DEVICE_ID_VIA_PT880		0x0258
-#define PCI_DEVICE_ID_VIA_PT880ULTRA	0x0308
-#define PCI_DEVICE_ID_VIA_PX8X0_0	0x0259
-#define PCI_DEVICE_ID_VIA_3269_0	0x0269
-#define PCI_DEVICE_ID_VIA_K8T800PRO_0	0x0282
-#define PCI_DEVICE_ID_VIA_3296_0	0x0296
-#define PCI_DEVICE_ID_VIA_8363_0	0x0305
-#define PCI_DEVICE_ID_VIA_P4M800CE	0x0314
-#define PCI_DEVICE_ID_VIA_P4M890	0x0327
-#define PCI_DEVICE_ID_VIA_VT3324	0x0324
-#define PCI_DEVICE_ID_VIA_VT3336	0x0336
-#define PCI_DEVICE_ID_VIA_VT3351	0x0351
-#define PCI_DEVICE_ID_VIA_VT3364	0x0364
-#define PCI_DEVICE_ID_VIA_8371_0	0x0391
-#define PCI_DEVICE_ID_VIA_8501_0	0x0501
-#define PCI_DEVICE_ID_VIA_82C561	0x0561
-#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
-#define PCI_DEVICE_ID_VIA_82C576	0x0576
-#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
-#define PCI_DEVICE_ID_VIA_82C596	0x0596
-#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
-#define PCI_DEVICE_ID_VIA_82C598_0	0x0598
-#define PCI_DEVICE_ID_VIA_8601_0	0x0601
-#define PCI_DEVICE_ID_VIA_8605_0	0x0605
-#define PCI_DEVICE_ID_VIA_82C686	0x0686
-#define PCI_DEVICE_ID_VIA_82C691_0	0x0691
-#define PCI_DEVICE_ID_VIA_82C576_1	0x1571
-#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
-#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
-#define PCI_DEVICE_ID_VIA_82C596_3	0x3050
-#define PCI_DEVICE_ID_VIA_82C596B_3	0x3051
-#define PCI_DEVICE_ID_VIA_82C686_4	0x3057
-#define PCI_DEVICE_ID_VIA_82C686_5	0x3058
-#define PCI_DEVICE_ID_VIA_8233_5	0x3059
-#define PCI_DEVICE_ID_VIA_8233_0	0x3074
-#define PCI_DEVICE_ID_VIA_8633_0	0x3091
-#define PCI_DEVICE_ID_VIA_8367_0	0x3099
-#define PCI_DEVICE_ID_VIA_8653_0	0x3101
-#define PCI_DEVICE_ID_VIA_8622		0x3102
-#define PCI_DEVICE_ID_VIA_8235_USB_2	0x3104
-#define PCI_DEVICE_ID_VIA_8233C_0	0x3109
-#define PCI_DEVICE_ID_VIA_8361		0x3112
-#define PCI_DEVICE_ID_VIA_XM266		0x3116
-#define PCI_DEVICE_ID_VIA_612X		0x3119
-#define PCI_DEVICE_ID_VIA_862X_0	0x3123
-#define PCI_DEVICE_ID_VIA_8753_0	0x3128
-#define PCI_DEVICE_ID_VIA_8233A		0x3147
-#define PCI_DEVICE_ID_VIA_8703_51_0	0x3148
-#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
-#define PCI_DEVICE_ID_VIA_XN266		0x3156
-#define PCI_DEVICE_ID_VIA_6410		0x3164
-#define PCI_DEVICE_ID_VIA_8754C_0	0x3168
-#define PCI_DEVICE_ID_VIA_8235		0x3177
-#define PCI_DEVICE_ID_VIA_8385_0	0x3188
-#define PCI_DEVICE_ID_VIA_8377_0	0x3189
-#define PCI_DEVICE_ID_VIA_8378_0	0x3205
-#define PCI_DEVICE_ID_VIA_8783_0	0x3208
-#define PCI_DEVICE_ID_VIA_8237		0x3227
-#define PCI_DEVICE_ID_VIA_8251		0x3287
-#define PCI_DEVICE_ID_VIA_8237A		0x3337
-#define PCI_DEVICE_ID_VIA_8237S		0x3372
-#define PCI_DEVICE_ID_VIA_SATA_EIDE	0x5324
-#define PCI_DEVICE_ID_VIA_8231		0x8231
-#define PCI_DEVICE_ID_VIA_8231_4	0x8235
-#define PCI_DEVICE_ID_VIA_8365_1	0x8305
-#define PCI_DEVICE_ID_VIA_CX700		0x8324
-#define PCI_DEVICE_ID_VIA_CX700_IDE	0x0581
-#define PCI_DEVICE_ID_VIA_VX800		0x8353
-#define PCI_DEVICE_ID_VIA_8371_1	0x8391
-#define PCI_DEVICE_ID_VIA_82C598_1	0x8598
-#define PCI_DEVICE_ID_VIA_838X_1	0xB188
-#define PCI_DEVICE_ID_VIA_83_87XX_1	0xB198
-
-#define PCI_VENDOR_ID_SIEMENS           0x110A
-#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
-
-#define PCI_VENDOR_ID_VORTEX		0x1119
-#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
-#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
-#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
-#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
-#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
-#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
-#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
-#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
-#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
-#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
-#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
-#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
-#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
-#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
-
-#define PCI_VENDOR_ID_EF		0x111a
-#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
-#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
-#define PCI_DEVICE_ID_EF_ATM_LANAI2	0x0003
-#define PCI_DEVICE_ID_EF_ATM_LANAIHB	0x0005
-
-#define PCI_VENDOR_ID_IDT		0x111d
-#define PCI_DEVICE_ID_IDT_IDT77201	0x0001
-
-#define PCI_VENDOR_ID_FORE		0x1127
-#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
-
-#define PCI_VENDOR_ID_PHILIPS		0x1131
-#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
-#define PCI_DEVICE_ID_PHILIPS_SAA9730	0x9730
-
-#define PCI_VENDOR_ID_EICON		0x1133
-#define PCI_DEVICE_ID_EICON_DIVA20	0xe002
-#define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
-#define PCI_DEVICE_ID_EICON_DIVA201	0xe005
-#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
-#define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
-#define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
-#define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
-#define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
-
-#define PCI_VENDOR_ID_CISCO		0x1137
-
-#define PCI_VENDOR_ID_ZIATECH		0x1138
-#define PCI_DEVICE_ID_ZIATECH_5550_HC	0x5550
- 
-
-#define PCI_VENDOR_ID_SYSKONNECT	0x1148
-#define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
-#define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
-#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
-#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
-#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
-
-#define PCI_VENDOR_ID_DIGI		0x114f
-#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E	0x0070
-#define PCI_DEVICE_ID_DIGI_DF_M_E	0x0071
-#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A	0x0072
-#define PCI_DEVICE_ID_DIGI_DF_M_A	0x0073
-#define PCI_DEVICE_ID_NEO_2DB9          0x00C8
-#define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
-#define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
-#define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
-#define PCIE_DEVICE_ID_NEO_4_IBM        0x00F4
-
-#define PCI_VENDOR_ID_XIRCOM		0x115d
-#define PCI_DEVICE_ID_XIRCOM_RBM56G	0x0101
-#define PCI_DEVICE_ID_XIRCOM_X3201_MDM	0x0103
-
-#define PCI_VENDOR_ID_SERVERWORKS	  0x1166
-#define PCI_DEVICE_ID_SERVERWORKS_HE	  0x0008
-#define PCI_DEVICE_ID_SERVERWORKS_LE	  0x0009
-#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
-#define PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB	0x0036
-#define PCI_DEVICE_ID_SERVERWORKS_EPB	  0x0103
-#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE	0x0132
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4	  0x0200
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5	  0x0201
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
-#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
-#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
-
-#define PCI_VENDOR_ID_SBE		0x1176
-#define PCI_DEVICE_ID_SBE_WANXL100	0x0301
-#define PCI_DEVICE_ID_SBE_WANXL200	0x0302
-#define PCI_DEVICE_ID_SBE_WANXL400	0x0104
-
-#define PCI_VENDOR_ID_TOSHIBA		0x1179
-#define PCI_DEVICE_ID_TOSHIBA_PICCOLO	0x0102
-#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1	0x0103
-#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2	0x0105
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC100	0x0617
-
-#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
-#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
-#define PCI_DEVICE_ID_TOSHIBA_TC35815_NWU	0x0031
-#define PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939	0x0032
-#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE	0x0105
-#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC	0x0108
-#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
-
-#define PCI_VENDOR_ID_ATTO		0x117c
-
-#define PCI_VENDOR_ID_RICOH		0x1180
-#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
-#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
-#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
-#define PCI_DEVICE_ID_RICOH_RL5C476	0x0476
-#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
-#define PCI_DEVICE_ID_RICOH_R5C822	0x0822
-#define PCI_DEVICE_ID_RICOH_R5C832	0x0832
-#define PCI_DEVICE_ID_RICOH_R5C843	0x0843
-
-#define PCI_VENDOR_ID_DLINK		0x1186
-#define PCI_DEVICE_ID_DLINK_DGE510T	0x4c00
-
-#define PCI_VENDOR_ID_ARTOP		0x1191
-#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
-#define PCI_DEVICE_ID_ARTOP_ATP860	0x0006
-#define PCI_DEVICE_ID_ARTOP_ATP860R	0x0007
-#define PCI_DEVICE_ID_ARTOP_ATP865	0x0008
-#define PCI_DEVICE_ID_ARTOP_ATP865R	0x0009
-#define PCI_DEVICE_ID_ARTOP_AEC7610	0x8002
-#define PCI_DEVICE_ID_ARTOP_AEC7612UW	0x8010
-#define PCI_DEVICE_ID_ARTOP_AEC7612U	0x8020
-#define PCI_DEVICE_ID_ARTOP_AEC7612S	0x8030
-#define PCI_DEVICE_ID_ARTOP_AEC7612D	0x8040
-#define PCI_DEVICE_ID_ARTOP_AEC7612SUW	0x8050
-#define PCI_DEVICE_ID_ARTOP_8060	0x8060
-
-#define PCI_VENDOR_ID_ZEITNET		0x1193
-#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
-#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
-
-#define PCI_VENDOR_ID_FUJITSU_ME	0x119e
-#define PCI_DEVICE_ID_FUJITSU_FS155	0x0001
-#define PCI_DEVICE_ID_FUJITSU_FS50	0x0003
-
-#define PCI_SUBVENDOR_ID_KEYSPAN	0x11a9
-#define PCI_SUBDEVICE_ID_KEYSPAN_SX2	0x5334
-
-#define PCI_VENDOR_ID_MARVELL		0x11ab
-#define PCI_DEVICE_ID_MARVELL_GT64111	0x4146
-#define PCI_DEVICE_ID_MARVELL_GT64260	0x6430
-#define PCI_DEVICE_ID_MARVELL_MV64360	0x6460
-#define PCI_DEVICE_ID_MARVELL_MV64460	0x6480
-#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND	0x4100
-#define PCI_DEVICE_ID_MARVELL_88ALP01_SD	0x4101
-#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC	0x4102
-
-#define PCI_VENDOR_ID_V3		0x11b0
-#define PCI_DEVICE_ID_V3_V960		0x0001
-#define PCI_DEVICE_ID_V3_V351		0x0002
-
-#define PCI_VENDOR_ID_ATT		0x11c1
-#define PCI_DEVICE_ID_ATT_VENUS_MODEM	0x480
-
-#define PCI_VENDOR_ID_SPECIALIX		0x11cb
-#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
-#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
-#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
-
-#define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
-#define PCI_DEVICE_ID_AD1889JS		0x1889
-
-#define PCI_DEVICE_ID_SEGA_BBA		0x1234
-
-#define PCI_VENDOR_ID_ZORAN		0x11de
-#define PCI_DEVICE_ID_ZORAN_36057	0x6057
-#define PCI_DEVICE_ID_ZORAN_36120	0x6120
-
-#define PCI_VENDOR_ID_COMPEX		0x11f6
-#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
-
-#define PCI_VENDOR_ID_RP		0x11fe
-#define PCI_DEVICE_ID_RP32INTF		0x0001
-#define PCI_DEVICE_ID_RP8INTF		0x0002
-#define PCI_DEVICE_ID_RP16INTF		0x0003
-#define PCI_DEVICE_ID_RP4QUAD		0x0004
-#define PCI_DEVICE_ID_RP8OCTA		0x0005
-#define PCI_DEVICE_ID_RP8J		0x0006
-#define PCI_DEVICE_ID_RP4J		0x0007
-#define PCI_DEVICE_ID_RP8SNI		0x0008	
-#define PCI_DEVICE_ID_RP16SNI		0x0009	
-#define PCI_DEVICE_ID_RPP4		0x000A
-#define PCI_DEVICE_ID_RPP8		0x000B
-#define PCI_DEVICE_ID_RP4M		0x000D
-#define PCI_DEVICE_ID_RP2_232		0x000E
-#define PCI_DEVICE_ID_RP2_422		0x000F
-#define PCI_DEVICE_ID_URP32INTF		0x0801
-#define PCI_DEVICE_ID_URP8INTF		0x0802
-#define PCI_DEVICE_ID_URP16INTF		0x0803
-#define PCI_DEVICE_ID_URP8OCTA		0x0805
-#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C       
-#define PCI_DEVICE_ID_UPCI_RM3_4PORT	0x080D
-#define PCI_DEVICE_ID_CRP16INTF		0x0903       
-
-#define PCI_VENDOR_ID_CYCLADES		0x120e
-#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
-#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
-#define PCI_DEVICE_ID_CYCLOM_4Y_Lo	0x0102
-#define PCI_DEVICE_ID_CYCLOM_4Y_Hi	0x0103
-#define PCI_DEVICE_ID_CYCLOM_8Y_Lo	0x0104
-#define PCI_DEVICE_ID_CYCLOM_8Y_Hi	0x0105
-#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
-#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
-#define PCI_DEVICE_ID_PC300_RX_2	0x0300
-#define PCI_DEVICE_ID_PC300_RX_1	0x0301
-#define PCI_DEVICE_ID_PC300_TE_2	0x0310
-#define PCI_DEVICE_ID_PC300_TE_1	0x0311
-#define PCI_DEVICE_ID_PC300_TE_M_2	0x0320
-#define PCI_DEVICE_ID_PC300_TE_M_1	0x0321
-
-#define PCI_VENDOR_ID_ESSENTIAL		0x120f
-#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
-
-#define PCI_VENDOR_ID_O2		0x1217
-#define PCI_DEVICE_ID_O2_6729		0x6729
-#define PCI_DEVICE_ID_O2_6730		0x673a
-#define PCI_DEVICE_ID_O2_6832		0x6832
-#define PCI_DEVICE_ID_O2_6836		0x6836
-
-#define PCI_VENDOR_ID_3DFX		0x121a
-#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
-#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
-#define PCI_DEVICE_ID_3DFX_BANSHEE	0x0003
-#define PCI_DEVICE_ID_3DFX_VOODOO3	0x0005
-#define PCI_DEVICE_ID_3DFX_VOODOO5	0x0009
-
-#define PCI_VENDOR_ID_AVM		0x1244
-#define PCI_DEVICE_ID_AVM_B1		0x0700
-#define PCI_DEVICE_ID_AVM_C4		0x0800
-#define PCI_DEVICE_ID_AVM_A1		0x0a00
-#define PCI_DEVICE_ID_AVM_A1_V2		0x0e00
-#define PCI_DEVICE_ID_AVM_C2		0x1100
-#define PCI_DEVICE_ID_AVM_T1		0x1200
-
-#define PCI_VENDOR_ID_STALLION		0x124d
-
-/* Allied Telesyn */
-#define PCI_VENDOR_ID_AT    		0x1259
-#define PCI_SUBDEVICE_ID_AT_2700FX	0x2701
-#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
-
-#define PCI_VENDOR_ID_ESS		0x125d
-#define PCI_DEVICE_ID_ESS_ESS1968	0x1968
-#define PCI_DEVICE_ID_ESS_ESS1978	0x1978
-#define PCI_DEVICE_ID_ESS_ALLEGRO_1	0x1988
-#define PCI_DEVICE_ID_ESS_ALLEGRO	0x1989
-#define PCI_DEVICE_ID_ESS_CANYON3D_2LE	0x1990
-#define PCI_DEVICE_ID_ESS_CANYON3D_2	0x1992
-#define PCI_DEVICE_ID_ESS_MAESTRO3	0x1998
-#define PCI_DEVICE_ID_ESS_MAESTRO3_1	0x1999
-#define PCI_DEVICE_ID_ESS_MAESTRO3_HW	0x199a
-#define PCI_DEVICE_ID_ESS_MAESTRO3_2	0x199b
-
-#define PCI_VENDOR_ID_SATSAGEM		0x1267
-#define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
-
-#define PCI_VENDOR_ID_ENSONIQ		0x1274
-#define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
-#define PCI_DEVICE_ID_ENSONIQ_ES1370	0x5000
-#define PCI_DEVICE_ID_ENSONIQ_ES1371	0x1371
-
-#define PCI_VENDOR_ID_TRANSMETA		0x1279
-#define PCI_DEVICE_ID_EFFICEON		0x0060
-
-#define PCI_VENDOR_ID_ROCKWELL		0x127A
-
-#define PCI_VENDOR_ID_ITE		0x1283
-#define PCI_DEVICE_ID_ITE_8211		0x8211
-#define PCI_DEVICE_ID_ITE_8212		0x8212
-#define PCI_DEVICE_ID_ITE_8213		0x8213
-#define PCI_DEVICE_ID_ITE_8152		0x8152
-#define PCI_DEVICE_ID_ITE_8872		0x8872
-#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
-
-/* formerly Platform Tech */
-#define PCI_DEVICE_ID_ESS_ESS0100	0x0100
-
-#define PCI_VENDOR_ID_ALTEON		0x12ae
-
-#define PCI_SUBVENDOR_ID_CONNECT_TECH			0x12c4
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232		0x0001
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232		0x0002
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232		0x0003
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485		0x0004
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4	0x0005
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485		0x0006
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2	0x0007
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485		0x0008
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6	0x0009
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1	0x000A
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1	0x000B
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ		0x000C
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM		0x000D
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI		0x0100
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2		0x0201
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4		0x0202
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232	0x0300
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232	0x0301
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232	0x0302
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1	0x0310
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2	0x0311
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4	0x0312
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2	0x0320
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4	0x0321
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8	0x0322
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485	0x0330
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485	0x0331
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485	0x0332
-
-#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
-#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
-
-#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16	0x0011
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC	0x0041
-#define PCI_SUBVENDOR_ID_CHASE_PCIRAS		0x124D
-#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4		0xF001
-#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8		0xF010
-
-#define PCI_VENDOR_ID_AUREAL		0x12eb
-#define PCI_DEVICE_ID_AUREAL_VORTEX_1	0x0001
-#define PCI_DEVICE_ID_AUREAL_VORTEX_2	0x0002
-#define PCI_DEVICE_ID_AUREAL_ADVANTAGE	0x0003
-
-#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
-#define PCI_DEVICE_ID_LML_33R10		0x8a02
-
-#define PCI_VENDOR_ID_ESDGMBH		0x12fe
-#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
-
-#define PCI_VENDOR_ID_SIIG		0x131f
-#define PCI_SUBVENDOR_ID_SIIG		0x131f
-#define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
-#define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
-#define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_550	0x1010
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_650	0x1011
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_850	0x1012
-#define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
-#define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
-#define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
-#define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
-#define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_550	0x1034
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_650	0x1035
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_850	0x1036
-#define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
-#define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
-#define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
-#define PCI_DEVICE_ID_SIIG_1S_20x_550	0x2000
-#define PCI_DEVICE_ID_SIIG_1S_20x_650	0x2001
-#define PCI_DEVICE_ID_SIIG_1S_20x_850	0x2002
-#define PCI_DEVICE_ID_SIIG_1P_20x	0x2020
-#define PCI_DEVICE_ID_SIIG_2P_20x	0x2021
-#define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
-#define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
-#define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_550	0x2040
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_650	0x2041
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_850	0x2042
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_550	0x2010
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_650	0x2011
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_850	0x2012
-#define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
-#define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
-#define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_550	0x2060
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_650	0x2061
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_850	0x2062
-#define PCI_DEVICE_ID_SIIG_8S_20x_550	0x2080
-#define PCI_DEVICE_ID_SIIG_8S_20x_650	0x2081
-#define PCI_DEVICE_ID_SIIG_8S_20x_850	0x2082
-#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL	0x2050
-
-#define PCI_VENDOR_ID_RADISYS		0x1331
-
-#define PCI_VENDOR_ID_MICRO_MEMORY		0x1332
-#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN	0x5415
-#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN	0x5425
-#define PCI_DEVICE_ID_MICRO_MEMORY_6155		0x6155
-
-#define PCI_VENDOR_ID_DOMEX		0x134a
-#define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
-
-#define PCI_VENDOR_ID_INTASHIELD	0x135a
-#define PCI_DEVICE_ID_INTASHIELD_IS200	0x0d80
-#define PCI_DEVICE_ID_INTASHIELD_IS400	0x0dc0
-
-#define PCI_VENDOR_ID_QUATECH		0x135C
-#define PCI_DEVICE_ID_QUATECH_QSC100	0x0010
-#define PCI_DEVICE_ID_QUATECH_DSC100	0x0020
-#define PCI_DEVICE_ID_QUATECH_ESC100D	0x0050
-#define PCI_DEVICE_ID_QUATECH_ESC100M	0x0060
-#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
-
-#define PCI_VENDOR_ID_SEALEVEL		0x135e
-#define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM422	0x7402
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM232	0x7202
-#define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
-#define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM8	0x7804
-
-#define PCI_VENDOR_ID_HYPERCOPE		0x1365
-#define PCI_DEVICE_ID_HYPERCOPE_PLX	0x9050
-#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO	0x0104
-#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO		0x0106
-#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO	0x0107
-#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2	0x0108
-
-#define PCI_VENDOR_ID_KAWASAKI		0x136b
-#define PCI_DEVICE_ID_MCHIP_KL5A72002	0xff01
-
-#define PCI_VENDOR_ID_CNET		0x1371
-#define PCI_DEVICE_ID_CNET_GIGACARD	0x434e
-
-#define PCI_VENDOR_ID_LMC		0x1376
-#define PCI_DEVICE_ID_LMC_HSSI		0x0003
-#define PCI_DEVICE_ID_LMC_DS3		0x0004
-#define PCI_DEVICE_ID_LMC_SSI		0x0005
-#define PCI_DEVICE_ID_LMC_T1		0x0006
-
-#define PCI_VENDOR_ID_NETGEAR		0x1385
-#define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
-
-#define PCI_VENDOR_ID_APPLICOM		0x1389
-#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
-#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
-#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
-
-#define PCI_VENDOR_ID_MOXA		0x1393
-#define PCI_DEVICE_ID_MOXA_RC7000	0x0001
-#define PCI_DEVICE_ID_MOXA_CP102	0x1020
-#define PCI_DEVICE_ID_MOXA_CP102UL	0x1021
-#define PCI_DEVICE_ID_MOXA_CP102U	0x1022
-#define PCI_DEVICE_ID_MOXA_C104		0x1040
-#define PCI_DEVICE_ID_MOXA_CP104U	0x1041
-#define PCI_DEVICE_ID_MOXA_CP104JU	0x1042
-#define PCI_DEVICE_ID_MOXA_CP104EL	0x1043
-#define PCI_DEVICE_ID_MOXA_CT114	0x1140
-#define PCI_DEVICE_ID_MOXA_CP114	0x1141
-#define PCI_DEVICE_ID_MOXA_CP118U	0x1180
-#define PCI_DEVICE_ID_MOXA_CP118EL	0x1181
-#define PCI_DEVICE_ID_MOXA_CP132	0x1320
-#define PCI_DEVICE_ID_MOXA_CP132U	0x1321
-#define PCI_DEVICE_ID_MOXA_CP134U	0x1340
-#define PCI_DEVICE_ID_MOXA_C168		0x1680
-#define PCI_DEVICE_ID_MOXA_CP168U	0x1681
-#define PCI_DEVICE_ID_MOXA_CP168EL	0x1682
-#define PCI_DEVICE_ID_MOXA_CP204J	0x2040
-#define PCI_DEVICE_ID_MOXA_C218		0x2180
-#define PCI_DEVICE_ID_MOXA_C320		0x3200
-
-#define PCI_VENDOR_ID_CCD		0x1397
-#define PCI_DEVICE_ID_CCD_HFC4S		0x08B4
-#define PCI_SUBDEVICE_ID_CCD_PMX2S	0x1234
-#define PCI_DEVICE_ID_CCD_HFC8S		0x16B8
-#define PCI_DEVICE_ID_CCD_2BD0		0x2bd0
-#define PCI_DEVICE_ID_CCD_HFCE1		0x30B1
-#define PCI_SUBDEVICE_ID_CCD_SPD4S	0x3136
-#define PCI_SUBDEVICE_ID_CCD_SPDE1	0x3137
-#define PCI_DEVICE_ID_CCD_B000		0xb000
-#define PCI_DEVICE_ID_CCD_B006		0xb006
-#define PCI_DEVICE_ID_CCD_B007		0xb007
-#define PCI_DEVICE_ID_CCD_B008		0xb008
-#define PCI_DEVICE_ID_CCD_B009		0xb009
-#define PCI_DEVICE_ID_CCD_B00A		0xb00a
-#define PCI_DEVICE_ID_CCD_B00B		0xb00b
-#define PCI_DEVICE_ID_CCD_B00C		0xb00c
-#define PCI_DEVICE_ID_CCD_B100		0xb100
-#define PCI_SUBDEVICE_ID_CCD_IOB4ST	0xB520
-#define PCI_SUBDEVICE_ID_CCD_IOB8STR	0xB521
-#define PCI_SUBDEVICE_ID_CCD_IOB8ST	0xB522
-#define PCI_SUBDEVICE_ID_CCD_IOB1E1	0xB523
-#define PCI_SUBDEVICE_ID_CCD_SWYX4S	0xB540
-#define PCI_SUBDEVICE_ID_CCD_JH4S20	0xB550
-#define PCI_SUBDEVICE_ID_CCD_IOB8ST_1	0xB552
-#define PCI_SUBDEVICE_ID_CCD_BN4S	0xB560
-#define PCI_SUBDEVICE_ID_CCD_BN8S	0xB562
-#define PCI_SUBDEVICE_ID_CCD_BNE1	0xB563
-#define PCI_SUBDEVICE_ID_CCD_BNE1D	0xB564
-#define PCI_SUBDEVICE_ID_CCD_BNE1DP	0xB565
-#define PCI_SUBDEVICE_ID_CCD_BN2S	0xB566
-#define PCI_SUBDEVICE_ID_CCD_BN1SM	0xB567
-#define PCI_SUBDEVICE_ID_CCD_BN4SM	0xB568
-#define PCI_SUBDEVICE_ID_CCD_BN2SM	0xB569
-#define PCI_SUBDEVICE_ID_CCD_BNE1M	0xB56A
-#define PCI_SUBDEVICE_ID_CCD_BN8SP	0xB56B
-#define PCI_SUBDEVICE_ID_CCD_HFC4S	0xB620
-#define PCI_SUBDEVICE_ID_CCD_HFC8S	0xB622
-#define PCI_DEVICE_ID_CCD_B700		0xb700
-#define PCI_DEVICE_ID_CCD_B701		0xb701
-#define PCI_SUBDEVICE_ID_CCD_HFCE1	0xC523
-#define PCI_SUBDEVICE_ID_CCD_OV2S	0xE884
-#define PCI_SUBDEVICE_ID_CCD_OV4S	0xE888
-#define PCI_SUBDEVICE_ID_CCD_OV8S	0xE998
-
-#define PCI_VENDOR_ID_EXAR		0x13a8
-#define PCI_DEVICE_ID_EXAR_XR17C152	0x0152
-#define PCI_DEVICE_ID_EXAR_XR17C154	0x0154
-#define PCI_DEVICE_ID_EXAR_XR17C158	0x0158
-
-#define PCI_VENDOR_ID_MICROGATE		0x13c0
-#define PCI_DEVICE_ID_MICROGATE_USC	0x0010
-#define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
-
-#define PCI_VENDOR_ID_3WARE		0x13C1
-#define PCI_DEVICE_ID_3WARE_1000	0x1000
-#define PCI_DEVICE_ID_3WARE_7000	0x1001
-#define PCI_DEVICE_ID_3WARE_9000	0x1002
-
-#define PCI_VENDOR_ID_IOMEGA		0x13ca
-#define PCI_DEVICE_ID_IOMEGA_BUZ	0x4231
-
-#define PCI_VENDOR_ID_ABOCOM		0x13D1
-#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
-
-#define PCI_VENDOR_ID_SUNDANCE		0x13f0
-
-#define PCI_VENDOR_ID_CMEDIA		0x13f6
-#define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
-#define PCI_DEVICE_ID_CMEDIA_CM8338B	0x0101
-#define PCI_DEVICE_ID_CMEDIA_CM8738	0x0111
-#define PCI_DEVICE_ID_CMEDIA_CM8738B	0x0112
-
-#define PCI_VENDOR_ID_LAVA		0x1407
-#define PCI_DEVICE_ID_LAVA_DSERIAL	0x0100 /* 2x 16550 */
-#define PCI_DEVICE_ID_LAVA_QUATRO_A	0x0101 /* 2x 16550, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_QUATRO_B	0x0102 /* 2x 16550, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_OCTO_A	0x0180 /* 4x 16550A, half of 8 port */
-#define PCI_DEVICE_ID_LAVA_OCTO_B	0x0181 /* 4x 16550A, half of 8 port */
-#define PCI_DEVICE_ID_LAVA_PORT_PLUS	0x0200 /* 2x 16650 */
-#define PCI_DEVICE_ID_LAVA_QUAD_A	0x0201 /* 2x 16650, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_QUAD_B	0x0202 /* 2x 16650, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_SSERIAL	0x0500 /* 1x 16550 */
-#define PCI_DEVICE_ID_LAVA_PORT_650	0x0600 /* 1x 16650 */
-#define PCI_DEVICE_ID_LAVA_PARALLEL	0x8000
-#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A	0x8002 /* The Lava Dual Parallel is */
-#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B	0x8003 /* two PCI devices on a card */
-#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR	0x8800
-
-#define PCI_VENDOR_ID_TIMEDIA		0x1409
-#define PCI_DEVICE_ID_TIMEDIA_1889	0x7168
-
-#define PCI_VENDOR_ID_ICE		0x1412
-#define PCI_DEVICE_ID_ICE_1712		0x1712
-#define PCI_DEVICE_ID_VT1724		0x1724
-
-#define PCI_VENDOR_ID_OXSEMI		0x1415
-#define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
-#define PCI_DEVICE_ID_OXSEMI_PCIe840		0xC000
-#define PCI_DEVICE_ID_OXSEMI_PCIe840_G		0xC004
-#define PCI_DEVICE_ID_OXSEMI_PCIe952_0		0xC100
-#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G	0xC104
-#define PCI_DEVICE_ID_OXSEMI_PCIe952_1		0xC110
-#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G	0xC114
-#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U	0xC118
-#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU	0xC11C
-#define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
-#define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
-#define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
-#define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
-#define PCI_DEVICE_ID_OXSEMI_16PCI952PP	0x9523
-
-#define PCI_VENDOR_ID_CHELSIO		0x1425
-
-#define PCI_VENDOR_ID_SAMSUNG		0x144d
-
-#define PCI_VENDOR_ID_MYRICOM		0x14c1
-
-#define PCI_VENDOR_ID_TITAN		0x14D2
-#define PCI_DEVICE_ID_TITAN_010L	0x8001
-#define PCI_DEVICE_ID_TITAN_100L	0x8010
-#define PCI_DEVICE_ID_TITAN_110L	0x8011
-#define PCI_DEVICE_ID_TITAN_200L	0x8020
-#define PCI_DEVICE_ID_TITAN_210L	0x8021
-#define PCI_DEVICE_ID_TITAN_400L	0x8040
-#define PCI_DEVICE_ID_TITAN_800L	0x8080
-#define PCI_DEVICE_ID_TITAN_100		0xA001
-#define PCI_DEVICE_ID_TITAN_200		0xA005
-#define PCI_DEVICE_ID_TITAN_400		0xA003
-#define PCI_DEVICE_ID_TITAN_800B	0xA004
-
-#define PCI_VENDOR_ID_PANACOM		0x14d4
-#define PCI_DEVICE_ID_PANACOM_QUADMODEM	0x0400
-#define PCI_DEVICE_ID_PANACOM_DUALMODEM	0x0402
-
-#define PCI_VENDOR_ID_SIPACKETS		0x14d9
-#define PCI_DEVICE_ID_SP1011		0x0010
-
-#define PCI_VENDOR_ID_AFAVLAB		0x14db
-#define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
-#define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
-#define PCI_SUBDEVICE_ID_AFAVLAB_P061		0x2150
-
-#define PCI_VENDOR_ID_BROADCOM		0x14e4
-#define PCI_DEVICE_ID_TIGON3_5752	0x1600
-#define PCI_DEVICE_ID_TIGON3_5752M	0x1601
-#define PCI_DEVICE_ID_NX2_5709		0x1639
-#define PCI_DEVICE_ID_NX2_5709S		0x163a
-#define PCI_DEVICE_ID_TIGON3_5700	0x1644
-#define PCI_DEVICE_ID_TIGON3_5701	0x1645
-#define PCI_DEVICE_ID_TIGON3_5702	0x1646
-#define PCI_DEVICE_ID_TIGON3_5703	0x1647
-#define PCI_DEVICE_ID_TIGON3_5704	0x1648
-#define PCI_DEVICE_ID_TIGON3_5704S_2	0x1649
-#define PCI_DEVICE_ID_NX2_5706		0x164a
-#define PCI_DEVICE_ID_NX2_5708		0x164c
-#define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
-#define PCI_DEVICE_ID_NX2_57710		0x164e
-#define PCI_DEVICE_ID_NX2_57711		0x164f
-#define PCI_DEVICE_ID_NX2_57711E	0x1650
-#define PCI_DEVICE_ID_TIGON3_5705	0x1653
-#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
-#define PCI_DEVICE_ID_TIGON3_5720	0x1658
-#define PCI_DEVICE_ID_TIGON3_5721	0x1659
-#define PCI_DEVICE_ID_TIGON3_5722	0x165a
-#define PCI_DEVICE_ID_TIGON3_5723	0x165b
-#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
-#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
-#define PCI_DEVICE_ID_TIGON3_5714	0x1668
-#define PCI_DEVICE_ID_TIGON3_5714S	0x1669
-#define PCI_DEVICE_ID_TIGON3_5780	0x166a
-#define PCI_DEVICE_ID_TIGON3_5780S	0x166b
-#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
-#define PCI_DEVICE_ID_TIGON3_5754M	0x1672
-#define PCI_DEVICE_ID_TIGON3_5755M	0x1673
-#define PCI_DEVICE_ID_TIGON3_5756	0x1674
-#define PCI_DEVICE_ID_TIGON3_5750	0x1676
-#define PCI_DEVICE_ID_TIGON3_5751	0x1677
-#define PCI_DEVICE_ID_TIGON3_5715	0x1678
-#define PCI_DEVICE_ID_TIGON3_5715S	0x1679
-#define PCI_DEVICE_ID_TIGON3_5754	0x167a
-#define PCI_DEVICE_ID_TIGON3_5755	0x167b
-#define PCI_DEVICE_ID_TIGON3_5750M	0x167c
-#define PCI_DEVICE_ID_TIGON3_5751M	0x167d
-#define PCI_DEVICE_ID_TIGON3_5751F	0x167e
-#define PCI_DEVICE_ID_TIGON3_5787F	0x167f
-#define PCI_DEVICE_ID_TIGON3_5761E	0x1680
-#define PCI_DEVICE_ID_TIGON3_5761	0x1681
-#define PCI_DEVICE_ID_TIGON3_5764	0x1684
-#define PCI_DEVICE_ID_TIGON3_5787M	0x1693
-#define PCI_DEVICE_ID_TIGON3_5782	0x1696
-#define PCI_DEVICE_ID_TIGON3_5784	0x1698
-#define PCI_DEVICE_ID_TIGON3_5785	0x1699
-#define PCI_DEVICE_ID_TIGON3_5786	0x169a
-#define PCI_DEVICE_ID_TIGON3_5787	0x169b
-#define PCI_DEVICE_ID_TIGON3_5788	0x169c
-#define PCI_DEVICE_ID_TIGON3_5789	0x169d
-#define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
-#define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
-#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
-#define PCI_DEVICE_ID_NX2_5706S		0x16aa
-#define PCI_DEVICE_ID_NX2_5708S		0x16ac
-#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
-#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
-#define PCI_DEVICE_ID_TIGON3_5781	0x16dd
-#define PCI_DEVICE_ID_TIGON3_5753	0x16f7
-#define PCI_DEVICE_ID_TIGON3_5753M	0x16fd
-#define PCI_DEVICE_ID_TIGON3_5753F	0x16fe
-#define PCI_DEVICE_ID_TIGON3_5901	0x170d
-#define PCI_DEVICE_ID_BCM4401B1		0x170c
-#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
-#define PCI_DEVICE_ID_TIGON3_5906	0x1712
-#define PCI_DEVICE_ID_TIGON3_5906M	0x1713
-#define PCI_DEVICE_ID_BCM4401		0x4401
-#define PCI_DEVICE_ID_BCM4401B0		0x4402
-
-#define PCI_VENDOR_ID_TOPIC		0x151f
-#define PCI_DEVICE_ID_TOPIC_TP560	0x0000
-
-#define PCI_VENDOR_ID_MAINPINE		0x1522
-#define PCI_DEVICE_ID_MAINPINE_PBRIDGE	0x0100
-#define PCI_VENDOR_ID_ENE		0x1524
-#define PCI_DEVICE_ID_ENE_CB712_SD	0x0550
-#define PCI_DEVICE_ID_ENE_CB712_SD_2	0x0551
-#define PCI_DEVICE_ID_ENE_CB714_SD	0x0750
-#define PCI_DEVICE_ID_ENE_CB714_SD_2	0x0751
-#define PCI_DEVICE_ID_ENE_1211		0x1211
-#define PCI_DEVICE_ID_ENE_1225		0x1225
-#define PCI_DEVICE_ID_ENE_1410		0x1410
-#define PCI_DEVICE_ID_ENE_710		0x1411
-#define PCI_DEVICE_ID_ENE_712		0x1412
-#define PCI_DEVICE_ID_ENE_1420		0x1420
-#define PCI_DEVICE_ID_ENE_720		0x1421
-#define PCI_DEVICE_ID_ENE_722		0x1422
-
-#define PCI_SUBVENDOR_ID_PERLE          0x155f
-#define PCI_SUBDEVICE_ID_PCI_RAS4       0xf001
-#define PCI_SUBDEVICE_ID_PCI_RAS8       0xf010
-
-#define PCI_VENDOR_ID_SYBA		0x1592
-#define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
-#define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
-
-#define PCI_VENDOR_ID_MORETON		0x15aa
-#define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
-
-#define PCI_VENDOR_ID_ZOLTRIX		0x15b0
-#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
-
-#define PCI_VENDOR_ID_MELLANOX		0x15b3
-#define PCI_DEVICE_ID_MELLANOX_TAVOR	0x5a44
-#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE	0x5a46
-#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
-#define PCI_DEVICE_ID_MELLANOX_ARBEL	0x6282
-#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
-#define PCI_DEVICE_ID_MELLANOX_SINAI	0x6274
-
-#define PCI_VENDOR_ID_QUICKNET		0x15e2
-#define PCI_DEVICE_ID_QUICKNET_XJ	0x0500
-
-/*
- * ADDI-DATA GmbH communication cards <info@addi-data.com>
- */
-#define PCI_VENDOR_ID_ADDIDATA_OLD             0x10E8
-#define PCI_VENDOR_ID_ADDIDATA                 0x15B8
-#define PCI_DEVICE_ID_ADDIDATA_APCI7500        0x7000
-#define PCI_DEVICE_ID_ADDIDATA_APCI7420        0x7001
-#define PCI_DEVICE_ID_ADDIDATA_APCI7300        0x7002
-#define PCI_DEVICE_ID_ADDIDATA_APCI7800        0x818E
-#define PCI_DEVICE_ID_ADDIDATA_APCI7500_2      0x7009
-#define PCI_DEVICE_ID_ADDIDATA_APCI7420_2      0x700A
-#define PCI_DEVICE_ID_ADDIDATA_APCI7300_2      0x700B
-#define PCI_DEVICE_ID_ADDIDATA_APCI7500_3      0x700C
-#define PCI_DEVICE_ID_ADDIDATA_APCI7420_3      0x700D
-#define PCI_DEVICE_ID_ADDIDATA_APCI7300_3      0x700E
-#define PCI_DEVICE_ID_ADDIDATA_APCI7800_3      0x700F
-
-#define PCI_VENDOR_ID_PDC		0x15e9
-
-#define PCI_VENDOR_ID_FARSITE           0x1619
-#define PCI_DEVICE_ID_FARSITE_T2P       0x0400
-#define PCI_DEVICE_ID_FARSITE_T4P       0x0440
-#define PCI_DEVICE_ID_FARSITE_T1U       0x0610
-#define PCI_DEVICE_ID_FARSITE_T2U       0x0620
-#define PCI_DEVICE_ID_FARSITE_T4U       0x0640
-#define PCI_DEVICE_ID_FARSITE_TE1       0x1610
-#define PCI_DEVICE_ID_FARSITE_TE1C      0x1612
-
-#define PCI_VENDOR_ID_ARIMA		0x161f
-
-#define PCI_VENDOR_ID_BROCADE		0x1657
-
-#define PCI_VENDOR_ID_SIBYTE		0x166d
-#define PCI_DEVICE_ID_BCM1250_PCI	0x0001
-#define PCI_DEVICE_ID_BCM1250_HT	0x0002
-
-#define PCI_VENDOR_ID_ATHEROS		0x168c
-
-#define PCI_VENDOR_ID_NETCELL		0x169c
-#define PCI_DEVICE_ID_REVOLUTION	0x0044
-
-#define PCI_VENDOR_ID_CENATEK		0x16CA
-#define PCI_DEVICE_ID_CENATEK_IDE	0x0001
-
-#define PCI_VENDOR_ID_VITESSE		0x1725
-#define PCI_DEVICE_ID_VITESSE_VSC7174	0x7174
-
-#define PCI_VENDOR_ID_LINKSYS		0x1737
-#define PCI_DEVICE_ID_LINKSYS_EG1064	0x1064
-
-#define PCI_VENDOR_ID_ALTIMA		0x173b
-#define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
-#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
-#define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
-#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
-
-#define PCI_VENDOR_ID_BELKIN		0x1799
-#define PCI_DEVICE_ID_BELKIN_F5D7010V7	0x701f
-
-#define PCI_VENDOR_ID_RDC		0x17f3
-#define PCI_DEVICE_ID_RDC_R6020		0x6020
-#define PCI_DEVICE_ID_RDC_R6030		0x6030
-#define PCI_DEVICE_ID_RDC_R6040		0x6040
-#define PCI_DEVICE_ID_RDC_R6060		0x6060
-#define PCI_DEVICE_ID_RDC_R6061		0x6061
-
-#define PCI_VENDOR_ID_LENOVO		0x17aa
-
-#define PCI_VENDOR_ID_ARECA		0x17d3
-#define PCI_DEVICE_ID_ARECA_1110	0x1110
-#define PCI_DEVICE_ID_ARECA_1120	0x1120
-#define PCI_DEVICE_ID_ARECA_1130	0x1130
-#define PCI_DEVICE_ID_ARECA_1160	0x1160
-#define PCI_DEVICE_ID_ARECA_1170	0x1170
-#define PCI_DEVICE_ID_ARECA_1200	0x1200
-#define PCI_DEVICE_ID_ARECA_1201	0x1201
-#define PCI_DEVICE_ID_ARECA_1202	0x1202
-#define PCI_DEVICE_ID_ARECA_1210	0x1210
-#define PCI_DEVICE_ID_ARECA_1220	0x1220
-#define PCI_DEVICE_ID_ARECA_1230	0x1230
-#define PCI_DEVICE_ID_ARECA_1260	0x1260
-#define PCI_DEVICE_ID_ARECA_1270	0x1270
-#define PCI_DEVICE_ID_ARECA_1280	0x1280
-#define PCI_DEVICE_ID_ARECA_1380	0x1380
-#define PCI_DEVICE_ID_ARECA_1381	0x1381
-#define PCI_DEVICE_ID_ARECA_1680	0x1680
-#define PCI_DEVICE_ID_ARECA_1681	0x1681
-
-#define PCI_VENDOR_ID_S2IO		0x17d5
-#define	PCI_DEVICE_ID_S2IO_WIN		0x5731
-#define	PCI_DEVICE_ID_S2IO_UNI		0x5831
-#define PCI_DEVICE_ID_HERC_WIN		0x5732
-#define PCI_DEVICE_ID_HERC_UNI		0x5832
-
-#define PCI_VENDOR_ID_SITECOM		0x182d
-#define PCI_DEVICE_ID_SITECOM_DC105V2	0x3069
-
-#define PCI_VENDOR_ID_TOPSPIN		0x1867
-
-#define PCI_VENDOR_ID_TDI               0x192E
-#define PCI_DEVICE_ID_TDI_EHCI          0x0101
-
-#define PCI_VENDOR_ID_FREESCALE		0x1957
-#define PCI_DEVICE_ID_MPC8548E		0x0012
-#define PCI_DEVICE_ID_MPC8548		0x0013
-#define PCI_DEVICE_ID_MPC8543E		0x0014
-#define PCI_DEVICE_ID_MPC8543		0x0015
-#define PCI_DEVICE_ID_MPC8547E		0x0018
-#define PCI_DEVICE_ID_MPC8545E		0x0019
-#define PCI_DEVICE_ID_MPC8545		0x001a
-#define PCI_DEVICE_ID_MPC8568E		0x0020
-#define PCI_DEVICE_ID_MPC8568		0x0021
-#define PCI_DEVICE_ID_MPC8567E		0x0022
-#define PCI_DEVICE_ID_MPC8567		0x0023
-#define PCI_DEVICE_ID_MPC8533E		0x0030
-#define PCI_DEVICE_ID_MPC8533		0x0031
-#define PCI_DEVICE_ID_MPC8544E		0x0032
-#define PCI_DEVICE_ID_MPC8544		0x0033
-#define PCI_DEVICE_ID_MPC8572E		0x0040
-#define PCI_DEVICE_ID_MPC8572		0x0041
-#define PCI_DEVICE_ID_MPC8536E		0x0050
-#define PCI_DEVICE_ID_MPC8536		0x0051
-#define PCI_DEVICE_ID_MPC8641		0x7010
-#define PCI_DEVICE_ID_MPC8641D		0x7011
-#define PCI_DEVICE_ID_MPC8610		0x7018
-
-#define PCI_VENDOR_ID_PASEMI		0x1959
-
-#define PCI_VENDOR_ID_ATTANSIC		0x1969
-#define PCI_DEVICE_ID_ATTANSIC_L1	0x1048
-#define PCI_DEVICE_ID_ATTANSIC_L2	0x2048
-
-#define PCI_VENDOR_ID_JMICRON		0x197B
-#define PCI_DEVICE_ID_JMICRON_JMB360	0x2360
-#define PCI_DEVICE_ID_JMICRON_JMB361	0x2361
-#define PCI_DEVICE_ID_JMICRON_JMB363	0x2363
-#define PCI_DEVICE_ID_JMICRON_JMB365	0x2365
-#define PCI_DEVICE_ID_JMICRON_JMB366	0x2366
-#define PCI_DEVICE_ID_JMICRON_JMB368	0x2368
-#define PCI_DEVICE_ID_JMICRON_JMB38X_SD	0x2381
-#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
-#define PCI_DEVICE_ID_JMICRON_JMB38X_MS	0x2383
-
-#define PCI_VENDOR_ID_KORENIX		0x1982
-#define PCI_DEVICE_ID_KORENIX_JETCARDF0	0x1600
-#define PCI_DEVICE_ID_KORENIX_JETCARDF1	0x16ff
-
-#define PCI_VENDOR_ID_TEKRAM		0x1de1
-#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
-
-#define PCI_VENDOR_ID_TEHUTI		0x1fc9
-#define PCI_DEVICE_ID_TEHUTI_3009	0x3009
-#define PCI_DEVICE_ID_TEHUTI_3010	0x3010
-#define PCI_DEVICE_ID_TEHUTI_3014	0x3014
-
-#define PCI_VENDOR_ID_HINT             0x3388
-#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
-
-#define PCI_VENDOR_ID_3DLABS		0x3d3d
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V	0x0009
-
-#define PCI_VENDOR_ID_NETXEN		0x4040
-#define PCI_DEVICE_ID_NX2031_10GXSR	0x0001
-#define PCI_DEVICE_ID_NX2031_10GCX4	0x0002
-#define PCI_DEVICE_ID_NX2031_4GCU	0x0003
-#define PCI_DEVICE_ID_NX2031_IMEZ	0x0004
-#define PCI_DEVICE_ID_NX2031_HMEZ	0x0005
-#define PCI_DEVICE_ID_NX2031_XG_MGMT	0x0024
-#define PCI_DEVICE_ID_NX2031_XG_MGMT2	0x0025
-#define PCI_DEVICE_ID_NX3031		0x0100
-
-#define PCI_VENDOR_ID_AKS		0x416c
-#define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
-
-#define PCI_VENDOR_ID_S3		0x5333
-#define PCI_DEVICE_ID_S3_TRIO		0x8811
-#define PCI_DEVICE_ID_S3_868		0x8880
-#define PCI_DEVICE_ID_S3_968		0x88f0
-#define PCI_DEVICE_ID_S3_SAVAGE4	0x8a25
-#define PCI_DEVICE_ID_S3_PROSAVAGE8	0x8d04
-#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
-
-#define PCI_VENDOR_ID_DUNORD		0x5544
-#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
-
-#define PCI_VENDOR_ID_DCI		0x6666
-#define PCI_DEVICE_ID_DCI_PCCOM4	0x0001
-#define PCI_DEVICE_ID_DCI_PCCOM8	0x0002
-#define PCI_DEVICE_ID_DCI_PCCOM2	0x0004
-
-#define PCI_VENDOR_ID_INTEL		0x8086
-#define PCI_DEVICE_ID_INTEL_EESSC	0x0008
-#define PCI_DEVICE_ID_INTEL_PXHD_0	0x0320
-#define PCI_DEVICE_ID_INTEL_PXHD_1	0x0321
-#define PCI_DEVICE_ID_INTEL_PXH_0	0x0329
-#define PCI_DEVICE_ID_INTEL_PXH_1	0x032A
-#define PCI_DEVICE_ID_INTEL_PXHV	0x032C
-#define PCI_DEVICE_ID_INTEL_82375	0x0482
-#define PCI_DEVICE_ID_INTEL_82424	0x0483
-#define PCI_DEVICE_ID_INTEL_82378	0x0484
-#define PCI_DEVICE_ID_INTEL_I960	0x0960
-#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
-#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
-#define PCI_DEVICE_ID_INTEL_82815_CGC	0x1132
-#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
-#define PCI_DEVICE_ID_INTEL_7505_0	0x2550  
-#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
-#define PCI_DEVICE_ID_INTEL_82437	0x122d
-#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
-#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
-#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
-#define PCI_DEVICE_ID_INTEL_82441	0x1237
-#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
-#define PCI_DEVICE_ID_INTEL_82439	0x1250
-#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
-#define PCI_DEVICE_ID_INTEL_82840_HB	0x1a21
-#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
-#define PCI_DEVICE_ID_INTEL_IOAT	0x1a38
-#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
-#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
-#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
-#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
-#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
-#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
-#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
-#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
-#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
-#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
-#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
-#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
-#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
-#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
-#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
-#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
-#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
-#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
-#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
-#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
-#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
-#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
-#define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
-#define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483
-#define PCI_DEVICE_ID_INTEL_82801CA_5	0x2485
-#define PCI_DEVICE_ID_INTEL_82801CA_6	0x2486
-#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
-#define PCI_DEVICE_ID_INTEL_82801CA_11	0x248b
-#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
-#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
-#define PCI_DEVICE_ID_INTEL_82801DB_1	0x24c1
-#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
-#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
-#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DB_9	0x24c9
-#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
-#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
-#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
-#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
-#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
-#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
-#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
-#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
-#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
-#define PCI_DEVICE_ID_INTEL_82801EB_12	0x24dc
-#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
-#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
-#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
-#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
-#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
-#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
-#define PCI_DEVICE_ID_INTEL_82820_HB	0x2500
-#define PCI_DEVICE_ID_INTEL_82820_UP_HB	0x2501
-#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
-#define PCI_DEVICE_ID_INTEL_82860_HB	0x2531
-#define PCI_DEVICE_ID_INTEL_E7501_MCH	0x254c
-#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
-#define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562
-#define PCI_DEVICE_ID_INTEL_82865_HB	0x2570
-#define PCI_DEVICE_ID_INTEL_82865_IG	0x2572
-#define PCI_DEVICE_ID_INTEL_82875_HB	0x2578
-#define PCI_DEVICE_ID_INTEL_82915G_HB	0x2580
-#define PCI_DEVICE_ID_INTEL_82915G_IG	0x2582
-#define PCI_DEVICE_ID_INTEL_82915GM_HB	0x2590
-#define PCI_DEVICE_ID_INTEL_82915GM_IG	0x2592
-#define PCI_DEVICE_ID_INTEL_5000_ERR	0x25F0
-#define PCI_DEVICE_ID_INTEL_5000_FBD0	0x25F5
-#define PCI_DEVICE_ID_INTEL_5000_FBD1	0x25F6
-#define PCI_DEVICE_ID_INTEL_82945G_HB	0x2770
-#define PCI_DEVICE_ID_INTEL_82945G_IG	0x2772
-#define PCI_DEVICE_ID_INTEL_3000_HB	0x2778
-#define PCI_DEVICE_ID_INTEL_82945GM_HB	0x27A0
-#define PCI_DEVICE_ID_INTEL_82945GM_IG	0x27A2
-#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
-#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
-#define PCI_DEVICE_ID_INTEL_ICH6_2	0x2642
-#define PCI_DEVICE_ID_INTEL_ICH6_16	0x266a
-#define PCI_DEVICE_ID_INTEL_ICH6_17	0x266d
-#define PCI_DEVICE_ID_INTEL_ICH6_18	0x266e
-#define PCI_DEVICE_ID_INTEL_ICH6_19	0x266f
-#define PCI_DEVICE_ID_INTEL_ESB2_0	0x2670
-#define PCI_DEVICE_ID_INTEL_ESB2_14	0x2698
-#define PCI_DEVICE_ID_INTEL_ESB2_17	0x269b
-#define PCI_DEVICE_ID_INTEL_ESB2_18	0x269e
-#define PCI_DEVICE_ID_INTEL_ICH7_0	0x27b8
-#define PCI_DEVICE_ID_INTEL_ICH7_1	0x27b9
-#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0
-#define PCI_DEVICE_ID_INTEL_ICH7_31	0x27bd
-#define PCI_DEVICE_ID_INTEL_ICH7_17	0x27da
-#define PCI_DEVICE_ID_INTEL_ICH7_19	0x27dd
-#define PCI_DEVICE_ID_INTEL_ICH7_20	0x27de
-#define PCI_DEVICE_ID_INTEL_ICH7_21	0x27df
-#define PCI_DEVICE_ID_INTEL_ICH8_0	0x2810
-#define PCI_DEVICE_ID_INTEL_ICH8_1	0x2811
-#define PCI_DEVICE_ID_INTEL_ICH8_2	0x2812
-#define PCI_DEVICE_ID_INTEL_ICH8_3	0x2814
-#define PCI_DEVICE_ID_INTEL_ICH8_4	0x2815
-#define PCI_DEVICE_ID_INTEL_ICH8_5	0x283e
-#define PCI_DEVICE_ID_INTEL_ICH8_6	0x2850
-#define PCI_DEVICE_ID_INTEL_ICH9_0	0x2910
-#define PCI_DEVICE_ID_INTEL_ICH9_1	0x2917
-#define PCI_DEVICE_ID_INTEL_ICH9_2	0x2912
-#define PCI_DEVICE_ID_INTEL_ICH9_3	0x2913
-#define PCI_DEVICE_ID_INTEL_ICH9_4	0x2914
-#define PCI_DEVICE_ID_INTEL_ICH9_5	0x2919
-#define PCI_DEVICE_ID_INTEL_ICH9_6	0x2930
-#define PCI_DEVICE_ID_INTEL_ICH9_7	0x2916
-#define PCI_DEVICE_ID_INTEL_ICH9_8	0x2918
-#define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG4	0x3429
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG5	0x342a
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG6	0x342b
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG7	0x342c
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG0	0x3430
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG1	0x3431
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG2	0x3432
-#define PCI_DEVICE_ID_INTEL_IOAT_TBG3	0x3433
-#define PCI_DEVICE_ID_INTEL_82830_HB	0x3575
-#define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577
-#define PCI_DEVICE_ID_INTEL_82855GM_HB	0x3580
-#define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582
-#define PCI_DEVICE_ID_INTEL_E7520_MCH	0x3590
-#define PCI_DEVICE_ID_INTEL_E7320_MCH	0x3592
-#define PCI_DEVICE_ID_INTEL_MCH_PA	0x3595
-#define PCI_DEVICE_ID_INTEL_MCH_PA1	0x3596
-#define PCI_DEVICE_ID_INTEL_MCH_PB	0x3597
-#define PCI_DEVICE_ID_INTEL_MCH_PB1	0x3598
-#define PCI_DEVICE_ID_INTEL_MCH_PC	0x3599
-#define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a
-#define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e
-#define PCI_DEVICE_ID_INTEL_IOAT_CNB	0x360b
-#define PCI_DEVICE_ID_INTEL_FBD_CNB	0x360c
-#define PCI_DEVICE_ID_INTEL_ICH10_0	0x3a14
-#define PCI_DEVICE_ID_INTEL_ICH10_1	0x3a16
-#define PCI_DEVICE_ID_INTEL_ICH10_2	0x3a18
-#define PCI_DEVICE_ID_INTEL_ICH10_3	0x3a1a
-#define PCI_DEVICE_ID_INTEL_ICH10_4	0x3a30
-#define PCI_DEVICE_ID_INTEL_ICH10_5	0x3a60
-#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN	0x3b00
-#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX	0x3b1f
-#define PCI_DEVICE_ID_INTEL_PCH_SMBUS	0x3b30
-#define PCI_DEVICE_ID_INTEL_IOAT_SNB	0x402f
-#define PCI_DEVICE_ID_INTEL_5100_16	0x65f0
-#define PCI_DEVICE_ID_INTEL_5100_21	0x65f5
-#define PCI_DEVICE_ID_INTEL_5100_22	0x65f6
-#define PCI_DEVICE_ID_INTEL_5400_ERR	0x4030
-#define PCI_DEVICE_ID_INTEL_5400_FBD0	0x4035
-#define PCI_DEVICE_ID_INTEL_5400_FBD1	0x4036
-#define PCI_DEVICE_ID_INTEL_IOAT_SCNB	0x65ff
-#define PCI_DEVICE_ID_INTEL_TOLAPAI_0	0x5031
-#define PCI_DEVICE_ID_INTEL_TOLAPAI_1	0x5032
-#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
-#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
-#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
-#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
-#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
-#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
-#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
-#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
-#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
-#define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
-#define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
-#define PCI_DEVICE_ID_INTEL_82810_MC3	0x7122
-#define PCI_DEVICE_ID_INTEL_82810_IG3	0x7123
-#define PCI_DEVICE_ID_INTEL_82810E_MC	0x7124
-#define PCI_DEVICE_ID_INTEL_82810E_IG	0x7125
-#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
-#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
-#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
-#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
-#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
-#define PCI_DEVICE_ID_INTEL_440MX	0x7195
-#define PCI_DEVICE_ID_INTEL_440MX_6	0x7196
-#define PCI_DEVICE_ID_INTEL_82443MX_0	0x7198
-#define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
-#define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
-#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
-#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
-#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
-#define PCI_DEVICE_ID_INTEL_SCH_LPC	0x8119
-#define PCI_DEVICE_ID_INTEL_SCH_IDE	0x811a
-#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
-#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
-#define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
-#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
-#define PCI_DEVICE_ID_INTEL_84460GX	0x84ea
-#define PCI_DEVICE_ID_INTEL_IXP4XX	0x8500
-#define PCI_DEVICE_ID_INTEL_IXP2800	0x9004
-#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152
-
-#define PCI_VENDOR_ID_SCALEMP		0x8686
-#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL	0x1010
-
-#define PCI_VENDOR_ID_COMPUTONE		0x8e0e
-#define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
-#define PCI_DEVICE_ID_COMPUTONE_PG	0x0302
-#define PCI_SUBVENDOR_ID_COMPUTONE	0x8e0e
-#define PCI_SUBDEVICE_ID_COMPUTONE_PG4	0x0001
-#define PCI_SUBDEVICE_ID_COMPUTONE_PG8	0x0002
-#define PCI_SUBDEVICE_ID_COMPUTONE_PG6	0x0003
-
-#define PCI_VENDOR_ID_KTI		0x8e2e
-
-#define PCI_VENDOR_ID_ADAPTEC		0x9004
-#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
-#define PCI_DEVICE_ID_ADAPTEC_7821	0x2178
-#define PCI_DEVICE_ID_ADAPTEC_38602	0x3860
-#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
-#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
-#define PCI_DEVICE_ID_ADAPTEC_3860	0x6038
-#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
-#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
-#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
-#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
-#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
-#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
-#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
-#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
-#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
-#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
-#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
-#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
-#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
-#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
-#define PCI_DEVICE_ID_ADAPTEC_7885	0x8578
-#define PCI_DEVICE_ID_ADAPTEC_7886	0x8678
-#define PCI_DEVICE_ID_ADAPTEC_7887	0x8778
-#define PCI_DEVICE_ID_ADAPTEC_7888	0x8878
-
-#define PCI_VENDOR_ID_ADAPTEC2		0x9005
-#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
-#define PCI_DEVICE_ID_ADAPTEC2_2930U2	0x0011
-#define PCI_DEVICE_ID_ADAPTEC2_7890B	0x0013
-#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
-#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
-#define PCI_DEVICE_ID_ADAPTEC2_3950U2D	0x0051
-#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
-#define PCI_DEVICE_ID_ADAPTEC2_7892A	0x0080
-#define PCI_DEVICE_ID_ADAPTEC2_7892B	0x0081
-#define PCI_DEVICE_ID_ADAPTEC2_7892D	0x0083
-#define PCI_DEVICE_ID_ADAPTEC2_7892P	0x008f
-#define PCI_DEVICE_ID_ADAPTEC2_7899A	0x00c0
-#define PCI_DEVICE_ID_ADAPTEC2_7899B	0x00c1
-#define PCI_DEVICE_ID_ADAPTEC2_7899D	0x00c3
-#define PCI_DEVICE_ID_ADAPTEC2_7899P	0x00cf
-#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN   0x0500
-#define PCI_DEVICE_ID_ADAPTEC2_SCAMP	0x0503
-
-#define PCI_VENDOR_ID_HOLTEK		0x9412
-#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
-
-#define PCI_VENDOR_ID_NETMOS		0x9710
-#define PCI_DEVICE_ID_NETMOS_9705	0x9705
-#define PCI_DEVICE_ID_NETMOS_9715	0x9715
-#define PCI_DEVICE_ID_NETMOS_9735	0x9735
-#define PCI_DEVICE_ID_NETMOS_9745	0x9745
-#define PCI_DEVICE_ID_NETMOS_9755	0x9755
-#define PCI_DEVICE_ID_NETMOS_9805	0x9805
-#define PCI_DEVICE_ID_NETMOS_9815	0x9815
-#define PCI_DEVICE_ID_NETMOS_9835	0x9835
-#define PCI_DEVICE_ID_NETMOS_9845	0x9845
-#define PCI_DEVICE_ID_NETMOS_9855	0x9855
-
-#define PCI_VENDOR_ID_3COM_2		0xa727
-
-#define PCI_VENDOR_ID_DIGIUM		0xd161
-#define PCI_DEVICE_ID_DIGIUM_HFC4S	0xb410
-
-#define PCI_SUBVENDOR_ID_EXSYS		0xd84d
-#define PCI_SUBDEVICE_ID_EXSYS_4014	0x4014
-#define PCI_SUBDEVICE_ID_EXSYS_4055	0x4055
-
-#define PCI_VENDOR_ID_TIGERJET		0xe159
-#define PCI_DEVICE_ID_TIGERJET_300	0x0001
-#define PCI_DEVICE_ID_TIGERJET_100	0x0002
-
-#define PCI_VENDOR_ID_XILINX_RME	0xea60
-#define PCI_DEVICE_ID_RME_DIGI32	0x9896
-#define PCI_DEVICE_ID_RME_DIGI32_PRO	0x9897
-#define PCI_DEVICE_ID_RME_DIGI32_8	0x9898
-
-#define PCI_VENDOR_ID_REDHAT_QUMRANET	0x1af4
-#define PCI_DEVICE_ID_VIRTIO_BLK	0x1001
diff --git a/qemu/roms/qemu-palcode/pci_regs.h b/qemu/roms/qemu-palcode/pci_regs.h
deleted file mode 100644
index e9f070fdb..000000000
--- a/qemu/roms/qemu-palcode/pci_regs.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- *	pci_regs.h
- *
- *	PCI standard defines
- *	Copyright 1994, Drew Eckhardt
- *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
- *
- *	For more information, please consult the following manuals (look at
- *	http://www.pcisig.com/ for how to get them):
- *
- *	PCI BIOS Specification
- *	PCI Local Bus Specification
- *	PCI to PCI Bridge Specification
- *	PCI System Design Guide
- *
- * 	For hypertransport information, please consult the following manuals
- * 	from http://www.hypertransport.org
- *
- *	The Hypertransport I/O Link Specification
- */
-
-#ifndef LINUX_PCI_REGS_H
-#define LINUX_PCI_REGS_H
-
-/*
- * Under PCI, each device has 256 bytes of configuration address space,
- * of which the first 64 bytes are standardized as follows:
- */
-#define PCI_VENDOR_ID		0x00	/* 16 bits */
-#define PCI_DEVICE_ID		0x02	/* 16 bits */
-#define PCI_COMMAND		0x04	/* 16 bits */
-#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
-#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
-#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
-#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
-#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
-#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
-#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
-#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
-#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
-#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
-#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
-
-#define PCI_STATUS		0x06	/* 16 bits */
-#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
-#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
-#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
-#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
-#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
-#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST		0x000
-#define  PCI_STATUS_DEVSEL_MEDIUM	0x200
-#define  PCI_STATUS_DEVSEL_SLOW		0x400
-#define  PCI_STATUS_SIG_TARGET_ABORT	0x800 /* Set on target abort */
-#define  PCI_STATUS_REC_TARGET_ABORT	0x1000 /* Master ack of " */
-#define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
-#define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
-#define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
-
-#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8 revision */
-#define PCI_REVISION_ID		0x08	/* Revision ID */
-#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE	0x0a	/* Device class */
-
-#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
-#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
-#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
-#define  PCI_HEADER_TYPE_NORMAL		0
-#define  PCI_HEADER_TYPE_BRIDGE		1
-#define  PCI_HEADER_TYPE_CARDBUS	2
-
-#define PCI_BIST		0x0f	/* 8 bits */
-#define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
-#define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
-#define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
-
-/*
- * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of
- * 0xffffffff to the register, and reading it back.  Only
- * 1 bits are decoded.
- */
-#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
-#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
-#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
-#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
-#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
-#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
-#define  PCI_BASE_ADDRESS_SPACE		0x01	/* 0 = memory, 1 = I/O */
-#define  PCI_BASE_ADDRESS_SPACE_IO	0x01
-#define  PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
-#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x06
-#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
-#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
-#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fU)
-#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03U)
-/* bit 1 is reserved if address_space = 1 */
-
-/* Header type 0 (normal devices) */
-#define PCI_CARDBUS_CIS		0x28
-#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
-#define PCI_SUBSYSTEM_ID	0x2e
-#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
-#define  PCI_ROM_ADDRESS_ENABLE	0x01
-#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
-
-#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
-
-/* 0x35-0x3b are reserved */
-#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
-#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
-#define PCI_MIN_GNT		0x3e	/* 8 bits */
-#define PCI_MAX_LAT		0x3f	/* 8 bits */
-
-/* Header type 1 (PCI-to-PCI bridges) */
-#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
-#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
-#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
-#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
-#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
-#define PCI_IO_LIMIT		0x1d
-#define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
-#define  PCI_IO_RANGE_TYPE_16	0x00
-#define  PCI_IO_RANGE_TYPE_32	0x01
-#define  PCI_IO_RANGE_MASK	(~0x0fUL)
-#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
-#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
-#define PCI_MEMORY_LIMIT	0x22
-#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
-#define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
-#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
-#define PCI_PREF_MEMORY_LIMIT	0x26
-#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
-#define  PCI_PREF_RANGE_TYPE_32	0x00
-#define  PCI_PREF_RANGE_TYPE_64	0x01
-#define  PCI_PREF_RANGE_MASK	(~0x0fUL)
-#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
-#define PCI_PREF_LIMIT_UPPER32	0x2c
-#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
-#define PCI_IO_LIMIT_UPPER16	0x32
-/* 0x34 same as for htype 0 */
-/* 0x35-0x3b is reserved */
-#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_BRIDGE_CONTROL	0x3e
-#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
-#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
-#define  PCI_BRIDGE_CTL_ISA	0x04	/* Enable ISA mode */
-#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
-#define  PCI_BRIDGE_CTL_MASTER_ABORT	0x20  /* Report master aborts */
-#define  PCI_BRIDGE_CTL_BUS_RESET	0x40	/* Secondary bus reset */
-#define  PCI_BRIDGE_CTL_FAST_BACK	0x80	/* Fast Back2Back enabled on secondary interface */
-
-/* Header type 2 (CardBus bridges) */
-#define PCI_CB_CAPABILITY_LIST	0x14
-/* 0x15 reserved */
-#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
-#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
-#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
-#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
-#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
-#define PCI_CB_MEMORY_BASE_0	0x1c
-#define PCI_CB_MEMORY_LIMIT_0	0x20
-#define PCI_CB_MEMORY_BASE_1	0x24
-#define PCI_CB_MEMORY_LIMIT_1	0x28
-#define PCI_CB_IO_BASE_0	0x2c
-#define PCI_CB_IO_BASE_0_HI	0x2e
-#define PCI_CB_IO_LIMIT_0	0x30
-#define PCI_CB_IO_LIMIT_0_HI	0x32
-#define PCI_CB_IO_BASE_1	0x34
-#define PCI_CB_IO_BASE_1_HI	0x36
-#define PCI_CB_IO_LIMIT_1	0x38
-#define PCI_CB_IO_LIMIT_1_HI	0x3a
-#define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_CB_BRIDGE_CONTROL	0x3e
-#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
-#define  PCI_CB_BRIDGE_CTL_SERR		0x02
-#define  PCI_CB_BRIDGE_CTL_ISA		0x04
-#define  PCI_CB_BRIDGE_CTL_VGA		0x08
-#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
-#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
-#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
-#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
-#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
-#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
-#define PCI_CB_SUBSYSTEM_VENDOR_ID	0x40
-#define PCI_CB_SUBSYSTEM_ID		0x42
-#define PCI_CB_LEGACY_MODE_BASE		0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
-/* 0x48-0x7f reserved */
-
-/* Capability lists */
-
-#define PCI_CAP_LIST_ID		0	/* Capability ID */
-#define  PCI_CAP_ID_PM		0x01	/* Power Management */
-#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
-#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
-#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
-#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
-#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
-#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
-#define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
-#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific */
-#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
-#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
-#define  PCI_CAP_ID_SHPC 	0x0C	/* PCI Standard Hot-Plug Controller */
-#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
-#define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
-#define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
-#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
-#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
-#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
-#define PCI_CAP_SIZEOF		4
-
-/* Power Management Registers */
-
-#define PCI_PM_PMC		2	/* PM Capabilities Register */
-#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
-#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
-#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
-#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
-#define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxilliary power support mask */
-#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
-#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
-#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
-#define  PCI_PM_CAP_PME_MASK	0xF800	/* PME Mask of all supported states */
-#define  PCI_PM_CAP_PME_D0	0x0800	/* PME# from D0 */
-#define  PCI_PM_CAP_PME_D1	0x1000	/* PME# from D1 */
-#define  PCI_PM_CAP_PME_D2	0x2000	/* PME# from D2 */
-#define  PCI_PM_CAP_PME_D3	0x4000	/* PME# from D3 (hot) */
-#define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
-#define  PCI_PM_CAP_PME_SHIFT	11	/* Start of the PME Mask in PMC */
-#define PCI_PM_CTRL		4	/* PM control and status register */
-#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
-#define  PCI_PM_CTRL_NO_SOFT_RESET	0x0004	/* No reset for D3hot->D0 */
-#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
-#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
-#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
-#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
-#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
-#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
-#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
-#define PCI_PM_DATA_REGISTER	7	/* (??) */
-#define PCI_PM_SIZEOF		8
-
-/* AGP registers */
-
-#define PCI_AGP_VERSION		2	/* BCD version number */
-#define PCI_AGP_RFU		3	/* Rest of capability flags */
-#define PCI_AGP_STATUS		4	/* Status register */
-#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
-#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
-#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
-#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
-#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
-#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
-#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
-#define PCI_AGP_COMMAND		8	/* Control register */
-#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
-#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
-#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
-#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
-#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
-#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
-#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
-#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
-#define PCI_AGP_SIZEOF		12
-
-/* Vital Product Data */
-
-#define PCI_VPD_ADDR		2	/* Address to access (15 bits!) */
-#define  PCI_VPD_ADDR_MASK	0x7fff	/* Address mask */
-#define  PCI_VPD_ADDR_F		0x8000	/* Write 0, 1 indicates completion */
-#define PCI_VPD_DATA		4	/* 32-bits of data returned here */
-
-/* Slot Identification */
-
-#define PCI_SID_ESR		2	/* Expansion Slot Register */
-#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
-#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
-#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
-
-/* Message Signalled Interrupts registers */
-
-#define PCI_MSI_FLAGS		2	/* Various flags */
-#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
-#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
-#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
-#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
-#define  PCI_MSI_FLAGS_MASKBIT	0x100	/* 64-bit mask bits allowed */
-#define PCI_MSI_RFU		3	/* Rest of capability flags */
-#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
-#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
-#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
-#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
-#define PCI_MSI_MASK_BIT	16	/* Mask bits register */
-
-/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
-#define PCI_MSIX_FLAGS		2
-#define  PCI_MSIX_FLAGS_QSIZE	0x7FF
-#define  PCI_MSIX_FLAGS_ENABLE	(1 << 15)
-#define  PCI_MSIX_FLAGS_MASKALL	(1 << 14)
-#define PCI_MSIX_FLAGS_BIRMASK	(7 << 0)
-#define PCI_MSIX_FLAGS_BITMASK	(1 << 0)
-
-/* CompactPCI Hotswap Register */
-
-#define PCI_CHSWP_CSR		2	/* Control and Status Register */
-#define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
-#define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
-#define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
-#define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
-#define  PCI_CHSWP_PI		0x30	/* Programming Interface */
-#define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
-#define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
-
-/* PCI-X registers */
-
-#define PCI_X_CMD		2	/* Modes & Features */
-#define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
-#define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
-#define  PCI_X_CMD_READ_512	0x0000	/* 512 byte maximum read byte count */
-#define  PCI_X_CMD_READ_1K	0x0004	/* 1Kbyte maximum read byte count */
-#define  PCI_X_CMD_READ_2K	0x0008	/* 2Kbyte maximum read byte count */
-#define  PCI_X_CMD_READ_4K	0x000c	/* 4Kbyte maximum read byte count */
-#define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
-				/* Max # of outstanding split transactions */
-#define  PCI_X_CMD_SPLIT_1	0x0000	/* Max 1 */
-#define  PCI_X_CMD_SPLIT_2	0x0010	/* Max 2 */
-#define  PCI_X_CMD_SPLIT_3	0x0020	/* Max 3 */
-#define  PCI_X_CMD_SPLIT_4	0x0030	/* Max 4 */
-#define  PCI_X_CMD_SPLIT_8	0x0040	/* Max 8 */
-#define  PCI_X_CMD_SPLIT_12	0x0050	/* Max 12 */
-#define  PCI_X_CMD_SPLIT_16	0x0060	/* Max 16 */
-#define  PCI_X_CMD_SPLIT_32	0x0070	/* Max 32 */
-#define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
-#define  PCI_X_CMD_VERSION(x) 	(((x) >> 12) & 3) /* Version */
-#define PCI_X_STATUS		4	/* PCI-X capabilities */
-#define  PCI_X_STATUS_DEVFN	0x000000ff	/* A copy of devfn */
-#define  PCI_X_STATUS_BUS	0x0000ff00	/* A copy of bus nr */
-#define  PCI_X_STATUS_64BIT	0x00010000	/* 64-bit device */
-#define  PCI_X_STATUS_133MHZ	0x00020000	/* 133 MHz capable */
-#define  PCI_X_STATUS_SPL_DISC	0x00040000	/* Split Completion Discarded */
-#define  PCI_X_STATUS_UNX_SPL	0x00080000	/* Unexpected Split Completion */
-#define  PCI_X_STATUS_COMPLEX	0x00100000	/* Device Complexity */
-#define  PCI_X_STATUS_MAX_READ	0x00600000	/* Designed Max Memory Read Count */
-#define  PCI_X_STATUS_MAX_SPLIT	0x03800000	/* Designed Max Outstanding Split Transactions */
-#define  PCI_X_STATUS_MAX_CUM	0x1c000000	/* Designed Max Cumulative Read Size */
-#define  PCI_X_STATUS_SPL_ERR	0x20000000	/* Rcvd Split Completion Error Msg */
-#define  PCI_X_STATUS_266MHZ	0x40000000	/* 266 MHz capable */
-#define  PCI_X_STATUS_533MHZ	0x80000000	/* 533 MHz capable */
-
-/* PCI Express capability registers */
-
-#define PCI_EXP_FLAGS		2	/* Capabilities register */
-#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
-#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
-#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
-#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
-#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
-#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
-#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
-#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
-#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
-#define PCI_EXP_DEVCAP		4	/* Device capabilities */
-#define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
-#define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
-#define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
-#define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
-#define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
-#define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
-#define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
-#define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
-#define  PCI_EXP_DEVCAP_RBER	0x8000	/* Role-Based Error Reporting */
-#define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
-#define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
-#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
-#define PCI_EXP_DEVCTL		8	/* Device Control */
-#define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
-#define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
-#define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
-#define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
-#define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
-#define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
-#define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
-#define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
-#define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
-#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
-#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
-#define PCI_EXP_DEVSTA		10	/* Device Status */
-#define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
-#define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
-#define  PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Request Detected */
-#define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
-#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
-#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
-#define  PCI_EXP_LNKCAP_ASPMS	0xc00	/* ASPM Support */
-#define  PCI_EXP_LNKCAP_L0SEL	0x7000	/* L0s Exit Latency */
-#define  PCI_EXP_LNKCAP_L1EL	0x38000	/* L1 Exit Latency */
-#define  PCI_EXP_LNKCAP_CLKPM	0x40000	/* L1 Clock Power Management */
-#define PCI_EXP_LNKCTL		16	/* Link Control */
-#define  PCI_EXP_LNKCTL_RL	0x20	/* Retrain Link */
-#define  PCI_EXP_LNKCTL_CCC	0x40	/* Common Clock COnfiguration */
-#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100	/* Enable clkreq */
-#define PCI_EXP_LNKSTA		18	/* Link Status */
-#define  PCI_EXP_LNKSTA_LT	0x800	/* Link Training */
-#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
-#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
-#define PCI_EXP_SLTCTL		24	/* Slot Control */
-#define PCI_EXP_SLTSTA		26	/* Slot Status */
-#define PCI_EXP_RTCTL		28	/* Root Control */
-#define  PCI_EXP_RTCTL_SECEE	0x01	/* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE	0x02	/* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE	0x04	/* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE	0x08	/* PME Interrupt Enable */
-#define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
-#define PCI_EXP_RTCAP		30	/* Root Capabilities */
-#define PCI_EXP_RTSTA		32	/* Root Status */
-#define PCI_EXP_DEVCAP2		36	/* Device Capabilities 2 */
-#define  PCI_EXP_DEVCAP2_ARI	0x20	/* Alternative Routing-ID */
-#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
-#define  PCI_EXP_DEVCTL2_ARI	0x20	/* Alternative Routing-ID */
-
-/* Extended Capabilities (PCI-X 2.0 and Express) */
-#define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
-#define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
-#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
-
-#define PCI_EXT_CAP_ID_ERR	1
-#define PCI_EXT_CAP_ID_VC	2
-#define PCI_EXT_CAP_ID_DSN	3
-#define PCI_EXT_CAP_ID_PWR	4
-#define PCI_EXT_CAP_ID_ARI	14
-
-/* Advanced Error Reporting */
-#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
-#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
-#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
-#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
-#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
-#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
-#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
-#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
-#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
-#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
-#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
-#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
-#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
-	/* Same bits as above */
-#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
-	/* Same bits as above */
-#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
-#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
-#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
-#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
-#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
-#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
-#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
-	/* Same bits as above */
-#define PCI_ERR_CAP		24	/* Advanced Error Capabilities */
-#define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
-#define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
-#define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
-#define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
-#define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
-#define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
-#define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
-/* Correctable Err Reporting Enable */
-#define PCI_ERR_ROOT_CMD_COR_EN		0x00000001
-/* Non-fatal Err Reporting Enable */
-#define PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002
-/* Fatal Err Reporting Enable */
-#define PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004
-#define PCI_ERR_ROOT_STATUS	48
-#define PCI_ERR_ROOT_COR_RCV		0x00000001	/* ERR_COR Received */
-/* Multi ERR_COR Received */
-#define PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002
-/* ERR_FATAL/NONFATAL Recevied */
-#define PCI_ERR_ROOT_UNCOR_RCV		0x00000004
-/* Multi ERR_FATAL/NONFATAL Recevied */
-#define PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008
-#define PCI_ERR_ROOT_FIRST_FATAL	0x00000010	/* First Fatal */
-#define PCI_ERR_ROOT_NONFATAL_RCV	0x00000020	/* Non-Fatal Received */
-#define PCI_ERR_ROOT_FATAL_RCV		0x00000040	/* Fatal Received */
-#define PCI_ERR_ROOT_COR_SRC	52
-#define PCI_ERR_ROOT_SRC	54
-
-/* Virtual Channel */
-#define PCI_VC_PORT_REG1	4
-#define PCI_VC_PORT_REG2	8
-#define PCI_VC_PORT_CTRL	12
-#define PCI_VC_PORT_STATUS	14
-#define PCI_VC_RES_CAP		16
-#define PCI_VC_RES_CTRL		20
-#define PCI_VC_RES_STATUS	26
-
-/* Power Budgeting */
-#define PCI_PWR_DSR		4	/* Data Select Register */
-#define PCI_PWR_DATA		8	/* Data Register */
-#define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
-#define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
-#define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
-#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
-#define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
-#define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
-#define PCI_PWR_CAP		12	/* Capability */
-#define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
-
-/*
- * Hypertransport sub capability types
- *
- * Unfortunately there are both 3 bit and 5 bit capability types defined
- * in the HT spec, catering for that is a little messy. You probably don't
- * want to use these directly, just use pci_find_ht_capability() and it
- * will do the right thing for you.
- */
-#define HT_3BIT_CAP_MASK	0xE0
-#define HT_CAPTYPE_SLAVE	0x00	/* Slave/Primary link configuration */
-#define HT_CAPTYPE_HOST		0x20	/* Host/Secondary link configuration */
-
-#define HT_5BIT_CAP_MASK	0xF8
-#define HT_CAPTYPE_IRQ		0x80	/* IRQ Configuration */
-#define HT_CAPTYPE_REMAPPING_40	0xA0	/* 40 bit address remapping */
-#define HT_CAPTYPE_REMAPPING_64 0xA2	/* 64 bit address remapping */
-#define HT_CAPTYPE_UNITID_CLUMP	0x90	/* Unit ID clumping */
-#define HT_CAPTYPE_EXTCONF	0x98	/* Extended Configuration Space Access */
-#define HT_CAPTYPE_MSI_MAPPING	0xA8	/* MSI Mapping Capability */
-#define  HT_MSI_FLAGS		0x02		/* Offset to flags */
-#define  HT_MSI_FLAGS_ENABLE	0x1		/* Mapping enable */
-#define  HT_MSI_FLAGS_FIXED	0x2		/* Fixed mapping only */
-#define  HT_MSI_FIXED_ADDR	0x00000000FEE00000ULL	/* Fixed addr */
-#define  HT_MSI_ADDR_LO		0x04		/* Offset to low addr bits */
-#define  HT_MSI_ADDR_LO_MASK	0xFFF00000	/* Low address bit mask */
-#define  HT_MSI_ADDR_HI		0x08		/* Offset to high addr bits */
-#define HT_CAPTYPE_DIRECT_ROUTE	0xB0	/* Direct routing configuration */
-#define HT_CAPTYPE_VCSET	0xB8	/* Virtual Channel configuration */
-#define HT_CAPTYPE_ERROR_RETRY	0xC0	/* Retry on error configuration */
-#define HT_CAPTYPE_GEN3		0xD0	/* Generation 3 hypertransport configuration */
-#define HT_CAPTYPE_PM		0xE0	/* Hypertransport powermanagement configuration */
-
-/* Alternative Routing-ID Interpretation */
-#define PCI_ARI_CAP		0x04	/* ARI Capability Register */
-#define  PCI_ARI_CAP_MFVC	0x0001	/* MFVC Function Groups Capability */
-#define  PCI_ARI_CAP_ACS	0x0002	/* ACS Function Groups Capability */
-#define  PCI_ARI_CAP_NFN(x)	(((x) >> 8) & 0xff) /* Next Function Number */
-#define PCI_ARI_CTRL		0x06	/* ARI Control Register */
-#define  PCI_ARI_CTRL_MFVC	0x0001	/* MFVC Function Groups Enable */
-#define  PCI_ARI_CTRL_ACS	0x0002	/* ACS Function Groups Enable */
-#define  PCI_ARI_CTRL_FG(x)	(((x) >> 4) & 7) /* Function Group */
-
-#endif /* LINUX_PCI_REGS_H */
diff --git a/qemu/roms/qemu-palcode/printf.c b/qemu/roms/qemu-palcode/printf.c
deleted file mode 100644
index 469b82cd3..000000000
--- a/qemu/roms/qemu-palcode/printf.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* A reduced version of the printf function.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include <stdarg.h>
-#include <stdbool.h>
-#include <string.h>
-#include "console.h"
-
-static int print_buf_pad(char *buf, int buflen, char *p, int width, int pad)
-{
-  int len = buf + buflen - p;
-  int r = 0;
-
-  if (width > len)
-    {
-      *--p = pad;
-      len++;
-
-      while (width > buflen)
-	{
-	  crb_puts(0, p, 1);
-	  width--;
-	  r++;
-	}
-      while (width > len)
-	*--p = pad, len++;
-    }
-
-  crb_puts(0, p, len);
-  return r + len;
-}
-
-static int print_decimal(unsigned long val, int width, int pad)
-{
-  char buf[32];
-  char *p = buf + sizeof(buf);
-
-  if (val == 0)
-    *--p = '0';
-  else
-    {
-      do
-	{
-	  unsigned long d, r;
-
-	  /* Compiling with -Os results in a call to the division routine.
-	     Do what the compiler ought to have done.  */
-	  d = __builtin_alpha_umulh(val, 0xcccccccccccccccd);
-	  d >>= 3;
-	  r = val - (d * 10);
-
-	  *--p = r + '0';
-	  val = d;
-	}
-      while (val);
-    }
-
-  return print_buf_pad(buf, sizeof(buf), p, width, pad);
-}
-
-static int print_hex(unsigned long val, int width, char pad)
-{
-  char buf[32];
-  char *p = buf + sizeof(buf);
-
-  if (val == 0)
-    *--p = '0';
-  else
-    {
-      do
-	{
-	  int d = val % 16;
-	  *--p = (d < 10 ? '0' : 'a' - 10) + d;
-	  val /= 16;
-	}
-      while (val);
-    }
-
-  return print_buf_pad(buf, sizeof(buf), p, width, pad);
-}
-
-int printf(const char *fmt, ...)
-{
-  va_list args;
-  unsigned long val;
-  int r = 0;
-
-  va_start(args, fmt);
-
-  for (; *fmt ; fmt++)
-    if (*fmt != '%')
-      {
-        crb_puts(0, fmt, 1);
-	r++;
-      }
-    else
-      {
-        const char *percent = fmt;
-	bool is_long = false;
-        char pad = ' ';
-        int width = 0;
-
-      restart:
-        switch (*++fmt)
-	  {
-	  case '%':
-	    crb_puts(0, "%", 1);
-	    r++;
-	    break;
-
-	  case 'l':
-	    is_long = true;
-	    goto restart;
-
-	  case 'd':
-	    if (is_long)
-	      {
-		long d = va_arg (args, long);
-		if (d < 0)
-		  {
-		    crb_puts(0, "-", 1);
-		    d = -d;
-		  }
-		val = d;
-	      }
-	    else
-	      {
-		int d = va_arg (args, int);
-		if (d < 0)
-		  {
-		    crb_puts(0, "-", 1);
-		    d = -d;
-		    r++;
-		  }
-		val = d;
-	      }
-	    goto do_unsigned;
-
-	  case 'u':
-	    if (is_long)
-	      val = va_arg (args, unsigned long);
-	    else
-	      val = va_arg (args, unsigned int);
-
-	  do_unsigned:
-	    r += print_decimal (val, width, pad);
-	    break;
-
-	  case 'x':
-	    if (is_long)
-	      val = va_arg (args, unsigned long);
-	    else
-	      val = va_arg (args, unsigned int);
-	    r += print_hex (val, width, pad);
-	    break;
-
-	  case 's':
-	    {
-	      const char *s = va_arg (args, const char *);
-	      int len = strlen(s);
-	      crb_puts(0, s, len);
-	      r += len;
-	    }
-	    break;
-
-	  case '0':
-	    pad = '0';
-          case '1' ... '9':
-	    width = *fmt - '0';
-	    while (fmt[1] >= '0' && fmt[1] <= '9')
-	      width = width * 10 + *++fmt - '0';
-	    goto restart;
-
-	  default:
-	    {
-	      int len = fmt - percent;
-	      crb_puts(0, percent, len);
-	      r += len;
-	    }
-	    break;
-	  }
-      }
-
-  va_end(args);
-  return r;
-}
diff --git a/qemu/roms/qemu-palcode/protos.h b/qemu/roms/qemu-palcode/protos.h
deleted file mode 100644
index 3ed13811f..000000000
--- a/qemu/roms/qemu-palcode/protos.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Declarations common the the C portions of the QEMU PALcode console.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef PROTOS_H
-#define PROTOS_H 1
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <string.h>
-
-
-/*
- * Call_Pal functions.
- */
-
-static inline void wrent(void *cb, unsigned long which)
-{
-  register void *a0 __asm__("$16") = cb;
-  register unsigned long a1 __asm__("$17") = which;
-
-  asm volatile ("call_pal 0x34"
-		: "+r"(a0), "+r"(a1)
-		: : "$1", "$22", "$23", "$24", "$25");
-}
-
-static inline unsigned long swpipl(unsigned long newipl)
-{
-  register unsigned long v0 __asm__("$0");
-  register unsigned long a0 __asm__("$16") = newipl;
-
-  asm volatile ("call_pal 0x35"
-		: "=r"(v0), "+r"(a0)
-		: : "$1", "$22", "$23", "$24", "$25");
-
-  return v0;
-}
-
-static inline unsigned long rdps(void)
-{
-  register unsigned long v0 __asm__("$0");
-
-  asm volatile ("call_pal 0x36"
-		: "=r"(v0) : : "$1", "$22", "$23", "$24", "$25");
-
-  return v0;
-}
-
-static inline void wrkgp(void)
-{
-  asm volatile ("mov $29, $16\n\tcall_pal 0x37"
-		: : : "$16", "$1", "$22", "$23", "$24", "$25");
-}
-
-static inline unsigned long wtint(unsigned long skip)
-{
-  register unsigned long v0 __asm__("$0");
-  register unsigned long a0 __asm__("$16") = skip;
-
-  asm volatile ("call_pal 0x3e"
-		: "=r"(v0), "+r"(a0)
-		: : "$1", "$22", "$23", "$24", "$25");
-
-  return v0;
-}
-
-/* 
- * Cserve functions.
- */
-
-static inline unsigned long ldq_p(unsigned long addr)
-{
-  register unsigned long v0 __asm__("$0");
-  register unsigned long a0 __asm__("$16") = 1;
-  register unsigned long a1 __asm__("$17") = addr;
-
-  asm volatile ("call_pal 9"
-		: "=r"(v0), "+r"(a0), "+r"(a1) :
-		: "$18", "$19", "$20", "$21");
-
-  return v0;
-}
-
-static inline unsigned long stq_p(unsigned long port, unsigned long val)
-{
-  register unsigned long v0 __asm__("$0");
-  register unsigned long a0 __asm__("$16") = 2;
-  register unsigned long a1 __asm__("$17") = port;
-  register unsigned long a2 __asm__("$18") = val;
-
-  asm volatile ("call_pal 9"
-		: "=r"(v0), "+r"(a0), "+r"(a1), "+r"(a2) :
-		: "$19", "$20", "$21");
-
-  return v0;
-}
-
-static inline unsigned long get_wall_time(void)
-{
-  register unsigned long v0 __asm__("$0");
-  register unsigned long a0 __asm__("$16") = 3;
-
-  asm("call_pal 9" : "=r"(v0), "+r"(a0) : : "$17", "$18", "$19", "$20", "$21");
-
-  return v0;
-}
-
-static inline unsigned long get_alarm(void)
-{
-  register unsigned long v0 __asm__("$0");
-  register unsigned long a0 __asm__("$16") = 4;
-
-  asm("call_pal 9" : "=r"(v0), "+r"(a0) : : "$17", "$18", "$19", "$20", "$21");
-
-  return v0;
-}
-
-static inline void set_alarm_rel(unsigned long nsec)
-{
-  register unsigned long a0 __asm__("$16") = 5;
-  register unsigned long a1 __asm__("$17") = nsec;
-
-  asm volatile ("call_pal 9"
-		: "+r"(a0), "+r"(a1)
-		: : "$0", "$18", "$19", "$20", "$21");
-}
-
-static inline void set_alarm_abs(unsigned long nsec)
-{
-  register unsigned long a0 __asm__("$16") = 6;
-  register unsigned long a1 __asm__("$17") = nsec;
-
-  asm volatile ("call_pal 9"
-		: "+r"(a0), "+r"(a1)
-		: : "$0", "$18", "$19", "$20", "$21");
-}
-
-/*
- * I/O functions
- */
-
-extern void *pci_io_base;
-extern void *pci_mem_base;
-
-static inline uint8_t inb(unsigned long port)
-{
-  return *(volatile uint8_t *)(pci_io_base + port);
-}
-
-static inline uint16_t inw(unsigned long port)
-{
-  return *(volatile uint16_t *)(pci_io_base + port);
-}
-
-static inline uint32_t inl(unsigned long port)
-{
-  return *(volatile uint32_t *)(pci_io_base + port);
-}
-
-static inline void outb(uint8_t val, unsigned long port)
-{
-  *(volatile uint8_t *)(pci_io_base + port) = val;
-}
-
-static inline void outw(uint16_t val, unsigned long port)
-{
-  *(volatile uint16_t *)(pci_io_base + port) = val;
-}
-
-static inline void outl(uint32_t val, unsigned long port)
-{
-  *(volatile uint32_t *)(pci_io_base + port) = val;
-}
-
-/*
- * CRB functions
- */
-
-extern unsigned long crb_dispatch(long select, long a1, long a2,
-                                  long a3, long a4);
-extern unsigned long crb_fixup(unsigned long vptptr, unsigned long hwrpb);
-
-/*
- * The Console
- */
-
-extern bool have_vga;
-
-extern void do_console(void);
-extern void entInt(void);
-
-/*
- * Utils
- */
-
-extern int printf(const char *, ...);
-extern void ndelay(unsigned long nsec);
-
-static inline void udelay(unsigned long msec)
-{
-  ndelay(msec * 1000);
-}
-
-/*
- * Initialization
- */
-extern void ps2port_setup(void);
-extern void pci_setup(void);
-extern void vgahw_init(void);
-
-#endif /* PROTOS_H */
diff --git a/qemu/roms/qemu-palcode/ps2port.c b/qemu/roms/qemu-palcode/ps2port.c
deleted file mode 100644
index 761c2e60b..000000000
--- a/qemu/roms/qemu-palcode/ps2port.c
+++ /dev/null
@@ -1,507 +0,0 @@
-// Support for handling the PS/2 mouse/keyboard ports.
-//
-// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
-// Several ideas taken from code Copyright (c) 1999-2004 Vojtech Pavlik
-//
-// This file may be distributed under the terms of the GNU LGPLv3 license.
-//
-// This file is copied (mostly) intact from SeaBIOS.
-
-#include "protos.h"
-#include "ioport.h"
-#include "ps2port.h"
-
-typedef uint64_t u64;
-
-#define dprintf(lvl, fmt, ...)
-#define warn_timeout()
-
-static inline u64
-calc_future_tsc(int timeout)
-{
-  return get_wall_time() + timeout;
-}
-
-static inline bool
-check_tsc(u64 end)
-{
-  return get_wall_time() > end;
-}
-
-static inline void
-yield(void)
-{
-  udelay(1);
-}
-
-static struct {
-  u8 ps2ctr;
-} ebda;
-
-#define GET_EBDA(VAR)		ebda.VAR
-#define SET_EBDA(VAR, VAL)	(ebda.VAR = (VAL))
-
-#define ASSERT32FLAT()
-#define CONFIG_PS2PORT 1
-
-#define enable_hwirq(level, func)
-#define run_thread(func, val)	func(val)
-
-/****************************************************************
- * Low level i8042 commands.
- ****************************************************************/
-
-// Timeout value.
-#define I8042_CTL_TIMEOUT       10000
-
-#define I8042_BUFFER_SIZE       16
-
-static int
-i8042_wait_read(void)
-{
-    dprintf(7, "i8042_wait_read\n");
-    int i;
-    for (i=0; i<I8042_CTL_TIMEOUT; i++) {
-        u8 status = inb(PORT_PS2_STATUS);
-        if (status & I8042_STR_OBF)
-            return 0;
-        udelay(50);
-    }
-    warn_timeout();
-    return -1;
-}
-
-static int
-i8042_wait_write(void)
-{
-    dprintf(7, "i8042_wait_write\n");
-    int i;
-    for (i=0; i<I8042_CTL_TIMEOUT; i++) {
-        u8 status = inb(PORT_PS2_STATUS);
-        if (! (status & I8042_STR_IBF))
-            return 0;
-        udelay(50);
-    }
-    warn_timeout();
-    return -1;
-}
-
-static int
-i8042_flush(void)
-{
-    dprintf(7, "i8042_flush\n");
-    int i;
-    for (i=0; i<I8042_BUFFER_SIZE; i++) {
-        u8 status = inb(PORT_PS2_STATUS);
-        if (! (status & I8042_STR_OBF))
-            return 0;
-        udelay(50);
-	inb(PORT_PS2_DATA);
-    }
-
-    warn_timeout();
-    return -1;
-}
-
-static int
-__i8042_command(int command, u8 *param)
-{
-    int receive = (command >> 8) & 0xf;
-    int send = (command >> 12) & 0xf;
-
-    // Send the command.
-    int ret = i8042_wait_write();
-    if (ret)
-        return ret;
-    outb(command, PORT_PS2_STATUS);
-
-    // Send parameters (if any).
-    int i;
-    for (i = 0; i < send; i++) {
-        ret = i8042_wait_write();
-        if (ret)
-            return ret;
-        outb(param[i], PORT_PS2_DATA);
-    }
-
-    // Receive parameters (if any).
-    for (i = 0; i < receive; i++) {
-        ret = i8042_wait_read();
-        if (ret)
-            return ret;
-        param[i] = inb(PORT_PS2_DATA);
-        dprintf(7, "i8042 param=%x\n", param[i]);
-    }
-
-    return 0;
-}
-
-static int
-i8042_command(int command, u8 *param)
-{
-    dprintf(7, "i8042_command cmd=%x\n", command);
-    int ret = __i8042_command(command, param);
-    if (ret)
-        dprintf(2, "i8042 command %x failed\n", command);
-    return ret;
-}
-
-static int
-i8042_kbd_write(u8 c)
-{
-    dprintf(7, "i8042_kbd_write c=%d\n", c);
-    int ret = i8042_wait_write();
-    if (! ret)
-        outb(c, PORT_PS2_DATA);
-    return ret;
-}
-
-static int
-i8042_aux_write(u8 c)
-{
-    return i8042_command(I8042_CMD_AUX_SEND, &c);
-}
-
-void
-i8042_reboot(void)
-{
-    int i;
-    for (i=0; i<10; i++) {
-        i8042_wait_write();
-        udelay(50);
-        outb(0xfe, PORT_PS2_STATUS); /* pulse reset low */
-        udelay(50);
-    }
-}
-
-
-/****************************************************************
- * Device commands.
- ****************************************************************/
-
-#define PS2_RET_ACK             0xfa
-#define PS2_RET_NAK             0xfe
-
-static int
-ps2_recvbyte(int aux, int needack, int timeout)
-{
-    u64 end = calc_future_tsc(timeout);
-    for (;;) {
-        u8 status = inb(PORT_PS2_STATUS);
-        if (status & I8042_STR_OBF) {
-            u8 data = inb(PORT_PS2_DATA);
-            dprintf(7, "ps2 read %x\n", data);
-
-            if (!!(status & I8042_STR_AUXDATA) == aux) {
-                if (!needack)
-                    return data;
-                if (data == PS2_RET_ACK)
-                    return data;
-                if (data == PS2_RET_NAK) {
-                    dprintf(1, "Got ps2 nak (status=%x)\n", status);
-                    return data;
-                }
-            }
-
-            // This data not part of command - just discard it.
-            dprintf(1, "Discarding ps2 data %02x (status=%02x)\n", data, status);
-        }
-
-        if (check_tsc(end)) {
-            // Don't warn on second byte of a reset
-            if (timeout > 100)
-                warn_timeout();
-            return -1;
-        }
-        yield();
-    }
-}
-
-static int
-ps2_sendbyte(int aux, u8 command, int timeout)
-{
-    dprintf(7, "ps2_sendbyte aux=%d cmd=%x\n", aux, command);
-    int ret;
-    if (aux)
-        ret = i8042_aux_write(command);
-    else
-        ret = i8042_kbd_write(command);
-    if (ret)
-        return ret;
-
-    // Read ack.
-    ret = ps2_recvbyte(aux, 1, timeout);
-    if (ret < 0)
-        return ret;
-    if (ret != PS2_RET_ACK)
-        return -1;
-
-    return 0;
-}
-
-static int
-__ps2_command(int aux, int command, u8 *param)
-{
-    int ret2;
-    int receive = (command >> 8) & 0xf;
-    int send = (command >> 12) & 0xf;
-
-    // Disable interrupts and keyboard/mouse.
-    u8 ps2ctr = GET_EBDA(ps2ctr);
-    u8 newctr = ((ps2ctr | I8042_CTR_AUXDIS | I8042_CTR_KBDDIS)
-                 & ~(I8042_CTR_KBDINT|I8042_CTR_AUXINT));
-    dprintf(6, "i8042 ctr old=%x new=%x\n", ps2ctr, newctr);
-    int ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
-    if (ret)
-        return ret;
-
-    // Flush any interrupts already pending.
-    yield();
-
-    // Enable port command is being sent to.
-    if (aux)
-        newctr &= ~I8042_CTR_AUXDIS;
-    else
-        newctr &= ~I8042_CTR_KBDDIS;
-    ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
-    if (ret)
-        goto fail;
-
-    if (command == ATKBD_CMD_RESET_BAT) {
-        // Reset is special wrt timeouts and bytes received.
-
-        // Send command.
-        ret = ps2_sendbyte(aux, command, 1000);
-        if (ret)
-            goto fail;
-
-        // Receive parameters.
-        ret = ps2_recvbyte(aux, 0, 4000);
-        if (ret < 0)
-            goto fail;
-        param[0] = ret;
-        ret = ps2_recvbyte(aux, 0, 100);
-        if (ret < 0)
-            // Some devices only respond with one byte on reset.
-            ret = 0;
-        param[1] = ret;
-    } else if (command == ATKBD_CMD_GETID) {
-        // Getid is special wrt bytes received.
-
-        // Send command.
-        ret = ps2_sendbyte(aux, command, 200);
-        if (ret)
-            goto fail;
-
-        // Receive parameters.
-        ret = ps2_recvbyte(aux, 0, 500);
-        if (ret < 0)
-            goto fail;
-        param[0] = ret;
-        if (ret == 0xab || ret == 0xac || ret == 0x2b || ret == 0x5d
-            || ret == 0x60 || ret == 0x47) {
-            // These ids (keyboards) return two bytes.
-            ret = ps2_recvbyte(aux, 0, 500);
-            if (ret < 0)
-                goto fail;
-            param[1] = ret;
-        } else {
-            param[1] = 0;
-        }
-    } else {
-        // Send command.
-        ret = ps2_sendbyte(aux, command, 200);
-        if (ret)
-            goto fail;
-
-        // Send parameters (if any).
-        int i;
-        for (i = 0; i < send; i++) {
-            ret = ps2_sendbyte(aux, param[i], 200);
-            if (ret)
-                goto fail;
-        }
-
-        // Receive parameters (if any).
-        for (i = 0; i < receive; i++) {
-            ret = ps2_recvbyte(aux, 0, 500);
-            if (ret < 0)
-                goto fail;
-            param[i] = ret;
-        }
-    }
-
-    ret = 0;
-
-fail:
-    // Restore interrupts and keyboard/mouse.
-    ret2 = i8042_command(I8042_CMD_CTL_WCTR, &ps2ctr);
-    if (ret2)
-        return ret2;
-
-    return ret;
-}
-
-static int
-ps2_command(int aux, int command, u8 *param)
-{
-    dprintf(7, "ps2_command aux=%d cmd=%x\n", aux, command);
-    int ret = __ps2_command(aux, command, param);
-    if (ret)
-        dprintf(2, "ps2 command %x failed (aux=%d)\n", command, aux);
-    return ret;
-}
-
-int
-ps2_kbd_command(int command, u8 *param)
-{
-    return ps2_command(0, command, param);
-}
-
-int
-ps2_mouse_command(int command, u8 *param)
-{
-    return ps2_command(1, command, param);
-}
-
-
-/****************************************************************
- * IRQ handlers
- ****************************************************************/
-#if 0
-
-// INT74h : PS/2 mouse hardware interrupt
-void VISIBLE16
-handle_74(void)
-{
-    if (! CONFIG_PS2PORT)
-        return;
-
-    debug_isr(DEBUG_ISR_74);
-
-    u8 v = inb(PORT_PS2_STATUS);
-    if ((v & (I8042_STR_OBF|I8042_STR_AUXDATA))
-        != (I8042_STR_OBF|I8042_STR_AUXDATA)) {
-        dprintf(1, "ps2 mouse irq but no mouse data.\n");
-        goto done;
-    }
-    v = inb(PORT_PS2_DATA);
-
-    if (!(GET_EBDA(ps2ctr) & I8042_CTR_AUXINT))
-        // Interrupts not enabled.
-        goto done;
-
-    process_mouse(v);
-
-done:
-    eoi_pic2();
-}
-
-// INT09h : Keyboard Hardware Service Entry Point
-void VISIBLE16
-handle_09(void)
-{
-    if (! CONFIG_PS2PORT)
-        return;
-
-    debug_isr(DEBUG_ISR_09);
-
-    // read key from keyboard controller
-    u8 v = inb(PORT_PS2_STATUS);
-    if (v & I8042_STR_AUXDATA) {
-        dprintf(1, "ps2 keyboard irq but found mouse data?!\n");
-        goto done;
-    }
-    v = inb(PORT_PS2_DATA);
-
-    if (!(GET_EBDA(ps2ctr) & I8042_CTR_KBDINT))
-        // Interrupts not enabled.
-        goto done;
-
-    process_key(v);
-
-done:
-    eoi_pic1();
-}
-
-#endif
-/****************************************************************
- * Setup
- ****************************************************************/
-
-static void
-keyboard_init(void *data)
-{
-    /* flush incoming keys */
-    int ret = i8042_flush();
-    if (ret)
-        return;
-
-    // Controller self-test.
-    u8 param[2];
-    ret = i8042_command(I8042_CMD_CTL_TEST, param);
-    if (ret)
-        return;
-    if (param[0] != 0x55) {
-        dprintf(1, "i8042 self test failed (got %x not 0x55)\n", param[0]);
-        return;
-    }
-
-    // Controller keyboard test.
-    ret = i8042_command(I8042_CMD_KBD_TEST, param);
-    if (ret)
-        return;
-    if (param[0] != 0x00) {
-        dprintf(1, "i8042 keyboard test failed (got %x not 0x00)\n", param[0]);
-        return;
-    }
-
-    // Disable keyboard and mouse events.
-    SET_EBDA(ps2ctr, I8042_CTR_KBDDIS | I8042_CTR_AUXDIS);
-
-
-    /* ------------------- keyboard side ------------------------*/
-    /* reset keyboard and self test  (keyboard side) */
-    ret = ps2_kbd_command(ATKBD_CMD_RESET_BAT, param);
-    if (ret)
-        return;
-    if (param[0] != 0xaa) {
-        dprintf(1, "keyboard self test failed (got %x not 0xaa)\n", param[0]);
-        return;
-    }
-
-    /* Disable keyboard */
-    ret = ps2_kbd_command(ATKBD_CMD_RESET_DIS, NULL);
-    if (ret)
-        return;
-
-    // Set scancode command (mode 2)
-    param[0] = 0x02;
-    ret = ps2_kbd_command(ATKBD_CMD_SSCANSET, param);
-    if (ret)
-        return;
-
-    // Keyboard Mode: disable mouse, scan code convert, enable kbd IRQ
-    SET_EBDA(ps2ctr, I8042_CTR_AUXDIS | I8042_CTR_XLATE | I8042_CTR_KBDINT);
-
-    /* Enable keyboard */
-    ret = ps2_kbd_command(ATKBD_CMD_ENABLE, NULL);
-    if (ret)
-        return;
-
-    dprintf(1, "PS2 keyboard initialized\n");
-}
-
-void
-ps2port_setup(void)
-{
-    ASSERT32FLAT();
-    if (! CONFIG_PS2PORT)
-        return;
-    dprintf(3, "init ps2port\n");
-
-    enable_hwirq(1, FUNC16(entry_09));
-    enable_hwirq(12, FUNC16(entry_74));
-
-    run_thread(keyboard_init, NULL);
-}
diff --git a/qemu/roms/qemu-palcode/ps2port.h b/qemu/roms/qemu-palcode/ps2port.h
deleted file mode 100644
index b5f54195e..000000000
--- a/qemu/roms/qemu-palcode/ps2port.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Basic ps2 port (keyboard/mouse) command handling.
-
-   This file is copied (mostly) intact from SeaBIOS.
-   It is covered by the GNU Lesser General Public License, v3.
-
-   You should have received a copy of the GNU Lesser General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef PS2PORT_H
-#define PS2PORT_H
-
-typedef uint8_t u8;
-
-// Standard commands.
-#define I8042_CMD_CTL_RCTR      0x0120
-#define I8042_CMD_CTL_WCTR      0x1060
-#define I8042_CMD_CTL_TEST      0x01aa
-
-#define I8042_CMD_KBD_TEST      0x01ab
-#define I8042_CMD_KBD_DISABLE   0x00ad
-#define I8042_CMD_KBD_ENABLE    0x00ae
-
-#define I8042_CMD_AUX_DISABLE   0x00a7
-#define I8042_CMD_AUX_ENABLE    0x00a8
-#define I8042_CMD_AUX_SEND      0x10d4
-
-// Keyboard commands
-#define ATKBD_CMD_SETLEDS       0x10ed
-#define ATKBD_CMD_SSCANSET      0x10f0
-#define ATKBD_CMD_GETID         0x02f2
-#define ATKBD_CMD_ENABLE        0x00f4
-#define ATKBD_CMD_RESET_DIS     0x00f5
-#define ATKBD_CMD_RESET_BAT     0x02ff
-
-// Mouse commands
-#define PSMOUSE_CMD_SETSCALE11  0x00e6
-#define PSMOUSE_CMD_SETSCALE21  0x00e7
-#define PSMOUSE_CMD_SETRES      0x10e8
-#define PSMOUSE_CMD_GETINFO     0x03e9
-#define PSMOUSE_CMD_GETID       0x02f2
-#define PSMOUSE_CMD_SETRATE     0x10f3
-#define PSMOUSE_CMD_ENABLE      0x00f4
-#define PSMOUSE_CMD_DISABLE     0x00f5
-#define PSMOUSE_CMD_RESET_BAT   0x02ff
-
-// Status register bits.
-#define I8042_STR_PARITY        0x80
-#define I8042_STR_TIMEOUT       0x40
-#define I8042_STR_AUXDATA       0x20
-#define I8042_STR_KEYLOCK       0x10
-#define I8042_STR_CMDDAT        0x08
-#define I8042_STR_MUXERR        0x04
-#define I8042_STR_IBF           0x02
-#define I8042_STR_OBF           0x01
-
-// Control register bits.
-#define I8042_CTR_KBDINT        0x01
-#define I8042_CTR_AUXINT        0x02
-#define I8042_CTR_IGNKEYLOCK    0x08
-#define I8042_CTR_KBDDIS        0x10
-#define I8042_CTR_AUXDIS        0x20
-#define I8042_CTR_XLATE         0x40
-
-// functions
-void i8042_reboot(void);
-int ps2_kbd_command(int command, u8 *param);
-int ps2_mouse_command(int command, u8 *param);
-void ps2port_setup(void);
-
-#endif // ps2port.h
diff --git a/qemu/roms/qemu-palcode/strlen.S b/qemu/roms/qemu-palcode/strlen.S
deleted file mode 100644
index 5a77d7293..000000000
--- a/qemu/roms/qemu-palcode/strlen.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * strlen.S (c) 1995 David Mosberger (davidm@cs.arizona.edu)
- *
- * Finds length of a 0-terminated string.  Optimized for the
- * Alpha architecture:
- *
- *	- memory accessed as aligned quadwords only
- *	- uses bcmpge to compare 8 bytes in parallel
- *	- does binary search to find 0 byte in last
- *	  quadword (HAKMEM needed 12 instructions to
- *	  do this instead of the 9 instructions that
- *	  binary search needs).
- */
-
-	.set noreorder
-	.set noat
-
-	.align 3
-
-	.globl	strlen
-	.ent	strlen
-strlen:
-	.frame	$sp, 0, $26, 0
-	.prologue 0
-
-	ldq_u	$1, 0($16)	# load first quadword ($16  may be misaligned)
-	lda	$2, -1($31)
-	insqh	$2, $16, $2
-	andnot	$16, 7, $0
-	or	$2, $1, $1
-	cmpbge	$31, $1, $2	# $2  <- bitmask: bit i == 1 <==> i-th byte == 0
-	bne	$2, found
-
-loop:	ldq	$1, 8($0)
-	addq	$0, 8, $0	# addr += 8
-	nop			# helps dual issue last two insns
-	cmpbge	$31, $1, $2
-	beq	$2, loop
-
-found:	blbs	$2, done	# make aligned case fast
-	negq	$2, $3
-	and	$2, $3, $2
-
-	and	$2, 0x0f, $1
-	addq	$0, 4, $3
-	cmoveq	$1, $3, $0
-
-	and	$2, 0x33, $1
-	addq	$0, 2, $3
-	cmoveq	$1, $3, $0
-
-	and	$2, 0x55, $1
-	addq	$0, 1, $3
-	cmoveq	$1, $3, $0
-
-done:	subq	$0, $16, $0
-	ret	$31, ($26)
-
-	.end	strlen
diff --git a/qemu/roms/qemu-palcode/sys-clipper.S b/qemu/roms/qemu-palcode/sys-clipper.S
deleted file mode 100644
index 50de347d8..000000000
--- a/qemu/roms/qemu-palcode/sys-clipper.S
+++ /dev/null
@@ -1,140 +0,0 @@
-/* PALcode and C runtime functions for the CLIPPER system emulation.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include "pal.h"
-#include SYSTEM_H
-
-/*
- * Sys_Setup
- *
- * Do any system specific setup necessary.
- *
- * INPUT PARAMETERS
- *
- *	a0 = whami
- *	p7 = return address
- */
-	.globl	Sys_Setup
-	.ent	Sys_Setup
-Sys_Setup:
-	.frame	$sp, 0, p7, 0
-	lda		t0, TYPHOON_CCHIP_DIR0
-	lda		t1, TYPHOON_CCHIP_DIR2
-	lda		t2, TYPHOON_CCHIP_IIC0
-	lda		t3, TYPHOON_CCHIP_IIC2
-	and		a0, 2, t4
-	cmovne		t4, t1, t0
-	cmovne		t4, t3, t2
-	and		a0, 1, t4
-	sll		t4, 6, t4
-	addq		t0, t4, t0
-	addq		t2, t4, t2
-	LOAD_PHYS_CCHIP	t4
-	addq		t0, t4, t0
-	addq		t2, t4, t2
-	mtpr		t0, ptCpuDIR
-	mtpr		t2, ptCpuIIC
-	ret
-	.end	Sys_Setup
-
-/*
- * Sys_Dev_Vector
- *
- * Load the SRM interrupt vector for the system.
- *
- * INPUT PARAMETERS
- *
- *	p7 = return address
- *
- * OUTPUT PARAMETERS
- *
- *	a1 = interrupt vector
- */
-
-	.globl	Sys_Dev_Vector
-	.ent	Sys_Dev_Vector
-Sys_Dev_Vector:
-	.frame	$sp, 0, p7, 0
-	mfpr	a1, ptCpuDIR		// Load int mask for this CPU
-	ldq_p	a1, 0(a1)
-	beq	a1, CallPal_Rti		// No interrupts asserted?
-
-	cttz	a1, a1			// Find the first asserted interrupt.
-
-	cmpeq	a1, 55, a0		// Is this an ISA interrupt?
-	addq	a1, 16, a1		// PCI interrupt numbers start at 16
-	beq	a0, 1f
-
-	LOAD_PHYS_PCHIP0_IACK a1	// IACK results in the ISA irq
-	ldl_p	a1, 0(a1)
-
-1:	sll	a1, 4, a1
-	lda	a1, 0x800(a1)
-	ret	$31, (p7), 0
-	.end Sys_Dev_Vector
-
-/*
- * Cserve_Ena
- *
- * Unmask a PCI interrupt
- */
-	.globl	Cserve_Ena
-Cserve_Ena:
-	// FIXME
-	hw_rei
-ENDFN	Cserve_Ena
-
-/*
- * Cserve_Dis
- *
- * Mask a PCI interrupt
- */
-	.globl	Cserve_Dis
-Cserve_Dis:
-	// FIXME
-	hw_rei
-ENDFN	Cserve_Dis
-
-/*
- * PCI parameters
- */
-
-	.section .sdata
-
-	.align	3
-	.globl	pci_io_base
-	.type	pci_io_base, @object
-	.size	pci_io_base, 8
-pci_io_base:
-	.quad	PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_IO
-
-	.globl	pci_conf_base
-	.type	pci_conf_base, @object
-	.size	pci_conf_base, 8
-pci_conf_base:
-	.quad	PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_CONF
-
-	.align	3
-	.globl	pci_mem_base
-	.type	pci_mem_base, @object
-	.size	pci_mem_base, 8
-pci_mem_base:
-	.quad	PIO_KSEG_ADDR + TYPHOON_PCHIP0_PCI_MEM
-
diff --git a/qemu/roms/qemu-palcode/sys-clipper.h b/qemu/roms/qemu-palcode/sys-clipper.h
deleted file mode 100644
index 31094ff38..000000000
--- a/qemu/roms/qemu-palcode/sys-clipper.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Declarations for the CLIPPER system emulation.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef SYS_CLIPPER_H
-#define SYS_CLIPPER_H 1
-
-#include "core-typhoon.h"
-
-#define SYS_TYPE	ST_DEC_TSUNAMI
-#define SYS_VARIATION	(5 << 10)
-#define SYS_REVISION	0
-
-#endif
diff --git a/qemu/roms/qemu-palcode/sys-sx164.h b/qemu/roms/qemu-palcode/sys-sx164.h
deleted file mode 100644
index 2cf6a9b97..000000000
--- a/qemu/roms/qemu-palcode/sys-sx164.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Declarations for the SX164 system emulation.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef SYS_SX164_H
-#define SYS_SX164_H 1
-
-#include "core_cia.h"
-
-#ifdef __ASSEMBLER__
-
-.macro	SYS_ACK_CLK	t0, t1, t2
-	LOAD_KSEG_PCI_IO \t0		// Set RTCADD (0x70) to index reg 0xC
-	mov	0xc, \t1
-	stb	\t1, 0x70(\t0)
-	ldbu	\t1, 0x71(\t0)		// Read RTCDAT to clear interrupt
-.endm
-
-.macro	SYS_DEV_VECTOR	ret
-	FIXME
-.endm
-
-#endif /* ASSEMBLER */
-
-#define SYS_TYPE	ST_DEC_EB164
-#define SYS_VARIATION	(15 << 10)
-#define SYS_REVISION	0
-
-#endif /* SYS_SX164_H */
diff --git a/qemu/roms/qemu-palcode/uart.c b/qemu/roms/qemu-palcode/uart.c
deleted file mode 100644
index 61e467a6f..000000000
--- a/qemu/roms/qemu-palcode/uart.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*****************************************************************************
-
-       Copyright � 1995, 1996 Digital Equipment Corporation,
-                       Maynard, Massachusetts.
-
-                        All Rights Reserved
-
-Permission to use, copy, modify, and distribute this software and its 
-documentation for any purpose and without fee is hereby granted, provided  
-that the copyright notice and this permission notice appear in all copies  
-of software and supporting documentation, and that the name of Digital not  
-be used in advertising or publicity pertaining to distribution of the software 
-without specific, written prior permission. Digital grants this permission 
-provided that you prominently mark, as not part of the original, any 
-modifications made to this software or documentation.
-
-Digital Equipment Corporation disclaims all warranties and/or guarantees  
-with regard to this software, including all implied warranties of fitness for 
-a particular purpose and merchantability, and makes no representations 
-regarding the use of, or the results of the use of, the software and 
-documentation in terms of correctness, accuracy, reliability, currentness or
-otherwise; and you rely on the software, documentation and results solely at 
-your own risk. 
-
-******************************************************************************/
-
-/*
- * david.rusling@reo.mts.dec.com
- *
- * Modified for QEMU PALcode by rth@twiddle.net.
- */
-
-#include "protos.h"
-#include "uart.h"
-
-#ifndef SERIAL_SPEED
-#define SERIAL_SPEED 9600
-#endif
-
-int
-uart_charav(int offset)
-{
-	return inb(com2Lsr + offset) & 1;
-}
-
-int
-uart_getchar(int offset)
-{
-	/* If interrupts are enabled, use wtint assuming that either the
-	   device itself will wake us, or that a clock interrupt will.  */
-	if ((rdps() & 7) == 0) {
-	    while (!uart_charav(offset)) {
-		wtint(0);
-	    }
-	} else {
-	    while (!uart_charav(offset))
-	        continue;
-	}
-
-	return inb(com2Rbr + offset);
-}
-
-void
-uart_putchar_raw(int offset, char c)
-{
-	while ((inb(com2Lsr + offset) & 0x20) == 0)
-		continue;
-	outb(c, com2Thr + offset);
-}
-
-void
-uart_putchar(int offset, char c)
-{
-	if (c == '\n')
-		uart_putchar_raw(offset, '\r');
-	uart_putchar_raw(offset, c);
-}
-
-void
-uart_puts(int offset, const char *s)
-{
-	while (*s != '\0')
-		uart_putchar(offset, *s++);
-}
-
-void
-uart_init_line(int offset, int baud)
-{
-	int i;
-	int baudconst;
-
-	switch (baud) {
-	case 56000:
-		baudconst = 2;
-		break;
-	case 38400:
-		baudconst = 3;
-		break;
-	case 19200:
-		baudconst = 6;
-		break;
-	case 9600:
-		baudconst = 12;
-		break;
-	case 4800:
-		baudconst = 24;
-		break;
-	case 2400:
-		baudconst = 48;
-		break;
-	case 1200:
-		baudconst = 96;
-		break;
-	case 300:
-		baudconst = 384;
-		break;
-	case 150:
-		baudconst = 768;
-		break;
-	default:
-		baudconst = 12;
-		break;
-	}
-
-
-	outb(0x87, com2Lcr + offset);
-	outb(0, com2Dlm + offset);
-	outb(baudconst, com2Dll + offset);
-	outb(0x07, com2Lcr + offset);
-	outb(0x0F, com2Mcr + offset);
-
-	for (i = 10; i > 0; i--) {
-		if (inb(com2Lsr + offset) == 0)
-			break;
-		inb(com2Rbr + offset);
-	}
-}
-
-void uart_init(void)
-{
-	uart_init_line(COM1, SERIAL_SPEED);
-	/* uart_init_line(COM2, SERIAL_SPEED); */
-}
diff --git a/qemu/roms/qemu-palcode/uart.h b/qemu/roms/qemu-palcode/uart.h
deleted file mode 100644
index bb47b0c83..000000000
--- a/qemu/roms/qemu-palcode/uart.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef __UART_H_LOADED
-#define __UART_H_LOADED
-/*****************************************************************************
-
-       Copyright � 1993, 1994 Digital Equipment Corporation,
-                       Maynard, Massachusetts.
-
-                        All Rights Reserved
-
-Permission to use, copy, modify, and distribute this software and its 
-documentation for any purpose and without fee is hereby granted, provided  
-that the copyright notice and this permission notice appear in all copies  
-of software and supporting documentation, and that the name of Digital not  
-be used in advertising or publicity pertaining to distribution of the software 
-without specific, written prior permission. Digital grants this permission 
-provided that you prominently mark, as not part of the original, any 
-modifications made to this software or documentation.
-
-Digital Equipment Corporation disclaims all warranties and/or guarantees  
-with regard to this software, including all implied warranties of fitness for 
-a particular purpose and merchantability, and makes no representations 
-regarding the use of, or the results of the use of, the software and 
-documentation in terms of correctness, accuracy, reliability, currentness or
-otherwise; and you rely on the software, documentation and results solely at 
-your own risk. 
-
-******************************************************************************/
-
-#define com1Rbr	0x3f8
-#define com1Thr	0x3f8
-#define com1Ier	0x3f9
-#define com1Iir	0x3fa
-#define com1Lcr	0x3fb
-#define com1Mcr	0x3fc
-#define com1Lsr	0x3fd
-#define com1Msr	0x3fe
-#define com1Scr	0x3ff
-#define com1Dll	0x3f8
-#define com1Dlm	0x3f9
-
-#define com2Rbr	0x2f8
-#define com2Thr	0x2f8
-#define com2Ier	0x2f9
-#define com2Iir	0x2fa
-#define com2Lcr	0x2fb
-#define com2Mcr	0x2fc
-#define com2Lsr	0x2fd
-#define com2Msr	0x2fe
-#define com2Scr	0x2ff
-#define com2Dll	0x2f8
-#define com2Dlm	0x2f9
-
-#define COM1	(com1Rbr - com2Rbr)
-#define COM2	0
-
-#ifndef __ASSEMBLER__
-
-extern int uart_charav(int port);
-extern int uart_getchar(int port);
-extern void uart_putchar_raw(int port, char c);
-extern void uart_putchar(int port, char c);
-extern void uart_puts(int port, const char *s);
-extern void uart_init_line(int port, int baud);
-extern void uart_init(void);
-
-#endif /* __ASSEMBLER__ */
-#endif /* __UART_H_LOADED */
diff --git a/qemu/roms/qemu-palcode/util.c b/qemu/roms/qemu-palcode/util.c
deleted file mode 100644
index 1444dd6b6..000000000
--- a/qemu/roms/qemu-palcode/util.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Utility functions for the QEMU PALcode.
-
-   Copyright (C) 2011 Richard Henderson
-
-   This file is part of QEMU PALcode.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
-   of the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include "protos.h"
-
-
-void
-ndelay(unsigned long nsec)
-{
-  unsigned long target, now;
-
-  /* ??? Fix race between setting an alarm and waiting for an interrupt,
-     so that we can use wtint here.  This isn't used much except for 
-     during startup, so it probably doesn't matter much.  */
-
-  now = get_wall_time();
-  target = now + nsec;
-
-  do
-    now = get_wall_time();
-  while (now < target);
-}
diff --git a/qemu/roms/qemu-palcode/vgafonts.c b/qemu/roms/qemu-palcode/vgafonts.c
deleted file mode 100644
index ef59c9b31..000000000
--- a/qemu/roms/qemu-palcode/vgafonts.c
+++ /dev/null
@@ -1,786 +0,0 @@
-#include "protos.h"
-#include "vgatables.h" // vgafont8
-
-#define VAR16
-
-/*
- * These fonts come from ftp://ftp.simtel.net/pub/simtelnet/msdos/screen/fntcol16.zip
- * The package is (c) by Joseph Gil
- * The individual fonts are public domain
- */
-u8 const vgafont8[256 * 8] VAR16 = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x7e, 0x81, 0xa5, 0x81, 0xbd, 0x99, 0x81, 0x7e,
-    0x7e, 0xff, 0xdb, 0xff, 0xc3, 0xe7, 0xff, 0x7e,
-    0x6c, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10, 0x00,
-    0x10, 0x38, 0x7c, 0xfe, 0x7c, 0x38, 0x10, 0x00,
-    0x38, 0x7c, 0x38, 0xfe, 0xfe, 0x7c, 0x38, 0x7c,
-    0x10, 0x10, 0x38, 0x7c, 0xfe, 0x7c, 0x38, 0x7c,
-    0x00, 0x00, 0x18, 0x3c, 0x3c, 0x18, 0x00, 0x00,
-    0xff, 0xff, 0xe7, 0xc3, 0xc3, 0xe7, 0xff, 0xff,
-    0x00, 0x3c, 0x66, 0x42, 0x42, 0x66, 0x3c, 0x00,
-    0xff, 0xc3, 0x99, 0xbd, 0xbd, 0x99, 0xc3, 0xff,
-    0x0f, 0x07, 0x0f, 0x7d, 0xcc, 0xcc, 0xcc, 0x78,
-    0x3c, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x7e, 0x18,
-    0x3f, 0x33, 0x3f, 0x30, 0x30, 0x70, 0xf0, 0xe0,
-    0x7f, 0x63, 0x7f, 0x63, 0x63, 0x67, 0xe6, 0xc0,
-    0x99, 0x5a, 0x3c, 0xe7, 0xe7, 0x3c, 0x5a, 0x99,
-    0x80, 0xe0, 0xf8, 0xfe, 0xf8, 0xe0, 0x80, 0x00,
-    0x02, 0x0e, 0x3e, 0xfe, 0x3e, 0x0e, 0x02, 0x00,
-    0x18, 0x3c, 0x7e, 0x18, 0x18, 0x7e, 0x3c, 0x18,
-    0x66, 0x66, 0x66, 0x66, 0x66, 0x00, 0x66, 0x00,
-    0x7f, 0xdb, 0xdb, 0x7b, 0x1b, 0x1b, 0x1b, 0x00,
-    0x3e, 0x63, 0x38, 0x6c, 0x6c, 0x38, 0xcc, 0x78,
-    0x00, 0x00, 0x00, 0x00, 0x7e, 0x7e, 0x7e, 0x00,
-    0x18, 0x3c, 0x7e, 0x18, 0x7e, 0x3c, 0x18, 0xff,
-    0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x18, 0x00,
-    0x18, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x00,
-    0x00, 0x18, 0x0c, 0xfe, 0x0c, 0x18, 0x00, 0x00,
-    0x00, 0x30, 0x60, 0xfe, 0x60, 0x30, 0x00, 0x00,
-    0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xfe, 0x00, 0x00,
-    0x00, 0x24, 0x66, 0xff, 0x66, 0x24, 0x00, 0x00,
-    0x00, 0x18, 0x3c, 0x7e, 0xff, 0xff, 0x00, 0x00,
-    0x00, 0xff, 0xff, 0x7e, 0x3c, 0x18, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x30, 0x78, 0x78, 0x30, 0x30, 0x00, 0x30, 0x00,
-    0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x6c, 0x6c, 0xfe, 0x6c, 0xfe, 0x6c, 0x6c, 0x00,
-    0x30, 0x7c, 0xc0, 0x78, 0x0c, 0xf8, 0x30, 0x00,
-    0x00, 0xc6, 0xcc, 0x18, 0x30, 0x66, 0xc6, 0x00,
-    0x38, 0x6c, 0x38, 0x76, 0xdc, 0xcc, 0x76, 0x00,
-    0x60, 0x60, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x18, 0x30, 0x60, 0x60, 0x60, 0x30, 0x18, 0x00,
-    0x60, 0x30, 0x18, 0x18, 0x18, 0x30, 0x60, 0x00,
-    0x00, 0x66, 0x3c, 0xff, 0x3c, 0x66, 0x00, 0x00,
-    0x00, 0x30, 0x30, 0xfc, 0x30, 0x30, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x60,
-    0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00,
-    0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0x80, 0x00,
-    0x7c, 0xc6, 0xce, 0xde, 0xf6, 0xe6, 0x7c, 0x00,
-    0x30, 0x70, 0x30, 0x30, 0x30, 0x30, 0xfc, 0x00,
-    0x78, 0xcc, 0x0c, 0x38, 0x60, 0xcc, 0xfc, 0x00,
-    0x78, 0xcc, 0x0c, 0x38, 0x0c, 0xcc, 0x78, 0x00,
-    0x1c, 0x3c, 0x6c, 0xcc, 0xfe, 0x0c, 0x1e, 0x00,
-    0xfc, 0xc0, 0xf8, 0x0c, 0x0c, 0xcc, 0x78, 0x00,
-    0x38, 0x60, 0xc0, 0xf8, 0xcc, 0xcc, 0x78, 0x00,
-    0xfc, 0xcc, 0x0c, 0x18, 0x30, 0x30, 0x30, 0x00,
-    0x78, 0xcc, 0xcc, 0x78, 0xcc, 0xcc, 0x78, 0x00,
-    0x78, 0xcc, 0xcc, 0x7c, 0x0c, 0x18, 0x70, 0x00,
-    0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x00,
-    0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x60,
-    0x18, 0x30, 0x60, 0xc0, 0x60, 0x30, 0x18, 0x00,
-    0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x00, 0x00,
-    0x60, 0x30, 0x18, 0x0c, 0x18, 0x30, 0x60, 0x00,
-    0x78, 0xcc, 0x0c, 0x18, 0x30, 0x00, 0x30, 0x00,
-    0x7c, 0xc6, 0xde, 0xde, 0xde, 0xc0, 0x78, 0x00,
-    0x30, 0x78, 0xcc, 0xcc, 0xfc, 0xcc, 0xcc, 0x00,
-    0xfc, 0x66, 0x66, 0x7c, 0x66, 0x66, 0xfc, 0x00,
-    0x3c, 0x66, 0xc0, 0xc0, 0xc0, 0x66, 0x3c, 0x00,
-    0xf8, 0x6c, 0x66, 0x66, 0x66, 0x6c, 0xf8, 0x00,
-    0xfe, 0x62, 0x68, 0x78, 0x68, 0x62, 0xfe, 0x00,
-    0xfe, 0x62, 0x68, 0x78, 0x68, 0x60, 0xf0, 0x00,
-    0x3c, 0x66, 0xc0, 0xc0, 0xce, 0x66, 0x3e, 0x00,
-    0xcc, 0xcc, 0xcc, 0xfc, 0xcc, 0xcc, 0xcc, 0x00,
-    0x78, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0x1e, 0x0c, 0x0c, 0x0c, 0xcc, 0xcc, 0x78, 0x00,
-    0xe6, 0x66, 0x6c, 0x78, 0x6c, 0x66, 0xe6, 0x00,
-    0xf0, 0x60, 0x60, 0x60, 0x62, 0x66, 0xfe, 0x00,
-    0xc6, 0xee, 0xfe, 0xfe, 0xd6, 0xc6, 0xc6, 0x00,
-    0xc6, 0xe6, 0xf6, 0xde, 0xce, 0xc6, 0xc6, 0x00,
-    0x38, 0x6c, 0xc6, 0xc6, 0xc6, 0x6c, 0x38, 0x00,
-    0xfc, 0x66, 0x66, 0x7c, 0x60, 0x60, 0xf0, 0x00,
-    0x78, 0xcc, 0xcc, 0xcc, 0xdc, 0x78, 0x1c, 0x00,
-    0xfc, 0x66, 0x66, 0x7c, 0x6c, 0x66, 0xe6, 0x00,
-    0x78, 0xcc, 0xe0, 0x70, 0x1c, 0xcc, 0x78, 0x00,
-    0xfc, 0xb4, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xfc, 0x00,
-    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x78, 0x30, 0x00,
-    0xc6, 0xc6, 0xc6, 0xd6, 0xfe, 0xee, 0xc6, 0x00,
-    0xc6, 0xc6, 0x6c, 0x38, 0x38, 0x6c, 0xc6, 0x00,
-    0xcc, 0xcc, 0xcc, 0x78, 0x30, 0x30, 0x78, 0x00,
-    0xfe, 0xc6, 0x8c, 0x18, 0x32, 0x66, 0xfe, 0x00,
-    0x78, 0x60, 0x60, 0x60, 0x60, 0x60, 0x78, 0x00,
-    0xc0, 0x60, 0x30, 0x18, 0x0c, 0x06, 0x02, 0x00,
-    0x78, 0x18, 0x18, 0x18, 0x18, 0x18, 0x78, 0x00,
-    0x10, 0x38, 0x6c, 0xc6, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
-    0x30, 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x78, 0x0c, 0x7c, 0xcc, 0x76, 0x00,
-    0xe0, 0x60, 0x60, 0x7c, 0x66, 0x66, 0xdc, 0x00,
-    0x00, 0x00, 0x78, 0xcc, 0xc0, 0xcc, 0x78, 0x00,
-    0x1c, 0x0c, 0x0c, 0x7c, 0xcc, 0xcc, 0x76, 0x00,
-    0x00, 0x00, 0x78, 0xcc, 0xfc, 0xc0, 0x78, 0x00,
-    0x38, 0x6c, 0x60, 0xf0, 0x60, 0x60, 0xf0, 0x00,
-    0x00, 0x00, 0x76, 0xcc, 0xcc, 0x7c, 0x0c, 0xf8,
-    0xe0, 0x60, 0x6c, 0x76, 0x66, 0x66, 0xe6, 0x00,
-    0x30, 0x00, 0x70, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0x0c, 0x00, 0x0c, 0x0c, 0x0c, 0xcc, 0xcc, 0x78,
-    0xe0, 0x60, 0x66, 0x6c, 0x78, 0x6c, 0xe6, 0x00,
-    0x70, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0x00, 0x00, 0xcc, 0xfe, 0xfe, 0xd6, 0xc6, 0x00,
-    0x00, 0x00, 0xf8, 0xcc, 0xcc, 0xcc, 0xcc, 0x00,
-    0x00, 0x00, 0x78, 0xcc, 0xcc, 0xcc, 0x78, 0x00,
-    0x00, 0x00, 0xdc, 0x66, 0x66, 0x7c, 0x60, 0xf0,
-    0x00, 0x00, 0x76, 0xcc, 0xcc, 0x7c, 0x0c, 0x1e,
-    0x00, 0x00, 0xdc, 0x76, 0x66, 0x60, 0xf0, 0x00,
-    0x00, 0x00, 0x7c, 0xc0, 0x78, 0x0c, 0xf8, 0x00,
-    0x10, 0x30, 0x7c, 0x30, 0x30, 0x34, 0x18, 0x00,
-    0x00, 0x00, 0xcc, 0xcc, 0xcc, 0xcc, 0x76, 0x00,
-    0x00, 0x00, 0xcc, 0xcc, 0xcc, 0x78, 0x30, 0x00,
-    0x00, 0x00, 0xc6, 0xd6, 0xfe, 0xfe, 0x6c, 0x00,
-    0x00, 0x00, 0xc6, 0x6c, 0x38, 0x6c, 0xc6, 0x00,
-    0x00, 0x00, 0xcc, 0xcc, 0xcc, 0x7c, 0x0c, 0xf8,
-    0x00, 0x00, 0xfc, 0x98, 0x30, 0x64, 0xfc, 0x00,
-    0x1c, 0x30, 0x30, 0xe0, 0x30, 0x30, 0x1c, 0x00,
-    0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00,
-    0xe0, 0x30, 0x30, 0x1c, 0x30, 0x30, 0xe0, 0x00,
-    0x76, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x10, 0x38, 0x6c, 0xc6, 0xc6, 0xfe, 0x00,
-    0x78, 0xcc, 0xc0, 0xcc, 0x78, 0x18, 0x0c, 0x78,
-    0x00, 0xcc, 0x00, 0xcc, 0xcc, 0xcc, 0x7e, 0x00,
-    0x1c, 0x00, 0x78, 0xcc, 0xfc, 0xc0, 0x78, 0x00,
-    0x7e, 0xc3, 0x3c, 0x06, 0x3e, 0x66, 0x3f, 0x00,
-    0xcc, 0x00, 0x78, 0x0c, 0x7c, 0xcc, 0x7e, 0x00,
-    0xe0, 0x00, 0x78, 0x0c, 0x7c, 0xcc, 0x7e, 0x00,
-    0x30, 0x30, 0x78, 0x0c, 0x7c, 0xcc, 0x7e, 0x00,
-    0x00, 0x00, 0x78, 0xc0, 0xc0, 0x78, 0x0c, 0x38,
-    0x7e, 0xc3, 0x3c, 0x66, 0x7e, 0x60, 0x3c, 0x00,
-    0xcc, 0x00, 0x78, 0xcc, 0xfc, 0xc0, 0x78, 0x00,
-    0xe0, 0x00, 0x78, 0xcc, 0xfc, 0xc0, 0x78, 0x00,
-    0xcc, 0x00, 0x70, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0x7c, 0xc6, 0x38, 0x18, 0x18, 0x18, 0x3c, 0x00,
-    0xe0, 0x00, 0x70, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0xc6, 0x38, 0x6c, 0xc6, 0xfe, 0xc6, 0xc6, 0x00,
-    0x30, 0x30, 0x00, 0x78, 0xcc, 0xfc, 0xcc, 0x00,
-    0x1c, 0x00, 0xfc, 0x60, 0x78, 0x60, 0xfc, 0x00,
-    0x00, 0x00, 0x7f, 0x0c, 0x7f, 0xcc, 0x7f, 0x00,
-    0x3e, 0x6c, 0xcc, 0xfe, 0xcc, 0xcc, 0xce, 0x00,
-    0x78, 0xcc, 0x00, 0x78, 0xcc, 0xcc, 0x78, 0x00,
-    0x00, 0xcc, 0x00, 0x78, 0xcc, 0xcc, 0x78, 0x00,
-    0x00, 0xe0, 0x00, 0x78, 0xcc, 0xcc, 0x78, 0x00,
-    0x78, 0xcc, 0x00, 0xcc, 0xcc, 0xcc, 0x7e, 0x00,
-    0x00, 0xe0, 0x00, 0xcc, 0xcc, 0xcc, 0x7e, 0x00,
-    0x00, 0xcc, 0x00, 0xcc, 0xcc, 0x7c, 0x0c, 0xf8,
-    0xc3, 0x18, 0x3c, 0x66, 0x66, 0x3c, 0x18, 0x00,
-    0xcc, 0x00, 0xcc, 0xcc, 0xcc, 0xcc, 0x78, 0x00,
-    0x18, 0x18, 0x7e, 0xc0, 0xc0, 0x7e, 0x18, 0x18,
-    0x38, 0x6c, 0x64, 0xf0, 0x60, 0xe6, 0xfc, 0x00,
-    0xcc, 0xcc, 0x78, 0xfc, 0x30, 0xfc, 0x30, 0x30,
-    0xf8, 0xcc, 0xcc, 0xfa, 0xc6, 0xcf, 0xc6, 0xc7,
-    0x0e, 0x1b, 0x18, 0x3c, 0x18, 0x18, 0xd8, 0x70,
-    0x1c, 0x00, 0x78, 0x0c, 0x7c, 0xcc, 0x7e, 0x00,
-    0x38, 0x00, 0x70, 0x30, 0x30, 0x30, 0x78, 0x00,
-    0x00, 0x1c, 0x00, 0x78, 0xcc, 0xcc, 0x78, 0x00,
-    0x00, 0x1c, 0x00, 0xcc, 0xcc, 0xcc, 0x7e, 0x00,
-    0x00, 0xf8, 0x00, 0xf8, 0xcc, 0xcc, 0xcc, 0x00,
-    0xfc, 0x00, 0xcc, 0xec, 0xfc, 0xdc, 0xcc, 0x00,
-    0x3c, 0x6c, 0x6c, 0x3e, 0x00, 0x7e, 0x00, 0x00,
-    0x38, 0x6c, 0x6c, 0x38, 0x00, 0x7c, 0x00, 0x00,
-    0x30, 0x00, 0x30, 0x60, 0xc0, 0xcc, 0x78, 0x00,
-    0x00, 0x00, 0x00, 0xfc, 0xc0, 0xc0, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0xfc, 0x0c, 0x0c, 0x00, 0x00,
-    0xc3, 0xc6, 0xcc, 0xde, 0x33, 0x66, 0xcc, 0x0f,
-    0xc3, 0xc6, 0xcc, 0xdb, 0x37, 0x6f, 0xcf, 0x03,
-    0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x18, 0x00,
-    0x00, 0x33, 0x66, 0xcc, 0x66, 0x33, 0x00, 0x00,
-    0x00, 0xcc, 0x66, 0x33, 0x66, 0xcc, 0x00, 0x00,
-    0x22, 0x88, 0x22, 0x88, 0x22, 0x88, 0x22, 0x88,
-    0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa,
-    0xdb, 0x77, 0xdb, 0xee, 0xdb, 0x77, 0xdb, 0xee,
-    0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18,
-    0x36, 0x36, 0x36, 0x36, 0xf6, 0x36, 0x36, 0x36,
-    0x00, 0x00, 0x00, 0x00, 0xfe, 0x36, 0x36, 0x36,
-    0x00, 0x00, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18,
-    0x36, 0x36, 0xf6, 0x06, 0xf6, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
-    0x00, 0x00, 0xfe, 0x06, 0xf6, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0xf6, 0x06, 0xfe, 0x00, 0x00, 0x00,
-    0x36, 0x36, 0x36, 0x36, 0xfe, 0x00, 0x00, 0x00,
-    0x18, 0x18, 0xf8, 0x18, 0xf8, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0xf8, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0x18, 0x18, 0x1f, 0x00, 0x00, 0x00,
-    0x18, 0x18, 0x18, 0x18, 0xff, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0xff, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0x18, 0x18, 0x1f, 0x18, 0x18, 0x18,
-    0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
-    0x18, 0x18, 0x18, 0x18, 0xff, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18,
-    0x36, 0x36, 0x36, 0x36, 0x37, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x37, 0x30, 0x3f, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x3f, 0x30, 0x37, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0xf7, 0x00, 0xff, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0xff, 0x00, 0xf7, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x37, 0x30, 0x37, 0x36, 0x36, 0x36,
-    0x00, 0x00, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00,
-    0x36, 0x36, 0xf7, 0x00, 0xf7, 0x36, 0x36, 0x36,
-    0x18, 0x18, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00,
-    0x36, 0x36, 0x36, 0x36, 0xff, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0xff, 0x00, 0xff, 0x18, 0x18, 0x18,
-    0x00, 0x00, 0x00, 0x00, 0xff, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x36, 0x36, 0x3f, 0x00, 0x00, 0x00,
-    0x18, 0x18, 0x1f, 0x18, 0x1f, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18,
-    0x00, 0x00, 0x00, 0x00, 0x3f, 0x36, 0x36, 0x36,
-    0x36, 0x36, 0x36, 0x36, 0xff, 0x36, 0x36, 0x36,
-    0x18, 0x18, 0xff, 0x18, 0xff, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0x18, 0x18, 0xf8, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x1f, 0x18, 0x18, 0x18,
-    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-    0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0,
-    0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
-    0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x76, 0xdc, 0xc8, 0xdc, 0x76, 0x00,
-    0x00, 0x78, 0xcc, 0xf8, 0xcc, 0xf8, 0xc0, 0xc0,
-    0x00, 0xfc, 0xcc, 0xc0, 0xc0, 0xc0, 0xc0, 0x00,
-    0x00, 0xfe, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x00,
-    0xfc, 0xcc, 0x60, 0x30, 0x60, 0xcc, 0xfc, 0x00,
-    0x00, 0x00, 0x7e, 0xd8, 0xd8, 0xd8, 0x70, 0x00,
-    0x00, 0x66, 0x66, 0x66, 0x66, 0x7c, 0x60, 0xc0,
-    0x00, 0x76, 0xdc, 0x18, 0x18, 0x18, 0x18, 0x00,
-    0xfc, 0x30, 0x78, 0xcc, 0xcc, 0x78, 0x30, 0xfc,
-    0x38, 0x6c, 0xc6, 0xfe, 0xc6, 0x6c, 0x38, 0x00,
-    0x38, 0x6c, 0xc6, 0xc6, 0x6c, 0x6c, 0xee, 0x00,
-    0x1c, 0x30, 0x18, 0x7c, 0xcc, 0xcc, 0x78, 0x00,
-    0x00, 0x00, 0x7e, 0xdb, 0xdb, 0x7e, 0x00, 0x00,
-    0x06, 0x0c, 0x7e, 0xdb, 0xdb, 0x7e, 0x60, 0xc0,
-    0x38, 0x60, 0xc0, 0xf8, 0xc0, 0x60, 0x38, 0x00,
-    0x78, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x00,
-    0x00, 0xfc, 0x00, 0xfc, 0x00, 0xfc, 0x00, 0x00,
-    0x30, 0x30, 0xfc, 0x30, 0x30, 0x00, 0xfc, 0x00,
-    0x60, 0x30, 0x18, 0x30, 0x60, 0x00, 0xfc, 0x00,
-    0x18, 0x30, 0x60, 0x30, 0x18, 0x00, 0xfc, 0x00,
-    0x0e, 0x1b, 0x1b, 0x18, 0x18, 0x18, 0x18, 0x18,
-    0x18, 0x18, 0x18, 0x18, 0x18, 0xd8, 0xd8, 0x70,
-    0x30, 0x30, 0x00, 0xfc, 0x00, 0x30, 0x30, 0x00,
-    0x00, 0x76, 0xdc, 0x00, 0x76, 0xdc, 0x00, 0x00,
-    0x38, 0x6c, 0x6c, 0x38, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
-    0x0f, 0x0c, 0x0c, 0x0c, 0xec, 0x6c, 0x3c, 0x1c,
-    0x78, 0x6c, 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00,
-    0x70, 0x18, 0x30, 0x60, 0x78, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-u8 const vgafont14[256 * 14] VAR16 = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7e, 0x81, 0xa5, 0x81, 0x81, 0xbd, 0x99, 0x81, 0x7e, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7e, 0xff, 0xdb, 0xff, 0xff, 0xc3, 0xe7, 0xff, 0x7e, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x6c, 0xfe, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x10, 0x38, 0x7c, 0xfe, 0x7c, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x3c, 0xe7, 0xe7, 0xe7, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0xff, 0xff, 0x7e, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3c, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xe7, 0xc3, 0xc3, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x3c, 0x66, 0x42, 0x42, 0x66, 0x3c, 0x00, 0x00, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0xc3, 0x99, 0xbd, 0xbd, 0x99, 0xc3, 0xff, 0xff, 0xff, 0xff,
- 0x00, 0x00, 0x1e, 0x0e, 0x1a, 0x32, 0x78, 0xcc, 0xcc, 0xcc, 0x78, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x3c, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x7e, 0x18, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x3f, 0x33, 0x3f, 0x30, 0x30, 0x30, 0x70, 0xf0, 0xe0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7f, 0x63, 0x7f, 0x63, 0x63, 0x63, 0x67, 0xe7, 0xe6, 0xc0, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x18, 0xdb, 0x3c, 0xe7, 0x3c, 0xdb, 0x18, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf8, 0xfe, 0xf8, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x02, 0x06, 0x0e, 0x3e, 0xfe, 0x3e, 0x0e, 0x06, 0x02, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x00, 0x66, 0x66, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7f, 0xdb, 0xdb, 0xdb, 0x7b, 0x1b, 0x1b, 0x1b, 0x1b, 0x00, 0x00, 0x00,
- 0x00, 0x7c, 0xc6, 0x60, 0x38, 0x6c, 0xc6, 0xc6, 0x6c, 0x38, 0x0c, 0xc6, 0x7c, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x7e, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x18, 0x0c, 0xfe, 0x0c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x30, 0x60, 0xfe, 0x60, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x28, 0x6c, 0xfe, 0x6c, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x10, 0x38, 0x38, 0x7c, 0x7c, 0xfe, 0xfe, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0xfe, 0xfe, 0x7c, 0x7c, 0x38, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x3c, 0x3c, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x66, 0x66, 0x66, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xc0, 0xc0, 0xc6, 0xcc, 0xd8, 0x30, 0x60, 0xdc, 0x86, 0x0c, 0x18, 0x3e, 0x00,
- 0x00, 0xc0, 0xc0, 0xc6, 0xcc, 0xd8, 0x30, 0x66, 0xce, 0x9e, 0x3e, 0x06, 0x06, 0x00,
- 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x3c, 0x3c, 0x3c, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x36, 0x6c, 0xd8, 0x6c, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xd8, 0x6c, 0x36, 0x6c, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44,
- 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa,
- 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xf6, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf6, 0x06, 0xf6, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 0xf6, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf6, 0x06, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x30, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf7, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xf7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf7, 0x00, 0xf7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x18, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xff, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x18, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0,
- 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xdc, 0xd8, 0xd8, 0xdc, 0x76, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x7c, 0xc6, 0xfc, 0xc6, 0xc6, 0xfc, 0xc0, 0xc0, 0x40, 0x00,
- 0x00, 0x00, 0xfe, 0xc6, 0xc6, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xfe, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xfe, 0xc6, 0x60, 0x30, 0x18, 0x30, 0x60, 0xc6, 0xfe, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0xd8, 0xd8, 0xd8, 0xd8, 0x70, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x7c, 0x60, 0x60, 0xc0, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x76, 0xdc, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7e, 0x18, 0x3c, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x7e, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x38, 0x6c, 0xc6, 0xc6, 0xfe, 0xc6, 0xc6, 0x6c, 0x38, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x38, 0x6c, 0xc6, 0xc6, 0xc6, 0x6c, 0x6c, 0x6c, 0xee, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x1e, 0x30, 0x18, 0x0c, 0x3e, 0x66, 0x66, 0x66, 0x3c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0xdb, 0xdb, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x03, 0x06, 0x7e, 0xdb, 0xdb, 0xf3, 0x7e, 0x60, 0xc0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x1c, 0x30, 0x60, 0x60, 0x7c, 0x60, 0x60, 0x30, 0x1c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x7c, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0xc6, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0xfe, 0x00, 0x00, 0xfe, 0x00, 0x00, 0xfe, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x18, 0x18, 0x7e, 0x18, 0x18, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x30, 0x18, 0x0c, 0x06, 0x0c, 0x18, 0x30, 0x00, 0x7e, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x0c, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0c, 0x00, 0x7e, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x0e, 0x1b, 0x1b, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xd8, 0xd8, 0x70, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7e, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x76, 0xdc, 0x00, 0x76, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x38, 0x6c, 0x6c, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0xec, 0x6c, 0x3c, 0x1c, 0x00, 0x00, 0x00,
- 0x00, 0xd8, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x70, 0xd8, 0x30, 0x60, 0xc8, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-u8 const vgafont16[256 * 16] VAR16 = {
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- 0x00, 0x00, 0x7e, 0x81, 0xa5, 0x81, 0x81, 0xbd, 0x99, 0x81, 0x81, 0x7e, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7e, 0xff, 0xdb, 0xff, 0xff, 0xc3, 0xe7, 0xff, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x6c, 0xfe, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x7c, 0xfe, 0x7c, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x18, 0x3c, 0x3c, 0xe7, 0xe7, 0xe7, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x18, 0x3c, 0x7e, 0xff, 0xff, 0x7e, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3c, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe7, 0xc3, 0xc3, 0xe7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x66, 0x42, 0x42, 0x66, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xc3, 0x99, 0xbd, 0xbd, 0x99, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x00, 0x00, 0x1e, 0x0e, 0x1a, 0x32, 0x78, 0xcc, 0xcc, 0xcc, 0xcc, 0x78, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x3c, 0x66, 0x66, 0x66, 0x66, 0x3c, 0x18, 0x7e, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x3f, 0x33, 0x3f, 0x30, 0x30, 0x30, 0x30, 0x70, 0xf0, 0xe0, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7f, 0x63, 0x7f, 0x63, 0x63, 0x63, 0x63, 0x67, 0xe7, 0xe6, 0xc0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x18, 0x18, 0xdb, 0x3c, 0xe7, 0x3c, 0xdb, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfe, 0xf8, 0xf0, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0xfe, 0x3e, 0x1e, 0x0e, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x00, 0x66, 0x66, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x7f, 0xdb, 0xdb, 0xdb, 0x7b, 0x1b, 0x1b, 0x1b, 0x1b, 0x1b, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x7c, 0xc6, 0x60, 0x38, 0x6c, 0xc6, 0xc6, 0x6c, 0x38, 0x0c, 0xc6, 0x7c, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xfe, 0xfe, 0xfe, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x7e, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x7e, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7e, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x0c, 0xfe, 0x0c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x60, 0xfe, 0x60, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x66, 0xff, 0x66, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x38, 0x7c, 0x7c, 0xfe, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xfe, 0xfe, 0x7c, 0x7c, 0x38, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x3c, 0x3c, 0x3c, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x66, 0x66, 0x66, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x6c, 0x6c, 0xfe, 0x6c, 0x6c, 0x6c, 0xfe, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x7c, 0xc6, 0xc2, 0xc0, 0x7c, 0x06, 0x06, 0x86, 0xc6, 0x7c, 0x18, 0x18, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc2, 0xc6, 0x0c, 0x18, 0x30, 0x60, 0xc6, 0x86, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x38, 0x6c, 0x6c, 0x38, 0x76, 0xdc, 0xcc, 0xcc, 0xcc, 0x76, 0x00, 0x00, 0x00, 0x00,
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- 0x00, 0x0e, 0x1b, 0x18, 0x18, 0x18, 0x7e, 0x18, 0x18, 0x18, 0x18, 0x18, 0xd8, 0x70, 0x00, 0x00,
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- 0x00, 0x0c, 0x18, 0x30, 0x00, 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3c, 0x00, 0x00, 0x00, 0x00,
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- 0x00, 0x18, 0x30, 0x60, 0x00, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x76, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x76, 0xdc, 0x00, 0xdc, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, 0x00,
- 0x76, 0xdc, 0x00, 0xc6, 0xe6, 0xf6, 0xfe, 0xde, 0xce, 0xc6, 0xc6, 0xc6, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x3c, 0x6c, 0x6c, 0x3e, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x38, 0x6c, 0x6c, 0x38, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x30, 0x30, 0x00, 0x30, 0x30, 0x60, 0xc0, 0xc6, 0xc6, 0x7c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xc0, 0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xc0, 0xc0, 0xc2, 0xc6, 0xcc, 0x18, 0x30, 0x60, 0xce, 0x9b, 0x06, 0x0c, 0x1f, 0x00, 0x00,
- 0x00, 0xc0, 0xc0, 0xc2, 0xc6, 0xcc, 0x18, 0x30, 0x66, 0xce, 0x96, 0x3e, 0x06, 0x06, 0x00, 0x00,
- 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x3c, 0x3c, 0x3c, 0x18, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x6c, 0xd8, 0x6c, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x6c, 0x36, 0x6c, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44, 0x11, 0x44,
- 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa,
- 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xf6, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf6, 0x06, 0xf6, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 0xf6, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf6, 0x06, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xf8, 0x18, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x30, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf7, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xf7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x37, 0x30, 0x37, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0xf7, 0x00, 0xf7, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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- 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0xff, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0xff, 0x18, 0xff, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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- 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7e, 0x18, 0x18, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x30, 0x18, 0x0c, 0x06, 0x0c, 0x18, 0x30, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x0c, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0c, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x0e, 0x1b, 0x1b, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
- 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xd8, 0xd8, 0xd8, 0x70, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7e, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xdc, 0x00, 0x76, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x38, 0x6c, 0x6c, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0xec, 0x6c, 0x6c, 0x3c, 0x1c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0xd8, 0x6c, 0x6c, 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x70, 0xd8, 0x30, 0x60, 0xc8, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
diff --git a/qemu/roms/qemu-palcode/vgaio.c b/qemu/roms/qemu-palcode/vgaio.c
deleted file mode 100644
index 2dd7eb750..000000000
--- a/qemu/roms/qemu-palcode/vgaio.c
+++ /dev/null
@@ -1,606 +0,0 @@
-// VGA io port access
-//
-// Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
-// Copyright (C) 2001-2008 the LGPL VGABios developers Team
-//
-// This file may be distributed under the terms of the GNU LGPLv3 license.
-
-#include "protos.h"
-#include "ioport.h"
-#include "pci.h"
-#include "pci_regs.h"
-#include "pci_ids.h"
-#include "vgatables.h"
-
-#define GET_FARVAR(seg, ofs)		(ofs)
-#define SET_FARVAR(seg, ofs, val)	((ofs) = (val))
-
-static struct saveBDAstate BDA;
-
-#define GET_BDA(field)			(BDA.field)
-#define GET_GLOBAL(val)			(val)
-
-// TODO
-//  * replace direct in/out calls with wrapper functions
-
-
-/****************************************************************
- * Attribute control
- ****************************************************************/
-
-void
-vgahw_screen_disable(void)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x00, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_screen_enable(void)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_set_border_color(u8 color)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x00, VGAREG_ACTL_ADDRESS);
-    u8 v1 = color & 0x0f;
-    if (v1 & 0x08)
-        v1 += 0x08;
-    outb(v1, VGAREG_ACTL_WRITE_DATA);
-
-    u8 v2 = color & 0x10;
-    int i;
-    for (i = 1; i < 4; i++) {
-        outb(i, VGAREG_ACTL_ADDRESS);
-
-        u8 cur = inb(VGAREG_ACTL_READ_DATA);
-        cur &= 0xef;
-        cur |= v2;
-        outb(cur, VGAREG_ACTL_WRITE_DATA);
-    }
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_set_overscan_border_color(u8 color)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x11, VGAREG_ACTL_ADDRESS);
-    outb(color, VGAREG_ACTL_WRITE_DATA);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-u8
-vgahw_get_overscan_border_color(void)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x11, VGAREG_ACTL_ADDRESS);
-    u8 v = inb(VGAREG_ACTL_READ_DATA);
-    inb(VGAREG_ACTL_RESET);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-    return v;
-}
-
-void
-vgahw_set_palette(u8 palid)
-{
-    inb(VGAREG_ACTL_RESET);
-    palid &= 0x01;
-    int i;
-    for (i = 1; i < 4; i++) {
-        outb(i, VGAREG_ACTL_ADDRESS);
-
-        u8 v = inb(VGAREG_ACTL_READ_DATA);
-        v &= 0xfe;
-        v |= palid;
-        outb(v, VGAREG_ACTL_WRITE_DATA);
-    }
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_set_single_palette_reg(u8 reg, u8 val)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(reg, VGAREG_ACTL_ADDRESS);
-    outb(val, VGAREG_ACTL_WRITE_DATA);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-u8
-vgahw_get_single_palette_reg(u8 reg)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(reg, VGAREG_ACTL_ADDRESS);
-    u8 v = inb(VGAREG_ACTL_READ_DATA);
-    inb(VGAREG_ACTL_RESET);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-    return v;
-}
-
-void
-vgahw_set_all_palette_reg(u8 *data_far)
-{
-    inb(VGAREG_ACTL_RESET);
-    int i;
-    for (i = 0; i < 0x10; i++) {
-        outb(i, VGAREG_ACTL_ADDRESS);
-        u8 val = GET_FARVAR(seg, *data_far);
-        outb(val, VGAREG_ACTL_WRITE_DATA);
-        data_far++;
-    }
-    outb(0x11, VGAREG_ACTL_ADDRESS);
-    outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_get_all_palette_reg(u8 *data_far)
-{
-    int i;
-    for (i = 0; i < 0x10; i++) {
-        inb(VGAREG_ACTL_RESET);
-        outb(i, VGAREG_ACTL_ADDRESS);
-        SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
-        data_far++;
-    }
-    inb(VGAREG_ACTL_RESET);
-    outb(0x11, VGAREG_ACTL_ADDRESS);
-    SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
-    inb(VGAREG_ACTL_RESET);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_toggle_intensity(u8 flag)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x10, VGAREG_ACTL_ADDRESS);
-    u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
-    outb(val, VGAREG_ACTL_WRITE_DATA);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_select_video_dac_color_page(u8 flag, u8 data)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x10, VGAREG_ACTL_ADDRESS);
-    u8 val = inb(VGAREG_ACTL_READ_DATA);
-    if (!(flag & 0x01)) {
-        // select paging mode
-        val = (val & 0x7f) | (data << 7);
-        outb(val, VGAREG_ACTL_WRITE_DATA);
-        outb(0x20, VGAREG_ACTL_ADDRESS);
-        return;
-    }
-    // select page
-    inb(VGAREG_ACTL_RESET);
-    outb(0x14, VGAREG_ACTL_ADDRESS);
-    if (!(val & 0x80))
-        data <<= 2;
-    data &= 0x0f;
-    outb(data, VGAREG_ACTL_WRITE_DATA);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-}
-
-void
-vgahw_read_video_dac_state(u8 *pmode, u8 *curpage)
-{
-    inb(VGAREG_ACTL_RESET);
-    outb(0x10, VGAREG_ACTL_ADDRESS);
-    u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
-
-    inb(VGAREG_ACTL_RESET);
-    outb(0x14, VGAREG_ACTL_ADDRESS);
-    u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
-    if (!(val1 & 0x01))
-        val2 >>= 2;
-
-    inb(VGAREG_ACTL_RESET);
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-
-    *pmode = val1;
-    *curpage = val2;
-}
-
-
-/****************************************************************
- * DAC control
- ****************************************************************/
-
-void
-vgahw_set_dac_regs(u8 *data_far, u8 start, int count)
-{
-    outb(start, VGAREG_DAC_WRITE_ADDRESS);
-    while (count) {
-        outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
-        data_far++;
-        outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
-        data_far++;
-        outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
-        data_far++;
-        count--;
-    }
-}
-
-void
-vgahw_get_dac_regs(u8 *data_far, u8 start, int count)
-{
-    outb(start, VGAREG_DAC_READ_ADDRESS);
-    while (count) {
-        SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
-        data_far++;
-        SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
-        data_far++;
-        SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
-        data_far++;
-        count--;
-    }
-}
-
-void
-vgahw_set_pel_mask(u8 val)
-{
-    outb(val, VGAREG_PEL_MASK);
-}
-
-u8
-vgahw_get_pel_mask(void)
-{
-    return inb(VGAREG_PEL_MASK);
-}
-
-void
-vgahw_save_dac_state(struct saveDACcolors *info)
-{
-    /* XXX: check this */
-    SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
-    SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
-    SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK));
-    vgahw_get_dac_regs(info->dac, 0, 256);
-    SET_FARVAR(seg, info->color_select, 0);
-}
-
-void
-vgahw_restore_dac_state(struct saveDACcolors *info)
-{
-    outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK);
-    vgahw_set_dac_regs(info->dac, 0, 256);
-    outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
-}
-
-
-/****************************************************************
- * Memory control
- ****************************************************************/
-
-void
-vgahw_sequ_write(u8 index, u8 value)
-{
-    outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
-}
-
-void
-vgahw_grdc_write(u8 index, u8 value)
-{
-    outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
-}
-
-void
-vgahw_set_text_block_specifier(u8 spec)
-{
-    outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
-}
-
-void
-get_font_access(void)
-{
-    outw(0x0100, VGAREG_SEQU_ADDRESS);
-    outw(0x0402, VGAREG_SEQU_ADDRESS);
-    outw(0x0704, VGAREG_SEQU_ADDRESS);
-    outw(0x0300, VGAREG_SEQU_ADDRESS);
-    outw(0x0204, VGAREG_GRDC_ADDRESS);
-    outw(0x0005, VGAREG_GRDC_ADDRESS);
-    outw(0x0406, VGAREG_GRDC_ADDRESS);
-}
-
-void
-release_font_access(void)
-{
-    outw(0x0100, VGAREG_SEQU_ADDRESS);
-    outw(0x0302, VGAREG_SEQU_ADDRESS);
-    outw(0x0304, VGAREG_SEQU_ADDRESS);
-    outw(0x0300, VGAREG_SEQU_ADDRESS);
-    u16 v = (inw(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
-    outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
-    outw(0x0004, VGAREG_GRDC_ADDRESS);
-    outw(0x1005, VGAREG_GRDC_ADDRESS);
-}
-
-
-/****************************************************************
- * CRTC registers
- ****************************************************************/
-
-static u16
-get_crtc(void)
-{
-    return GET_BDA(crtc_address);
-}
-
-void
-vgahw_set_cursor_shape(u8 start, u8 end)
-{
-    u16 crtc_addr = get_crtc();
-    outb(0x0a, crtc_addr);
-    outb(start, crtc_addr + 1);
-    outb(0x0b, crtc_addr);
-    outb(end, crtc_addr + 1);
-}
-
-void
-vgahw_set_active_page(u16 address)
-{
-    u16 crtc_addr = get_crtc();
-    outb(0x0c, crtc_addr);
-    outb((address & 0xff00) >> 8, crtc_addr + 1);
-    outb(0x0d, crtc_addr);
-    outb(address & 0x00ff, crtc_addr + 1);
-}
-
-void
-vgahw_set_cursor_pos(u16 address)
-{
-    u16 crtc_addr = get_crtc();
-    outb(0x0e, crtc_addr);
-    outb((address & 0xff00) >> 8, crtc_addr + 1);
-    outb(0x0f, crtc_addr);
-    outb(address & 0x00ff, crtc_addr + 1);
-}
-
-void
-vgahw_set_scan_lines(u8 lines)
-{
-    u16 crtc_addr = get_crtc();
-    outb(0x09, crtc_addr);
-    u8 crtc_r9 = inb(crtc_addr + 1);
-    crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
-    outb(crtc_r9, crtc_addr + 1);
-}
-
-// Get vertical display end
-u16
-vgahw_get_vde(void)
-{
-    u16 crtc_addr = get_crtc();
-    outb(0x12, crtc_addr);
-    u16 vde = inb(crtc_addr + 1);
-    outb(0x07, crtc_addr);
-    u8 ovl = inb(crtc_addr + 1);
-    vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
-    return vde;
-}
-
-
-/****************************************************************
- * Save/Restore/Set state
- ****************************************************************/
-
-void
-vgahw_save_state(struct saveVideoHardware *info)
-{
-    u16 crtc_addr = get_crtc();
-    SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
-    SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
-    SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
-    inb(VGAREG_ACTL_RESET);
-    u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
-    SET_FARVAR(seg, info->actl_index, ar_index);
-    SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
-
-    u16 i;
-    for (i=0; i<4; i++) {
-        outb(i+1, VGAREG_SEQU_ADDRESS);
-        SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA));
-    }
-    outb(0, VGAREG_SEQU_ADDRESS);
-    SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA));
-
-    for (i=0; i<25; i++) {
-        outb(i, crtc_addr);
-        SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1));
-    }
-
-    for (i=0; i<20; i++) {
-        inb(VGAREG_ACTL_RESET);
-        outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
-        SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA));
-    }
-    inb(VGAREG_ACTL_RESET);
-
-    for (i=0; i<9; i++) {
-        outb(i, VGAREG_GRDC_ADDRESS);
-        SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA));
-    }
-
-    SET_FARVAR(seg, info->crtc_addr, crtc_addr);
-
-    /* XXX: read plane latches */
-    for (i=0; i<4; i++)
-        SET_FARVAR(seg, info->plane_latch[i], 0);
-}
-
-void
-vgahw_restore_state(struct saveVideoHardware *info)
-{
-    // Reset Attribute Ctl flip-flop
-    inb(VGAREG_ACTL_RESET);
-
-    u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
-
-    u16 i;
-    for (i=0; i<4; i++) {
-        outb(i+1, VGAREG_SEQU_ADDRESS);
-        outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA);
-    }
-    outb(0, VGAREG_SEQU_ADDRESS);
-    outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA);
-
-    // Disable CRTC write protection
-    outw(0x0011, crtc_addr);
-    // Set CRTC regs
-    for (i=0; i<25; i++)
-        if (i != 0x11) {
-            outb(i, crtc_addr);
-            outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1);
-        }
-    // select crtc base address
-    u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
-    if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
-        v |= 0x01;
-    outb(v, VGAREG_WRITE_MISC_OUTPUT);
-
-    // enable write protection if needed
-    outb(0x11, crtc_addr);
-    outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1);
-
-    // Set Attribute Ctl
-    u16 ar_index = GET_FARVAR(seg, info->actl_index);
-    inb(VGAREG_ACTL_RESET);
-    for (i=0; i<20; i++) {
-        outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
-        outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
-    }
-    outb(ar_index, VGAREG_ACTL_ADDRESS);
-    inb(VGAREG_ACTL_RESET);
-
-    for (i=0; i<9; i++) {
-        outb(i, VGAREG_GRDC_ADDRESS);
-        outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA);
-    }
-
-    outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
-    outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
-    outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
-    outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
-}
-
-void
-vgahw_set_mode(struct VideoParam_s *vparam_g)
-{
-    // Reset Attribute Ctl flip-flop
-    inb(VGAREG_ACTL_RESET);
-
-    // Set Attribute Ctl
-    u16 i;
-    for (i = 0; i <= 0x13; i++) {
-        outb(i, VGAREG_ACTL_ADDRESS);
-        outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
-    }
-    outb(0x14, VGAREG_ACTL_ADDRESS);
-    outb(0x00, VGAREG_ACTL_WRITE_DATA);
-
-    // Set Sequencer Ctl
-    outb(0, VGAREG_SEQU_ADDRESS);
-    outb(0x03, VGAREG_SEQU_DATA);
-    for (i = 1; i <= 4; i++) {
-        outb(i, VGAREG_SEQU_ADDRESS);
-        outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
-    }
-
-    // Set Grafx Ctl
-    for (i = 0; i <= 8; i++) {
-        outb(i, VGAREG_GRDC_ADDRESS);
-        outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
-    }
-
-    // Set CRTC address VGA or MDA
-    u8 miscreg = GET_GLOBAL(vparam_g->miscreg);
-    u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
-    if (!(miscreg & 1))
-        crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
-
-    // Disable CRTC write protection
-    outw(0x0011, crtc_addr);
-    // Set CRTC regs
-    for (i = 0; i <= 0x18; i++) {
-        outb(i, crtc_addr);
-        outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
-    }
-
-    // Set the misc register
-    outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
-
-    // Enable video
-    outb(0x20, VGAREG_ACTL_ADDRESS);
-    inb(VGAREG_ACTL_RESET);
-}
-
-
-/****************************************************************
- * Misc
- ****************************************************************/
-
-void
-vgahw_enable_video_addressing(u8 disable)
-{
-    u8 v = (disable & 1) ? 0x00 : 0x02;
-    u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
-    outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
-}
-
-void
-vgahw_init(void)
-{
-  struct vgamode_s *vmode_g;
-  int bdf, max;
-
-  foreachpci(bdf, max)
-    {
-      uint16_t class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
-      if (class == PCI_CLASS_DISPLAY_VGA)
-        goto found;
-    }
-  return;
-
- found:
-  have_vga = 1;
-
-  vmode_g = find_vga_entry(3);
-
-  vgahw_sequ_write(0, 1);	// Assert sync reset
-  
-  // Switch to color mode and enable CPU access 480 lines
-  outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
-
-  vgahw_sequ_write(0, 3);	// De-assert sync reset
-
-  vgahw_set_mode(vmode_g->vparam);
-
-  vgahw_sequ_write(4, 0x06); // disable odd/even + chain4
-  vgahw_sequ_write(1, vmode_g->vparam->sequ_regs[1] | 0x20); // disable video
-  vgahw_grdc_write(5, vmode_g->vparam->grdc_regs[5] & 0xef); // disable odd/even
-  vgahw_grdc_write(6, 0x05); // set mem map to 0xa0000 and graphics mode
-  vgahw_sequ_write(2, 0x04); // enable write plane 2
-
-  {
-    unsigned char *font_ptr = pci_mem_base + SEG_GRAPH*16;
-    int i;
-
-    for (i = 0; i < 0x100; i++)
-      __builtin_memcpy(font_ptr + i*32, vgafont16 + i*16, 16);
-  }
-
-  {
-    int i = vmode_g->dacsize / 3;
-    vgahw_set_dac_regs(vmode_g->dac, 0, i);
-  }
-
-  vgahw_sequ_write(4, 0x2); // enable odd/even
-  vgahw_set_mode(vmode_g->vparam);
-}
diff --git a/qemu/roms/qemu-palcode/vgatables.c b/qemu/roms/qemu-palcode/vgatables.c
deleted file mode 100644
index 8c934c054..000000000
--- a/qemu/roms/qemu-palcode/vgatables.c
+++ /dev/null
@@ -1,441 +0,0 @@
-// Tables used by VGA bios
-//
-// Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
-// Copyright (C) 2001-2008 the LGPL VGABios developers Team
-//
-// This file may be distributed under the terms of the GNU LGPLv3 license.
-
-#include "protos.h"
-#include "vgatables.h" // struct VideoParamTableEntry_s
-
-#define ARRAY_SIZE(var)	(sizeof(var) / sizeof(var[0]))
-#define GET_GLOBAL(var) (var)
-#define VAR16
-
-/****************************************************************
- * Video parameter table
- ****************************************************************/
-
-struct VideoParam_s video_param_table[] VAR16 = {
-    // index=0x00 no mode defined
-    {},
-    // index=0x01 no mode defined
-    {},
-    // index=0x02 no mode defined
-    {},
-    // index=0x03 no mode defined
-    {},
-    // index=0x04 vga mode 0x04
-    { 40, 24, 8, 0x0800,      /* tw, th-1, ch, slength */
-      { 0x09, 0x03, 0x00, 0x02 },    /* sequ_regs */
-      0x63,                      /* miscreg */
-      { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
-        0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
-        0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-        0x01, 0x00, 0x03, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff }, /* grdc_regs */
-    },
-    /* index=0x05 vga mode 0x05 */
-    { 40, 24, 8, 0x0800,     /* tw, th-1, ch, slength */
-      { 0x09, 0x03, 0x00, 0x02 },    /* sequ_regs */
-      0x63,                      /* miscreg */
-      { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
-        0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
-        0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-        0x01, 0x00, 0x03, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x0f, 0xff }, /* grdc_regs */
-    },
-    /* index=0x06 vga mode 0x06 */
-    { 80, 24, 8, 0x1000,     /* tw, th-1, ch, slength */
-      { 0x01, 0x01, 0x00, 0x06 },    /* sequ_regs */
-      0x63,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
-        0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xc2,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
-        0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
-        0x01, 0x00, 0x01, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x07 vga mode 0x07 */
-    { 80, 24, 16, 0x1000,    /* tw, th-1, ch, slength */
-      { 0x00, 0x03, 0x00, 0x02 },    /* sequ_regs */
-      0x66,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
-        0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
-        0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-        0x0e, 0x00, 0x0f, 0x08 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x08 no mode defined */
-    {},
-    /* index=0x09 no mode defined */
-    {},
-    /* index=0x0a no mode defined */
-    {},
-    /* index=0x0b no mode defined */
-    {},
-    /* index=0x0c no mode defined */
-    {},
-    /* index=0x0d vga mode 0x0d */
-    { 40, 24, 8, 0x2000,     /* tw, th-1, ch, slength */
-      { 0x09, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0x63,                      /* miscreg */
-      { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0x80, 0xbf, 0x1f,
-        0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-        0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-        0x01, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x0e vga mode 0x0e */
-    { 80, 24, 8, 0x4000,     /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0x63,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
-        0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-        0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-        0x01, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x0f no mode defined */
-    {},
-    /* index=0x10 no mode defined */
-    {},
-    /* index=0x11 vga mode 0x0f */
-    { 80, 24, 14, 0x8000,    /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0xa3,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
-        0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00,
-        0x00, 0x08, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
-        0x01, 0x00, 0x01, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x12 vga mode 0x10 */
-    { 80, 24, 14, 0x8000,    /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0xa3,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
-        0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x83, 0x85, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
-        0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-        0x01, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x13 no mode defined */
-    {},
-    /* index=0x14 no mode defined */
-    {},
-    /* index=0x15 no mode defined */
-    {},
-    /* index=0x16 no mode defined */
-    {},
-    /* index=0x17 vga mode 0x01 */
-    { 40, 24, 16, 0x0800,    /* tw, th-1, ch, slength */
-      { 0x08, 0x03, 0x00, 0x02 },    /* sequ_regs */
-      0x67,                      /* miscreg */
-      { 0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,
-        0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
-        0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-        0x0c, 0x00, 0x0f, 0x08 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff }, /* grdc_regs */
-    },
-    /* index=0x18 vga mode 0x03 */
-    { 80, 24, 16, 0x1000,    /* tw, th-1, ch, slength */
-      { 0x00, 0x03, 0x00, 0x02 },    /* sequ_regs */
-      0x67,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
-        0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
-        0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-        0x0c, 0x00, 0x0f, 0x08 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x19 vga mode 0x07 */
-    { 80, 24, 16, 0x1000,    /* tw, th-1, ch, slength */
-      { 0x00, 0x03, 0x00, 0x02 },    /* sequ_regs */
-      0x66,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
-        0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
-        0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
-        0x0e, 0x00, 0x0f, 0x08 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x0f, 0xff }, /* grdc_regs */
-    },
-    /* index=0x1a vga mode 0x11 */
-    { 80, 29, 16, 0x0000,    /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0xe3,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
-        0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f,
-        0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f,
-        0x01, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-    },
-    /* index=0x1b vga mode 0x12 */
-    { 80, 29, 16, 0x0000,    /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0xe3,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
-        0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0xea, 0x8c, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
-        0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-        0x01, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x1c vga mode 0x13 */
-    { 40, 24, 8, 0x0000,     /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x0e },    /* sequ_regs */
-      0x63,                      /* miscreg */
-      { 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f,
-        0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x9c, 0x8e, 0x8f, 0x28, 0x40, 0x96, 0xb9, 0xa3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-        0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-        0x41, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-    /* index=0x1d vga mode 0x6a */
-    { 100, 36, 16, 0x0000,   /* tw, th-1, ch, slength */
-      { 0x01, 0x0f, 0x00, 0x06 },    /* sequ_regs */
-      0xe3,                      /* miscreg */
-      { 0x7f, 0x63, 0x63, 0x83, 0x6b, 0x1b, 0x72, 0xf0,
-        0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x59, 0x8d, 0x57, 0x32, 0x00, 0x57, 0x73, 0xe3,
-        0xff },                      /* crtc_regs */
-      { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
-        0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-        0x01, 0x00, 0x0f, 0x00 },    /* actl_regs */
-      { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff }, /* grdc_regs */
-     },
-};
-
-
-/****************************************************************
- * Palette definitions
- ****************************************************************/
-
-/* Mono */
-static u8 palette0[] VAR16 = {
-  0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
-  0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f,
-  0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f,
-  0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
-  0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a, 0x2a,0x2a,0x2a,
-  0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f,
-  0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f, 0x3f,0x3f,0x3f
-};
-
-static u8 palette1[] VAR16 = {
-  0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
-  0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
-  0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
-  0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
-  0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f,
-  0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
-  0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f,
-  0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
-  0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
-  0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
-  0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
-  0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
-  0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f,
-  0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
-  0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f,
-  0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f
-};
-
-static u8 palette2[] VAR16 = {
-  0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
-  0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x2a,0x00, 0x2a,0x2a,0x2a,
-  0x00,0x00,0x15, 0x00,0x00,0x3f, 0x00,0x2a,0x15, 0x00,0x2a,0x3f,
-  0x2a,0x00,0x15, 0x2a,0x00,0x3f, 0x2a,0x2a,0x15, 0x2a,0x2a,0x3f,
-  0x00,0x15,0x00, 0x00,0x15,0x2a, 0x00,0x3f,0x00, 0x00,0x3f,0x2a,
-  0x2a,0x15,0x00, 0x2a,0x15,0x2a, 0x2a,0x3f,0x00, 0x2a,0x3f,0x2a,
-  0x00,0x15,0x15, 0x00,0x15,0x3f, 0x00,0x3f,0x15, 0x00,0x3f,0x3f,
-  0x2a,0x15,0x15, 0x2a,0x15,0x3f, 0x2a,0x3f,0x15, 0x2a,0x3f,0x3f,
-  0x15,0x00,0x00, 0x15,0x00,0x2a, 0x15,0x2a,0x00, 0x15,0x2a,0x2a,
-  0x3f,0x00,0x00, 0x3f,0x00,0x2a, 0x3f,0x2a,0x00, 0x3f,0x2a,0x2a,
-  0x15,0x00,0x15, 0x15,0x00,0x3f, 0x15,0x2a,0x15, 0x15,0x2a,0x3f,
-  0x3f,0x00,0x15, 0x3f,0x00,0x3f, 0x3f,0x2a,0x15, 0x3f,0x2a,0x3f,
-  0x15,0x15,0x00, 0x15,0x15,0x2a, 0x15,0x3f,0x00, 0x15,0x3f,0x2a,
-  0x3f,0x15,0x00, 0x3f,0x15,0x2a, 0x3f,0x3f,0x00, 0x3f,0x3f,0x2a,
-  0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f,
-  0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f
-};
-
-static u8 palette3[] VAR16 = {
-  0x00,0x00,0x00, 0x00,0x00,0x2a, 0x00,0x2a,0x00, 0x00,0x2a,0x2a,
-  0x2a,0x00,0x00, 0x2a,0x00,0x2a, 0x2a,0x15,0x00, 0x2a,0x2a,0x2a,
-  0x15,0x15,0x15, 0x15,0x15,0x3f, 0x15,0x3f,0x15, 0x15,0x3f,0x3f,
-  0x3f,0x15,0x15, 0x3f,0x15,0x3f, 0x3f,0x3f,0x15, 0x3f,0x3f,0x3f,
-  0x00,0x00,0x00, 0x05,0x05,0x05, 0x08,0x08,0x08, 0x0b,0x0b,0x0b,
-  0x0e,0x0e,0x0e, 0x11,0x11,0x11, 0x14,0x14,0x14, 0x18,0x18,0x18,
-  0x1c,0x1c,0x1c, 0x20,0x20,0x20, 0x24,0x24,0x24, 0x28,0x28,0x28,
-  0x2d,0x2d,0x2d, 0x32,0x32,0x32, 0x38,0x38,0x38, 0x3f,0x3f,0x3f,
-  0x00,0x00,0x3f, 0x10,0x00,0x3f, 0x1f,0x00,0x3f, 0x2f,0x00,0x3f,
-  0x3f,0x00,0x3f, 0x3f,0x00,0x2f, 0x3f,0x00,0x1f, 0x3f,0x00,0x10,
-  0x3f,0x00,0x00, 0x3f,0x10,0x00, 0x3f,0x1f,0x00, 0x3f,0x2f,0x00,
-  0x3f,0x3f,0x00, 0x2f,0x3f,0x00, 0x1f,0x3f,0x00, 0x10,0x3f,0x00,
-  0x00,0x3f,0x00, 0x00,0x3f,0x10, 0x00,0x3f,0x1f, 0x00,0x3f,0x2f,
-  0x00,0x3f,0x3f, 0x00,0x2f,0x3f, 0x00,0x1f,0x3f, 0x00,0x10,0x3f,
-  0x1f,0x1f,0x3f, 0x27,0x1f,0x3f, 0x2f,0x1f,0x3f, 0x37,0x1f,0x3f,
-  0x3f,0x1f,0x3f, 0x3f,0x1f,0x37, 0x3f,0x1f,0x2f, 0x3f,0x1f,0x27,
-
-  0x3f,0x1f,0x1f, 0x3f,0x27,0x1f, 0x3f,0x2f,0x1f, 0x3f,0x37,0x1f,
-  0x3f,0x3f,0x1f, 0x37,0x3f,0x1f, 0x2f,0x3f,0x1f, 0x27,0x3f,0x1f,
-  0x1f,0x3f,0x1f, 0x1f,0x3f,0x27, 0x1f,0x3f,0x2f, 0x1f,0x3f,0x37,
-  0x1f,0x3f,0x3f, 0x1f,0x37,0x3f, 0x1f,0x2f,0x3f, 0x1f,0x27,0x3f,
-  0x2d,0x2d,0x3f, 0x31,0x2d,0x3f, 0x36,0x2d,0x3f, 0x3a,0x2d,0x3f,
-  0x3f,0x2d,0x3f, 0x3f,0x2d,0x3a, 0x3f,0x2d,0x36, 0x3f,0x2d,0x31,
-  0x3f,0x2d,0x2d, 0x3f,0x31,0x2d, 0x3f,0x36,0x2d, 0x3f,0x3a,0x2d,
-  0x3f,0x3f,0x2d, 0x3a,0x3f,0x2d, 0x36,0x3f,0x2d, 0x31,0x3f,0x2d,
-  0x2d,0x3f,0x2d, 0x2d,0x3f,0x31, 0x2d,0x3f,0x36, 0x2d,0x3f,0x3a,
-  0x2d,0x3f,0x3f, 0x2d,0x3a,0x3f, 0x2d,0x36,0x3f, 0x2d,0x31,0x3f,
-  0x00,0x00,0x1c, 0x07,0x00,0x1c, 0x0e,0x00,0x1c, 0x15,0x00,0x1c,
-  0x1c,0x00,0x1c, 0x1c,0x00,0x15, 0x1c,0x00,0x0e, 0x1c,0x00,0x07,
-  0x1c,0x00,0x00, 0x1c,0x07,0x00, 0x1c,0x0e,0x00, 0x1c,0x15,0x00,
-  0x1c,0x1c,0x00, 0x15,0x1c,0x00, 0x0e,0x1c,0x00, 0x07,0x1c,0x00,
-  0x00,0x1c,0x00, 0x00,0x1c,0x07, 0x00,0x1c,0x0e, 0x00,0x1c,0x15,
-  0x00,0x1c,0x1c, 0x00,0x15,0x1c, 0x00,0x0e,0x1c, 0x00,0x07,0x1c,
-
-  0x0e,0x0e,0x1c, 0x11,0x0e,0x1c, 0x15,0x0e,0x1c, 0x18,0x0e,0x1c,
-  0x1c,0x0e,0x1c, 0x1c,0x0e,0x18, 0x1c,0x0e,0x15, 0x1c,0x0e,0x11,
-  0x1c,0x0e,0x0e, 0x1c,0x11,0x0e, 0x1c,0x15,0x0e, 0x1c,0x18,0x0e,
-  0x1c,0x1c,0x0e, 0x18,0x1c,0x0e, 0x15,0x1c,0x0e, 0x11,0x1c,0x0e,
-  0x0e,0x1c,0x0e, 0x0e,0x1c,0x11, 0x0e,0x1c,0x15, 0x0e,0x1c,0x18,
-  0x0e,0x1c,0x1c, 0x0e,0x18,0x1c, 0x0e,0x15,0x1c, 0x0e,0x11,0x1c,
-  0x14,0x14,0x1c, 0x16,0x14,0x1c, 0x18,0x14,0x1c, 0x1a,0x14,0x1c,
-  0x1c,0x14,0x1c, 0x1c,0x14,0x1a, 0x1c,0x14,0x18, 0x1c,0x14,0x16,
-  0x1c,0x14,0x14, 0x1c,0x16,0x14, 0x1c,0x18,0x14, 0x1c,0x1a,0x14,
-  0x1c,0x1c,0x14, 0x1a,0x1c,0x14, 0x18,0x1c,0x14, 0x16,0x1c,0x14,
-  0x14,0x1c,0x14, 0x14,0x1c,0x16, 0x14,0x1c,0x18, 0x14,0x1c,0x1a,
-  0x14,0x1c,0x1c, 0x14,0x1a,0x1c, 0x14,0x18,0x1c, 0x14,0x16,0x1c,
-  0x00,0x00,0x10, 0x04,0x00,0x10, 0x08,0x00,0x10, 0x0c,0x00,0x10,
-  0x10,0x00,0x10, 0x10,0x00,0x0c, 0x10,0x00,0x08, 0x10,0x00,0x04,
-  0x10,0x00,0x00, 0x10,0x04,0x00, 0x10,0x08,0x00, 0x10,0x0c,0x00,
-  0x10,0x10,0x00, 0x0c,0x10,0x00, 0x08,0x10,0x00, 0x04,0x10,0x00,
-
-  0x00,0x10,0x00, 0x00,0x10,0x04, 0x00,0x10,0x08, 0x00,0x10,0x0c,
-  0x00,0x10,0x10, 0x00,0x0c,0x10, 0x00,0x08,0x10, 0x00,0x04,0x10,
-  0x08,0x08,0x10, 0x0a,0x08,0x10, 0x0c,0x08,0x10, 0x0e,0x08,0x10,
-  0x10,0x08,0x10, 0x10,0x08,0x0e, 0x10,0x08,0x0c, 0x10,0x08,0x0a,
-  0x10,0x08,0x08, 0x10,0x0a,0x08, 0x10,0x0c,0x08, 0x10,0x0e,0x08,
-  0x10,0x10,0x08, 0x0e,0x10,0x08, 0x0c,0x10,0x08, 0x0a,0x10,0x08,
-  0x08,0x10,0x08, 0x08,0x10,0x0a, 0x08,0x10,0x0c, 0x08,0x10,0x0e,
-  0x08,0x10,0x10, 0x08,0x0e,0x10, 0x08,0x0c,0x10, 0x08,0x0a,0x10,
-  0x0b,0x0b,0x10, 0x0c,0x0b,0x10, 0x0d,0x0b,0x10, 0x0f,0x0b,0x10,
-  0x10,0x0b,0x10, 0x10,0x0b,0x0f, 0x10,0x0b,0x0d, 0x10,0x0b,0x0c,
-  0x10,0x0b,0x0b, 0x10,0x0c,0x0b, 0x10,0x0d,0x0b, 0x10,0x0f,0x0b,
-  0x10,0x10,0x0b, 0x0f,0x10,0x0b, 0x0d,0x10,0x0b, 0x0c,0x10,0x0b,
-  0x0b,0x10,0x0b, 0x0b,0x10,0x0c, 0x0b,0x10,0x0d, 0x0b,0x10,0x0f,
-  0x0b,0x10,0x10, 0x0b,0x0f,0x10, 0x0b,0x0d,0x10, 0x0b,0x0c,0x10,
-  0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00,
-  0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00, 0x00,0x00,0x00
-};
-
-
-/****************************************************************
- * Video mode list
- ****************************************************************/
-
-#define PAL(x) x, sizeof(x)
-#define VPARAM(x) &video_param_table[x]
-
-static struct vgamode_s vga_modes[] VAR16 = {
-    //mode vparam        model bits  sstart     pelm  dac
-    {0x00, VPARAM(0x17), CTEXT,   4, SEG_CTEXT, 0xFF, PAL(palette2)},
-    {0x01, VPARAM(0x17), CTEXT,   4, SEG_CTEXT, 0xFF, PAL(palette2)},
-    {0x02, VPARAM(0x18), CTEXT,   4, SEG_CTEXT, 0xFF, PAL(palette2)},
-    {0x03, VPARAM(0x18), CTEXT,   4, SEG_CTEXT, 0xFF, PAL(palette2)},
-    {0x04, VPARAM(0x04), CGA,     2, SEG_CTEXT, 0xFF, PAL(palette1)},
-    {0x05, VPARAM(0x05), CGA,     2, SEG_CTEXT, 0xFF, PAL(palette1)},
-    {0x06, VPARAM(0x06), CGA,     1, SEG_CTEXT, 0xFF, PAL(palette1)},
-    {0x07, VPARAM(0x07), MTEXT,   4, SEG_MTEXT, 0xFF, PAL(palette0)},
-    {0x0D, VPARAM(0x0d), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette1)},
-    {0x0E, VPARAM(0x0e), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette1)},
-    {0x0F, VPARAM(0x11), PLANAR1, 1, SEG_GRAPH, 0xFF, PAL(palette0)},
-    {0x10, VPARAM(0x12), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette2)},
-    {0x11, VPARAM(0x1a), PLANAR1, 1, SEG_GRAPH, 0xFF, PAL(palette2)},
-    {0x12, VPARAM(0x1b), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette2)},
-    {0x13, VPARAM(0x1c), LINEAR8, 8, SEG_GRAPH, 0xFF, PAL(palette3)},
-    {0x6A, VPARAM(0x1d), PLANAR4, 4, SEG_GRAPH, 0xFF, PAL(palette2)},
-};
-
-struct vgamode_s *
-find_vga_entry(u8 mode)
-{
-    int i;
-    for (i = 0; i < ARRAY_SIZE(vga_modes); i++) {
-        struct vgamode_s *vmode_g = &vga_modes[i];
-        if (GET_GLOBAL(vmode_g->svgamode) == mode)
-            return vmode_g;
-    }
-    return NULL;
-}
-
-// u16 video_save_pointer_table[14] VAR16;
-
-
-/****************************************************************
- * Static functionality table
- ****************************************************************/
-
-u8 static_functionality[0x10] VAR16 = {
- /* 0 */ 0xff,  // All modes supported #1
- /* 1 */ 0xe0,  // All modes supported #2
- /* 2 */ 0x0f,  // All modes supported #3
- /* 3 */ 0x00, 0x00, 0x00, 0x00,  // reserved
- /* 7 */ 0x07,  // 200, 350, 400 scan lines
- /* 8 */ 0x02,  // mamimum number of visible charsets in text mode
- /* 9 */ 0x08,  // total number of charset blocks in text mode
- /* a */ 0xe7,  // Change to add new functions
- /* b */ 0x0c,  // Change to add new functions
- /* c */ 0x00,  // reserved
- /* d */ 0x00,  // reserved
- /* e */ 0x00,  // Change to add new functions
- /* f */ 0x00   // reserved
-};
diff --git a/qemu/roms/qemu-palcode/vgatables.h b/qemu/roms/qemu-palcode/vgatables.h
deleted file mode 100644
index 153a3cc94..000000000
--- a/qemu/roms/qemu-palcode/vgatables.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* VGA register definitions
-
-   This file is copied (somewhat) intact from SeaBIOS.
-   It is covered by the GNU Lesser General Public License, v3.
-
-   You should have received a copy of the GNU Lesser General Public License
-   along with this program; see the file COPYING.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#ifndef VGATABLES_H
-#define VGATABLES_H
-
-typedef uint8_t u8;
-typedef uint16_t u16;
-
-
-/*
- *
- * VGA registers
- *
- */
-#define VGAREG_ACTL_ADDRESS            0x3c0
-#define VGAREG_ACTL_WRITE_DATA         0x3c0
-#define VGAREG_ACTL_READ_DATA          0x3c1
-
-#define VGAREG_INPUT_STATUS            0x3c2
-#define VGAREG_WRITE_MISC_OUTPUT       0x3c2
-#define VGAREG_VIDEO_ENABLE            0x3c3
-#define VGAREG_SEQU_ADDRESS            0x3c4
-#define VGAREG_SEQU_DATA               0x3c5
-
-#define VGAREG_PEL_MASK                0x3c6
-#define VGAREG_DAC_STATE               0x3c7
-#define VGAREG_DAC_READ_ADDRESS        0x3c7
-#define VGAREG_DAC_WRITE_ADDRESS       0x3c8
-#define VGAREG_DAC_DATA                0x3c9
-
-#define VGAREG_READ_FEATURE_CTL        0x3ca
-#define VGAREG_READ_MISC_OUTPUT        0x3cc
-
-#define VGAREG_GRDC_ADDRESS            0x3ce
-#define VGAREG_GRDC_DATA               0x3cf
-
-#define VGAREG_MDA_CRTC_ADDRESS        0x3b4
-#define VGAREG_MDA_CRTC_DATA           0x3b5
-#define VGAREG_VGA_CRTC_ADDRESS        0x3d4
-#define VGAREG_VGA_CRTC_DATA           0x3d5
-
-#define VGAREG_MDA_WRITE_FEATURE_CTL   0x3ba
-#define VGAREG_VGA_WRITE_FEATURE_CTL   0x3da
-#define VGAREG_ACTL_RESET              0x3da
-
-#define VGAREG_MDA_MODECTL             0x3b8
-#define VGAREG_CGA_MODECTL             0x3d8
-#define VGAREG_CGA_PALETTE             0x3d9
-
-/* Video memory */
-#define SEG_GRAPH                      0xA000
-#define SEG_CTEXT                      0xB800
-#define SEG_MTEXT                      0xB000
-
-/*
- * Tables of default values for each mode
- */
-#define TEXT       0x80
-
-#define CTEXT      (0x00 | TEXT)
-#define MTEXT      (0x01 | TEXT)
-#define CGA        0x02
-#define PLANAR1    0x03
-#define PLANAR4    0x04
-#define LINEAR8    0x05
-
-// for SVGA
-#define LINEAR15   0x10
-#define LINEAR16   0x11
-#define LINEAR24   0x12
-#define LINEAR32   0x13
-
-#define SCREEN_IO_START(x,y,p) (((((x)*(y)) | 0x00ff) + 1) * (p))
-#define SCREEN_MEM_START(x,y,p) SCREEN_IO_START(((x)*2),(y),(p))
-
-/* standard BIOS Video Parameter Table */
-struct __attribute__((packed)) VideoParam_s {
-    u8 twidth;
-    u8 theightm1;
-    u8 cheight;
-    u16 slength;
-    u8 sequ_regs[4];
-    u8 miscreg;
-    u8 crtc_regs[25];
-    u8 actl_regs[20];
-    u8 grdc_regs[9];
-};
-
-struct vgamode_s {
-    u8 svgamode;
-    struct VideoParam_s *vparam;
-    u8 memmodel;    /* CTEXT,MTEXT,CGA,PL1,PL2,PL4,P8,P15,P16,P24,P32 */
-    u8 pixbits;
-    u16 sstart;
-    u8 pelmask;
-    u8 *dac;
-    u16 dacsize;
-};
-
-struct saveVideoHardware {
-    u8 sequ_index;
-    u8 crtc_index;
-    u8 grdc_index;
-    u8 actl_index;
-    u8 feature;
-    u8 sequ_regs[4];
-    u8 sequ0;
-    u8 crtc_regs[25];
-    u8 actl_regs[20];
-    u8 grdc_regs[9];
-    u16 crtc_addr;
-    u8 plane_latch[4];
-};
-
-struct saveBDAstate {
-    u8 video_mode;
-    u16 video_cols;
-    u16 video_pagesize;
-    u16 crtc_address;
-    u8 video_rows;
-    u16 char_height;
-    u8 video_ctl;
-    u8 video_switches;
-    u8 modeset_ctl;
-    u16 cursor_type;
-    u16 cursor_pos[8];
-    u16 video_pagestart;
-    u8 video_page;
-#if 0
-    /* current font */
-    struct segoff_s font0;
-    struct segoff_s font1;
-#endif
-};
-
-struct saveDACcolors {
-    u8 rwmode;
-    u8 peladdr;
-    u8 pelmask;
-    u8 dac[768];
-    u8 color_select;
-};
-
-// vgatables.c
-struct vgamode_s *find_vga_entry(u8 mode);
-extern u16 video_save_pointer_table[];
-extern struct VideoParam_s video_param_table[];
-extern u8 static_functionality[];
-
-// vgafonts.c
-extern const u8 vgafont8[];
-extern const u8 vgafont14[];
-extern const u8 vgafont16[];
-extern const u8 vgafont14alt[];
-extern const u8 vgafont16alt[];
-
-// vga.c
-struct carattr {
-    u8 car, attr, use_attr;
-};
-struct cursorpos {
-    u8 x, y, page;
-};
-
-// vgafb.c
-void clear_screen(struct vgamode_s *vmode_g);
-void vgafb_scroll(int nblines, int attr
-                  , struct cursorpos ul, struct cursorpos lr);
-void vgafb_write_char(struct cursorpos cp, struct carattr ca);
-struct carattr vgafb_read_char(struct cursorpos cp);
-void vgafb_write_pixel(u8 color, u16 x, u16 y);
-u8 vgafb_read_pixel(u16 x, u16 y);
-void vgafb_load_font(u16 seg, void *src_far, u16 count
-                     , u16 start, u8 destflags, u8 fontsize);
-
-// vgaio.c
-void vgahw_screen_disable(void);
-void vgahw_screen_enable(void);
-void vgahw_set_border_color(u8 color);
-void vgahw_set_overscan_border_color(u8 color);
-u8 vgahw_get_overscan_border_color(void);
-void vgahw_set_palette(u8 palid);
-void vgahw_set_single_palette_reg(u8 reg, u8 val);
-u8 vgahw_get_single_palette_reg(u8 reg);
-void vgahw_set_all_palette_reg(u8 *data);
-void vgahw_get_all_palette_reg(u8 *data);
-void vgahw_toggle_intensity(u8 flag);
-void vgahw_select_video_dac_color_page(u8 flag, u8 data);
-void vgahw_read_video_dac_state(u8 *pmode, u8 *curpage);
-void vgahw_set_dac_regs(u8 *data, u8 start, int count);
-void vgahw_get_dac_regs(u8 *data, u8 start, int count);
-void vgahw_set_pel_mask(u8 val);
-u8 vgahw_get_pel_mask(void);
-void vgahw_save_dac_state(struct saveDACcolors *info);
-void vgahw_restore_dac_state(struct saveDACcolors *info);
-void vgahw_sequ_write(u8 index, u8 value);
-void vgahw_grdc_write(u8 index, u8 value);
-void vgahw_set_text_block_specifier(u8 spec);
-void get_font_access(void);
-void release_font_access(void);
-void vgahw_set_cursor_shape(u8 start, u8 end);
-void vgahw_set_active_page(u16 address);
-void vgahw_set_cursor_pos(u16 address);
-void vgahw_set_scan_lines(u8 lines);
-u16 vgahw_get_vde(void);
-void vgahw_save_state(struct saveVideoHardware *info);
-void vgahw_restore_state(struct saveVideoHardware *info);
-void vgahw_set_mode(struct VideoParam_s *vparam_g);
-void vgahw_enable_video_addressing(u8 disable);
-void vgahw_init(void);
-
-// clext.c
-void cirrus_set_video_mode(u8 mode);
-void cirrus_init(void);
-
-#endif // vgatables.h
author	RajithaY <rajithax.yerrumsetty@intel.com>	2017-04-25 03:31:15 -0700
committer	Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com>	2017-05-22 06:48:08 +0000
commit	bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
tree	ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/qemu-palcode
parent	a14b48d18a9ed03ec191cf16b162206998a895ce (diff)