diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/openbios/utils/devbios | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/openbios/utils/devbios')
18 files changed, 3470 insertions, 0 deletions
diff --git a/qemu/roms/openbios/utils/devbios/COPYING b/qemu/roms/openbios/utils/devbios/COPYING new file mode 100644 index 000000000..486e6387f --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/COPYING @@ -0,0 +1,353 @@ + + NOTE! The GPL below is copyrighted by the Free Software + Foundation, but the instance of code that it refers to (/dev/bios + driver)is copyrighted by me and others who actually wrote it. + + Also note that the only valid version of the GPL as far as this driver + is concerned is _this_ particular version of the license (ie v2, not + v2.2 or v3.x or whatever), unless explicitly otherwise stated. + + Stefan Reinauer + +---------------------------------------- + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/qemu/roms/openbios/utils/devbios/CREDITS b/qemu/roms/openbios/utils/devbios/CREDITS new file mode 100644 index 000000000..cd642676c --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/CREDITS @@ -0,0 +1,4 @@ + +Thanks to Michael Gibson from eSeSiX for donating a cs5530 +based thin client for porting /dev/bios. + diff --git a/qemu/roms/openbios/utils/devbios/ChangeLog b/qemu/roms/openbios/utils/devbios/ChangeLog new file mode 100644 index 000000000..3c8e5654d --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/ChangeLog @@ -0,0 +1,295 @@ +NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! + +/dev/bios is obsolete and no longer under development. Please adapt all +changes to the "flashrom" utility of LinuxBIOS. This utility can be found +at LinuxBIOSv2/utils/flashrom in the LinuxBIOS v2 repository. LinuxBIOS +is available at http://www.linuxbios.org/ + +I'm also looking for volunteers to port all features available in /dev/bios +to flashrom so /dev/bios can be dropped from the OpenBIOS tree. These features +include + +- block information about flash chips +- block wise writing of flash chips +- lots of supported flash chips and vendors. + +If you have questions, contact Stefan Reinauer <stepan@coresystems.de> + +NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! + + +ChangeLog for /dev/bios + +** 2004/03/31 ******************************************************** + + * Added fix from Alex Beregszaszi to remove global *bios + +** 2004/03/05 ******************************************************** + + * fix compiling for 2.6 kernels. + +** 03/06/04 ********************************************************** + + * add SST49LF080A + * small 2.5 fix. + +** 02/06/10 ********************************************************** + + * some changes to detect pci cards firmware. + * pci cards firmware can be read even if flashing is not possible. + This is a new feature and might cause problems on some systems. + +** 02/04/16 ********************************************************** + + * reorganize Makefile, include .config from kernel. + * platform fixes for clean compilation. + +** 02/04/12 ********************************************************** + + * proprietary x86-64 support. + * change ruffian probe address + +** 02/03/28 ********************************************************** + + * proper implementation of system firmware detection on LX164 Alphas + * partly include jedec command cleanup patch from Pierrick Hascoet + <pierrick.hascoet@hydromel.net> + +** 02/03/11 ********************************************************** + + * only probe 512k on CS5530(A) + * add EON EN29F002 chips. + +** 02/02/22 ********************************************************** + + * rewrite major parts of bridge probing to make driver more generic. + * add Ali chipset support + * Saner iounmap() of flash devices. + +** 02/02/18 * 0.3.2 ************************************************** + + * change cs5530 driver to map high rom range instead of low one + and don't use positive decode. + * remove ruffian flag. Alpha (164LX/UX) almost works with pc code. + * don't rely on register defaults in intel 8xx driver. + * updated pci device list. more entries, join amd and via entry. + * fix error handling in chipset detection. + * add support for Reliance/ServerWorks chipsets + * enable 1M 512k on intel 4x0 chips where it's possible + * cleanup proc file handling + +** 02/02/17 ********************************************************** + + * rewrote chipset initialisation skeleton. + * fix pci bios (un)mapping. + * experimental support for AlphaPC 164UX (Ruffian) + (probes at 0xfffffffffffc0000 instead of 0xfffffc87C0000000 + * initial code for FWH mode chips + * Fix Toggle-Until-Ready code. + +** 02/02/16 ********************************************************** + + * iounmapping fixed. no more address space wasted. + * /proc/bios shows physical address now. dmesg shows + physical address and virtual memory area and offset. + +** 02/02/13 ********************************************************** + + * added i820/i830 chipset support + * added AMD 751/760MP(X) support + * added support for Itanium and 84460GX chipset + * added experimental support for some flash chips (ST, Intel, + Winbond) + * use spinlocks instead of hard cli() + +** 02/02/11 ********************************************************** + + * added GPL licence tag + * remove low bios area access tweaking for intel drivers + * speed up SST 39SF020 write + * fix compilation for 2.5 kernels + +** 02/02/05 ********************************************************** + + * added support for cs5530 (nsc/cyrix mediagx) chipset + * reorganized shadow/wp handling + * probe for 2mb high memory area instead of 256k only + +** 01/08/01 * 0.3.1 ************************************************** + + * compiles and works with Linux kernel 2.4 + * rewrote flash chip probing + * always use ioremap now + * flash chips above 128k should work transparent + * Support for newer VIA chipsets + +** 00/10/15 * 0.3.0pre1 ********************************************** + + * added patch from Eric Estabrook + * support for 256k flash chips on intel 430/440 chipsets and via vp3 + * split up source into several files + * Changes for Ruffian AXP machines. Does not work (yet). + +** 99/07/29 * 0.2.101 ************************************************ + + * Oh well.. 11 months? Impossible. I am a lazy guy. Implemented + some support for VIA Apollo VP3. Don't know whether it works, since + I don't have one. + +** 98/09/06 ********************************************************** + +patches by prumpf@jcsbs.lanobis.de: + * The pointer to bios_release in bios.c was on the flush pointer's + position. This caused Oopses. + * When bios_read was called with a file position after the actual end + of bios, it tried to read non-existant memory positions due to size + being unsigned (it isn't anymore) , causing spontaneous reboots on + my system + +** 98/08/22 ********************************************************** + + * Well,.. The diskless spectacle (0.2.100) was caused by a little bug + in in handling Intel PCI chipsets. Works now. + * Threw out the chipset_backout stuff. the PCI chipset handling should + always leave the machine in the same state it was before. ALWAYS. + +** 98/08/18 * 0.2.100 ************************************************ + + * Threw out the mem_type stuff. There are more important things than + this. + * Argh! After flashing fine on an Intel 28F001BT, the computer kept + hanging in an endless loop and refused writing the emergency boot + block to the end :-( There's some work until 0.3 is ready. + Implemented a timeout so that the system will not hang forever if + the flashchip behaves unexpected. + * Removed x86 probing in a loop. I think it never found anything else + but the system bios and *maybe* the graphics adapter bios. On the + other hand, it reconfigures some networking cards to silence. + Bad thing on diskless Linux boxes :) + +** 98/08/15 ********************************************************** + + * added some changes for intel to compile without warnings.. + +** 98/08/02 ********************************************************** + + * What a boring job! Checked some dozen of flash chip entries today + and added a lot of new ones. I bet it gets hard to find anything + this driver does not know. + +** 98/07/28 ********************************************************** + + * Yeah! Atmel Chips finally work.. These Atmel guys are really weird. + * Testing last instead of first written byte now, when polling for the + end of a write access. + +** 98/07/28 ********************************************************** + + * Well, I am definitely spending too much time in IRC, but detecting + PCI cards' bioses works now (at least for me) + * Thrown out some obsolete stuff. + * Declared PCI and Flash reading/writing __inline__. Don't know, + whether this is a good idea. But let's try it for a while. + * Aaaargh! Some major mistakes in handling whether a flash has to + be erased before programming. FIXED! + * Even worse. An endless loop made it into writing in 0.2.99. Sorry! + I had no chance to test writing on an intel board with that release. + At least my warning, not to write, made sense. + * Intel flashchips are supported now!! It's at least tested on my + Alpha AXP LX164 Board (1MByte i28f008 chip) But all Intel flash chips + seem to work in the same way. + * Atmel 64kByte flash chips supported. + +** 98/07/27 ********************************************************** + + * Split up flash_probe in 2 parts to be able to expand probing on + PCI bioses and others correctly. + * Turned around 1st and 2nd probing codes. This is funny, Atmel + Flashroms give some wrong numbers if they are probed with the + 0x80/0x60 way. I only hope that no flashchips react on the + 0x90 method with wrong values. + +** 98/07/19 * V0.2.99 ************************************************ + + * Reading the flashchip works now on Alpha AXP (at least on my LX164 + Board) + Writing ought to work, too, but Intel Flashchips are not supported + yet. This should be done until 0.3.0. + NOTE: I have no idea whether this driver still works on intel + boards or not. There have been too many changes. Please try, but + do not flash with this release of the driver. + * Minor Changes and fixes. Naming scheme changed a bit. This version + might work on James Mastros' machine again ?!? + +** 98/07/11 ********************************************************** + + * Started porting stuff to Alpha AXP architecture to continue testing + the flashing routines. We have a lot of tests next week, so I + won't get much stuff done.. + Porting to AXP seems to be much more work than I thought. It may + take some time until the next version is released. + * Moved major number again. This time we have an official major + number for /dev/bios. Thanks to Hans Peter Anvin. + (Well, we have this one since May 1st, sorry for the delay) + +** 98/06/26 * V0.2.95 ************************************************ + + * added all Manufacturer IDs from the JEDEC standards publication. + * sorry for not having released a new version since months, but + my x86 machine died and I have no chance to do any testing right + now. I guess I must get a new Intel box, as Alpha AXP are all + delivered with the same Intel flash chips. + +** 98/04/30 * V0.2.9 ************************************************* + + * removed ioctls. They have been really unneccesary and did not fit + into the new driver layout. + * cleaned up the code. Hey, it should be readable again. + * Moved device minors from 10+ to 0+ + * Rewrote most of the documentation + * changed intel shadowing routines. Now original values are saved + and shadowing is turned off for 0xc0000 to 0xdffff, too (This + was needed to support 2MBit system bios flash chips. Thanks again + to Matthew Harrell for intensive testing. + * Removed dirty hacks from bios_read_proc() + * Added some fields to struct flashdevice to support all ROM types, + not only flash roms. Probing for other types still missing. + * Implemented probing for some strange Winbond chips (0x80/0x20). + +** 98/04/27 * V0.2.8 ************************************************* + + *** Attention *** This version has a lot of changes since + 0.2.7, so be very careful, when testing. Things may + be broken that used to work. + + * Rewrote big parts of the driver to (theoretically) support + multiple flash chips and/or ROM areas. + * Tried to implement support for 2MBit System BIOS chips, but + I have no idea, whether it works. I don't have one. + * added some more OPTi, SiS and VIA PCI chipsets to chipset list. + They have no function yet, though. + * Some weird computers have an ISA bridge, but don't have it declared + as one. Now probing for known ISA bridge IDs. (Thanks to Matthew + Harrell for reporting this.) + * Added some new flashchip IDs and made some old ones work. + +** 98/04/24 * V0.2.7 ************************************************* + + * rewrote shadowing and wp functions to use a pci_functions structure + This makes it very easy to include new PCI chipsets. + * function chipset_init() detects PCI chipset. + * modversions support. Thanks to Matthew Harrell. + * moved PCI bridge detection to chipset_init() + +** 98/04/23 * V0.2.6 ************************************************* + + * repaired flashchip_ready_toggle and flashchip_ready_poll. + * Set WRITE_DELAY to 300 as it should be (works now) + * NOTE: These two changes make the operation of /dev/bios + theoretically correct, and by that quite secure. + +********************************************************************** + +There was no ChangeLog for versions prior to 0.2.6 + +Stefan Reinauer, <stepan@openbios.org> diff --git a/qemu/roms/openbios/utils/devbios/Makefile b/qemu/roms/openbios/utils/devbios/Makefile new file mode 100644 index 000000000..b6f7611bd --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/Makefile @@ -0,0 +1,22 @@ +# comment this if you don't want debugging information +CFLAGS += -DDEBUG + +TARGET = bios.o +OBJS = bios_core.o flashchips.o pcisets.o \ + filesystem.o procfs.o programming.o + +obj-m := $(TARGET) +bios-objs := $(OBJS) + +all: module comp + +clean: + -rm -f $(TARGET) $(OBJS) comp *.o bios.ko + -rm -rf .*.cmd .tmp_versions +module: + make -C /usr/src/linux SUBDIRS=`pwd` modules + +comp: comp.c + $(CC) comp.c -O2 -o comp + strip comp + diff --git a/qemu/roms/openbios/utils/devbios/Makefile.24 b/qemu/roms/openbios/utils/devbios/Makefile.24 new file mode 100644 index 000000000..85717c4d4 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/Makefile.24 @@ -0,0 +1,81 @@ +CC = gcc +LD = ld + +KERNEL = /usr/src/linux +#KERNEL = /lib/modules/`uname -r`/build + +ARCH = $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/) + +ifeq ($(KERNEL)/.config,$(wildcard $(KERNEL)/.config)) +include $(KERNEL)/.config +endif + +CFLAGS = -D__KERNEL__ -I${KERNEL}/include -Wall \ + -Wstrict-prototypes -Wno-trigraphs -O2 \ + -fomit-frame-pointer -fno-common \ + -fno-strict-aliasing -pipe -DMODULE + +# comment this if you don't want debugging information +CFLAGS += -DDEBUG + +# see if we need module versions +ifdef CONFIG_MODVERSIONS +CFLAGS += -DMODVERSIONS +endif + +ifeq ($(ARCH),alpha) +CFLAGS += -mno-fp-regs -ffixed-8 -mcpu=ev5 -Wa,-mev6 +LDFLAGS = -m elf64alpha +endif + +ifeq ($(ARCH),sparc64) +CFLAGS += -mno-fpu -mtune=ultrasparc -mmedlow -ffixed-g4 \ + -fcall-used-g5 -fcall-used-g7 +LDFLAGS = -m elf_sparc64 +endif + +ifeq ($(ARCH),i386) +CFLAGS += -mpreferred-stack-boundary=2 -march=i586 +LDFLAGS = -m elf_i386 +endif + +ifeq ($(ARCH), x86_64) +CFLAGS += -mno-red-zone -mcmodel=kernel -fno-reorder-blocks \ + -finline-limit=2000 -fno-strength-reduce +LDFLAGS = -m elf_x86_64 +endif + +ifeq ($(ARCH),ia64) +CFLAGS += -ffixed-r13 -mfixed-range=f10-f15,f32-f127 \ + -falign-functions=32 +LDFLAGS = -m elf64_ia64 +endif + +.SUFFIXES: .o .c .h + +TARGET = bios.o +OBJS = bios_core.o flashchips.o pcisets.o \ + filesystem.o procfs.o programming.o + +all: $(TARGET) comp + +$(TARGET): $(OBJS) + $(LD) $(LDFLAGS) -r -o $(TARGET) $(OBJS) + +clean: + -rm -f $(TARGET) $(OBJS) comp *.o + +.c.o: + $(CC) $(INCLUDES) -c $(INCDIRS) $(CFLAGS) $(X_CFLAGS) $(DEBUGFLAGS) $*.c -o $@ + +comp: comp.c + $(CC) comp.c -O2 -o comp + strip comp + +bios_core.o: bios_core.c bios.h pcisets.h flashchips.h programming.h +filesystem.o: filesystem.c bios.h pcisets.h flashchips.h programming.h +flashchips.o: flashchips.c bios.h flashchips.h +pcisets.o: pcisets.c bios.h pcisets.h flashchips.h programming.h +procfs.o: procfs.c bios.h pcisets.h flashchips.h programming.h +programming.o: programming.c bios.h pcisets.h flashchips.h programming.h + diff --git a/qemu/roms/openbios/utils/devbios/README.bios b/qemu/roms/openbios/utils/devbios/README.bios new file mode 100644 index 000000000..45bd9a809 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/README.bios @@ -0,0 +1,256 @@ +NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! + +/dev/bios is obsolete and no longer under development. Please adapt all +changes to the "flashrom" utility of LinuxBIOS. This utility can be found +at LinuxBIOSv2/utils/flashrom in the LinuxBIOS v2 repository. LinuxBIOS +is available at http://www.linuxbios.org/ + +I'm also looking for volunteers to port all features available in /dev/bios +to flashrom so /dev/bios can be dropped from the OpenBIOS tree. These features +include + +- block information about flash chips +- block wise writing of flash chips +- lots of supported flash chips and vendors. + +If you have questions, contact Stefan Reinauer <stepan@coresystems.de> + +NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! NOTE! + + +/dev/bios documentation 2002/02/19 + +Table of contents +------------------ + + 1. What is /dev/bios? + 2. What hardware/software do I need to run /dev/bios? + 3. Where to get the latest release of /dev/bios + 4. How to get /dev/bios work + 5. Writing to the devices + 6. About PCI chipsets (ix86 only) + 7. About APM Powermanagement (ix86 only) + 8. About different flashchips. + 9. Hints for BIOS flashing + +If you want better information on this driver, read the ChangeLog, +mail me or read the source, Luke :-) + +1. What is /dev/bios? +---------------------- + +This is a kernel driver for different kinds of (Flash)BIOSs that are +available in today's hardware. + +There are well known BIOSs for + - System BIOS (resides at 0xe0000 on Intel PCs) + - graphics hardware + - SCSI host adapters + - networking interfaces with 'BOOT ROM' + - ... + +While in former times these BIOSs were implemented by using ROM or +EPROM (both can't be updated without opening your computer) today's +PC hardware is often delivered with so called FLASH ROMs. These +can simply be updated by software. This driver has the approach to +make Linux read and write flash roms. + +One word before you read ahead: This is still alpha software and +writing to your flash roms may destroy them. So if you notice anything +strange, don't even think about going on, but write some mail to: + + Stefan Reinauer <stepan@openbios.org> + +Please note that I am not responsible in any way for what you +do with this code or for what this code does with your computer. + +2. What hardware/software do I need to run /dev/bios? +------------------------------------------------------ + +Currently this driver supports ix86 (mainly Pentium, +PPro, PII/III, Athlon, but some 486s), Itanium and Alpha +architecture. +It supports all flash chips from 32k to 2M (theoretically). +Minimum kernel version is v2.2.x, but it's wise to use a +2.4.x kernel. + +3. Where to get the latest release of /dev/bios? +------------------------------------------------- + +/dev/bios was recently integrated into the OpenBIOS CVS +tree for easier maintainance. General information can be +found on the /dev/bios status page: +http://www.freiburg.linux.de/OpenBIOS/status/devbios.html +Latest releases of /dev/bios can be found at the download page: +http://www.freiburg.linux.de/OpenBIOS/dev/download.html +Latest development trees of /dev/bios can be found in the +OpenBIOS CVS. For information how to access it, go to +http://www.freiburg.linux.de/OpenBIOS/dev/cvs.html + +4. How do I get /dev/bios work +------------------------------- + +Create the system bios device with + + mknod /dev/bios c 104 0 + +Now you can add devices for the other BIOSs (often known as option +roms) in your Computer, i.e. like this: + + mknod /dev/gfxbios c 104 1 + mknod /dev/hddbios c 104 2 + mknod /dev/netbios c 104 3 + +The order of the devices may vary on your computer, maybe you even don't +have a flash bios on your network card or on your scsi host adapter. You will +have to decide this after playing around a bit. + +Now you have to compile and insert the kernel driver module: + + cd devbios + make clean && make + insmod bios.o + +Now you have a new device, /dev/bios and, if you have +your kernel configured to have the /proc/ interface, +you have a status file /proc/bios. + +Since this driver is in an early state, you should have +a look at dmesg very often. + +5. Writing to the devices +-------------------------- + +If you insert bios.o without any options, you are not able +to write any of the devices. To enable writing, you should +use + insmod bios.o write=1 + +Writing is now possible with i.e. + dd if=yourbios.bin of=/dev/bios bs=128k count=1 +or + dd if=yourbios.bin of=/dev/bios bs=256k count=1 + +depending on the size of your flash chip. + +You can use 'cat' for flashing as well. Note: Many flashchips are +sectored and the whole sector has to be rewritten, the 4k clusters +of cat may be very slow (and an 112 kb sector has to be written 28 +times completely instead of 1 time with dd) + +Make sure that your file "yourbios.bin" is a valid bios image for +your motherboard and that it is not pkzipped or exe-pkzipped. +(Usually, a 128kb bios images consist of 112kb lha-compressed data, +2*4kb ESCD and DMI (PnP) Data and an 8 kb emergency boot block.) + +Writing to /dev/bios does not work for many chips right now. Write +accesses are ignored in this case. If you want an unsupported flash +rom supported, please mail me. +WARNING: Setting an unsupported chip to "supported" without changing +the rest of the code will *very likely* destroy the contents of your +chip. + +On machines with an AWARD bios you can test whether writing works +safely by only deleting the ESCD/DMI memory on the flash chip. +This data is rewritten by the bios when empty, corrupted or when +you put in a new expansion device. In that case you should see a +message stating "Updating ESCD" during the next boot. + +Please have a close look at the size of your flash chip. For 128k +flash chips, try + + dd if=/dev/zero of=/dev/bios bs=4096 seek=28 count=2 + +For 256k flash chips, you _MUST_ use the following line instead, +or your system bios is going byebye: + + dd if=/dev/zero of=/dev/bios bs=4096 seek=56 count=2 + +Attention: I found other machines with their ESCD memory in the +first sectors of the flash chip. These are afaics 512k+ chips +often connected via a firmware hub. +Behaviour of other BIOSs may be similar, but I can't give you +any warranty it works. + +NOTE: If you listen to music from your soundcard while flashing, +you may get errors like this: + Sound: DMA (output) timed out - IRQ/DRQ config error? + +Second, sound switches off while flashing. This is because all +IRQs are blocked while the write procedure to ensure it doesn't +get disturbed by any other hardware. + +6. About PCI chipsets +---------------------- + +Because this driver uses direct PCI accesses to switch shadowing +and write protection of the bios off on PC architecture, each PCI +chipset (or at least chipset group) has to be implemented and +tested seperately. Successfully tested PCI chipsets are + + * Intel 430HX/TX, 440BX/ZX, 460, 8x0 + * UMC 486 (8881F/8886A) + * VIA (M)VP3 + * AMD Irongate and others + * ServerWorks chipsets + * NSC CS5530 (geode companion) + +Any success/error reports are highly welcome. If you need a certain +system type supported, contact me. + + +7. About APM Power Management (ix86 only) +------------------------------------------ + +This driver is known to cause kernel oopses with some of the chipset +drivers when APM is enabled. Reason is that the flash chip is mapped +to the low bios address space which makes the unpacked bios image vanish +so all pointers to APM functions are invalid. +Nowadays most of the chipset drivers only map the high bios area, so +this problem should not occur on any but old UMC/SiS chipsets. If you +encounter oopses while reading/probing flash devices, disable power +management before any write attempts. To achieve so, please pass "apm=off" +as a kernel option, if your kernel is compiled with APM support. + + + +8. About different flashchips +------------------------------ + +Flash chips, /dev/bios has been successfully tested (writing) on: + + * Winbond 29EE011 + * Intel 28F008(SA) + * Atmel AT29C512 + * SST 29EE010, 39SF020 + +It *should* work, if you see a "Supported: yes" in /proc/bios, but +I am not responsible in any way for what you do.. Please be careful. +Please report any working flash chips so that this list can be completed. +Currently many more flash chips than mentioned here will work. +If you need a certain flash device supported, contact me. + +9. Hints for BIOS-Flashing +--------------------------- + +* Always try to write to the ESCD/DMI Memory before you overwrite the rest + of a bios (ix86) If you get ANY errors in dmesg output, DO NOT CONTINUE! +* Always "diff" the new bios with the written image before rebooting +* You may use comp, a little utility in the devbios source tree instead + of diff. It has a nicer output for binary files. +* on Intel, only write the first 120k of an image to the System ROM, this keeps + the emergency bootblock working. + +************** FINAL NOTE ***************************** + +If you want to help this project, send me + + * /proc/bios-output + * dmesg-output (after insmodding the driver) + * your system-configuration + (e.g. output of lspci or /proc/bus/pci/devices) + * any comments + * any ideas + + Stefan Reinauer <stepan@openbios.org> + diff --git a/qemu/roms/openbios/utils/devbios/ToDo b/qemu/roms/openbios/utils/devbios/ToDo new file mode 100644 index 000000000..2d320a9ee --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/ToDo @@ -0,0 +1,33 @@ +ToDo-/Buglist 2003/06/04 (0.4pre6) +---------------------------------- + +Memory Stuff + * devbios does not find any flash chip on some systems even though + they are supported. One of the reasons this might happen is that + the flash memory area is hidden using the CPUs mtrrs. If you have + a Pentium II/III/IV or AMD K6/K7 board, you might try + echo "base=0xffe00000 size=0x200000 type=uncachable" >| /proc/mtrr + before loading the module. + +Misc Stuff + * port this driver to fit into the linux kernel's + mtd device drivers. + * join with ctflasher code + * port to *BSD (if anybody wants that) + * disable NMI watchdog while flashing, if active + +PCI Stuff + * unshadow functions do not work on certain 440BX/GX chipsets? + when loading the module, no system flashchip is detected. + * change unshadow functions not to touch low bios area to + be apm and pci bios safe. + +Module stuff + * /proc/sys/kernel/bios-writable + +Flashchip Stuff + * Finnish FWH support. + * Implement writing for Macronix and AMD. + (Catalyst have Intel and AMD compatible chips) + * Implement write protection checking some flash chips have. + * Test/complete existing support diff --git a/qemu/roms/openbios/utils/devbios/bios.h b/qemu/roms/openbios/utils/devbios/bios.h new file mode 100644 index 000000000..b27372d04 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/bios.h @@ -0,0 +1,38 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * bios.h - compile time configuration and globals + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +#include <linux/spinlock.h> + +#define BIOS_MAJOR 104 +#define BIOS_MAXDEV 8 +#define BIOS_VERSION "0.4rc1" + +// #define UTC_BIOS + +extern int write; +extern unsigned char *bios; +extern spinlock_t bios_lock; + diff --git a/qemu/roms/openbios/utils/devbios/bios_core.c b/qemu/roms/openbios/utils/devbios/bios_core.c new file mode 100644 index 000000000..d165cdb3e --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/bios_core.c @@ -0,0 +1,198 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * bios_core.c - core skeleton + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +#include <linux/config.h> +#include <linux/version.h> +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#ifdef MODULE +#ifdef MODVERSIONS +#include <linux/modversions.h> +#endif +#endif +#include <linux/module.h> +#endif +#include <linux/pci.h> +#include <linux/errno.h> +#include <linux/vmalloc.h> +#include <linux/init.h> + +#include <asm/io.h> + +#include "bios.h" +#include "pcisets.h" +#include "flashchips.h" +#include "programming.h" + +extern struct file_operations bios_fops; +int bios_proc_register(void); +int bios_proc_unregister(void); + +int write = 0; + +spinlock_t bios_lock = SPIN_LOCK_UNLOCKED; + +/* + * ****************************************** + * + * Cleanup + * + * ****************************************** + */ + +static void free_iomaps(void) +{ + unsigned long lastmapped=0; + unsigned int i; + + /* We remember the last mapped area to be sure that we only iounmap + * every mapped area once. If two flash devices are in the same + * area but do not occur sequentially during probing you have a + * seriously strange hardware + */ + for (i=0; i<flashcount; i++) { + if (lastmapped==flashdevices[i].mapped) + continue; + iounmap((void *)flashdevices[i].mapped); + lastmapped=flashdevices[i].mapped; + } +} + +/* + * ****************************************** + * + * Initialization + * + * ****************************************** + */ + +void probe_system(void) +{ +#ifdef __alpha__ + probe_alphafw(); +#endif + /* This function checks all flash media attached to + * PCI devices in the system. This means NON-PCI systems + * don't work. This causes machine checks on my LX164 test + * machine, so leave it away until it's fixed. This is + * needed for Ruffians, so we check the machine type + * in probe_alphafw() and call probe_pcibus from there. + * This could use some cleanup + */ +#ifndef __alpha__ + probe_pcibus(); +#endif +} + +static __init int bios_init(void) +{ + printk(KERN_INFO "BIOS driver v" BIOS_VERSION " (writing %s) for " + UTS_RELEASE "\n", write?"enabled":"disabled"); + +#if !defined(UTC_BIOS) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + if (!pci_present()) { + printk(KERN_WARNING "BIOS: No PCI system."); + return -EBUSY; + } +#endif + + /* Probe for flash devices */ + probe_system(); + + if (flashcount==0) { + printk(KERN_WARNING "BIOS: No flash devices found.\n"); + return -EBUSY; + } + + if (register_chrdev(BIOS_MAJOR, "bios", &bios_fops) == -EBUSY) { + printk(KERN_WARNING "BIOS: Could not register bios device.\n"); + free_iomaps(); + return -EBUSY; + } + +#ifdef CONFIG_PROC_FS + bios_proc_register(); +#endif + return 0; +} + +/* + * ****************************************** + * + * module handling + * + * ****************************************** + */ + +#ifdef MODULE +MODULE_PARM(write,"i"); +MODULE_AUTHOR("Stefan Reinauer <stepan@openbios.org>"); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,10) +MODULE_LICENSE("GPL"); +#endif + +static __exit void cleanup_bios_module (void) +{ +#ifdef CONFIG_PROC_FS + bios_proc_unregister(); +#endif + free_iomaps(); + + unregister_chrdev(BIOS_MAJOR, "bios"); + printk(KERN_INFO "BIOS driver removed.\n"); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +int init_module(void) +{ + return bios_init(); +} + +void cleanup_module(void) +{ + cleanup_bios_module(); +} +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,74) +module_init(bios_init); +module_exit(cleanup_bios_module); +#endif + +void inc_mod(void) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + MOD_INC_USE_COUNT; +#endif +} + +void dec_mod(void) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + MOD_DEC_USE_COUNT; +#endif +} + +#endif diff --git a/qemu/roms/openbios/utils/devbios/comp.c b/qemu/roms/openbios/utils/devbios/comp.c new file mode 100644 index 000000000..9d2acb147 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/comp.c @@ -0,0 +1,47 @@ +/* Simple utility to compare 2 files. + * Diff or cmp are not sufficient, when + * comparing bioses :-) + * + * Copyright (c) 1998-2000 by Stefan Reinauer + */ + + +#include <stdio.h> + +int main (int argc, char *argv[]) +{ + FILE *eins,*zwei; + int a,b,i=0,flag=0; + + if(argv[1]==NULL||argv[2]==NULL) { + printf ("Usage: %s file1 file2\n %s compares two files.\n",argv[0],argv[0]); + return 0; + } + eins=fopen(argv[1],"r"); + zwei=fopen(argv[2],"r"); + + if (eins==NULL) { + printf ("File %s not found or unreadable.\n",argv[1]); + return 0; + } + if (zwei==NULL) { + printf ("File %s not found or unreadable.\n",argv[2]); + fclose (eins); + return 0; + } + + while (!feof(eins)) { + a=fgetc(eins); + b=fgetc(zwei); + if (flag==0 && (a==-1||b==-1) && (a!=-1||b!=-1)) { + printf ("One file ended. Printing the rest of the other.\n"); + flag=1; + } + if(a!=b) printf ("0x%06x: 0x%02x -> 0x%02x\n",i,a,b); + i++; + } + + fclose(eins); + fclose(zwei); + return 0; +} diff --git a/qemu/roms/openbios/utils/devbios/filesystem.c b/qemu/roms/openbios/utils/devbios/filesystem.c new file mode 100644 index 000000000..0dab71128 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/filesystem.c @@ -0,0 +1,300 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * filesystem.c - vfs character device interface + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +#include <linux/config.h> +#include <linux/version.h> +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) && defined(MODVERSIONS) +#include <linux/modversions.h> +#endif +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/types.h> +#include <linux/vmalloc.h> +#include <linux/fcntl.h> +#include <linux/delay.h> + +#include <asm/uaccess.h> + +#include "bios.h" +#include "flashchips.h" +#include "pcisets.h" +#include "programming.h" + +#ifdef MODULE +void inc_mod(void); +void dec_mod(void); +#endif + +/* + * ****************************************** + * + * /dev/bios filesystem operations + * + * ****************************************** + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define FDEV (MINOR(file->f_dentry->d_inode->i_rdev)) +#else +#define FDEV (iminor(file->f_dentry->d_inode)) +#endif +#define CFLASH flashdevices[FDEV] +// #define BIOS_SIZE ((flashchips[CFLASH.flashnum].size)*1024) +#define BIOS_SIZE (CFLASH.size) + +static loff_t bios_llseek(struct file *file, loff_t offset, int origin ) +{ + currflash=FDEV; + switch(origin) { + case 0: + break; + case 1: + offset += file->f_pos; + break; + case 2: + offset += BIOS_SIZE; + break; + } + return((offset >= 0)?(file->f_pos = offset):-EINVAL); +} + +static ssize_t bios_read(struct file *file, char *buffer, size_t count, loff_t *ppos) +{ + signed int size=((BIOS_SIZE-*ppos>count) ? count : BIOS_SIZE-*ppos); + unsigned char *addr = (unsigned char*)CFLASH.mapped + CFLASH.offset; + int i; + + currflash = FDEV; + + devices[flashdevices[currflash].idx].activate(); + + for (i=0;i<size;i++) + buffer[i]=flash_readb(addr,*ppos+i); + + devices[flashdevices[currflash].idx].deactivate(); + + *ppos+=size; + return size; +} + +static ssize_t bios_write(struct file *file, const char *buffer, size_t count, loff_t *ppos) +{ + unsigned long flags; + unsigned int offset=0, startsec=0, endsec=0; + unsigned int secnum=0, size=0, writeoffs=0; + unsigned int i, fn; + unsigned char *clipboard; + unsigned char *addr = (unsigned char*)CFLASH.mapped + CFLASH.offset; + + currflash=FDEV; + fn=CFLASH.flashnum; + + /* Some security checks. */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + if (!suser()) + return -EACCES; +#endif + + if (!write) { + printk (KERN_WARNING "Writing is disabled for security reasons. RTFM.\n"); + return -EACCES; + } + + if (!flashchips[fn].supported) { + printk (KERN_ERR "BIOS: Flash device not supported.\n"); + return -EMEDIUMTYPE; + } + + if ( count > BIOS_SIZE-*ppos ) + return -EFBIG; + + /* FIXME: Autoselect(AMD) BC-90 + * -> 00/MID; + * 01/PID; + * 02/Protected (1=yes/0=no) + */ + + /* Determine size of data to be written */ + + if (!(flashchips[fn].flags & f_needs_erase) ) { + offset=(unsigned int)*ppos&~(flashchips[fn].pagesize-1); + size=(((unsigned int)*ppos+count+(flashchips[fn].pagesize-1))& + ~(flashchips[CFLASH.flashnum].pagesize-1))-offset; + } else { + while (flashchips[fn].sectors[secnum] <= flashchips[fn].size ) { + if ((unsigned int)*ppos >= flashchips[fn].sectors[secnum]*1024) { + offset=flashchips[fn].sectors[secnum]*1024; + startsec=secnum; + } + if ((unsigned int)*ppos+count-1 <= flashchips[fn].sectors[secnum]*1024) { + size=(flashchips[fn].sectors[secnum]*1024)-offset; + endsec=secnum-1; + break; + } + secnum++; + } + } + +#ifdef DEBUG + printk (KERN_DEBUG "BIOS: Write [0x%06x..0x%06x] [0x%06x..0x%06x]\n", + (unsigned int)(*ppos),(unsigned int)(*ppos+count-1),offset,offset+size-1); +#endif + + /* prepare data for writing */ + + clipboard=vmalloc(size); + + spin_lock_irqsave(&bios_lock, flags); + + devices[flashdevices[currflash].idx].activate(); + + for (i=0; i < size; i++) + clipboard[i] = flash_readb(addr,offset+i); + + copy_from_user(clipboard+(*ppos-offset), buffer, count); + + /* start write access */ + + if (flashchips[fn].flags & f_intel_compl) { + iflash_erase_sectors(addr,fn,startsec,endsec); + + for (i=0;i<size;i++) + iflash_program_byte(addr, offset+i, clipboard[i]); + + flash_command(addr, 0xff); + + } else { + + if (flashchips[fn].flags & f_needs_erase) { + if (size == flashchips[fn].size*1024) { /* whole chip erase */ + printk (KERN_DEBUG "BIOS: Erasing via whole chip method\n"); + flash_erase(addr, fn); + } else { + printk (KERN_DEBUG "BIOS: Erasing via sector method\n"); + flash_erase_sectors(addr, fn,startsec,endsec); + } + } + + while (size>0) { + if ((flashchips[fn].flags & f_manuf_compl) != f_atmel_compl) { + flash_program(addr); + } else { + flash_program_atmel(addr); + } + for (i=0;i<flashchips[fn].pagesize;i++) { + flash_writeb(addr,offset+writeoffs+i,clipboard[writeoffs+i]); + } + if ((flashchips[fn].flags & f_manuf_compl) == f_atmel_compl) { + udelay(750); + } else { + if (flashchips[fn].pagesize==1) + udelay(30); + else + udelay(300); + } + + if (flash_ready_poll(addr,offset+writeoffs+flashchips[fn].pagesize-1, + clipboard[writeoffs+flashchips[fn].pagesize-1])) { + printk (KERN_ERR "BIOS: Error occured, please repeat write operation.\n"); + } + flash_command(addr, 0xf0); + + writeoffs += flashchips[fn].pagesize; + size -= flashchips[fn].pagesize; + } + } + + devices[flashdevices[currflash].idx].deactivate(); + + spin_unlock_irqrestore(&bios_lock, flags); + + vfree(clipboard); + + *ppos+=count; + return count; +} + +static int bios_open(struct inode *inode, struct file *file) +{ + currflash=FDEV; + + if (flashcount<=FDEV) { + printk (KERN_ERR "BIOS: There is no device (%d).\n",FDEV); + return -ENODEV; + } + +#ifdef DEBUG + printk(KERN_DEBUG "BIOS: Opening device %d\n",FDEV); +#endif + /* Only one shall open for writing */ + + if ((CFLASH.open_cnt && (file->f_flags & O_EXCL)) || + (CFLASH.open_mode & O_EXCL) || + ((file->f_mode & 2) && (CFLASH.open_mode & O_RDWR))) + return -EBUSY; + + if (file->f_flags & O_EXCL) + CFLASH.open_mode |= O_EXCL; + + if (file->f_mode & 2) + CFLASH.open_mode |= O_RDWR; + + CFLASH.open_cnt++; + + +#ifdef MODULE + inc_mod(); +#endif + return 0; +} + +static int bios_release(struct inode *inode, struct file *file) +{ + currflash=FDEV; + if (file->f_flags & O_EXCL) + CFLASH.open_mode &= ~O_EXCL; + + if (file->f_mode & 2) + CFLASH.open_mode &= ~O_RDWR; + + CFLASH.open_cnt--; + +#ifdef MODULE + dec_mod(); +#endif + return 0; +} + +struct file_operations bios_fops = { + .owner = THIS_MODULE, + .llseek = bios_llseek, + .read = bios_read, + .write = bios_write, + .open = bios_open, + .release = bios_release, +}; + diff --git a/qemu/roms/openbios/utils/devbios/flashchips.c b/qemu/roms/openbios/utils/devbios/flashchips.c new file mode 100644 index 000000000..460a85def --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/flashchips.c @@ -0,0 +1,313 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * flashchips.c - contains all information about supported flash devices. + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ +// <-- C++ style comments are for experimental comments only. +// They will disappear as soon as I fixed all the stuff. + +#include "bios.h" +#include "flashchips.h" + +unsigned int currflash=0; + +const manufacturer_t manufacturers[] = +{ + { "AMD", 0x01 }, + { "AMI", 0x02 }, + { "Fairchild", 0x83 }, + { "Fujitsu", 0x04 }, + { "GTE", 0x85 }, + { "Harris", 0x86 }, + { "Hitachi", 0x07 }, + { "Inmos", 0x08 }, + { "Intel", 0x89 }, + { "I.T.T.", 0x8A }, + { "Intersil", 0x0B }, + { "Monolithic Memories",0x8C }, + { "Mostek", 0x0D }, + { "Motorola", 0x0E }, + { "National", 0x8F }, + { "NEC", 0x10 }, + { "RCA", 0x91 }, + { "Raytheon", 0x92 }, + { "Rockwell", 0x13 }, + { "Seeq", 0x94 }, + { "Philips Semi.", 0x15 }, + { "Synertek", 0x16 }, + { "Texas Instruments", 0x97 }, + { "Toshiba", 0x98 }, + { "Xicor", 0x19 }, + { "Zilog", 0x1A }, + { "Eurotechnique", 0x9B }, + { "Mitsubishi", 0x1C }, + { "PMC Flash", 0x9D }, + { "Exel", 0x9E }, + { "Atmel", 0x1F }, + { "SGS/Thomson", 0x20 }, + { "Lattice Semi.", 0xA1 }, + { "NCR", 0xA2 }, + { "Wafer Scale Integr.",0x23 }, + { "IBM", 0xA4 }, + { "Tristar", 0x25 }, + { "Visic", 0x26 }, + { "Intl. CMOS Tech.", 0xA7 }, + { "SSSI", 0xA8 }, + { "MicrochipTech.", 0x29 }, + { "Ricoh Ltd.", 0x2A }, + { "VLSI", 0xAB }, + { "Micron Technology", 0x2C }, + { "Hyundai Elect.", 0xAD }, + { "OKI Semiconductor", 0xAE }, + { "ACTEL", 0x2F }, + { "Sharp", 0xB0 }, + { "Catalyst", 0x31 }, + { "Panasonic", 0x32 }, + { "IDT", 0xB3 }, + { "Cypress", 0x34 }, + { "DEC", 0xB5 }, + { "LSI Logic", 0xB6 }, + { "Plessey", 0x37 }, + { "UTMC", 0x38 }, + { "Thinking Machine", 0xB9 }, + { "Thomson CSF", 0xBA }, + { "Integ. CMOS(Vertex)",0x3B }, + { "Honeywell", 0xBC }, + { "Tektronix", 0x3D }, + { "Sun Microsystems", 0x3E }, + { "SST", 0xBF }, + { "MOSEL", 0x40 }, + { "Siemens", 0xC1 }, + { "Macronix", 0xC2 }, + { "Xerox", 0x43 }, + { "Plus Logic", 0xC4 }, + { "SunDisk", 0x45 }, + { "Elan Circuit Tech.", 0x46 }, + { "Europ. Silicon Str.",0xC7 }, + { "Apple Computer", 0xC8 }, + { "Xilinx", 0xC9 }, + { "Compaq", 0x4A }, + { "Protocol Engines", 0xCB }, + { "SCI", 0x4C }, + { "Seiko Instruments", 0xCD }, + { "Samsung", 0xCE }, + { "I3 Design System", 0x4F }, + { "Klic", 0xD0 }, + { "Crosspoint Sol.", 0x51 }, + { "Alliance Semicond.", 0x52 }, + { "Tandem", 0xD3 }, + { "Hewlett-Packard", 0x54 }, + { "Intg. Silicon Sol.", 0xD5 }, + { "Brooktree", 0xD6 }, + { "New Media", 0x57 }, + { "MHS Electronic", 0x58 }, + { "Performance Semi.", 0xD9 }, + { "Winbond", 0xDA }, + { "Kawasaki Steel", 0x5B }, + { "Bright Micro", 0xDC }, + { "TECMAR", 0x5D }, + { "Exar", 0x5E }, + { "PCMCIA", 0xDF }, + { "Goldstar", 0xE0 }, + { "Northern Telecom", 0x61 }, + { "Sanyo", 0x62 }, + { "Array Microsystems", 0xE3 }, + { "Crystal Semicond.", 0x64 }, + { "Analog Devices", 0xE5 }, + { "PMC-Sierra", 0xE6 }, + { "Asparix", 0x67 }, + { "Convex Computer", 0x68 }, + { "Quality Semicond.", 0xE9 }, + { "Nimbus Technology", 0xEA }, + { "Transwitch", 0x6B }, + { "ITT Intermetall", 0xEC }, + { "Cannon", 0x6D }, + { "Altera", 0x6E }, + { "NEXCOM", 0xEF }, + { "QUALCOMM", 0x70 }, + { "Sony", 0xF1 }, + { "Cray Research", 0xF2 }, + { "AMS(Austria Micro)", 0x73 }, + { "Vitesse", 0xF4 }, + { "Aster Electronics", 0x75 }, + { "Bay Networks(Synoptic)", 0x76 }, + { "Zentrum Mikroelec.", 0xF7 }, + { "TRW", 0xF8 }, + { "Thesys", 0x79 }, + { "Solbourne Computer", 0x7A }, + { "Allied-Signal", 0xFB }, + { "Dialog", 0x7C }, + { "Media Vision", 0xFD }, + { "Level One Commun.", 0xFE }, + { "Eon", 0x7F }, + + { "Unknown", 0x00 } +}; + +const flashchip_t flashchips[] = +{ + /* AMD */ + { "29F016B", 0xad01, 5, 2048, 0, 1, 1, (int []) { 0,2048 } }, + { "29F080B", 0xd501, 5, 1024, 0, 1, 1, (int []) { 0,1024 } }, + { "29F800BT", 0xd601, 5, 1024, 0, 1, 1, (int []) { 0,1024 } }, + { "29F800BB", 0x5801, 5, 1024, 0, 1, 1, (int []) { 0,1024 } }, + { "29F040B", 0xa401, 5, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "29F400T", 0x2301, 5, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "29LV004T", 0xb501, 3, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "29LV400T", 0xb901, 3, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "29F400B", 0xab01, 5, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "29LV004B", 0xb601, 3, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "29LV400B", 0xba01, 3, 512, 0, 1, 1, (int []) { 0, 512 } }, + { "28F020A", 0x2901, 12, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "28F020", 0x2a01, 12, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29F002T", 0xb001, 5, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29LV002T", 0x4001, 3, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29LV200T", 0x3b01, 3, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29F200T", 0x5101, 5, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29F002B", 0x3401, 5, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29LV002B", 0xc201, 3, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29LV200B", 0xbf01, 3, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29F200B", 0x5701, 5, 256, 0, 1, 1, (int []) { 0, 256 } }, + { "29F010", 0x2001, 5, 128, 0, 1, 1, (int []) { 0, 128 } }, + { "28F010A", 0xa201, 12, 128, 0, 1, 1, (int []) { 0, 128 } }, + { "28F010", 0xa701, 12, 128, 0, 1, 1, (int []) { 0, 128 } }, + { "29F100T", 0xd901, 5, 64, 0, 1, 1, (int []) { 0, 64 } }, + { "29F100B", 0xdf01, 5, 64, 0, 1, 1, (int []) { 0, 64 } }, + { "28F512A", 0xae01, 12, 64, 0, 1, 1, (int []) { 0, 64 } }, + { "28F512", 0x2501, 12, 64, 0, 1, 1, (int []) { 0, 64 } }, + { "28F256A", 0x2f01, 12, 32, 0, 1, 1, (int []) { 0, 32 } }, + { "28F256", 0xa101, 12, 32, 0, 128, 1, (int []) { 0, 32 } }, + + /* Atmel */ + { "AT49BV010", 0x851f, 3, 128, 0, 128, 1, (int []) { 0, 128 } }, +//Word { "AT49F1025", 0x851f, 5, 128, 0, 256, 1, (int []) { 0, 128 } }, + { "AT49x020", 0x0b1f, 5, 256, 0, 128, 1, (int []) { 0, 256 } }, + { "AT49F040", 0x131f, 5, 512, 0, 128, 1, (int []) { 0, 512 } }, + { "AT49F010", 0x171f, 5, 128, 0, 128, 1, (int []) { 0, 128 } }, + { "AT49F080", 0x231f, 5, 1024, 0, 128, 1, (int []) { 0,1024 } }, + { "AT29C040A", 0xa41f, 5, 512, 1, 256, 4, (int []) { 0, 512 } }, +//Word { "AT29C1024", 0x251f, 3, 128, 0, 128, 0, (int []) { 0, 128 } }, +//Word { "AT29LV1024", 0x261f, 3, 128, 0, 128, 0, (int []) { 0, 128 } }, + { "AT49F080T", 0xa71f, 5, 1024, 0, 128, 1, (int []) { 0,1024 } }, + { "AT29BV010A", 0x351f, 3, 128, 1, 128, 4, (int []) { 0, 128 } }, + { "AT29BV020", 0xba1f, 3, 256, 1, 256, 4, (int []) { 0, 256 } }, + { "AT29LV256", 0xbc1f, 3, 32, 1, 64, 4, (int []) { 0, 32 } }, + { "AT29LV512", 0x3d1f, 3, 64, 1, 128, 4, (int []) { 0, 64 } }, + { "AT29BV040A", 0xc41f, 3, 512, 1, 256, 4, (int []) { 0, 512 } }, + { "AT29C010A", 0xd51f, 5, 128, 1, 128, 4, (int []) { 0, 128 } }, + { "AT29C020", 0xda1f, 5, 256, 1, 256, 4, (int []) { 0, 256 } }, + { "AT29C256", 0xdc1f, 3, 32, 1, 64, 4, (int []) { 0, 32 } }, + { "AT29C512", 0x5d1f, 5, 64, 1, 128, 4, (int []) { 0, 64 } }, + + /* Catalyst */ + { "CAT28F150T", 0x0431, 12, 192, 1, 128, 3, (int []) { 0, 64,160,168,176,192 } }, + { "CAT28F150B", 0x8531, 12, 192, 1, 128, 3, (int []) { 0, 16, 24, 32,128, 192 } }, + { "CAT28F001T", 0x9431, 12, 128, 1, 128, 3, (int []) { 0,112,116,120,128 } }, + { "CAT28F001B", 0x1531, 12, 128, 1, 128, 3, (int []) { 0, 8, 12, 16,128 } }, + { "CAT29F002T", 0xb031, 5, 256, 0, 128, 1, (int []) { 0, 64,128,192,224,232,240,256 } }, + { "CAT29F002B", 0x3431, 5, 256, 0, 128, 1, (int []) { 0, 16, 24, 32, 64,128,192,256 } }, + { "CAT28F002T", 0x7c31, 12, 256, 1, 128, 3, (int []) { 0,128,224,232,240,256 } }, + { "CAT28F002B", 0xfd31, 12, 256, 1, 128, 3, (int []) { 0, 16, 24, 32,128,256 } }, + { "CAT28F020" , 0xbd31, 12, 256, 0, 1, 1, (int []) { 0,256 } }, +//Word { "CAT28F102" , 0x5131, 12, 128, 0, 0, 0, (int []) { 0,128 } }, + { "CAT28F010" , 0xb431, 12, 128, 0, 1, 1, (int []) { 0,128 } }, + { "CAT28F512" , 0xb831, 12, 64, 0, 1, 1, (int []) { 0, 64 } }, + + { "29F040", 0xa404, 5, 512, 1, 1, 1, (int []) { 0, 64, 128, 192, 256, 320, 384, 448, 512 } }, /* Fujitsu */ + + + /* Intel */ + { "28F010", 0x3489, 12, 128, 0, 128, 1, (int []) { 0,128 } }, + { "28F020", 0x3d89, 12, 256, 0, 128, 1, (int []) { 0,256 } }, + { "28F001BX-T", 0x9489, 12, 128, 1, 128, 3, (int []) { 0,112,116,120,128 } }, + { "28F001BX-B", 0x9589, 12, 128, 1, 128, 3, (int []) { 0, 8, 12, 16,128 } }, +//Word { "28F400BX-T", 0x7089, 12, 512, 0, 256, 3, (int []) { 0,128,256,384,480,488,496,512 } }, +//Word { "28F400BX-B", 0xF189, 12, 512, 0, 256, 3, (int []) { 0, 16, 24, 32,128,256,384,512 } }, +//Word { "28F200-T", 0xF489, 12, 256, 0, 256, 3, (int []) { 0,128,224,232,240,256} }, +//Word { "28F200-B", 0x7589, 12, 256, 0, 256, 3, (int []) { 0, 16, 24, 32,128,256 } }, + { "28F016B3-T", 0xd089, 3, 1024, 0, 1, 3, (int []) { 0, 2048 } }, + { "28F016B3-B", 0xd189, 3, 1024, 0, 1, 3, (int []) { 0, 2048 } }, + { "28F008B3-T", 0xd289, 3, 1024, 0, 1, 3, (int []) { 0, 1024 } }, + { "28F008B3-B", 0xd389, 3, 1024, 0, 1, 3, (int []) { 0, 1024 } }, + { "28F004B3-T", 0xd489, 3, 512, 0, 128, 3, (int []) { 0,128,256,384,480,488,496,512 } }, + { "28F004B3-B", 0xd589, 3, 512, 0, 128, 3, (int []) { 0, 16, 24, 32,128,256,384,512 } }, + { "28F004BX-T", 0xF889, 12, 512, 1, 128, 3, (int []) { 0,128,256,384,480,488,496,512 } }, + { "28F004BX-B", 0x7989, 12, 512, 1, 128, 3, (int []) { 0, 16, 24, 32,128,256,384,512 } }, + { "28F002-T", 0x7c89, 12, 256, 1, 128, 3, (int []) { 0,128,224,232,240,256 } }, + { "28F002-B", 0xfd89, 12, 256, 1, 256, 3, (int []) { 0, 16, 24, 32,128,256 } }, + { "28F008??", 0xa289, 12, 1024, 1, 1, 3, (int []) { 0, 64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024 } }, + { "28F008SA", 0xa189, 12, 1024, 1, 1, 3, (int []) { 0, 64,128,192,256,320,384,448,512,576,640,704,768,832,896,960,1024 } }, + { "28F004??", 0xad89, 5, 512, 0, 1, 3, (int []) { 0, 512} }, + { "28F008??", 0xac89, 5, 1024, 0, 1, 3, (int []) { 0,1024} }, + + /* Eon */ + { "E28F004S5", 0x7f8f, 5, 512, 1, 1, 3, (int []) { 0, 64,128,192,256,320,384,448,512 } }, + { "EN29F002B", 0x977f, 5, 256, 1, 1, 1, (int []) { 0, 16, 24, 32,128,256 } }, + { "EN29F002T", 0x927f, 5, 256, 1, 1, 1, (int []) { 0,128,224,232,240,256 } }, + + /* SST */ + { "28EE011", 0x01bf, 5, 128, 0, 128, 0, (int []) { 0, 128 } }, + { "28EE040", 0x04bf, 5, 512, 0, 128, 0, (int []) { 0, 512 } }, + { "29EE010", 0x07bf, 5, 128, 1, 128, 0, (int []) { 0, 128 } }, + { "29x010", 0x08bf, 3, 128, 0, 128, 0, (int []) { 0, 128 } }, + { "29EE020", 0x10bf, 5, 256, 0, 128, 0, (int []) { 0, 256 } }, + { "29x020", 0x92bf, 3, 256, 0, 128, 0, (int []) { 0, 256 } }, + { "29x512", 0x3dbf, 3, 64, 0, 128, 0, (int []) { 0, 64 } }, + { "29EE512", 0x5dbf, 5, 64, 0, 128, 0, (int []) { 0, 64 } }, + { "29x020", 0x92bf, 3, 256, 0, 128, 0, (int []) { 0, 256 } }, + { "39SF020", 0xb6bf, 5, 256, 1, 1, 0x81, (int []) { 0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256 } }, + { "49LF002A", 0x57bf, 3, 256, 0, 1, 0x81, (int[]) {0,256} }, + { "49LF003A", 0x1bbf, 3, 384, 0, 1, 0x81, (int[]) {0,384} }, + { "49LF004A", 0x60bf, 3, 512, 1, 1, 0x09, (int[]) {0, 4, 8, 12, 16, 24,28, 32, 512} }, + { "49LF008A", 0x5abf, 3, 1024, 0, 1, 0x81, (int[]) {0,1024} }, + { "49LF020", 0x61bf, 3, 256, 1, 4096, 0, (int[]) {0,256} }, + { "49LF040", 0x51bf, 3, 512, 1, 4096, 0, (int[]) {0,512} }, + { "49LF080A", 0x5bbf, 3, 1024, 1, 4096, 0, (int[]) {0,1024} }, + + /* Macronix */ + { "MX28F1000AP",0x1ac2, 12, 128, 0, 1, 1, (int []) { 0, 16, 32, 48, 64, 80, 96,112,116,120,124,128 } }, + { "MX28F1000P", 0x91c2, 12, 128, 0, 1, 1, (int []) { 0, 16, 32, 48, 64, 80, 96,112,128 } }, + { "MX28F1000PC",0xf7c2, 12, 128, 0, 1, 1, (int []) { 0, 16, 32, 48, 64, 80, 96,112,128 } }, +//id? { "MX28F1000PPC",0x7fc2,12, 128, 0, 1, 1, (int []) { 0, 16, 32, 48, 64, 80, 96,112,116,120,124,128 } }, + { "MX29F1610A", 0xfac2, 5, 2048, 1, 128, 0, (int []) { 0, 2048} }, + + /* Winbond */ + { "W29EE011", 0xc1da, 5, 128, 1, 128, 0, (int []) { 0, 128 } }, + { "W29C020", 0x45da, 5, 256, 1, 128, 0, (int []) { 0, 256 } }, + { "W29C040/042",0x46da, 5, 512, 1, 256, 0, (int []) { 0, 512 } }, + { "W29EE512", 0xc8da, 5, 64, 1, 128, 0, (int []) { 0, 64 } }, + { "W29C101", 0x4fda, 5, 128, 1, 256, 0, (int []) { 0, 128 } }, + { "W49V002", 0xb0da, 3, 256, 1, 1, 1, (int []) { 0, 64, 128, 192, 224, 232, 240, 256 } }, + //{ "W49F002", 0x0bda, 5, 256, 1, 1, 1, (int []) { 0, 64, 128, 192, 224, 232, 240, 256 } }, + { "W49F002U", 0x0bda, 5, 256, 1, 1,0x09, (int []) { 0, 128, 224, 232, 240, 256 } }, /* Winbond */ + + /* SGS/Thomson */ + { "M29F002B(N)T", 0xb020, 5, 256, 0, 1, 0, (int[]) {0, 64, 128, 256 } }, + { "M29F002B(N)B", 0x3420, 5, 256, 0, 1, 0, (int[]) {0, 256 } }, + { "M50FW040", 0x2c20, 3, 512, 1, 128, 0x0b, (int []) { 0, 64, 128, 192, 256, 320, 384, 448, 512 } }, + + { "Pm29F002T", 0x1d9d, 5, 256, 1, 1, 0x1, (int []) { 0,128,224,232,240,256 } }, + /* default entry */ + { "Unknown", 0x0000, 0, 0, 0, 0, 0, (int []) { 0 } } +}; + diff --git a/qemu/roms/openbios/utils/devbios/flashchips.h b/qemu/roms/openbios/utils/devbios/flashchips.h new file mode 100644 index 000000000..3e6e5a6e0 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/flashchips.h @@ -0,0 +1,81 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * flashchips.h - flash device structures. + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +/* + * flags structure + * bit 0 = needs erase before write (f_needs_erase) + * bit 1-3 flash manu type + * bit 4-6 probably needed for more manu + * bit 7 = sector erase happens one sector at a time + * (f_slow_sector_erase) + */ + +#define f_needs_erase 0x01 + +/* 3 bit for flashtype */ +#define f_manuf_compl 0x0e /* Mask out bits 1-3 */ +#define f_intel_compl 0x02 /* 001 */ +#define f_atmel_compl 0x04 /* 010 */ +#define f_fwh_compl 0x08 /* 100 */ + +#define f_slow_sector_erase 0x80 + +#define FLASH_UNKNOWN 0 +#define FLASH_CFI 1 +#define FLASH_JEDEC 2 + +typedef struct flashdevice { + unsigned long mapped; + unsigned long physical; + unsigned long offset; + unsigned int flashnum, manufnum; + unsigned short id; + unsigned int size, sectors; + unsigned int idx; + void *data; + int open_mode, open_cnt; +} flashdevice_t; + +typedef struct flashchip { + char *name; + unsigned short id; + unsigned int voltage; + unsigned int size; /* KBytes */ + unsigned int supported; + unsigned int pagesize; /* Bytes */ + unsigned int flags; + unsigned int *sectors; /* Kbytes[] including end of last sector */ +} flashchip_t; + +typedef struct manufacturer { + char *name; + unsigned short id; +} manufacturer_t; + +extern unsigned int currflash; +extern flashdevice_t flashdevices[BIOS_MAXDEV]; +extern const flashchip_t flashchips[]; +extern const manufacturer_t manufacturers[]; diff --git a/qemu/roms/openbios/utils/devbios/pcisets.c b/qemu/roms/openbios/utils/devbios/pcisets.c new file mode 100644 index 000000000..91b9e0ea0 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/pcisets.c @@ -0,0 +1,630 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * pcisets.c - support functions to map flash devices to kernel space + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +#include <linux/config.h> +#include <linux/version.h> +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#ifdef MODVERSIONS +#include <linux/modversions.h> +#endif +#endif +#include <linux/pci.h> +#include <linux/types.h> +#include <linux/ioport.h> +#include <asm/io.h> +#ifdef __alpha__ +#include <asm/hwrpb.h> +#endif + +#include "bios.h" +#include "flashchips.h" +#include "pcisets.h" +#include "programming.h" + +#ifdef CONFIG_PCI +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +#define pci_find_class pci_get_class +#endif + +#define pci_id(dev) ((dev->vendor<<16) | (dev->device)) +struct pci_dev *hostbridge=NULL; +static unsigned char pci_dummy[4]; + +/* + * ****************************************** + * + * own pci/shadow handling; We can't use + * the PCI bios here as it would sweep + * itself out! + * + * ****************************************** + */ + +static int pci_read(struct pci_dev *dev, unsigned char where) +{ + if (!dev) return 0; + + outl((0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | + (where & ~3)), 0xCF8); + mb(); + return inb(0xCFC + (where&3)); +} + +static void pci_write(struct pci_dev *dev, unsigned char where, unsigned char value) +{ + if (!dev) return; + outl((0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | + (where & ~3)), 0xCF8); + mb(); + outb(value, 0xCFC + (where&3)); +} + +/* + * standard system firmware adress emitter + */ + +static int system_memarea(unsigned long *address, unsigned long *size, + struct pci_dev *dev) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + const struct pci_driver *drv; + drv = pci_dev_driver(dev); +#endif +#ifndef __alpha__ + *address=0xffe00000; + *size=2048*1024; +#else + *address=0xfffffffffc000000; + *size=512*1024; +#endif + printk(KERN_INFO "BIOS: Probing system firmware with " + "%ldk rom area @0x%lx (%04x:%04x)\n", + (*size>>10), *address, dev->vendor, dev->device ); +#ifdef CONFIG_PCI_NAMES +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + if (drv) printk(KERN_INFO "BIOS: System device is %s\n", drv->name); +#else + printk(KERN_INFO "BIOS: System device is %s\n", dev->name); +#endif +#endif + return 0; +} + +static int memarea_256k(unsigned long *address, unsigned long *size, + struct pci_dev *dev) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + const struct pci_driver *drv; + drv = pci_dev_driver(dev); +#endif + *address=0xfffc0000; + *size=256*1024; + printk(KERN_INFO "BIOS: Probing system firmware with " + "%ldk rom area @0x%lx (%04x:%04x)\n", + (*size>>10), *address, dev->vendor, dev->device ); +#ifdef CONFIG_PCI_NAMES +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + if (drv) printk(KERN_INFO "BIOS: System device is %s\n", drv->name); +#else + printk(KERN_INFO "BIOS: System device is %s\n", dev->name); +#endif +#endif + return 0; +} + +/* + * standard address emitter for normal pci devices + */ + +static int default_memarea(unsigned long *address, unsigned long *size, + struct pci_dev *dev) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + *address=dev->resource[PCI_ROM_RESOURCE].start; + *size=dev->resource[PCI_ROM_RESOURCE].end - *address + 1; +#else + *address=0xdeadbeef; + *size=0x00000000; +#endif + if (*address && (signed long)*address!=-1 ) { + printk (KERN_DEBUG "BIOS: Probing PCI device %02x:%02x.%01x " + "with %ldk rom area @ 0x%lx\n", + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), + (*size>>10), *address); + return 1; + } + *address=0xdeadbeef; + *size=0x00000000; + return 0; +} + +#ifdef __alpha__ +void probe_alphafw(void) +{ + switch(hwrpb->sys_type) { + case ST_DEC_EB164: + /* Fall through */ + break; + case ST_DTI_RUFFIAN: + /* case ST_DEC_TSUNAMI: // This crashes for whatever reason */ + probe_pcibus(); + return; + default: + printk(KERN_INFO "BIOS: unsupported alpha motherboard.\n"); + return; + } + + /* LX164 has system variation 0x2000 */ + if (hwrpb->sys_variation == 0x2000) + printk(KERN_INFO "BIOS: LX164 detected\n"); + else + printk(KERN_INFO "BIOS: EB164 board detected. Sys_var=0x%lx\n", + hwrpb->sys_variation); + + flashdevices[flashcount].data=(void *)0xfff80000; + flash_probe_area(0xfff80000, 512*1024, 0); +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#define pci_for_each_dev(dev) \ + for(dev = pci_devices->next; dev != pci_devices; dev = dev->next) +#endif +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,74) +#define pci_for_each_dev(dev) \ + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev))) +#endif + +#define DEVICE(x) devices[g].pcidevs[x] +void probe_pcibus(void) +{ + struct pci_dev *dev=NULL; + unsigned int g=0, d, map_always=0; + unsigned long addr, size; + + /* Look whether we find something supported */ + pci_for_each_dev(dev) { + /* Search all device groups */ + for (g=0; DEVICE(0); g++ ) { + /* Search all devices in group */ + for (d=0; DEVICE(d) && DEVICE(d) != pci_id(dev); d++); + if(DEVICE(d) == pci_id(dev)) + break; + } + + flashdevices[flashcount].idx=g; + flashdevices[flashcount].data=dev; + + map_always=devices[g].memarea(&addr, &size, dev); +#ifdef DEBUG_PCI + printk(KERN_INFO "BIOS: device=%x, cs=%d addr=%lx, size=%ld\n", + pci_id(dev),g, addr,size); +#endif + if(!size) + continue; + + flash_probe_area(addr, size, map_always); + } +} +#undef DEVICE + +/* Intel 430, 440, 450 PCI Chipsets */ + +#define CURRENT ((struct pci_dev *)flashdevices[currflash].data) +static int gporeg_save; +static void intel4x0_activate(void) +{ +#ifdef __ABIT_BE6II_v11__ +#define GPONUM 26 +#define GPOREG_OFFSET 0x34 + register unsigned int gporeg; + /* Read Bus 0, Dev 7, Func 3, Reg 40-44 (Power Managment Base Address) */ + outl (0x80003B40, 0x0CF8); + /* calc General Purpose Output Register I/O port address */ + gporeg = (0xFFFFFFFE & inl (0x0CFC)) + GPOREG_OFFSET; + + /* Set GPO26 to 0 */ + gporeg_save=inl(gporeg); + printk(KERN_DEBUG "BIOS: GPOREG=0x%08x, mask=0x%x, new=0x%x\n",gporeg_save, (~(1<<GPONUM)), gporeg_save&(~(1<<GPONUM))); + outl (gporeg_save&(~(1<<GPONUM)), gporeg); +#undef GPOREG_OFFSET +#endif + + pci_dummy[0]=pci_read(CURRENT, 0x4e); + pci_dummy[1]=pci_read(CURRENT, 0x4f); + + /* Write and 128k enable */ + pci_dummy[2]=0x44; //0xC4 + + if (CURRENT->device < 0x7000) { + /* enable 512k */ + pci_dummy[2]|=0x80; + } else { + /* enable 1M */ + pci_write(CURRENT, 0x4f, pci_dummy[1] | 0x02); + } + + pci_write(CURRENT, 0x4e, pci_dummy[0] | pci_dummy[2]); + + // printk(KERN_DEBUG "BIOS: isa bridge cfg is 0x%02x\n", pci_dummy[0]); +} + +static void intel4x0_deactivate(void) +{ +#ifdef __ABIT_BE6II_v11__ +#define GPOREG_OFFSET 0x34 + register unsigned long gporeg; + + /* Read Bus 0, Dev 7, Func 3, Reg 40-44 (Power Managment Base Address) */ + outl (0x80003B40, 0x0CF8); + /* calc General Purpose Output Register I/O port address */ + gporeg = (0xFFFFFFFE & inl (0x0CFC)) + GPOREG_OFFSET; + + /* Reset GBO26 */ + outl (gporeg_save, gporeg); +#undef GPOREG_OFFSET +#endif + pci_write(CURRENT, 0x4e, pci_dummy[0]); + pci_write(CURRENT, 0x4f, pci_dummy[1]); +} + +/* preliminary support for Intel 830 mobile chipset. untested!! */ + +static void intel8x0_activate(void) +{ + pci_dummy[0]=pci_read(CURRENT, 0x4e); + pci_dummy[1]=pci_read(CURRENT, 0xe3); + pci_write(CURRENT, 0x4e, pci_dummy[0] | 0x01); + pci_write(CURRENT, 0xe3, pci_dummy[1] | 0xC0); + + // We don't have to change FWH_DEC_EN1, as it decodes + // all memory areas to the FWH per default. + // We try it anyways. + + // FWH_DEC_EN1: isabridge, 0xe3, 8bit, default 0xff. + // FWH_SEL1: isabridge, 0xe8, 32bit, default 0x00112233 (??) + + //printk(KERN_DEBUG "BIOS: BIOS_CNTL is 0x%02x\n", pci_dummy[0]); + //printk(KERN_DEBUG "BIOS: FWH_DEC_EN1 is 0x%02x\n", pci_dummy[1]); +} + +static void intel8x0_deactivate(void) +{ + pci_write(CURRENT, 0x4e, pci_dummy[0]); + pci_write(CURRENT, 0xe3, pci_dummy[1]); +} + +/* AMD 760/756/751 & VIA (M)VP3 */ + +static void amd7xx_activate(void) +{ + pci_dummy[0]=pci_read(CURRENT, 0x40); /* IO Control 1 */ + pci_dummy[1]=pci_read(CURRENT, 0x43); /* SEGEN */ + + pci_write(CURRENT, 0x40, pci_dummy[0] | 0x01); + pci_write(CURRENT, 0x43, pci_dummy[1] | 0x80); +} + +static void amd7xx_deactivate(void) +{ + pci_write(CURRENT, 0x43, pci_dummy[1]); + pci_write(CURRENT, 0x40, pci_dummy[0]); +} + +static void viamvp3_activate(void) +{ + hostbridge = pci_find_class(PCI_CLASS_BRIDGE_HOST<<8,NULL); + if (!hostbridge) + return; + pci_dummy[0]=pci_read(hostbridge,0x52); + pci_write(hostbridge, 0x52, pci_dummy[0] & 0xcf); + pci_dummy[1]=pci_read(hostbridge, 0x63); + pci_write(hostbridge, 0x63, pci_dummy[1] & 0x0f); + pci_dummy[2]=pci_read(CURRENT,0x43); + pci_write(CURRENT, 0x43, pci_dummy[2] |0xF8); + + pci_write(CURRENT, 0x40, pci_read(CURRENT,0x40) | 0x01); +} + +static void viamvp3_deactivate(void) +{ + if (!hostbridge) + return; + pci_write(CURRENT, 0x40, pci_read(CURRENT,0x40) & 0xfe); + pci_write(hostbridge, 0x63, pci_dummy[1]); + pci_write(hostbridge, 0x52, pci_dummy[0]); + pci_write(CURRENT, 0x43, pci_dummy[2]); +} + +/* SiS works with 530/5595 chipsets */ + +static void sis_activate(void) +{ + char b; + hostbridge = pci_find_class(PCI_CLASS_BRIDGE_HOST<<8,NULL); + if (!hostbridge) + return; + + pci_dummy[0]=pci_read(hostbridge, 0x76); + pci_dummy[1]=readb(0x51); + pci_dummy[2]=pci_read(CURRENT, 0x40); + pci_dummy[3]=pci_read(CURRENT, 0x45); + + /* disable shadow */ + pci_write(hostbridge, 0x76, 0x00); + /* disable cache */ + writeb(pci_dummy[1] & 0x7f, 0x51); + + /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */ + pci_write(CURRENT, 0x40, pci_dummy[2]|0x0b); + /* Flash write enable on SiS 540/630 */ + pci_write(CURRENT, 0x45, pci_dummy[3]|0x40); + + /* The same thing on SiS 950 SuperIO side */ + outb(0x87, 0x2e); + outb(0x01, 0x2e); + outb(0x55, 0x2e); + outb(0x55, 0x2e); + if (inb(0x2f) != 0x87) { + /* printf("Can not access SiS 950\n"); */ + return; + } + + outb(0x24, 0x2e); + b = inb(0x2f) | 0xfc; + outb(0x24, 0x2e); + outb(b, 0x2f); + outb(0x02, 0x2e); + outb(0x02, 0x2f); +} + +static void sis_deactivate(void) +{ + if (!hostbridge) + return; + + /* Restore PCI Registers */ + pci_write(hostbridge, 0x76, pci_dummy[0]); + pci_write(CURRENT, 0x45, pci_dummy[2]); + pci_write(CURRENT, 0x45, pci_dummy[3]); + /* restore cache to original status */ + writeb(pci_dummy[1], 0x51); +} + +/* UMC 486 Chipset 8881/886a */ + +static void umc_activate(void) +{ + hostbridge = pci_find_class(PCI_CLASS_BRIDGE_HOST<<8,NULL); + if (!hostbridge) + return; + + pci_dummy[0]=pci_read(hostbridge, 0x54); + pci_dummy[1]=pci_read(hostbridge, 0x55); + + pci_write(hostbridge, 0x54, 0x00); + pci_write(hostbridge, 0x55, 0x40); + + pci_write(CURRENT,0x47, pci_read(CURRENT,0x47) & ~0x40); +} + +static void umc_deactivate(void) +{ + if (!hostbridge) + return; + + pci_write(CURRENT, 0x47, pci_read(CURRENT,0x47) | 0x40); + + pci_write(hostbridge, 0x54, pci_dummy[0]); + pci_write(hostbridge, 0x55, pci_dummy[1]); +} + +/* CS5530 functions */ + +static void cs5530_activate(void) +{ + /* Save modified registers for later reset */ + pci_dummy[0]=pci_read(CURRENT,0x52); + pci_dummy[1]=pci_read(CURRENT,0x5b); + + /* enable rom write access */ + pci_write(CURRENT, 0x52, pci_dummy[0]|0x06); + + /* enable rom positive decode */ + // pci_write(CURRENT,0x5b, pci_dummy[1]|0x20); + // pci_write(CURRENT,0x52, pci_read(CURRENT,0x52)|0x01); +} + +static void cs5530_deactivate(void) +{ + pci_write(CURRENT, 0x52, pci_dummy[0]); + // pci_write(CURRENT, 0x5b, pci_dummy[1]); +} + +/* Reliance / ServerWorks */ + +static void reliance_activate(void) +{ + pci_dummy[0]=pci_read(CURRENT,0x41); + pci_dummy[1]=pci_read(CURRENT,0x70); + pci_dummy[2]=inb(0xc6f); + + /* Enable 512k */ + pci_write(CURRENT, 0x41, pci_dummy[0] | 0x02); + /* Enable 4MB */ + pci_write(CURRENT, 0x70, pci_dummy[1] | 0x80); + /* Enable flash write */ + outb(pci_dummy[2] | 0x40, 0xc6f); +} + +static void reliance_deactivate(void) +{ + pci_write(CURRENT, 0x41, pci_dummy[0]); + pci_write(CURRENT, 0x70, pci_dummy[1]); + outb(pci_dummy[2], 0xc6f); +} + +/* ALi Methods - untested */ +static void ali_activate(void) +{ + pci_dummy[0]=pci_read(CURRENT, 0x47); + pci_dummy[1]=pci_read(CURRENT, 0x79); + pci_dummy[2]=pci_read(CURRENT, 0x7f); + + /* write enable, 256k enable */ +#ifdef OLD_ALi + pci_write(CURRENT, 0x47, pci_dummy[0]|0x47); +#else + pci_write(CURRENT, 0x47, pci_dummy[0]|0x43); +#endif + + /* M1543C rev B1 supports 512k. Register reserved before */ +#ifdef OLD_ALi + pci_write(CURRENT, 0x79, pci_dummy[1]|0x10); + pci_write(CURRENT, 0x7f, pci_dummy[2]|0x01); +#else + pci_write(CURRENT, 0x7b, pci_dummy[1]|0x10); +#endif +} + +static void ali_deactivate(void) +{ + pci_write(CURRENT, 0x47, pci_dummy[0]); + pci_write(CURRENT, 0x79, pci_dummy[1]); + pci_write(CURRENT, 0x7f, pci_dummy[2]); +} + +/* Default routines. Use these if nothing else works */ +#if 0 +static unsigned int def_addr; +#endif +static void default_activate(void) +{ +#if 0 && LINUX_VERSION_CODE > KERNEL_VERSION(2,4,0) + struct resource *r; + + r=&CURRENT->resource[PCI_ROM_RESOURCE]; + + r->flags |= PCI_ROM_ADDRESS_ENABLE; + r->flags &= ~(IORESOURCE_READONLY|IORESOURCE_CACHEABLE); + pci_read_config_dword(CURRENT, CURRENT->rom_base_reg, &def_addr); + if (def_addr) + pci_write_config_dword (CURRENT, CURRENT->rom_base_reg, + def_addr|PCI_ROM_ADDRESS_ENABLE); +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + long ret; + + if (pci_enable_device(CURRENT)) + return; + + pci_write_config_dword (CURRENT, CURRENT->rom_base_reg, + pci_resource_start(CURRENT, PCI_ROM_RESOURCE)| + PCI_ROM_ADDRESS_ENABLE); + + ret=(long)request_mem_region( pci_resource_start(CURRENT, + PCI_ROM_RESOURCE), pci_resource_len(CURRENT, + PCI_ROM_RESOURCE), "Firmware memory"); + if (!ret) + printk (KERN_ERR "BIOS: cannot reserve MMROM region " + "0x%lx+0x%lx\n", + pci_resource_start(CURRENT, PCI_ROM_RESOURCE), + pci_resource_len(CURRENT, PCI_ROM_RESOURCE)); + else + printk (KERN_INFO "BIOS: mapped rom region to 0x%lx\n", ret); +#endif +} + +static void default_deactivate(void) +{ +#if 0 && LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + struct resource *r; + r=&CURRENT->resource[PCI_ROM_RESOURCE]; + r->flags &= ~PCI_ROM_ADDRESS_ENABLE; + r->flags |= (IORESOURCE_READONLY|IORESOURCE_CACHEABLE); + pci_write_config_dword (CURRENT, CURRENT->rom_base_reg, def_addr); +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + release_mem_region(pci_resource_start(CURRENT, PCI_ROM_RESOURCE), + pci_resource_len(CURRENT, PCI_ROM_RESOURCE)); +#endif +} + +const struct flashdev devices[] = { + /* Intel 4x0 chipsets */ + { (int[]) { 0x8086122e, 0x80861234, 0x80867000, 0x80867110, + 0x80867198, 0 }, + intel4x0_activate, intel4x0_deactivate, system_memarea }, + + /* Intel 8x0 chipsets */ + { (int[]) { 0x80862410, 0x80862420, 0x80862440, 0x8086244c, + 0x80862480, 0x8086248c, 0x80867600, 0 }, + intel8x0_activate, intel8x0_deactivate, system_memarea }, + + /* Irongate 75x, AMD-76xMP(X), VT8231/3 */ + { (int[]) { 0x10227400, 0x10227408, 0x10227410, 0x10227440, + 0x11068231, 0x11063074, 0 }, + amd7xx_activate, amd7xx_deactivate, system_memarea }, + + /* AMD Hammer (thor chipset) */ + { (int[]) { 0x10227468, 0 }, + amd7xx_activate, amd7xx_deactivate, system_memarea }, + + /* VIA (M)VP3, VT82C686 [Apollo Super South] */ + { (int[]) { 0x11060586, 0x11060596, 0x11060686, 0 }, + viamvp3_activate, viamvp3_deactivate, memarea_256k }, + + /* UMC */ + { (int[]) { 0x1060886a, 0x10600886, 0x1060e886, 0x10608886, 0 }, + umc_activate, umc_deactivate, system_memarea }, + + /* SiS */ + { (int[]) { 0x10390008, 0x10390018, 0 }, + sis_activate, sis_deactivate, system_memarea }, + + /* OPTi */ + { (int[]) { 0x1045c558, 0 }, + default_activate, default_deactivate, system_memarea }, + + /* NSC CS5530(A) */ + { (int[]) { 0x10780100, 0 }, + cs5530_activate, cs5530_deactivate, memarea_256k }, + + /* Reliance/ServerWorks NB6xxx */ + { (int[]) { 0x11660200, 0 }, + reliance_activate, reliance_deactivate, system_memarea }, + + /* ALi */ + { (int[]) { 0x10b91523, 0x10b91533, 0x10b91543, 0 }, + ali_activate, ali_deactivate, system_memarea }, + + { (int[]) { 0x00000000 }, + default_activate, default_deactivate, default_memarea } +}; + +#endif /* CONFIG_PCI */ + diff --git a/qemu/roms/openbios/utils/devbios/pcisets.h b/qemu/roms/openbios/utils/devbios/pcisets.h new file mode 100644 index 000000000..1045f0a42 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/pcisets.h @@ -0,0 +1,45 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * pcisets.h - structures for device bindings + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +#include <linux/pci.h> + +#ifdef CONFIG_PCI + +struct flashdev { + unsigned int *pcidevs; + void (*activate)(void); + void (*deactivate) (void); + int (*memarea)(unsigned long *address, unsigned long *size, + struct pci_dev *dev); +}; + +extern const struct flashdev devices[]; + +void probe_pcibus(void); +#ifdef __alpha__ +void probe_alphafw(void); +#endif +#endif diff --git a/qemu/roms/openbios/utils/devbios/procfs.c b/qemu/roms/openbios/utils/devbios/procfs.c new file mode 100644 index 000000000..12ad17e3e --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/procfs.c @@ -0,0 +1,162 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * procfs.c - proc filesystem handling for flash device listing. + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +#include <linux/config.h> +#include <linux/version.h> +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) && defined(MODVERSIONS) +#include <linux/modversions.h> +#endif +#include <linux/proc_fs.h> + +#ifdef CONFIG_PROC_FS +#include "bios.h" +#include "pcisets.h" +#include "flashchips.h" +#include "programming.h" + +struct proc_dir_entry *proc_bios; + +#define PRINT_PROC(fmt,args...) \ + do { \ + if (!run) \ + break; \ + len += sprintf( buffer+len, fmt, ##args ); \ + if (begin + len > offset + size) \ + run=0; \ + else if (begin + len < offset) { \ + begin += len; \ + len = 0; \ + } \ + } while (0) + +/* + * ****************************************** + * + * /proc/bios handling + * + * ****************************************** + */ + +#define CFLASH flashdevices[i] +#define FLASH flashchips[CFLASH.flashnum] +#define MANUF manufacturers[CFLASH.manufnum] + +int bios_read_proc(char *buffer, char **start, off_t offset, int size, int *eof, void *data) +{ + int len=0, run=1, i; + off_t begin = 0; + + for (i=0;i<flashcount;i++) { +#ifdef DEBUG_PROC + printk(KERN_DEBUG "BIOS: processing proc info for " + "flashchip %d\n",i+1); +#endif + if (i) /* empty line is seperator between flash chips */ + PRINT_PROC("\n"); + + PRINT_PROC("Memory Address : 0x%08lx\n", + (unsigned long)CFLASH.physical); + PRINT_PROC("Memory Size : %d kByte\n", CFLASH.size>>10); + PRINT_PROC("Flash Type : "); + + if (CFLASH.id == 0) { + PRINT_PROC("ROM\n"); + continue; + } + + /* Flash chip completely unknown -> output ID and proceed */ + if (FLASH.id == 0) { + PRINT_PROC("unknown %s device (id 0x%04x)\n", + MANUF.name, CFLASH.id); + PRINT_PROC("Supported : no\n"); + continue; + } + + PRINT_PROC("%s %s (%dV)\n", MANUF.name, + FLASH.name, FLASH.voltage); + + PRINT_PROC("Supported : %s\n", + FLASH.supported ? "yes": "no"); +#ifdef DEBUG + PRINT_PROC("Pagetable : %d Byte\n", FLASH.pagesize ); + + PRINT_PROC("Erase first : %s\n", + FLASH.flags & f_needs_erase ? "yes": "no"); + + PRINT_PROC("Intel compliant : %s\n", + FLASH.flags & f_intel_compl ? "yes": "no"); + + PRINT_PROC("FWH compliant : %s\n", + FLASH.flags & f_fwh_compl ? "yes": "no"); + + if (CFLASH.sectors > 1) + PRINT_PROC("Sectors : %d\n", CFLASH.sectors); +#endif + } +#ifdef DEBUG_PROC + printk(KERN_DEBUG "BIOS: read_proc done.\n"); +#endif + /* set to 1 if we're done */ + *eof=run; + + if (offset >= begin + len) + return 0; + + *start = buffer + (begin - offset); + + return (size < begin + len - offset ? size : begin + len - offset); +} +#undef FLASH +#undef MANUF +#undef CFLASH + +#ifdef PROC_WRITEABLE +int bios_write_proc(struct file *file, const char *buffer, unsigned long count, void *data) +{ + printk (KERN_INFO "%s\n",buffer); + return count; +} +#endif + +int bios_proc_register(void) +{ + if ((proc_bios = create_proc_entry("bios", 0, 0))) { + proc_bios->read_proc = bios_read_proc; +#ifdef PROC_WRITABLE + proc_bios->write_proc = bios_write_proc; +#endif + return 0; + } + return 1; +} + +int bios_proc_unregister(void) +{ + if (proc_bios) + remove_proc_entry("bios", 0); + return 0; +} +#endif diff --git a/qemu/roms/openbios/utils/devbios/programming.c b/qemu/roms/openbios/utils/devbios/programming.c new file mode 100644 index 000000000..e1b35a34b --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/programming.c @@ -0,0 +1,539 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * programming.c - flash device programming and probing algorithms. + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +// <-- C++ style comments are for experimental comments only. +// They will disappear as soon as I fixed all the stuff. + +/* #define DEBUG_PROBING */ + +#include <linux/config.h> +#include <linux/version.h> +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) && defined(MODVERSIONS) +#include <linux/modversions.h> +#endif + +#include <linux/pci.h> +#include <linux/errno.h> +#include <linux/types.h> +#include <linux/vmalloc.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <asm/io.h> +#include <asm/delay.h> +#include <asm/uaccess.h> + +#include "bios.h" +#include "pcisets.h" +#include "flashchips.h" +#include "programming.h" + +struct flashdevice flashdevices[BIOS_MAXDEV]; +int flashcount; + +/* + * ****************************************** + * + * flashchip handling + * + * ****************************************** + */ + + +void flash_command (unsigned char *addr, unsigned char command) +#if 1 +{ + flash_writeb(addr, 0x5555, 0xaa); + flash_writeb(addr, 0x2AAA, 0x55); + flash_writeb(addr, 0x5555, command); +} +void fwh_flash_command(unsigned char *addr, unsigned char command) +#endif +{ + flash_writeb(addr, 0x75555, 0xaa); + flash_writeb(addr, 0x72aaa, 0x55); + flash_writeb(addr, 0x75555, command); +} + +#define CFLASH flashdevices[flashcount] +int flash_probe_address(void *address) +{ + int flashnum=0, manufnum=0, sectors=0; + unsigned short flash_id, testflash; + unsigned long flags; +#ifdef DEBUG_PROBING + printk( KERN_DEBUG "BIOS: Probing for flash chip @0x%08lx\n", (unsigned long) address); +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + save_flags(flags); +#endif + spin_lock_irqsave(&bios_lock, flags); + + testflash= (flash_readb(address, 0))+(flash_readb(address, 1)<<8); + + /* 1st method: Intel, Atmel listen to this.. */ + + flash_command(address, 0x90); + udelay(20); + + flash_id = (flash_readb(address, 0))+(flash_readb(address, 1)<<8); + +#ifdef DEBUG_PROBING + printk (KERN_DEBUG "BIOS: testflash[%04x] flash_id[%04x]\n", + testflash, flash_id); +#endif + + /* 2nd method: Winbond (I think this is Jedec standard) */ + + if (flash_id==testflash) { +#ifdef DEBUG_PROBING + printk (KERN_DEBUG "BIOS: Trying 2nd ID method.\n"); +#endif + flash_command(address, 0xf0); /* Reset */ + udelay(20); + + flash_command(address, 0x80); + flash_command(address, 0x60); + udelay(20); + + flash_id = (flash_readb(address, 0))+(flash_readb(address, 1)<<8); +#ifdef DEBUG_PROBING + printk (KERN_DEBUG "BIOS: testflash[%04x] flash_id[%04x]\n", + testflash, flash_id); +#endif + } + + /* 3rd Method: Some Winbonds seem to want this */ + + if (flash_id==testflash) { +#ifdef DEBUG_PROBING + printk (KERN_DEBUG "BIOS: Trying 3rd ID method.\n"); +#endif + flash_command(address, 0xf0); /* Reset again */ + udelay(20); + + flash_command(address, 0x80); + flash_command(address, 0x20); + udelay(20); + + flash_id = (flash_readb(address, 0))+(flash_readb(address, 1)<<8); +#ifdef DEBUG_PROBING + printk (KERN_DEBUG "BIOS: testflash[%04x] flash_id[%04x]\n", + testflash, flash_id); +#endif + } + + if (flash_id==0x7f7f && flash_readb(address, 0x100)==0x1c) { + /* We have an Eon flashchip. They keep their + * device id at 0x101 instead of 0x1 + */ + printk(KERN_INFO "BIOS: Eon flash device detected\n"); + flash_id=(flash_readb(address, 0x1))+(flash_readb(address, 0x101)<<8); + } + + flash_command(address, 0xf0); + udelay(20); + + spin_unlock_irqrestore(&bios_lock, flags); + + if (flash_id==testflash) return 0; /* Nothing found :-( */ + + while (flashchips[flashnum].id!=0) { + if (flash_id==flashchips[flashnum].id) + break; + flashnum++; + } + + while (manufacturers[manufnum].id!=0) { + if ((flash_id&0xff)==manufacturers[manufnum].id) + break; + manufnum++; + } + + if (flashchips[flashnum].id) { + while (flashchips[flashnum].sectors[sectors]<flashchips[flashnum].size) + sectors++; + } + + if (flashcount >= BIOS_MAXDEV) { + printk(KERN_DEBUG "BIOS: Too many flash devices found.\n"); + return -1; + } + + CFLASH.flashnum = flashnum; + CFLASH.manufnum = manufnum; + CFLASH.id = flash_id; + CFLASH.size = (flashchips[flashnum].size<<10); + CFLASH.sectors = sectors; + CFLASH.open_mode= 0; + CFLASH.open_cnt = 0; + + return 1; +} + +void flash_probe_area(unsigned long romaddr, unsigned long romsize, + int map_always) +{ + unsigned long probeaddr; + unsigned char *mapped; + + mapped=ioremap(romaddr, romsize); + + devices[flashdevices[currflash].idx].activate(); + + probeaddr=(unsigned long)mapped; + + while ( probeaddr < (unsigned long)mapped + romsize - 0x5555 ) { + if ( flash_probe_address ((void *)probeaddr) != 1) { + probeaddr += 4*1024; + continue; + } + + CFLASH.offset = probeaddr-(unsigned long)mapped; + CFLASH.mapped = (unsigned long)mapped; + CFLASH.physical = romaddr+CFLASH.offset; + + printk( KERN_INFO "BIOS: flash device with size " + "%dk (ID 0x%04x) found.\n", + CFLASH.size >> 10, CFLASH.id); + + printk( KERN_INFO "BIOS: physical address " + "0x%08lx (va=0x%08lx+0x%lx).\n", + CFLASH.physical, (unsigned long)CFLASH.mapped, + CFLASH.offset); + + if (flashchips[CFLASH.flashnum].flags&f_fwh_compl) { + unsigned long t_lk; + unsigned int i=7; + printk(KERN_INFO "BIOS: FWH compliant " + "chip detected.\n"); + for (t_lk=0xffb80002; t_lk<=0xffbf0002; t_lk+=0x10000) + { + printk(KERN_INFO "Lock register %d " + "(0x%08lx): 0x%x\n", + i, t_lk, (unsigned int) + (readb(phys_to_virt(t_lk)))); + i--; + } + } + flashcount++; + currflash++; +#ifdef MULTIPLE_FLASH + probeaddr += flashdevices[flashcount-1].size; + flashdevices[flashcount].mapped=flashdevices[flashcount-1].mapped; + flashdevices[flashcount].data=flashdevices[flashcount-1].data; + continue; +#else + break; +#endif + } + + /* We might want to always map the memory + * region in certain cases + */ + + if (map_always) { + CFLASH.flashnum = 0; + CFLASH.manufnum = 0; + CFLASH.id = 0; + CFLASH.size = romsize; + CFLASH.sectors = 0; + CFLASH.open_mode= 0; + CFLASH.open_cnt = 0; + CFLASH.offset = 0; + CFLASH.mapped = (unsigned long)mapped; + CFLASH.physical = romaddr; + printk( KERN_INFO "BIOS: rom device with size " + "%dk registered.\n", CFLASH.size >> 10); + flashcount++; currflash++; + return; + } + + /* We found nothing in this area, so let's unmap it again */ + + if (flashcount && flashdevices[flashcount-1].mapped != (unsigned long)mapped) + iounmap(mapped); + + devices[flashdevices[currflash].idx].deactivate(); +} + +#undef CFLASH + +void flash_program (unsigned char *addr) +{ + flash_command(addr, 0xa0); +} + +void flash_program_atmel (unsigned char *addr) +{ + flash_command(addr, 0x80); + flash_command(addr, 0x20); +} + +int flash_erase (unsigned char *addr, unsigned int flashnum) +{ + flash_command(addr, 0x80); + flash_command(addr, 0x10); + udelay(80); + return flash_ready_toggle(addr, 0); +} + +int flash_erase_sectors (unsigned char *addr, unsigned int flashnum, unsigned int startsec, unsigned int endsec) +{ + unsigned int sector; + + if (!(flashchips[flashnum].flags & f_slow_sector_erase)) { + flash_command(addr, 0x80); + + if (flashchips[flashnum].flags&f_fwh_compl) { + flash_writeb(addr, 0x75555,0xaa); + flash_writeb(addr, 0x72aaa,0x55); + } else { + flash_writeb(addr, 0x5555,0xaa); + flash_writeb(addr, 0x2aaa,0x55); + } + + for (sector=startsec; sector <= endsec; sector++) { + flash_writeb (addr, flashchips[flashnum].sectors[sector]*1024, 0x30); + } + + udelay(150); // 80 max normally, wait 150usec to be sure +#if 0 + if (flashchips[flashnum].flags&f_fwh_compl) +#endif + return flash_ready_toggle(addr, flashchips[flashnum].sectors[sector-1]*1024); +#if 0 + else + return flash_ready_poll(addr, flashchips[flashnum].sectors[sector-1]*1024, 0xff); +#endif + } + + /* sectors must be sent the sector erase command for every sector */ + for (sector=startsec; sector <= endsec; sector++) { + flash_command(addr, 0x80); + if (flashchips[flashnum].flags&f_fwh_compl) { + flash_writeb(addr, 0x75555,0xaa); + flash_writeb(addr, 0x72aaa,0x55); + } else { + flash_writeb(addr, 0x5555,0xaa); + flash_writeb(addr, 0x2aaa,0x55); + } + + flash_writeb(addr, flashchips[flashnum].sectors[sector]*1024, 0x30); + udelay(150); +#if 0 + if (flashchips[flashnum].flags&f_fwh_compl) +#endif + flash_ready_toggle(addr, flashchips[flashnum].sectors[sector] *1024); +#if 0 + else + flash_ready_poll(addr, flashchips[flashnum].sectors[sector]*1024, 0xff); +#endif + } + + return 0; + +} + +/* waiting for the end of programming/erasure by using the toggle method. + * As long as there is a programming procedure going on, bit 6 of the last + * written byte is toggling it's state with each consecutive read. + * The toggling stops as soon as the procedure is completed. + * This function returns 0 if everything is ok, 1 if an error occured + * while programming was in progress. + */ + +int flash_ready_toggle (unsigned char *addr, unsigned int offset) +{ + unsigned long int timeout=0; + unsigned char oldflag, flag; + int loop=1; + + oldflag=flash_readb(addr, offset) & 0x40; + + while (loop && (timeout<0x7fffffff)) { + flag=flash_readb(addr, offset) & 0x40; + + if (flag == oldflag) + loop=0; + + oldflag=flag; + timeout++; + } + + if (loop) { + printk(KERN_DEBUG "BIOS: operation timed out (Toggle)\n"); + return 1; + } + + return 0; +} + +/* This functions is similar to the above one. While a programming + * procedure is going on, bit 7 of the last written data byte is + * inverted. When the procedure is completed, bit 7 contains the + * correct data value + */ + +int flash_ready_poll (unsigned char *addr, unsigned int offset, unsigned char data) +{ + unsigned long int timeout=0; + unsigned char flag; + + flag=flash_readb(addr, offset); + + while ( ( flag & 0x80) != ( data & 0x80)) { + if ( ( flag & 0x80 ) == ( data & 0x80 ) ) { +#ifdef DBGTIMEOUT + printk(KERN_DEBUG "BIOS: Timeout value (EOT Polling) %ld\n",timeout); +#endif + return 0; + } + flag=flash_readb(addr, offset); + if (timeout++>12800) { // 10 times more than usual. + printk(KERN_ERR "BIOS: EOT Polling timed out at 0x%08x." + " Try again or increase max. timeout.\n",offset); + return 1; + } + if ((flag & 0x80) == ( data & 0x80)) { + flag=flash_readb(addr, offset); + } + } +#ifdef DBGTIMEOUT + printk(KERN_DEBUG "BIOS: Timeout value (EOT Polling) %ld\n",timeout); +#endif + + flag=flash_readb(addr, offset); + if ( ( flag & 0x80 ) == ( data & 0x80 ) ) return 0; else return 1; +} + + + +void iflash_program_byte (unsigned char *addr, unsigned int offset, unsigned char data) +{ + unsigned long int timeout=0; + unsigned char flag; + + flash_writeb (addr, offset, 0x40); + flash_writeb (addr, offset, data); + + flash_writeb (addr, offset, 0x70); /* Read Status */ + do { + flag=flash_readb (addr, offset); + if (timeout++>100) { // usually 2 or 3 :-) + printk(KERN_ERR "BIOS: Intel programming timed out at" + "0x%08x. Try again or increase max. timeout.\n",offset); + return; + } + } while ((flag&0x80) != 0x80); + +#ifdef DBGTIMEOUT + printk (KERN_DEBUG"BIOS: Timeout value (Intel byte program) %ld\n",timeout); +#endif + + if (flag&0x18) { + flash_writeb (addr, offset, 0x50); /* Reset Status Register */ + printk (KERN_ERR "BIOS: Error occured, please repeat write operation. (intel)\n"); + } + + flash_writeb (addr, offset, 0xff); +} + + + +int iflash_erase_sectors (unsigned char *addr, unsigned int flashnum, unsigned int startsec, unsigned int endsec) +{ + unsigned long int timeout; + unsigned int sector, offset=0; + unsigned char flag; + + for (sector=startsec; sector<=endsec; sector++) { + offset=(flashchips[flashnum].sectors[sector]*1024); + flash_writeb (addr, offset, 0x20); + flash_writeb (addr, offset, 0xd0); + + flash_writeb (addr, offset, 0x70); /* Read Status */ + timeout=0; + do { + flag=flash_readb (addr, offset); + if (timeout++>1440000) { // usually 144000 + printk(KERN_ERR "BIOS: Intel sector erase timed out at 0x%08x. Try again or increase max. timeout.\n",offset); + return 1; + } + } while ((flag&0x80) != 0x80); + +#ifdef DBGTIMEOUT + printk (KERN_DEBUG "BIOS: Timeout value (Intel sector erase) %ld\n",timeout); +#endif + + if (flag&0x28) { + flash_writeb (addr, offset, 0x50); + flash_writeb (addr, offset, 0xff); + return 1; /* Error! */ + } + } + + flash_writeb (addr, offset, 0xff); + return 0; +} + + + +unsigned char flash_readb(unsigned char *addr, unsigned int offset) +{ +#if defined(__alpha__) + if (flashdevices[currflash].data==(void *)0xfff80000) { + if (offset<0x80000) + outb(0x00,0x800); + else { + outb(0x01, 0x800); + offset-=0x80000; + } + } +#endif + return readb(addr+offset); +} + + + +void flash_writeb(unsigned char *addr, unsigned int offset, unsigned char data) +{ +#if defined(__alpha__) + if (flashdevices[currflash].data==(void *)0xfff80000) { + if (offset<0x80000) + outb(0x00,0x800); + else { + outb(0x01, 0x800); + offset-=0x80000; + } + } +#endif +/* + printk(KERN_DEBUG "BIOS: writing 0x%02x to 0x%lx+0x%x\n", + data,bios,offset); + */ + writeb(data,addr+offset); +} diff --git a/qemu/roms/openbios/utils/devbios/programming.h b/qemu/roms/openbios/utils/devbios/programming.h new file mode 100644 index 000000000..3ad104e86 --- /dev/null +++ b/qemu/roms/openbios/utils/devbios/programming.h @@ -0,0 +1,73 @@ +/* + * OpenBIOS - free your system! + * ( firmware/flash device driver for Linux ) + * + * programming.h - prototypes for flash device programming + * + * This program is part of a free implementation of the IEEE 1275-1994 + * Standard for Boot (Initialization Configuration) Firmware. + * + * Copyright (C) 1998-2004 Stefan Reinauer, <stepan@openbios.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + */ + +/* Addresses */ +#define ADDR_MANUFACTURER 0x0000 +#define ADDR_DEVICE_ID 0x0001 +#define ADDR_SECTOR_LOCK 0x0002 +#define ADDR_HANDSHAKE 0x0003 + +#define ADDR_UNLOCK_1 0x5555 +#define ADDR_UNLOCK_2 0x2AAA +#define ADDR_COMMAND 0x5555 + +/* Commands */ +#define CMD_UNLOCK_DATA_1 0xAA +#define CMD_UNLOCK_DATA_2 0x55 +#define CMD_MANUFACTURER_UNLOCK_DATA 0x90 +#define CMD_UNLOCK_BYPASS_MODE 0x20 +#define CMD_PROGRAM_UNLOCK_DATA 0xA0 +#define CMD_RESET_DATA 0xF0 +#define CMD_SECTOR_ERASE_UNLOCK_DATA 0x80 +#define CMD_SECTOR_ERASE_UNLOCK_DATA_2 0x30 +#define CMD_ERASE_DATA 0x10 +#define CMD_UNLOCK_SECTOR 0x60 + +extern int flashcount; + +void flash_command(unsigned char *addr, unsigned char command); + +void flash_program (unsigned char *addr); +void flash_program_atmel (unsigned char *addr); + +int flash_ready_toggle (unsigned char *addr, unsigned int offset); +int flash_ready_poll (unsigned char *addr, unsigned int offset, unsigned char data); + +int flash_erase (unsigned char *addr, unsigned int flashnum); +int flash_erase_sectors (unsigned char *addr, unsigned int flashnum, + unsigned int startsec, unsigned int endsec); + +void iflash_program_byte (unsigned char *addr, unsigned int offset, unsigned char data); +int iflash_erase_sectors (unsigned char *addr, unsigned int flashnum, unsigned int startsec, unsigned int endsec); + +unsigned char flash_readb(unsigned char *addr, unsigned int offset); +void flash_writeb(unsigned char *addr, unsigned int offset, unsigned char data); + + +int flash_probe_address(void *address); +void flash_probe_area(unsigned long romaddr, unsigned long romsize, + int map_always); + |