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author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
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committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/pc-bios/s390-ccw/start.S | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/pc-bios/s390-ccw/start.S')
-rw-r--r-- | qemu/pc-bios/s390-ccw/start.S | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/qemu/pc-bios/s390-ccw/start.S b/qemu/pc-bios/s390-ccw/start.S new file mode 100644 index 000000000..b6dd8c2fb --- /dev/null +++ b/qemu/pc-bios/s390-ccw/start.S @@ -0,0 +1,65 @@ +/* + * First stage boot loader for virtio devices. The compiled output goes + * into the pc-bios directory of qemu. + * + * Copyright (c) 2013 Alexander Graf <agraf@suse.de> + * Copyright 2013 IBM Corp. + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at + * your option) any later version. See the COPYING file in the top-level + * directory. + */ + + .globl _start +_start: + +larl %r15, stack + 0x8000 /* Set up stack */ +larl %r6, boot_value +stg %r7, 0(%r6) /* save the boot_value before any function calls */ +j main /* And call C */ + +/* + * void disabled_wait(void) + * + * stops the current guest cpu. + */ + .globl disabled_wait +disabled_wait: + larl %r1,disabled_wait_psw + lpswe 0(%r1) + + +/* + * void consume_sclp_int(void) + * + * eats one sclp interrupt + */ + .globl consume_sclp_int +consume_sclp_int: + /* enable service interrupts in cr0 */ + stctg 0,0,0(15) + oi 6(15), 0x2 + lctlg 0,0,0(15) + /* prepare external call handler */ + larl %r1, external_new_code + stg %r1, 0x1b8 + larl %r1, external_new_mask + mvc 0x1b0(8),0(%r1) + /* load enabled wait PSW */ + larl %r1, enabled_wait_psw + lpswe 0(%r1) + +external_new_code: + /* disable service interrupts in cr0 */ + stctg 0,0,0(15) + ni 6(15), 0xfd + lctlg 0,0,0(15) + br 14 + + .align 8 +disabled_wait_psw: + .quad 0x0002000180000000,0x0000000000000000 +enabled_wait_psw: + .quad 0x0302000180000000,0x0000000000000000 +external_new_mask: + .quad 0x0000000180000000 |