Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

6 files changed, 0 insertions, 496 deletions

diff --git a/qemu/include/hw/pci-host/apb.h b/qemu/include/hw/pci-host/apb.h
deleted file mode 100644
index 736db6118..000000000
--- a/qemu/include/hw/pci-host/apb.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef APB_PCI_H
-#define APB_PCI_H
-
-#include "qemu-common.h"
-
-PCIBus *pci_apb_init(hwaddr special_base,
-                     hwaddr mem_base,
-                     qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
-                     qemu_irq **pbm_irqs);
-#endif
diff --git a/qemu/include/hw/pci-host/gpex.h b/qemu/include/hw/pci-host/gpex.h
deleted file mode 100644
index 68c93488c..000000000
--- a/qemu/include/hw/pci-host/gpex.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * QEMU Generic PCI Express Bridge Emulation
- *
- * Copyright (C) 2015 Alexander Graf <agraf@suse.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-
-#ifndef HW_GPEX_H
-#define HW_GPEX_H
-
-#include "hw/hw.h"
-#include "hw/sysbus.h"
-#include "hw/pci/pci.h"
-#include "hw/pci/pcie_host.h"
-
-#define TYPE_GPEX_HOST "gpex-pcihost"
-#define GPEX_HOST(obj) \
-     OBJECT_CHECK(GPEXHost, (obj), TYPE_GPEX_HOST)
-
-#define TYPE_GPEX_ROOT_DEVICE "gpex-root"
-#define MCH_PCI_DEVICE(obj) \
-     OBJECT_CHECK(GPEXRootState, (obj), TYPE_GPEX_ROOT_DEVICE)
-
-#define GPEX_NUM_IRQS 4
-
-typedef struct GPEXRootState {
-    /*< private >*/
-    PCIDevice parent_obj;
-    /*< public >*/
-} GPEXRootState;
-
-typedef struct GPEXHost {
-    /*< private >*/
-    PCIExpressHost parent_obj;
-    /*< public >*/
-
-    GPEXRootState gpex_root;
-
-    MemoryRegion io_ioport;
-    MemoryRegion io_mmio;
-    qemu_irq irq[GPEX_NUM_IRQS];
-} GPEXHost;
-
-#endif /* HW_GPEX_H */
diff --git a/qemu/include/hw/pci-host/pam.h b/qemu/include/hw/pci-host/pam.h
deleted file mode 100644
index 6116c638f..000000000
--- a/qemu/include/hw/pci-host/pam.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef QEMU_PAM_H
-#define QEMU_PAM_H
-
-/*
- * Copyright (c) 2006 Fabrice Bellard
- * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
- *               VA Linux Systems Japan K.K.
- * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
- *
- * Split out from piix.c
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/*
- * SMRAM memory area and PAM memory area in Legacy address range for PC.
- * PAM: Programmable Attribute Map registers
- *
- * 0xa0000 - 0xbffff compatible SMRAM
- *
- * 0xc0000 - 0xc3fff Expansion area memory segments
- * 0xc4000 - 0xc7fff
- * 0xc8000 - 0xcbfff
- * 0xcc000 - 0xcffff
- * 0xd0000 - 0xd3fff
- * 0xd4000 - 0xd7fff
- * 0xd8000 - 0xdbfff
- * 0xdc000 - 0xdffff
- * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
- * 0xe4000 - 0xe7fff
- * 0xe8000 - 0xebfff
- * 0xec000 - 0xeffff
- *
- * 0xf0000 - 0xfffff System BIOS Area Memory Segments
- */
-
-#include "qemu-common.h"
-#include "exec/memory.h"
-
-#define SMRAM_C_BASE    0xa0000
-#define SMRAM_C_END     0xc0000
-#define SMRAM_C_SIZE    0x20000
-
-#define PAM_EXPAN_BASE  0xc0000
-#define PAM_EXPAN_SIZE  0x04000
-
-#define PAM_EXBIOS_BASE 0xe0000
-#define PAM_EXBIOS_SIZE 0x04000
-
-#define PAM_BIOS_BASE   0xf0000
-#define PAM_BIOS_END    0xfffff
-/* 64KB: Intel 3 series express chipset family p. 58*/
-#define PAM_BIOS_SIZE   0x10000
-
-/* PAM registers: log nibble and high nibble*/
-#define PAM_ATTR_WE     ((uint8_t)2)
-#define PAM_ATTR_RE     ((uint8_t)1)
-#define PAM_ATTR_MASK   ((uint8_t)3)
-
-/* SMRAM register */
-#define SMRAM_D_OPEN           ((uint8_t)(1 << 6))
-#define SMRAM_D_CLS            ((uint8_t)(1 << 5))
-#define SMRAM_D_LCK            ((uint8_t)(1 << 4))
-#define SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
-#define SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
-#define SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
-
-typedef struct PAMMemoryRegion {
-    MemoryRegion alias[4];  /* index = PAM value */
-    unsigned current;
-} PAMMemoryRegion;
-
-void init_pam(DeviceState *dev, MemoryRegion *ram, MemoryRegion *system,
-              MemoryRegion *pci, PAMMemoryRegion *mem, uint32_t start, uint32_t size);
-void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val);
-
-#endif /* QEMU_PAM_H */
diff --git a/qemu/include/hw/pci-host/ppce500.h b/qemu/include/hw/pci-host/ppce500.h
deleted file mode 100644
index 61f773ef3..000000000
--- a/qemu/include/hw/pci-host/ppce500.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef PPCE500_PCI_H
-#define PPCE500_PCI_H
-
-static inline int ppce500_pci_map_irq_slot(int devno, int irq_num)
-{
-    return (devno + irq_num) % 4;
-}
-
-#endif
diff --git a/qemu/include/hw/pci-host/q35.h b/qemu/include/hw/pci-host/q35.h
deleted file mode 100644
index c5c073dde..000000000
--- a/qemu/include/hw/pci-host/q35.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * q35.h
- *
- * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
- *                    VA Linux Systems Japan K.K.
- * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-
-#ifndef HW_Q35_H
-#define HW_Q35_H
-
-#include "hw/hw.h"
-#include "hw/isa/isa.h"
-#include "hw/sysbus.h"
-#include "hw/i386/pc.h"
-#include "hw/isa/apm.h"
-#include "hw/pci/pci.h"
-#include "hw/pci/pcie_host.h"
-#include "hw/acpi/acpi.h"
-#include "hw/acpi/ich9.h"
-#include "hw/pci-host/pam.h"
-#include "hw/i386/intel_iommu.h"
-
-#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
-#define Q35_HOST_DEVICE(obj) \
-     OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE)
-
-#define TYPE_MCH_PCI_DEVICE "mch"
-#define MCH_PCI_DEVICE(obj) \
-     OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
-
-typedef struct MCHPCIState {
-    /*< private >*/
-    PCIDevice parent_obj;
-    /*< public >*/
-
-    MemoryRegion *ram_memory;
-    MemoryRegion *pci_address_space;
-    MemoryRegion *system_memory;
-    MemoryRegion *address_space_io;
-    PAMMemoryRegion pam_regions[13];
-    MemoryRegion smram_region, open_high_smram;
-    MemoryRegion smram, low_smram, high_smram;
-    MemoryRegion tseg_blackhole, tseg_window;
-    PcPciInfo pci_info;
-    ram_addr_t below_4g_mem_size;
-    ram_addr_t above_4g_mem_size;
-    uint64_t pci_hole64_size;
-    uint32_t short_root_bus;
-    IntelIOMMUState *iommu;
-} MCHPCIState;
-
-typedef struct Q35PCIHost {
-    /*< private >*/
-    PCIExpressHost parent_obj;
-    /*< public >*/
-
-    MCHPCIState mch;
-} Q35PCIHost;
-
-#define Q35_MASK(bit, ms_bit, ls_bit) \
-((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
-
-/*
- * gmch part
- */
-
-/* PCI configuration */
-#define MCH_HOST_BRIDGE                        "MCH"
-
-#define MCH_HOST_BRIDGE_CONFIG_ADDR            0xcf8
-#define MCH_HOST_BRIDGE_CONFIG_DATA            0xcfc
-
-/* D0:F0 configuration space */
-#define MCH_HOST_BRIDGE_REVISION_DEFAULT       0x0
-
-#define MCH_HOST_BRIDGE_PCIEXBAR               0x60    /* 64bit register */
-#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE          8       /* 64bit register */
-#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT       0xb0000000
-#define MCH_HOST_BRIDGE_PCIEXBAR_MAX           (0x10000000) /* 256M */
-#define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK         Q35_MASK(64, 35, 28)
-#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK      ((uint64_t)(1 << 26))
-#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK       ((uint64_t)(1 << 25))
-#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK   ((uint64_t)(0x3 << 1))
-#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M   ((uint64_t)(0x0 << 1))
-#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M   ((uint64_t)(0x1 << 1))
-#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M    ((uint64_t)(0x2 << 1))
-#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD    ((uint64_t)(0x3 << 1))
-#define MCH_HOST_BRIDGE_PCIEXBAREN             ((uint64_t)1)
-
-#define MCH_HOST_BRIDGE_PAM_NB                 7
-#define MCH_HOST_BRIDGE_PAM_SIZE               7
-#define MCH_HOST_BRIDGE_PAM0                   0x90
-#define MCH_HOST_BRIDGE_PAM_BIOS_AREA          0xf0000
-#define MCH_HOST_BRIDGE_PAM_AREA_SIZE          0x10000 /* 16KB */
-#define MCH_HOST_BRIDGE_PAM1                   0x91
-#define MCH_HOST_BRIDGE_PAM_EXPAN_AREA         0xc0000
-#define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE         0x04000
-#define MCH_HOST_BRIDGE_PAM2                   0x92
-#define MCH_HOST_BRIDGE_PAM3                   0x93
-#define MCH_HOST_BRIDGE_PAM4                   0x94
-#define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA        0xe0000
-#define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE        0x04000
-#define MCH_HOST_BRIDGE_PAM5                   0x95
-#define MCH_HOST_BRIDGE_PAM6                   0x96
-#define MCH_HOST_BRIDGE_PAM_WE_HI              ((uint8_t)(0x2 << 4))
-#define MCH_HOST_BRIDGE_PAM_RE_HI              ((uint8_t)(0x1 << 4))
-#define MCH_HOST_BRIDGE_PAM_HI_MASK            ((uint8_t)(0x3 << 4))
-#define MCH_HOST_BRIDGE_PAM_WE_LO              ((uint8_t)0x2)
-#define MCH_HOST_BRIDGE_PAM_RE_LO              ((uint8_t)0x1)
-#define MCH_HOST_BRIDGE_PAM_LO_MASK            ((uint8_t)0x3)
-#define MCH_HOST_BRIDGE_PAM_WE                 ((uint8_t)0x2)
-#define MCH_HOST_BRIDGE_PAM_RE                 ((uint8_t)0x1)
-#define MCH_HOST_BRIDGE_PAM_MASK               ((uint8_t)0x3)
-
-#define MCH_HOST_BRIDGE_SMRAM                  0x9d
-#define MCH_HOST_BRIDGE_SMRAM_SIZE             2
-#define MCH_HOST_BRIDGE_SMRAM_D_OPEN           ((uint8_t)(1 << 6))
-#define MCH_HOST_BRIDGE_SMRAM_D_CLS            ((uint8_t)(1 << 5))
-#define MCH_HOST_BRIDGE_SMRAM_D_LCK            ((uint8_t)(1 << 4))
-#define MCH_HOST_BRIDGE_SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
-#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
-#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
-#define MCH_HOST_BRIDGE_SMRAM_C_BASE           0xa0000
-#define MCH_HOST_BRIDGE_SMRAM_C_END            0xc0000
-#define MCH_HOST_BRIDGE_SMRAM_C_SIZE           0x20000
-#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END  0x100000
-#define MCH_HOST_BRIDGE_SMRAM_DEFAULT           \
-    MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
-#define MCH_HOST_BRIDGE_SMRAM_WMASK             \
-    (MCH_HOST_BRIDGE_SMRAM_D_OPEN |             \
-     MCH_HOST_BRIDGE_SMRAM_D_CLS |              \
-     MCH_HOST_BRIDGE_SMRAM_D_LCK |              \
-     MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
-#define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK         \
-    MCH_HOST_BRIDGE_SMRAM_D_CLS
-
-#define MCH_HOST_BRIDGE_ESMRAMC                0x9e
-#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME       ((uint8_t)(1 << 7))
-#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR        ((uint8_t)(1 << 6))
-#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE       ((uint8_t)(1 << 5))
-#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1          ((uint8_t)(1 << 4))
-#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2          ((uint8_t)(1 << 3))
-#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK   ((uint8_t)(0x3 << 1))
-#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB    ((uint8_t)(0x0 << 1))
-#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB    ((uint8_t)(0x1 << 1))
-#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB    ((uint8_t)(0x2 << 1))
-#define MCH_HOST_BRIDGE_ESMRAMC_T_EN           ((uint8_t)1)
-#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
-    (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
-     MCH_HOST_BRIDGE_ESMRAMC_SM_L1 |    \
-     MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
-#define MCH_HOST_BRIDGE_ESMRAMC_WMASK               \
-    (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME |             \
-     MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK |         \
-     MCH_HOST_BRIDGE_ESMRAMC_T_EN)
-#define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK     0
-
-/* D1:F0 PCIE* port*/
-#define MCH_PCIE_DEV                           1
-#define MCH_PCIE_FUNC                          0
-
-uint64_t mch_mcfg_base(void);
-
-#endif /* HW_Q35_H */
diff --git a/qemu/include/hw/pci-host/spapr.h b/qemu/include/hw/pci-host/spapr.h
deleted file mode 100644
index 03ee00640..000000000
--- a/qemu/include/hw/pci-host/spapr.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * QEMU SPAPR PCI BUS definitions
- *
- * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-#if !defined(__HW_SPAPR_H__)
-#error Please include spapr.h before this file!
-#endif
-
-#if !defined(__HW_SPAPR_PCI_H__)
-#define __HW_SPAPR_PCI_H__
-
-#include "hw/pci/pci.h"
-#include "hw/pci/pci_host.h"
-#include "hw/ppc/xics.h"
-
-#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
-
-#define SPAPR_PCI_HOST_BRIDGE(obj) \
-    OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
-
-typedef struct sPAPRPHBState sPAPRPHBState;
-
-typedef struct spapr_pci_msi {
-    uint32_t first_irq;
-    uint32_t num;
-} spapr_pci_msi;
-
-typedef struct spapr_pci_msi_mig {
-    uint32_t key;
-    spapr_pci_msi value;
-} spapr_pci_msi_mig;
-
-struct sPAPRPHBState {
-    PCIHostState parent_obj;
-
-    uint32_t index;
-    uint64_t buid;
-    char *dtbusname;
-    bool dr_enabled;
-
-    MemoryRegion memspace, iospace;
-    hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
-    MemoryRegion memwindow, iowindow, msiwindow;
-
-    uint32_t dma_liobn;
-    hwaddr dma_win_addr, dma_win_size;
-    AddressSpace iommu_as;
-    MemoryRegion iommu_root;
-
-    struct spapr_pci_lsi {
-        uint32_t irq;
-    } lsi_table[PCI_NUM_PINS];
-
-    GHashTable *msi;
-    /* Temporary cache for migration purposes */
-    int32_t msi_devs_num;
-    spapr_pci_msi_mig *msi_devs;
-
-    QLIST_ENTRY(sPAPRPHBState) list;
-};
-
-#define SPAPR_PCI_MAX_INDEX          255
-
-#define SPAPR_PCI_BASE_BUID          0x800000020000000ULL
-
-#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
-
-#define SPAPR_PCI_WINDOW_BASE        0x10000000000ULL
-#define SPAPR_PCI_WINDOW_SPACING     0x1000000000ULL
-#define SPAPR_PCI_MMIO_WIN_OFF       0xA0000000
-#define SPAPR_PCI_MMIO_WIN_SIZE      (SPAPR_PCI_WINDOW_SPACING - \
-                                     SPAPR_PCI_MEM_WIN_BUS_OFFSET)
-#define SPAPR_PCI_IO_WIN_OFF         0x80000000
-#define SPAPR_PCI_IO_WIN_SIZE        0x10000
-
-#define SPAPR_PCI_MSI_WINDOW         0x40000000000ULL
-
-static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
-{
-    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
-
-    return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
-}
-
-PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
-
-int spapr_populate_pci_dt(sPAPRPHBState *phb,
-                          uint32_t xics_phandle,
-                          void *fdt);
-
-void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr);
-
-void spapr_pci_rtas_init(void);
-
-sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
-PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
-                              uint32_t config_addr);
-
-/* VFIO EEH hooks */
-#ifdef CONFIG_LINUX
-bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
-int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
-                                  unsigned int addr, int option);
-int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
-int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
-int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
-void spapr_phb_vfio_reset(DeviceState *qdev);
-#else
-static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
-{
-    return false;
-}
-static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
-                                                unsigned int addr, int option)
-{
-    return RTAS_OUT_HW_ERROR;
-}
-static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
-                                               int *state)
-{
-    return RTAS_OUT_HW_ERROR;
-}
-static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
-{
-    return RTAS_OUT_HW_ERROR;
-}
-static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
-{
-    return RTAS_OUT_HW_ERROR;
-}
-static inline void spapr_phb_vfio_reset(DeviceState *qdev)
-{
-}
-#endif
-
-#endif /* __HW_SPAPR_PCI_H__ */