diff options
| author |   RajithaY <rajithax.yerrumsetty@intel.com> | 2017-04-25 03:31:15 -0700 |
|---|---|---|
| committer | Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> | 2017-05-22 06:48:08 +0000 |
| commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
| tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/include/hw/net/mii.h | |
| parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) | |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/include/hw/net/mii.h')
| -rw-r--r-- | qemu/include/hw/net/mii.h | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/qemu/include/hw/net/mii.h b/qemu/include/hw/net/mii.h deleted file mode 100644 index 9fdd7bbe7..000000000 --- a/qemu/include/hw/net/mii.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Common network MII address and register definitions. - * - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * Allwinner EMAC register definitions from Linux kernel are: - * Copyright 2012 Stefan Roese <sr@denx.de> - * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> - * Copyright 1997 Sten Wang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef MII_H -#define MII_H - -/* PHY registers */ -#define MII_BMCR 0 -#define MII_BMSR 1 -#define MII_PHYID1 2 -#define MII_PHYID2 3 -#define MII_ANAR 4 -#define MII_ANLPAR 5 -#define MII_ANER 6 -#define MII_NSR 16 -#define MII_LBREMR 17 -#define MII_REC 18 -#define MII_SNRDR 19 -#define MII_TEST 25 - -/* PHY registers fields */ -#define MII_BMCR_RESET (1 << 15) -#define MII_BMCR_LOOPBACK (1 << 14) -#define MII_BMCR_SPEED (1 << 13) -#define MII_BMCR_AUTOEN (1 << 12) -#define MII_BMCR_FD (1 << 8) - -#define MII_BMSR_100TX_FD (1 << 14) -#define MII_BMSR_100TX_HD (1 << 13) -#define MII_BMSR_10T_FD (1 << 12) -#define MII_BMSR_10T_HD (1 << 11) -#define MII_BMSR_MFPS (1 << 6) -#define MII_BMSR_AN_COMP (1 << 5) -#define MII_BMSR_AUTONEG (1 << 3) -#define MII_BMSR_LINK_ST (1 << 2) - -#define MII_ANAR_TXFD (1 << 8) -#define MII_ANAR_TX (1 << 7) -#define MII_ANAR_10FD (1 << 6) -#define MII_ANAR_10 (1 << 5) -#define MII_ANAR_CSMACD (1 << 0) - -#define MII_ANLPAR_ACK (1 << 14) -#define MII_ANLPAR_TXFD (1 << 8) -#define MII_ANLPAR_TX (1 << 7) -#define MII_ANLPAR_10FD (1 << 6) -#define MII_ANLPAR_10 (1 << 5) -#define MII_ANLPAR_CSMACD (1 << 0) - -/* List of vendor identifiers */ -/* RealTek 8201 */ -#define RTL8201CP_PHYID1 0x0000 -#define RTL8201CP_PHYID2 0x8201 - -/* National Semiconductor DP83848 */ -#define DP83848_PHYID1 0x2000 -#define DP83848_PHYID2 0x5c90 - -#endif /* MII_H */ |