Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

9 files changed, 0 insertions, 502 deletions

diff --git a/qemu/include/hw/intc/allwinner-a10-pic.h b/qemu/include/hw/intc/allwinner-a10-pic.h
deleted file mode 100644
index 5721b2e6b..000000000
--- a/qemu/include/hw/intc/allwinner-a10-pic.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef AW_A10_PIC_H
-#define AW_A10_PIC_H
-
-#define TYPE_AW_A10_PIC  "allwinner-a10-pic"
-#define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC)
-
-#define AW_A10_PIC_VECTOR       0
-#define AW_A10_PIC_BASE_ADDR    4
-#define AW_A10_PIC_PROTECT      8
-#define AW_A10_PIC_NMI          0xc
-#define AW_A10_PIC_IRQ_PENDING  0x10
-#define AW_A10_PIC_FIQ_PENDING  0x20
-#define AW_A10_PIC_SELECT       0x30
-#define AW_A10_PIC_ENABLE       0x40
-#define AW_A10_PIC_MASK         0x50
-
-#define AW_A10_PIC_INT_NR       95
-#define AW_A10_PIC_REG_NUM      DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32)
-
-typedef struct AwA10PICState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-    /*< public >*/
-    MemoryRegion iomem;
-    qemu_irq parent_fiq;
-    qemu_irq parent_irq;
-
-    uint32_t vector;
-    uint32_t base_addr;
-    uint32_t protect;
-    uint32_t nmi;
-    uint32_t irq_pending[AW_A10_PIC_REG_NUM];
-    uint32_t fiq_pending[AW_A10_PIC_REG_NUM];
-    uint32_t select[AW_A10_PIC_REG_NUM];
-    uint32_t enable[AW_A10_PIC_REG_NUM];
-    uint32_t mask[AW_A10_PIC_REG_NUM];
-    /*priority setting here*/
-} AwA10PICState;
-
-#endif
diff --git a/qemu/include/hw/intc/arm_gic.h b/qemu/include/hw/intc/arm_gic.h
deleted file mode 100644
index 0971e3771..000000000
--- a/qemu/include/hw/intc/arm_gic.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * ARM GIC support
- *
- * Copyright (c) 2012 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_GIC_H
-#define HW_ARM_GIC_H
-
-#include "arm_gic_common.h"
-
-#define TYPE_ARM_GIC "arm_gic"
-#define ARM_GIC(obj) \
-     OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
-#define ARM_GIC_CLASS(klass) \
-     OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
-#define ARM_GIC_GET_CLASS(obj) \
-     OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
-
-typedef struct ARMGICClass {
-    /*< private >*/
-    ARMGICCommonClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-} ARMGICClass;
-
-#endif
diff --git a/qemu/include/hw/intc/arm_gic_common.h b/qemu/include/hw/intc/arm_gic_common.h
deleted file mode 100644
index f4c349a2e..000000000
--- a/qemu/include/hw/intc/arm_gic_common.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * ARM GIC support
- *
- * Copyright (c) 2012 Linaro Limited
- * Written by Peter Maydell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_GIC_COMMON_H
-#define HW_ARM_GIC_COMMON_H
-
-#include "hw/sysbus.h"
-
-/* Maximum number of possible interrupts, determined by the GIC architecture */
-#define GIC_MAXIRQ 1020
-/* First 32 are private to each CPU (SGIs and PPIs). */
-#define GIC_INTERNAL 32
-#define GIC_NR_SGIS 16
-/* Maximum number of possible CPU interfaces, determined by GIC architecture */
-#define GIC_NCPU 8
-
-#define MAX_NR_GROUP_PRIO 128
-#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
-
-#define GIC_MIN_BPR 0
-#define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
-
-typedef struct gic_irq_state {
-    /* The enable bits are only banked for per-cpu interrupts.  */
-    uint8_t enabled;
-    uint8_t pending;
-    uint8_t active;
-    uint8_t level;
-    bool model; /* 0 = N:N, 1 = 1:N */
-    bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
-    uint8_t group;
-} gic_irq_state;
-
-typedef struct GICState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-    /*< public >*/
-
-    qemu_irq parent_irq[GIC_NCPU];
-    qemu_irq parent_fiq[GIC_NCPU];
-    /* GICD_CTLR; for a GIC with the security extensions the NS banked version
-     * of this register is just an alias of bit 1 of the S banked version.
-     */
-    uint32_t ctlr;
-    /* GICC_CTLR; again, the NS banked version is just aliases of bits of
-     * the S banked register, so our state only needs to store the S version.
-     */
-    uint32_t cpu_ctlr[GIC_NCPU];
-
-    gic_irq_state irq_state[GIC_MAXIRQ];
-    uint8_t irq_target[GIC_MAXIRQ];
-    uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
-    uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
-    /* For each SGI on the target CPU, we store 8 bits
-     * indicating which source CPUs have made this SGI
-     * pending on the target CPU. These correspond to
-     * the bytes in the GIC_SPENDSGIR* registers as
-     * read by the target CPU.
-     */
-    uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
-
-    uint16_t priority_mask[GIC_NCPU];
-    uint16_t running_priority[GIC_NCPU];
-    uint16_t current_pending[GIC_NCPU];
-
-    /* If we present the GICv2 without security extensions to a guest,
-     * the guest can configure the GICC_CTLR to configure group 1 binary point
-     * in the abpr.
-     * For a GIC with Security Extensions we use use bpr for the
-     * secure copy and abpr as storage for the non-secure copy of the register.
-     */
-    uint8_t  bpr[GIC_NCPU];
-    uint8_t  abpr[GIC_NCPU];
-
-    /* The APR is implementation defined, so we choose a layout identical to
-     * the KVM ABI layout for QEMU's implementation of the gic:
-     * If an interrupt for preemption level X is active, then
-     *   APRn[X mod 32] == 0b1,  where n = X / 32
-     * otherwise the bit is clear.
-     */
-    uint32_t apr[GIC_NR_APRS][GIC_NCPU];
-    uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
-
-    uint32_t num_cpu;
-
-    MemoryRegion iomem; /* Distributor */
-    /* This is just so we can have an opaque pointer which identifies
-     * both this GIC and which CPU interface we should be accessing.
-     */
-    struct GICState *backref[GIC_NCPU];
-    MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
-    uint32_t num_irq;
-    uint32_t revision;
-    bool security_extn;
-    bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
-    int dev_fd; /* kvm device fd if backed by kvm vgic support */
-    Error *migration_blocker;
-} GICState;
-
-#define TYPE_ARM_GIC_COMMON "arm_gic_common"
-#define ARM_GIC_COMMON(obj) \
-     OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
-#define ARM_GIC_COMMON_CLASS(klass) \
-     OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
-#define ARM_GIC_COMMON_GET_CLASS(obj) \
-     OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
-
-typedef struct ARMGICCommonClass {
-    /*< private >*/
-    SysBusDeviceClass parent_class;
-    /*< public >*/
-
-    void (*pre_save)(GICState *s);
-    void (*post_load)(GICState *s);
-} ARMGICCommonClass;
-
-void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
-                            const MemoryRegionOps *ops);
-
-#endif
diff --git a/qemu/include/hw/intc/arm_gicv3_common.h b/qemu/include/hw/intc/arm_gicv3_common.h
deleted file mode 100644
index c2fd8da4e..000000000
--- a/qemu/include/hw/intc/arm_gicv3_common.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * ARM GIC support
- *
- * Copyright (c) 2012 Linaro Limited
- * Copyright (c) 2015 Huawei.
- * Written by Peter Maydell
- * Extended to 64 cores by Shlomo Pongratz
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_ARM_GICV3_COMMON_H
-#define HW_ARM_GICV3_COMMON_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gic_common.h"
-
-typedef struct GICv3State {
-    /*< private >*/
-    SysBusDevice parent_obj;
-    /*< public >*/
-
-    qemu_irq *parent_irq;
-    qemu_irq *parent_fiq;
-
-    MemoryRegion iomem_dist; /* Distributor */
-    MemoryRegion iomem_redist; /* Redistributors */
-
-    uint32_t num_cpu;
-    uint32_t num_irq;
-    uint32_t revision;
-    bool security_extn;
-
-    int dev_fd; /* kvm device fd if backed by kvm vgic support */
-} GICv3State;
-
-#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
-#define ARM_GICV3_COMMON(obj) \
-     OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
-#define ARM_GICV3_COMMON_CLASS(klass) \
-     OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON)
-#define ARM_GICV3_COMMON_GET_CLASS(obj) \
-     OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
-
-typedef struct ARMGICv3CommonClass {
-    /*< private >*/
-    SysBusDeviceClass parent_class;
-    /*< public >*/
-
-    void (*pre_save)(GICv3State *s);
-    void (*post_load)(GICv3State *s);
-} ARMGICv3CommonClass;
-
-void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
-                              const MemoryRegionOps *ops);
-
-#endif
diff --git a/qemu/include/hw/intc/aspeed_vic.h b/qemu/include/hw/intc/aspeed_vic.h
deleted file mode 100644
index 107ff17c3..000000000
--- a/qemu/include/hw/intc/aspeed_vic.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * ASPEED Interrupt Controller (New)
- *
- * Andrew Jeffery <andrew@aj.id.au>
- *
- * Copyright 2016 IBM Corp.
- *
- * This code is licensed under the GPL version 2 or later.  See
- * the COPYING file in the top-level directory.
- *
- * Need to add SVIC and CVIC support
- */
-#ifndef ASPEED_VIC_H
-#define ASPEED_VIC_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_ASPEED_VIC "aspeed.vic"
-#define ASPEED_VIC(obj) OBJECT_CHECK(AspeedVICState, (obj), TYPE_ASPEED_VIC)
-
-#define ASPEED_VIC_NR_IRQS 51
-
-typedef struct AspeedVICState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion iomem;
-    qemu_irq irq;
-    qemu_irq fiq;
-
-    uint64_t level;
-    uint64_t raw;
-    uint64_t select;
-    uint64_t enable;
-    uint64_t trigger;
-
-    /* 0=edge, 1=level */
-    uint64_t sense;
-
-    /* 0=single-edge, 1=dual-edge */
-    uint64_t dual_edge;
-
-    /* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
-    uint64_t event;
-} AspeedVICState;
-
-#endif /* ASPEED_VIC_H */
diff --git a/qemu/include/hw/intc/bcm2835_ic.h b/qemu/include/hw/intc/bcm2835_ic.h
deleted file mode 100644
index fb75fa006..000000000
--- a/qemu/include/hw/intc/bcm2835_ic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- * This code is licensed under the GNU GPLv2 and later.
- */
-
-#ifndef BCM2835_IC_H
-#define BCM2835_IC_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_BCM2835_IC "bcm2835-ic"
-#define BCM2835_IC(obj) OBJECT_CHECK(BCM2835ICState, (obj), TYPE_BCM2835_IC)
-
-#define BCM2835_IC_GPU_IRQ "gpu-irq"
-#define BCM2835_IC_ARM_IRQ "arm-irq"
-
-typedef struct BCM2835ICState {
-    /*< private >*/
-    SysBusDevice busdev;
-    /*< public >*/
-
-    MemoryRegion iomem;
-    qemu_irq irq;
-    qemu_irq fiq;
-
-    /* 64 GPU IRQs + 8 ARM IRQs = 72 total (GPU first) */
-    uint64_t gpu_irq_level, gpu_irq_enable;
-    uint8_t arm_irq_level, arm_irq_enable;
-    bool fiq_enable;
-    uint8_t fiq_select;
-} BCM2835ICState;
-
-#endif
diff --git a/qemu/include/hw/intc/bcm2836_control.h b/qemu/include/hw/intc/bcm2836_control.h
deleted file mode 100644
index 613f3c418..000000000
--- a/qemu/include/hw/intc/bcm2836_control.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Raspberry Pi emulation (c) 2012 Gregory Estrade
- * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
- *
- * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
- * Written by Andrew Baumann
- *
- * This code is licensed under the GNU GPLv2 and later.
- */
-
-#ifndef BCM2836_CONTROL_H
-#define BCM2836_CONTROL_H
-
-#include "hw/sysbus.h"
-
-/* 4 mailboxes per core, for 16 total */
-#define BCM2836_NCORES 4
-#define BCM2836_MBPERCORE 4
-
-#define TYPE_BCM2836_CONTROL "bcm2836-control"
-#define BCM2836_CONTROL(obj) \
-    OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
-
-typedef struct BCM2836ControlState {
-    /*< private >*/
-    SysBusDevice busdev;
-    /*< public >*/
-    MemoryRegion iomem;
-
-    /* mailbox state */
-    uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
-
-    /* interrupt routing/control registers */
-    uint8_t route_gpu_irq, route_gpu_fiq;
-    uint32_t timercontrol[BCM2836_NCORES];
-    uint32_t mailboxcontrol[BCM2836_NCORES];
-
-    /* interrupt status regs (derived from input pins; not visible to user) */
-    bool gpu_irq, gpu_fiq;
-    uint8_t timerirqs[BCM2836_NCORES];
-
-    /* interrupt source registers, post-routing (also input-derived; visible) */
-    uint32_t irqsrc[BCM2836_NCORES];
-    uint32_t fiqsrc[BCM2836_NCORES];
-
-    /* outputs to CPU cores */
-    qemu_irq irq[BCM2836_NCORES];
-    qemu_irq fiq[BCM2836_NCORES];
-} BCM2836ControlState;
-
-#endif
diff --git a/qemu/include/hw/intc/imx_avic.h b/qemu/include/hw/intc/imx_avic.h
deleted file mode 100644
index 1b8076901..000000000
--- a/qemu/include/hw/intc/imx_avic.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * i.MX31 Vectored Interrupt Controller
- *
- * Note this is NOT the PL192 provided by ARM, but
- * a custom implementation by Freescale.
- *
- * Copyright (c) 2008 OKL
- * Copyright (c) 2011 NICTA Pty Ltd
- * Originally written by Hans Jiang
- * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
- *
- * This code is licensed under the GPL version 2 or later.  See
- * the COPYING file in the top-level directory.
- *
- * TODO: implement vectors.
- */
-#ifndef IMX_AVIC_H
-#define IMX_AVIC_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_IMX_AVIC "imx.avic"
-#define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
-
-#define IMX_AVIC_NUM_IRQS 64
-
-/* Interrupt Control Bits */
-#define ABFLAG (1<<25)
-#define ABFEN  (1<<24)
-#define NIDIS  (1<<22) /* Normal Interrupt disable */
-#define FIDIS  (1<<21) /* Fast interrupt disable */
-#define NIAD   (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
-#define FIAD   (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
-#define NM     (1<<18) /* Normal interrupt mode */
-
-#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
-#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
-
-typedef struct IMXAVICState{
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion iomem;
-    uint64_t pending;
-    uint64_t enabled;
-    uint64_t is_fiq;
-    uint32_t intcntl;
-    uint32_t intmask;
-    qemu_irq irq;
-    qemu_irq fiq;
-    uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
-} IMXAVICState;
-
-#endif /* IMX_AVIC_H */
diff --git a/qemu/include/hw/intc/realview_gic.h b/qemu/include/hw/intc/realview_gic.h
deleted file mode 100644
index 1783ea11b..000000000
--- a/qemu/include/hw/intc/realview_gic.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * ARM RealView Emulation Baseboard Interrupt Controller
- *
- * Copyright (c) 2006-2007 CodeSourcery.
- * Written by Paul Brook
- *
- * This code is licensed under the GPL.
- */
-
-#ifndef HW_INTC_REALVIEW_GIC_H
-#define HW_INTC_REALVIEW_GIC_H
-
-#include "hw/sysbus.h"
-#include "hw/intc/arm_gic.h"
-
-#define TYPE_REALVIEW_GIC "realview_gic"
-#define REALVIEW_GIC(obj) \
-    OBJECT_CHECK(RealViewGICState, (obj), TYPE_REALVIEW_GIC)
-
-typedef struct RealViewGICState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion container;
-
-    GICState gic;
-} RealViewGICState;
-
-#endif