diff options
author | 2017-04-25 03:31:15 -0700 | |
---|---|---|
committer | 2017-05-22 06:48:08 +0000 | |
commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/include/hw/arm | |
parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/include/hw/arm')
-rw-r--r-- | qemu/include/hw/arm/allwinner-a10.h | 42 | ||||
-rw-r--r-- | qemu/include/hw/arm/arm.h | 143 | ||||
-rw-r--r-- | qemu/include/hw/arm/ast2400.h | 35 | ||||
-rw-r--r-- | qemu/include/hw/arm/bcm2835_peripherals.h | 48 | ||||
-rw-r--r-- | qemu/include/hw/arm/bcm2836.h | 35 | ||||
-rw-r--r-- | qemu/include/hw/arm/digic.h | 43 | ||||
-rw-r--r-- | qemu/include/hw/arm/exynos4210.h | 137 | ||||
-rw-r--r-- | qemu/include/hw/arm/fdt.h | 34 | ||||
-rw-r--r-- | qemu/include/hw/arm/fsl-imx25.h | 249 | ||||
-rw-r--r-- | qemu/include/hw/arm/fsl-imx31.h | 122 | ||||
-rw-r--r-- | qemu/include/hw/arm/linux-boot-if.h | 43 | ||||
-rw-r--r-- | qemu/include/hw/arm/omap.h | 1015 | ||||
-rw-r--r-- | qemu/include/hw/arm/primecell.h | 12 | ||||
-rw-r--r-- | qemu/include/hw/arm/pxa.h | 191 | ||||
-rw-r--r-- | qemu/include/hw/arm/raspi_platform.h | 128 | ||||
-rw-r--r-- | qemu/include/hw/arm/sharpsl.h | 17 | ||||
-rw-r--r-- | qemu/include/hw/arm/soc_dma.h | 116 | ||||
-rw-r--r-- | qemu/include/hw/arm/stm32f205_soc.h | 57 | ||||
-rw-r--r-- | qemu/include/hw/arm/sysbus-fdt.h | 60 | ||||
-rw-r--r-- | qemu/include/hw/arm/virt-acpi-build.h | 45 | ||||
-rw-r--r-- | qemu/include/hw/arm/virt.h | 73 | ||||
-rw-r--r-- | qemu/include/hw/arm/xlnx-zynqmp.h | 90 |
22 files changed, 0 insertions, 2735 deletions
diff --git a/qemu/include/hw/arm/allwinner-a10.h b/qemu/include/hw/arm/allwinner-a10.h deleted file mode 100644 index 6b32a99e2..000000000 --- a/qemu/include/hw/arm/allwinner-a10.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef ALLWINNER_H_ - -#include "qemu-common.h" -#include "qemu/error-report.h" -#include "hw/char/serial.h" -#include "hw/arm/arm.h" -#include "hw/timer/allwinner-a10-pit.h" -#include "hw/intc/allwinner-a10-pic.h" -#include "hw/net/allwinner_emac.h" -#include "hw/ide/pci.h" -#include "hw/ide/ahci.h" - -#include "sysemu/sysemu.h" -#include "exec/address-spaces.h" - - -#define AW_A10_PIC_REG_BASE 0x01c20400 -#define AW_A10_PIT_REG_BASE 0x01c20c00 -#define AW_A10_UART0_REG_BASE 0x01c28000 -#define AW_A10_EMAC_BASE 0x01c0b000 -#define AW_A10_SATA_BASE 0x01c18000 - -#define AW_A10_SDRAM_BASE 0x40000000 - -#define TYPE_AW_A10 "allwinner-a10" -#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10) - -typedef struct AwA10State { - /*< private >*/ - DeviceState parent_obj; - /*< public >*/ - - ARMCPU cpu; - qemu_irq irq[AW_A10_PIC_INT_NR]; - AwA10PITState timer; - AwA10PICState intc; - AwEmacState emac; - AllwinnerAHCIState sata; -} AwA10State; - -#define ALLWINNER_H_ -#endif diff --git a/qemu/include/hw/arm/arm.h b/qemu/include/hw/arm/arm.h deleted file mode 100644 index b2517f9a4..000000000 --- a/qemu/include/hw/arm/arm.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Misc ARM declarations - * - * Copyright (c) 2006 CodeSourcery. - * Written by Paul Brook - * - * This code is licensed under the LGPL. - * - */ - -#ifndef ARM_MISC_H -#define ARM_MISC_H 1 - -#include "exec/memory.h" -#include "hw/irq.h" -#include "qemu/notify.h" -#include "cpu.h" - -typedef enum { - ARM_ENDIANNESS_UNKNOWN = 0, - ARM_ENDIANNESS_LE, - ARM_ENDIANNESS_BE8, - ARM_ENDIANNESS_BE32, -} arm_endianness; - -/* armv7m.c */ -DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, - const char *kernel_filename, const char *cpu_model); - -/* - * struct used as a parameter of the arm_load_kernel machine init - * done notifier - */ -typedef struct { - Notifier notifier; /* actual notifier */ - ARMCPU *cpu; /* handle to the first cpu object */ -} ArmLoadKernelNotifier; - -/* arm_boot.c */ -struct arm_boot_info { - uint64_t ram_size; - const char *kernel_filename; - const char *kernel_cmdline; - const char *initrd_filename; - const char *dtb_filename; - hwaddr loader_start; - /* multicore boards that use the default secondary core boot functions - * need to put the address of the secondary boot code, the boot reg, - * and the GIC address in the next 3 values, respectively. boards that - * have their own boot functions can use these values as they want. - */ - hwaddr smp_loader_start; - hwaddr smp_bootreg_addr; - hwaddr gic_cpu_if_addr; - int nb_cpus; - int board_id; - /* ARM machines that support the ARM Security Extensions use this field to - * control whether Linux is booted as secure(true) or non-secure(false). - */ - bool secure_boot; - int (*atag_board)(const struct arm_boot_info *info, void *p); - /* multicore boards that use the default secondary core boot functions - * can ignore these two function calls. If the default functions won't - * work, then write_secondary_boot() should write a suitable blob of - * code mimicking the secondary CPU startup process used by the board's - * boot loader/boot ROM code, and secondary_cpu_reset_hook() should - * perform any necessary CPU reset handling and set the PC for the - * secondary CPUs to point at this boot blob. - */ - void (*write_secondary_boot)(ARMCPU *cpu, - const struct arm_boot_info *info); - void (*secondary_cpu_reset_hook)(ARMCPU *cpu, - const struct arm_boot_info *info); - /* if a board is able to create a dtb without a dtb file then it - * sets get_dtb. This will only be used if no dtb file is provided - * by the user. On success, sets *size to the length of the created - * dtb, and returns a pointer to it. (The caller must free this memory - * with g_free() when it has finished with it.) On failure, returns NULL. - */ - void *(*get_dtb)(const struct arm_boot_info *info, int *size); - /* if a board needs to be able to modify a device tree provided by - * the user it should implement this hook. - */ - void (*modify_dtb)(const struct arm_boot_info *info, void *fdt); - /* machine init done notifier executing arm_load_dtb */ - ArmLoadKernelNotifier load_kernel_notifier; - /* Used internally by arm_boot.c */ - int is_linux; - hwaddr initrd_start; - hwaddr initrd_size; - hwaddr entry; - - /* Boot firmware has been loaded, typically at address 0, with -bios or - * -pflash. It also implies that fw_cfg_find() will succeed. - */ - bool firmware_loaded; - - /* Address at which board specific loader/setup code exists. If enabled, - * this code-blob will run before anything else. It must return to the - * caller via the link register. There is no stack set up. Enabled by - * defining write_board_setup, which is responsible for loading the blob - * to the specified address. - */ - hwaddr board_setup_addr; - void (*write_board_setup)(ARMCPU *cpu, - const struct arm_boot_info *info); - - /* If set, the board specific loader/setup blob will be run from secure - * mode, regardless of secure_boot. The blob becomes responsible for - * changing to non-secure state if implementing a non-secure boot - */ - bool secure_board_setup; - - arm_endianness endianness; -}; - -/** - * arm_load_kernel - Loads memory with everything needed to boot - * - * @cpu: handle to the first CPU object - * @info: handle to the boot info struct - * Registers a machine init done notifier that copies to memory - * everything needed to boot, depending on machine and user options: - * kernel image, boot loaders, initrd, dtb. Also registers the CPU - * reset handler. - * - * In case the machine file supports the platform bus device and its - * dynamically instantiable sysbus devices, this function must be called - * before sysbus-fdt arm_register_platform_bus_fdt_creator. Indeed the - * machine init done notifiers are called in registration reverse order. - */ -void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info); - -/* Write a secure board setup routine with a dummy handler for SMCs */ -void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, - const struct arm_boot_info *info, - hwaddr mvbar_addr); - -/* Multiplication factor to convert from system clock ticks to qemu timer - ticks. */ -extern int system_clock_scale; - -#endif /* !ARM_MISC_H */ diff --git a/qemu/include/hw/arm/ast2400.h b/qemu/include/hw/arm/ast2400.h deleted file mode 100644 index f16a1ed25..000000000 --- a/qemu/include/hw/arm/ast2400.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * ASPEED AST2400 SoC - * - * Andrew Jeffery <andrew@aj.id.au> - * - * Copyright 2016 IBM Corp. - * - * This code is licensed under the GPL version 2 or later. See - * the COPYING file in the top-level directory. - */ - -#ifndef AST2400_H -#define AST2400_H - -#include "hw/arm/arm.h" -#include "hw/intc/aspeed_vic.h" -#include "hw/timer/aspeed_timer.h" - -typedef struct AST2400State { - /*< private >*/ - DeviceState parent; - - /*< public >*/ - ARMCPU *cpu; - MemoryRegion iomem; - AspeedVICState vic; - AspeedTimerCtrlState timerctrl; -} AST2400State; - -#define TYPE_AST2400 "ast2400" -#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400) - -#define AST2400_SDRAM_BASE 0x40000000 - -#endif /* AST2400_H */ diff --git a/qemu/include/hw/arm/bcm2835_peripherals.h b/qemu/include/hw/arm/bcm2835_peripherals.h deleted file mode 100644 index e12ae3721..000000000 --- a/qemu/include/hw/arm/bcm2835_peripherals.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2835_PERIPHERALS_H -#define BCM2835_PERIPHERALS_H - -#include "qemu-common.h" -#include "exec/address-spaces.h" -#include "hw/sysbus.h" -#include "hw/char/bcm2835_aux.h" -#include "hw/display/bcm2835_fb.h" -#include "hw/dma/bcm2835_dma.h" -#include "hw/intc/bcm2835_ic.h" -#include "hw/misc/bcm2835_property.h" -#include "hw/misc/bcm2835_mbox.h" -#include "hw/sd/sdhci.h" - -#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" -#define BCM2835_PERIPHERALS(obj) \ - OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS) - -typedef struct BCM2835PeripheralState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr; - MemoryRegion ram_alias[4]; - qemu_irq irq, fiq; - - SysBusDevice *uart0; - BCM2835AuxState aux; - BCM2835FBState fb; - BCM2835DMAState dma; - BCM2835ICState ic; - BCM2835PropertyState property; - BCM2835MboxState mboxes; - SDHCIState sdhci; -} BCM2835PeripheralState; - -#endif /* BCM2835_PERIPHERALS_H */ diff --git a/qemu/include/hw/arm/bcm2836.h b/qemu/include/hw/arm/bcm2836.h deleted file mode 100644 index 76de1996a..000000000 --- a/qemu/include/hw/arm/bcm2836.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Raspberry Pi emulation (c) 2012 Gregory Estrade - * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous - * - * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft - * Written by Andrew Baumann - * - * This code is licensed under the GNU GPLv2 and later. - */ - -#ifndef BCM2836_H -#define BCM2836_H - -#include "hw/arm/arm.h" -#include "hw/arm/bcm2835_peripherals.h" -#include "hw/intc/bcm2836_control.h" - -#define TYPE_BCM2836 "bcm2836" -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) - -#define BCM2836_NCPUS 4 - -typedef struct BCM2836State { - /*< private >*/ - DeviceState parent_obj; - /*< public >*/ - - uint32_t enabled_cpus; - - ARMCPU cpus[BCM2836_NCPUS]; - BCM2836ControlState control; - BCM2835PeripheralState peripherals; -} BCM2836State; - -#endif /* BCM2836_H */ diff --git a/qemu/include/hw/arm/digic.h b/qemu/include/hw/arm/digic.h deleted file mode 100644 index a739d6ae6..000000000 --- a/qemu/include/hw/arm/digic.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Misc Canon DIGIC declarations. - * - * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef HW_ARM_DIGIC_H -#define HW_ARM_DIGIC_H - -#include "cpu.h" - -#include "hw/timer/digic-timer.h" -#include "hw/char/digic-uart.h" - -#define TYPE_DIGIC "digic" - -#define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC) - -#define DIGIC4_NB_TIMERS 3 - -typedef struct DigicState { - /*< private >*/ - DeviceState parent_obj; - /*< public >*/ - - ARMCPU cpu; - - DigicTimerState timer[DIGIC4_NB_TIMERS]; - DigicUartState uart; -} DigicState; - -#endif /* HW_ARM_DIGIC_H */ diff --git a/qemu/include/hw/arm/exynos4210.h b/qemu/include/hw/arm/exynos4210.h deleted file mode 100644 index 5c1820f88..000000000 --- a/qemu/include/hw/arm/exynos4210.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Samsung exynos4210 SoC emulation - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. - * Maksim Kozlov <m.kozlov@samsung.com> - * Evgeny Voevodin <e.voevodin@samsung.com> - * Igor Mitsyanko <i.mitsyanko@samsung.com> - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - * - */ - - -#ifndef EXYNOS4210_H_ -#define EXYNOS4210_H_ - -#include "qemu-common.h" -#include "exec/memory.h" - -#define EXYNOS4210_NCPUS 2 - -#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 -#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 -#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ - -#define EXYNOS4210_IROM_BASE_ADDR 0x00000000 -#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ -#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 -#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ - -#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 -#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ - -/* Secondary CPU startup code is in IROM memory */ -#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR -#define EXYNOS4210_SMP_BOOT_SIZE 0x1000 -#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR -/* Secondary CPU polling address to get loader start from */ -#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 - -#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 -#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000 - -/* - * exynos4210 IRQ subsystem stub definitions. - */ -#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */ - -#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64 -#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16 -#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \ - (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8) -#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ - (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) - -#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) -#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) -#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ - ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) - -/* IRQs number for external and internal GIC */ -#define EXYNOS4210_EXT_GIC_NIRQ (160-32) -#define EXYNOS4210_INT_GIC_NIRQ 64 - -#define EXYNOS4210_I2C_NUMBER 9 - -typedef struct Exynos4210Irq { - qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; - qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; - qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; - qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; - qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; -} Exynos4210Irq; - -typedef struct Exynos4210State { - ARMCPU *cpu[EXYNOS4210_NCPUS]; - Exynos4210Irq irqs; - qemu_irq *irq_table; - - MemoryRegion chipid_mem; - MemoryRegion iram_mem; - MemoryRegion irom_mem; - MemoryRegion irom_alias_mem; - MemoryRegion dram0_mem; - MemoryRegion dram1_mem; - MemoryRegion boot_secondary; - MemoryRegion bootreg_mem; - I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; -} Exynos4210State; - -void exynos4210_write_secondary(ARMCPU *cpu, - const struct arm_boot_info *info); - -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, - unsigned long ram_size); - -/* Initialize exynos4210 IRQ subsystem stub */ -qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); - -/* Initialize board IRQs. - * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ -void exynos4210_init_board_irqs(Exynos4210Irq *s); - -/* Get IRQ number from exynos4210 IRQ subsystem stub. - * To identify IRQ source use internal combiner group and bit number - * grp - group number - * bit - bit number inside group */ -uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); - -/* - * Get Combiner input GPIO into irqs structure - */ -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, - int ext); - -/* - * exynos4210 UART - */ -DeviceState *exynos4210_uart_create(hwaddr addr, - int fifo_size, - int channel, - CharDriverState *chr, - qemu_irq irq); - -#endif /* EXYNOS4210_H_ */ diff --git a/qemu/include/hw/arm/fdt.h b/qemu/include/hw/arm/fdt.h deleted file mode 100644 index c3d501501..000000000 --- a/qemu/include/hw/arm/fdt.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * - * Copyright (c) 2015 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - * - * Define macros useful when building ARM device tree nodes - */ - -#ifndef QEMU_ARM_FDT_H -#define QEMU_ARM_FDT_H - -#define GIC_FDT_IRQ_TYPE_SPI 0 -#define GIC_FDT_IRQ_TYPE_PPI 1 - -#define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 -#define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 -#define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 -#define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 - -#define GIC_FDT_IRQ_PPI_CPU_START 8 -#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 - -#endif diff --git a/qemu/include/hw/arm/fsl-imx25.h b/qemu/include/hw/arm/fsl-imx25.h deleted file mode 100644 index d0e8e9d95..000000000 --- a/qemu/include/hw/arm/fsl-imx25.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Freescale i.MX25 SoC emulation - * - * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#ifndef FSL_IMX25_H -#define FSL_IMX25_H - -#include "hw/arm/arm.h" -#include "hw/intc/imx_avic.h" -#include "hw/misc/imx25_ccm.h" -#include "hw/char/imx_serial.h" -#include "hw/timer/imx_gpt.h" -#include "hw/timer/imx_epit.h" -#include "hw/net/imx_fec.h" -#include "hw/i2c/imx_i2c.h" -#include "hw/gpio/imx_gpio.h" -#include "exec/memory.h" - -#define TYPE_FSL_IMX25 "fsl,imx25" -#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25) - -#define FSL_IMX25_NUM_UARTS 5 -#define FSL_IMX25_NUM_GPTS 4 -#define FSL_IMX25_NUM_EPITS 2 -#define FSL_IMX25_NUM_I2CS 3 -#define FSL_IMX25_NUM_GPIOS 4 - -typedef struct FslIMX25State { - /*< private >*/ - DeviceState parent_obj; - - /*< public >*/ - ARMCPU cpu; - IMXAVICState avic; - IMX25CCMState ccm; - IMXSerialState uart[FSL_IMX25_NUM_UARTS]; - IMXGPTState gpt[FSL_IMX25_NUM_GPTS]; - IMXEPITState epit[FSL_IMX25_NUM_EPITS]; - IMXFECState fec; - IMXI2CState i2c[FSL_IMX25_NUM_I2CS]; - IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; - MemoryRegion rom[2]; - MemoryRegion iram; - MemoryRegion iram_alias; -} FslIMX25State; - -/** - * i.MX25 memory map - **************************************************************** - * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes) - * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved - * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes) - * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved - * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved - * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved - * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved - * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved - * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers - * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX - * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL - * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers - * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory - * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers - * 0x43F1_8000 0x43F7_FFFF 416 Kbytes Reserved - * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1 - * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3 - * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1 - * 0x43F8_C000 0x43F8_FFFF 16 Kbytes CAN-2 - * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1 - * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2 - * 0x43F9_8000 0x43F9_BFFF 16 Kbytes I2C-2 - * 0x43F9_C000 0x43F9_FFFF 16 Kbytes 1-Wire - * 0x43FA_0000 0x43FA_3FFF 16 Kbytes ATA (CPU side) - * 0x43FA_4000 0x43FA_7FFF 16 Kbytes CSPI-1 - * 0x43FA_8000 0x43FA_BFFF 16 Kbytes KPP - * 0x43FA_C000 0x43FA_FFFF 16 Kbytes IOMUXC - * 0x43FB_0000 0x43FB_3FFF 16 Kbytes AUDMUX - * 0x43FB_4000 0x43FB_7FFF 16 Kbytes Reserved - * 0x43FB_8000 0x43FB_BFFF 16 Kbytes ECT (IP BUS A) - * 0x43FB_C000 0x43FB_FFFF 16 Kbytes ECT (IP BUS B) - * 0x43FC_0000 0x43FF_FFFF 256 Kbytes Reserved AIPS A off-platform slots - * 0x4400_0000 0x4FFF_FFFF 192 Mbytes Reserved - * 0x5000_0000 0x5000_3FFF 16 Kbytes SPBA base address - * 0x5000_4000 0x5000_7FFF 16 Kbytes CSPI-3 - * 0x5000_8000 0x5000_BFFF 16 Kbytes UART-4 - * 0x5000_C000 0x5000_FFFF 16 Kbytes UART-3 - * 0x5001_0000 0x5001_3FFF 16 Kbytes CSPI-2 - * 0x5001_4000 0x5001_7FFF 16 Kbytes SSI-2 - * 0x5001_C000 0x5001_FFFF 16 Kbytes Reserved - * 0x5002_0000 0x5002_3FFF 16 Kbytes ATA - * 0x5002_4000 0x5002_7FFF 16 Kbytes SIM-1 - * 0x5002_8000 0x5002_BFFF 16 Kbytes SIM-2 - * 0x5002_C000 0x5002_FFFF 16 Kbytes UART-5 - * 0x5003_0000 0x5003_3FFF 16 Kbytes TSC - * 0x5003_4000 0x5003_7FFF 16 Kbytes SSI-1 - * 0x5003_8000 0x5003_BFFF 16 Kbytes FEC - * 0x5003_C000 0x5003_FFFF 16 Kbytes SPBA registers - * 0x5004_0000 0x51FF_FFFF 32 Mbytes (minus 256 Kbytes) - * 0x5200_0000 0x53EF_FFFF 31 Mbytes Reserved - * 0x53F0_0000 0x53F0_3FFF 16 Kbytes AIPS B control registers - * 0x53F0_4000 0x53F7_FFFF 496 Kbytes Reserved - * 0x53F8_0000 0x53F8_3FFF 16 Kbytes CCM - * 0x53F8_4000 0x53F8_7FFF 16 Kbytes GPT-4 - * 0x53F8_8000 0x53F8_BFFF 16 Kbytes GPT-3 - * 0x53F8_C000 0x53F8_FFFF 16 Kbytes GPT-2 - * 0x53F9_0000 0x53F9_3FFF 16 Kbytes GPT-1 - * 0x53F9_4000 0x53F9_7FFF 16 Kbytes EPIT-1 - * 0x53F9_8000 0x53F9_BFFF 16 Kbytes EPIT-2 - * 0x53F9_C000 0x53F9_FFFF 16 Kbytes GPIO-4 - * 0x53FA_0000 0x53FA_3FFF 16 Kbytes PWM-2 - * 0x53FA_4000 0x53FA_7FFF 16 Kbytes GPIO-3 - * 0x53FA_8000 0x53FA_BFFF 16 Kbytes PWM-3 - * 0x53FA_C000 0x53FA_FFFF 16 Kbytes SCC - * 0x53FB_0000 0x53FB_3FFF 16 Kbytes RNGB - * 0x53FB_4000 0x53FB_7FFF 16 Kbytes eSDHC-1 - * 0x53FB_8000 0x53FB_BFFF 16 Kbytes eSDHC-2 - * 0x53FB_C000 0x53FB_FFFF 16 Kbytes LCDC - * 0x53FC_0000 0x53FC_3FFF 16 Kbytes SLCDC - * 0x53FC_4000 0x53FC_7FFF 16 Kbytes Reserved - * 0x53FC_8000 0x53FC_BFFF 16 Kbytes PWM-4 - * 0x53FC_C000 0x53FC_FFFF 16 Kbytes GPIO-1 - * 0x53FD_0000 0x53FD_3FFF 16 Kbytes GPIO-2 - * 0x53FD_4000 0x53FD_7FFF 16 Kbytes SDMA - * 0x53FD_8000 0x53FD_BFFF 16 Kbytes Reserved - * 0x53FD_C000 0x53FD_FFFF 16 Kbytes WDOG - * 0x53FE_0000 0x53FE_3FFF 16 Kbytes PWM-1 - * 0x53FE_4000 0x53FE_7FFF 16 Kbytes Reserved - * 0x53FE_8000 0x53FE_BFFF 16 Kbytes Reserved - * 0x53FE_C000 0x53FE_FFFF 16 Kbytes RTICv3 - * 0x53FF_0000 0x53FF_3FFF 16 Kbytes IIM - * 0x53FF_4000 0x53FF_7FFF 16 Kbytes USB - * 0x53FF_8000 0x53FF_BFFF 16 Kbytes CSI - * 0x53FF_C000 0x53FF_FFFF 16 Kbytes DryIce - * 0x5400_0000 0x5FFF_FFFF 192 Mbytes Reserved (aliased AIPS B slots) - * 0x6000_0000 0x67FF_FFFF 128 Mbytes ARM926 platform ROMPATCH - * 0x6800_0000 0x6FFF_FFFF 128 Mbytes ARM926 platform ASIC - * 0x7000_0000 0x77FF_FFFF 128 Mbytes Reserved - * 0x7800_0000 0x7801_FFFF 128 Kbytes RAM - * 0x7802_0000 0x7FFF_FFFF 128 Mbytes (minus 128 Kbytes) - * 0x8000_0000 0x8FFF_FFFF 256 Mbytes SDRAM bank 0 - * 0x9000_0000 0x9FFF_FFFF 256 Mbytes SDRAM bank 1 - * 0xA000_0000 0xA7FF_FFFF 128 Mbytes WEIM CS0 (flash 128) 1 - * 0xA800_0000 0xAFFF_FFFF 128 Mbytes WEIM CS1 (flash 64) 1 - * 0xB000_0000 0xB1FF_FFFF 32 Mbytes WEIM CS2 (SRAM) - * 0xB200_0000 0xB3FF_FFFF 32 Mbytes WEIM CS3 (SRAM) - * 0xB400_0000 0xB5FF_FFFF 32 Mbytes WEIM CS4 - * 0xB600_0000 0xB7FF_FFFF 32 Mbytes Reserved - * 0xB800_0000 0xB800_0FFF 4 Kbytes Reserved - * 0xB800_1000 0xB800_1FFF 4 Kbytes SDRAM control registers - * 0xB800_2000 0xB800_2FFF 4 Kbytes WEIM control registers - * 0xB800_3000 0xB800_3FFF 4 Kbytes M3IF control registers - * 0xB800_4000 0xB800_4FFF 4 Kbytes EMI control registers - * 0xB800_5000 0xBAFF_FFFF 32 Mbytes (minus 20 Kbytes) - * 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer - * 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer - * 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved - * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers - * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved - * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved - */ - -#define FSL_IMX25_ROM0_ADDR 0x00000000 -#define FSL_IMX25_ROM0_SIZE 0x4000 -#define FSL_IMX25_ROM1_ADDR 0x00404000 -#define FSL_IMX25_ROM1_SIZE 0x4000 -#define FSL_IMX25_I2C1_ADDR 0x43F80000 -#define FSL_IMX25_I2C1_SIZE 0x4000 -#define FSL_IMX25_I2C3_ADDR 0x43F84000 -#define FSL_IMX25_I2C3_SIZE 0x4000 -#define FSL_IMX25_UART1_ADDR 0x43F90000 -#define FSL_IMX25_UART1_SIZE 0x4000 -#define FSL_IMX25_UART2_ADDR 0x43F94000 -#define FSL_IMX25_UART2_SIZE 0x4000 -#define FSL_IMX25_I2C2_ADDR 0x43F98000 -#define FSL_IMX25_I2C2_SIZE 0x4000 -#define FSL_IMX25_UART4_ADDR 0x50008000 -#define FSL_IMX25_UART4_SIZE 0x4000 -#define FSL_IMX25_UART3_ADDR 0x5000C000 -#define FSL_IMX25_UART3_SIZE 0x4000 -#define FSL_IMX25_UART5_ADDR 0x5002C000 -#define FSL_IMX25_UART5_SIZE 0x4000 -#define FSL_IMX25_FEC_ADDR 0x50038000 -#define FSL_IMX25_FEC_SIZE 0x4000 -#define FSL_IMX25_CCM_ADDR 0x53F80000 -#define FSL_IMX25_CCM_SIZE 0x4000 -#define FSL_IMX25_GPT4_ADDR 0x53F84000 -#define FSL_IMX25_GPT4_SIZE 0x4000 -#define FSL_IMX25_GPT3_ADDR 0x53F88000 -#define FSL_IMX25_GPT3_SIZE 0x4000 -#define FSL_IMX25_GPT2_ADDR 0x53F8C000 -#define FSL_IMX25_GPT2_SIZE 0x4000 -#define FSL_IMX25_GPT1_ADDR 0x53F90000 -#define FSL_IMX25_GPT1_SIZE 0x4000 -#define FSL_IMX25_EPIT1_ADDR 0x53F94000 -#define FSL_IMX25_EPIT1_SIZE 0x4000 -#define FSL_IMX25_EPIT2_ADDR 0x53F98000 -#define FSL_IMX25_EPIT2_SIZE 0x4000 -#define FSL_IMX25_GPIO4_ADDR 0x53F9C000 -#define FSL_IMX25_GPIO4_SIZE 0x4000 -#define FSL_IMX25_GPIO3_ADDR 0x53FA4000 -#define FSL_IMX25_GPIO3_SIZE 0x4000 -#define FSL_IMX25_GPIO1_ADDR 0x53FCC000 -#define FSL_IMX25_GPIO1_SIZE 0x4000 -#define FSL_IMX25_GPIO2_ADDR 0x53FD0000 -#define FSL_IMX25_GPIO2_SIZE 0x4000 -#define FSL_IMX25_AVIC_ADDR 0x68000000 -#define FSL_IMX25_AVIC_SIZE 0x4000 -#define FSL_IMX25_IRAM_ADDR 0x78000000 -#define FSL_IMX25_IRAM_SIZE 0x20000 -#define FSL_IMX25_IRAM_ALIAS_ADDR 0x78020000 -#define FSL_IMX25_IRAM_ALIAS_SIZE 0x7FE0000 -#define FSL_IMX25_SDRAM0_ADDR 0x80000000 -#define FSL_IMX25_SDRAM0_SIZE 0x10000000 -#define FSL_IMX25_SDRAM1_ADDR 0x90000000 -#define FSL_IMX25_SDRAM1_SIZE 0x10000000 - -#define FSL_IMX25_UART1_IRQ 45 -#define FSL_IMX25_UART2_IRQ 32 -#define FSL_IMX25_UART3_IRQ 18 -#define FSL_IMX25_UART4_IRQ 5 -#define FSL_IMX25_UART5_IRQ 40 -#define FSL_IMX25_GPT1_IRQ 54 -#define FSL_IMX25_GPT2_IRQ 53 -#define FSL_IMX25_GPT3_IRQ 29 -#define FSL_IMX25_GPT4_IRQ 1 -#define FSL_IMX25_EPIT1_IRQ 28 -#define FSL_IMX25_EPIT2_IRQ 27 -#define FSL_IMX25_FEC_IRQ 57 -#define FSL_IMX25_I2C1_IRQ 3 -#define FSL_IMX25_I2C2_IRQ 4 -#define FSL_IMX25_I2C3_IRQ 10 -#define FSL_IMX25_GPIO1_IRQ 52 -#define FSL_IMX25_GPIO2_IRQ 51 -#define FSL_IMX25_GPIO3_IRQ 16 -#define FSL_IMX25_GPIO4_IRQ 23 - -#endif /* FSL_IMX25_H */ diff --git a/qemu/include/hw/arm/fsl-imx31.h b/qemu/include/hw/arm/fsl-imx31.h deleted file mode 100644 index d408abbba..000000000 --- a/qemu/include/hw/arm/fsl-imx31.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Freescale i.MX31 SoC emulation - * - * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#ifndef FSL_IMX31_H -#define FSL_IMX31_H - -#include "hw/arm/arm.h" -#include "hw/intc/imx_avic.h" -#include "hw/misc/imx31_ccm.h" -#include "hw/char/imx_serial.h" -#include "hw/timer/imx_gpt.h" -#include "hw/timer/imx_epit.h" -#include "hw/i2c/imx_i2c.h" -#include "hw/gpio/imx_gpio.h" -#include "exec/memory.h" - -#define TYPE_FSL_IMX31 "fsl,imx31" -#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31) - -#define FSL_IMX31_NUM_UARTS 2 -#define FSL_IMX31_NUM_EPITS 2 -#define FSL_IMX31_NUM_I2CS 3 -#define FSL_IMX31_NUM_GPIOS 3 - -typedef struct FslIMX31State { - /*< private >*/ - DeviceState parent_obj; - - /*< public >*/ - ARMCPU cpu; - IMXAVICState avic; - IMX31CCMState ccm; - IMXSerialState uart[FSL_IMX31_NUM_UARTS]; - IMXGPTState gpt; - IMXEPITState epit[FSL_IMX31_NUM_EPITS]; - IMXI2CState i2c[FSL_IMX31_NUM_I2CS]; - IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS]; - MemoryRegion secure_rom; - MemoryRegion rom; - MemoryRegion iram; - MemoryRegion iram_alias; -} FslIMX31State; - -#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000 -#define FSL_IMX31_SECURE_ROM_SIZE 0x4000 -#define FSL_IMX31_ROM_ADDR 0x00404000 -#define FSL_IMX31_ROM_SIZE 0x4000 -#define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000 -#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000 -#define FSL_IMX31_IRAM_ADDR 0x1FFFC000 -#define FSL_IMX31_IRAM_SIZE 0x4000 -#define FSL_IMX31_I2C1_ADDR 0x43F80000 -#define FSL_IMX31_I2C1_SIZE 0x4000 -#define FSL_IMX31_I2C3_ADDR 0x43F84000 -#define FSL_IMX31_I2C3_SIZE 0x4000 -#define FSL_IMX31_UART1_ADDR 0x43F90000 -#define FSL_IMX31_UART1_SIZE 0x4000 -#define FSL_IMX31_UART2_ADDR 0x43F94000 -#define FSL_IMX31_UART2_SIZE 0x4000 -#define FSL_IMX31_I2C2_ADDR 0x43F98000 -#define FSL_IMX31_I2C2_SIZE 0x4000 -#define FSL_IMX31_CCM_ADDR 0x53F80000 -#define FSL_IMX31_CCM_SIZE 0x4000 -#define FSL_IMX31_GPT_ADDR 0x53F90000 -#define FSL_IMX31_GPT_SIZE 0x4000 -#define FSL_IMX31_EPIT1_ADDR 0x53F94000 -#define FSL_IMX31_EPIT1_SIZE 0x4000 -#define FSL_IMX31_EPIT2_ADDR 0x53F98000 -#define FSL_IMX31_EPIT2_SIZE 0x4000 -#define FSL_IMX31_GPIO3_ADDR 0x53FA4000 -#define FSL_IMX31_GPIO3_SIZE 0x4000 -#define FSL_IMX31_GPIO1_ADDR 0x53FCC000 -#define FSL_IMX31_GPIO1_SIZE 0x4000 -#define FSL_IMX31_GPIO2_ADDR 0x53FD0000 -#define FSL_IMX31_GPIO2_SIZE 0x4000 -#define FSL_IMX31_AVIC_ADDR 0x68000000 -#define FSL_IMX31_AVIC_SIZE 0x100 -#define FSL_IMX31_SDRAM0_ADDR 0x80000000 -#define FSL_IMX31_SDRAM0_SIZE 0x10000000 -#define FSL_IMX31_SDRAM1_ADDR 0x90000000 -#define FSL_IMX31_SDRAM1_SIZE 0x10000000 -#define FSL_IMX31_FLASH0_ADDR 0xA0000000 -#define FSL_IMX31_FLASH0_SIZE 0x8000000 -#define FSL_IMX31_FLASH1_ADDR 0xA8000000 -#define FSL_IMX31_FLASH1_SIZE 0x8000000 -#define FSL_IMX31_CS2_ADDR 0xB0000000 -#define FSL_IMX31_CS2_SIZE 0x2000000 -#define FSL_IMX31_CS3_ADDR 0xB2000000 -#define FSL_IMX31_CS3_SIZE 0x2000000 -#define FSL_IMX31_CS4_ADDR 0xB4000000 -#define FSL_IMX31_CS4_SIZE 0x2000000 -#define FSL_IMX31_CS5_ADDR 0xB6000000 -#define FSL_IMX31_CS5_SIZE 0x2000000 -#define FSL_IMX31_NAND_ADDR 0xB8000000 -#define FSL_IMX31_NAND_SIZE 0x1000 - -#define FSL_IMX31_EPIT2_IRQ 27 -#define FSL_IMX31_EPIT1_IRQ 28 -#define FSL_IMX31_GPT_IRQ 29 -#define FSL_IMX31_UART2_IRQ 32 -#define FSL_IMX31_UART1_IRQ 45 -#define FSL_IMX31_I2C1_IRQ 10 -#define FSL_IMX31_I2C2_IRQ 4 -#define FSL_IMX31_I2C3_IRQ 3 -#define FSL_IMX31_GPIO1_IRQ 52 -#define FSL_IMX31_GPIO2_IRQ 51 -#define FSL_IMX31_GPIO3_IRQ 56 - -#endif /* FSL_IMX31_H */ diff --git a/qemu/include/hw/arm/linux-boot-if.h b/qemu/include/hw/arm/linux-boot-if.h deleted file mode 100644 index aba4479a1..000000000 --- a/qemu/include/hw/arm/linux-boot-if.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * hw/arm/linux-boot-if.h : interface for devices which need to behave - * specially for direct boot of an ARM Linux kernel - */ - -#ifndef HW_ARM_LINUX_BOOT_IF_H -#define HW_ARM_LINUX_BOOT_IF_H - -#include "qom/object.h" - -#define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if" -#define ARM_LINUX_BOOT_IF_CLASS(klass) \ - OBJECT_CLASS_CHECK(ARMLinuxBootIfClass, (klass), TYPE_ARM_LINUX_BOOT_IF) -#define ARM_LINUX_BOOT_IF_GET_CLASS(obj) \ - OBJECT_GET_CLASS(ARMLinuxBootIfClass, (obj), TYPE_ARM_LINUX_BOOT_IF) -#define ARM_LINUX_BOOT_IF(obj) \ - INTERFACE_CHECK(ARMLinuxBootIf, (obj), TYPE_ARM_LINUX_BOOT_IF) - -typedef struct ARMLinuxBootIf { - /*< private >*/ - Object parent_obj; -} ARMLinuxBootIf; - -typedef struct ARMLinuxBootIfClass { - /*< private >*/ - InterfaceClass parent_class; - - /*< public >*/ - /** arm_linux_init: configure the device for a direct boot - * of an ARM Linux kernel (so that device reset puts it into - * the state the kernel expects after firmware initialization, - * rather than the true hardware reset state). This callback is - * called once after machine construction is complete (before the - * first system reset). - * - * @obj: the object implementing this interface - * @secure_boot: true if we are booting Secure, false for NonSecure - * (or for a CPU which doesn't support TrustZone) - */ - void (*arm_linux_init)(ARMLinuxBootIf *obj, bool secure_boot); -} ARMLinuxBootIfClass; - -#endif diff --git a/qemu/include/hw/arm/omap.h b/qemu/include/hw/arm/omap.h deleted file mode 100644 index 0ad5fb883..000000000 --- a/qemu/include/hw/arm/omap.h +++ /dev/null @@ -1,1015 +0,0 @@ -/* - * Texas Instruments OMAP processors. - * - * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 or - * (at your option) version 3 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ -#ifndef hw_omap_h -#include "exec/memory.h" -# define hw_omap_h "omap.h" -#include "hw/irq.h" - -# define OMAP_EMIFS_BASE 0x00000000 -# define OMAP2_Q0_BASE 0x00000000 -# define OMAP_CS0_BASE 0x00000000 -# define OMAP_CS1_BASE 0x04000000 -# define OMAP_CS2_BASE 0x08000000 -# define OMAP_CS3_BASE 0x0c000000 -# define OMAP_EMIFF_BASE 0x10000000 -# define OMAP_IMIF_BASE 0x20000000 -# define OMAP_LOCALBUS_BASE 0x30000000 -# define OMAP2_Q1_BASE 0x40000000 -# define OMAP2_L4_BASE 0x48000000 -# define OMAP2_SRAM_BASE 0x40200000 -# define OMAP2_L3_BASE 0x68000000 -# define OMAP2_Q2_BASE 0x80000000 -# define OMAP2_Q3_BASE 0xc0000000 -# define OMAP_MPUI_BASE 0xe1000000 - -# define OMAP730_SRAM_SIZE 0x00032000 -# define OMAP15XX_SRAM_SIZE 0x00030000 -# define OMAP16XX_SRAM_SIZE 0x00004000 -# define OMAP1611_SRAM_SIZE 0x0003e800 -# define OMAP242X_SRAM_SIZE 0x000a0000 -# define OMAP243X_SRAM_SIZE 0x00010000 -# define OMAP_CS0_SIZE 0x04000000 -# define OMAP_CS1_SIZE 0x04000000 -# define OMAP_CS2_SIZE 0x04000000 -# define OMAP_CS3_SIZE 0x04000000 - -/* omap_clk.c */ -struct omap_mpu_state_s; -typedef struct clk *omap_clk; -omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); -void omap_clk_init(struct omap_mpu_state_s *mpu); -void omap_clk_adduser(struct clk *clk, qemu_irq user); -void omap_clk_get(omap_clk clk); -void omap_clk_put(omap_clk clk); -void omap_clk_onoff(omap_clk clk, int on); -void omap_clk_canidle(omap_clk clk, int can); -void omap_clk_setrate(omap_clk clk, int divide, int multiply); -int64_t omap_clk_getrate(omap_clk clk); -void omap_clk_reparent(omap_clk clk, omap_clk parent); - -/* OMAP2 l4 Interconnect */ -struct omap_l4_s; -struct omap_l4_region_s { - hwaddr offset; - size_t size; - int access; -}; -struct omap_l4_agent_info_s { - int ta; - int region; - int regions; - int ta_region; -}; -struct omap_target_agent_s { - MemoryRegion iomem; - struct omap_l4_s *bus; - int regions; - const struct omap_l4_region_s *start; - hwaddr base; - uint32_t component; - uint32_t control; - uint32_t status; -}; -struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, - hwaddr base, int ta_num); - -struct omap_target_agent_s; -struct omap_target_agent_s *omap_l4ta_get( - struct omap_l4_s *bus, - const struct omap_l4_region_s *regions, - const struct omap_l4_agent_info_s *agents, - int cs); -hwaddr omap_l4_attach(struct omap_target_agent_s *ta, - int region, MemoryRegion *mr); -hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, - int region); -hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, - int region); - -/* OMAP2 SDRAM controller */ -struct omap_sdrc_s; -struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, - hwaddr base); -void omap_sdrc_reset(struct omap_sdrc_s *s); - -/* OMAP2 general purpose memory controller */ -struct omap_gpmc_s; -struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, - hwaddr base, - qemu_irq irq, qemu_irq drq); -void omap_gpmc_reset(struct omap_gpmc_s *s); -void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); -void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); - -/* - * Common IRQ numbers for level 1 interrupt handler - * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. - */ -# define OMAP_INT_CAMERA 1 -# define OMAP_INT_FIQ 3 -# define OMAP_INT_RTDX 6 -# define OMAP_INT_DSP_MMU_ABORT 7 -# define OMAP_INT_HOST 8 -# define OMAP_INT_ABORT 9 -# define OMAP_INT_BRIDGE_PRIV 13 -# define OMAP_INT_GPIO_BANK1 14 -# define OMAP_INT_UART3 15 -# define OMAP_INT_TIMER3 16 -# define OMAP_INT_DMA_CH0_6 19 -# define OMAP_INT_DMA_CH1_7 20 -# define OMAP_INT_DMA_CH2_8 21 -# define OMAP_INT_DMA_CH3 22 -# define OMAP_INT_DMA_CH4 23 -# define OMAP_INT_DMA_CH5 24 -# define OMAP_INT_DMA_LCD 25 -# define OMAP_INT_TIMER1 26 -# define OMAP_INT_WD_TIMER 27 -# define OMAP_INT_BRIDGE_PUB 28 -# define OMAP_INT_TIMER2 30 -# define OMAP_INT_LCD_CTRL 31 - -/* - * Common OMAP-15xx IRQ numbers for level 1 interrupt handler - */ -# define OMAP_INT_15XX_IH2_IRQ 0 -# define OMAP_INT_15XX_LB_MMU 17 -# define OMAP_INT_15XX_LOCAL_BUS 29 - -/* - * OMAP-1510 specific IRQ numbers for level 1 interrupt handler - */ -# define OMAP_INT_1510_SPI_TX 4 -# define OMAP_INT_1510_SPI_RX 5 -# define OMAP_INT_1510_DSP_MAILBOX1 10 -# define OMAP_INT_1510_DSP_MAILBOX2 11 - -/* - * OMAP-310 specific IRQ numbers for level 1 interrupt handler - */ -# define OMAP_INT_310_McBSP2_TX 4 -# define OMAP_INT_310_McBSP2_RX 5 -# define OMAP_INT_310_HSB_MAILBOX1 12 -# define OMAP_INT_310_HSAB_MMU 18 - -/* - * OMAP-1610 specific IRQ numbers for level 1 interrupt handler - */ -# define OMAP_INT_1610_IH2_IRQ 0 -# define OMAP_INT_1610_IH2_FIQ 2 -# define OMAP_INT_1610_McBSP2_TX 4 -# define OMAP_INT_1610_McBSP2_RX 5 -# define OMAP_INT_1610_DSP_MAILBOX1 10 -# define OMAP_INT_1610_DSP_MAILBOX2 11 -# define OMAP_INT_1610_LCD_LINE 12 -# define OMAP_INT_1610_GPTIMER1 17 -# define OMAP_INT_1610_GPTIMER2 18 -# define OMAP_INT_1610_SSR_FIFO_0 29 - -/* - * OMAP-730 specific IRQ numbers for level 1 interrupt handler - */ -# define OMAP_INT_730_IH2_FIQ 0 -# define OMAP_INT_730_IH2_IRQ 1 -# define OMAP_INT_730_USB_NON_ISO 2 -# define OMAP_INT_730_USB_ISO 3 -# define OMAP_INT_730_ICR 4 -# define OMAP_INT_730_EAC 5 -# define OMAP_INT_730_GPIO_BANK1 6 -# define OMAP_INT_730_GPIO_BANK2 7 -# define OMAP_INT_730_GPIO_BANK3 8 -# define OMAP_INT_730_McBSP2TX 10 -# define OMAP_INT_730_McBSP2RX 11 -# define OMAP_INT_730_McBSP2RX_OVF 12 -# define OMAP_INT_730_LCD_LINE 14 -# define OMAP_INT_730_GSM_PROTECT 15 -# define OMAP_INT_730_TIMER3 16 -# define OMAP_INT_730_GPIO_BANK5 17 -# define OMAP_INT_730_GPIO_BANK6 18 -# define OMAP_INT_730_SPGIO_WR 29 - -/* - * Common IRQ numbers for level 2 interrupt handler - */ -# define OMAP_INT_KEYBOARD 1 -# define OMAP_INT_uWireTX 2 -# define OMAP_INT_uWireRX 3 -# define OMAP_INT_I2C 4 -# define OMAP_INT_MPUIO 5 -# define OMAP_INT_USB_HHC_1 6 -# define OMAP_INT_McBSP3TX 10 -# define OMAP_INT_McBSP3RX 11 -# define OMAP_INT_McBSP1TX 12 -# define OMAP_INT_McBSP1RX 13 -# define OMAP_INT_UART1 14 -# define OMAP_INT_UART2 15 -# define OMAP_INT_USB_W2FC 20 -# define OMAP_INT_1WIRE 21 -# define OMAP_INT_OS_TIMER 22 -# define OMAP_INT_OQN 23 -# define OMAP_INT_GAUGE_32K 24 -# define OMAP_INT_RTC_TIMER 25 -# define OMAP_INT_RTC_ALARM 26 -# define OMAP_INT_DSP_MMU 28 - -/* - * OMAP-1510 specific IRQ numbers for level 2 interrupt handler - */ -# define OMAP_INT_1510_BT_MCSI1TX 16 -# define OMAP_INT_1510_BT_MCSI1RX 17 -# define OMAP_INT_1510_SoSSI_MATCH 19 -# define OMAP_INT_1510_MEM_STICK 27 -# define OMAP_INT_1510_COM_SPI_RO 31 - -/* - * OMAP-310 specific IRQ numbers for level 2 interrupt handler - */ -# define OMAP_INT_310_FAC 0 -# define OMAP_INT_310_USB_HHC_2 7 -# define OMAP_INT_310_MCSI1_FE 16 -# define OMAP_INT_310_MCSI2_FE 17 -# define OMAP_INT_310_USB_W2FC_ISO 29 -# define OMAP_INT_310_USB_W2FC_NON_ISO 30 -# define OMAP_INT_310_McBSP2RX_OF 31 - -/* - * OMAP-1610 specific IRQ numbers for level 2 interrupt handler - */ -# define OMAP_INT_1610_FAC 0 -# define OMAP_INT_1610_USB_HHC_2 7 -# define OMAP_INT_1610_USB_OTG 8 -# define OMAP_INT_1610_SoSSI 9 -# define OMAP_INT_1610_BT_MCSI1TX 16 -# define OMAP_INT_1610_BT_MCSI1RX 17 -# define OMAP_INT_1610_SoSSI_MATCH 19 -# define OMAP_INT_1610_MEM_STICK 27 -# define OMAP_INT_1610_McBSP2RX_OF 31 -# define OMAP_INT_1610_STI 32 -# define OMAP_INT_1610_STI_WAKEUP 33 -# define OMAP_INT_1610_GPTIMER3 34 -# define OMAP_INT_1610_GPTIMER4 35 -# define OMAP_INT_1610_GPTIMER5 36 -# define OMAP_INT_1610_GPTIMER6 37 -# define OMAP_INT_1610_GPTIMER7 38 -# define OMAP_INT_1610_GPTIMER8 39 -# define OMAP_INT_1610_GPIO_BANK2 40 -# define OMAP_INT_1610_GPIO_BANK3 41 -# define OMAP_INT_1610_MMC2 42 -# define OMAP_INT_1610_CF 43 -# define OMAP_INT_1610_WAKE_UP_REQ 46 -# define OMAP_INT_1610_GPIO_BANK4 48 -# define OMAP_INT_1610_SPI 49 -# define OMAP_INT_1610_DMA_CH6 53 -# define OMAP_INT_1610_DMA_CH7 54 -# define OMAP_INT_1610_DMA_CH8 55 -# define OMAP_INT_1610_DMA_CH9 56 -# define OMAP_INT_1610_DMA_CH10 57 -# define OMAP_INT_1610_DMA_CH11 58 -# define OMAP_INT_1610_DMA_CH12 59 -# define OMAP_INT_1610_DMA_CH13 60 -# define OMAP_INT_1610_DMA_CH14 61 -# define OMAP_INT_1610_DMA_CH15 62 -# define OMAP_INT_1610_NAND 63 - -/* - * OMAP-730 specific IRQ numbers for level 2 interrupt handler - */ -# define OMAP_INT_730_HW_ERRORS 0 -# define OMAP_INT_730_NFIQ_PWR_FAIL 1 -# define OMAP_INT_730_CFCD 2 -# define OMAP_INT_730_CFIREQ 3 -# define OMAP_INT_730_I2C 4 -# define OMAP_INT_730_PCC 5 -# define OMAP_INT_730_MPU_EXT_NIRQ 6 -# define OMAP_INT_730_SPI_100K_1 7 -# define OMAP_INT_730_SYREN_SPI 8 -# define OMAP_INT_730_VLYNQ 9 -# define OMAP_INT_730_GPIO_BANK4 10 -# define OMAP_INT_730_McBSP1TX 11 -# define OMAP_INT_730_McBSP1RX 12 -# define OMAP_INT_730_McBSP1RX_OF 13 -# define OMAP_INT_730_UART_MODEM_IRDA_2 14 -# define OMAP_INT_730_UART_MODEM_1 15 -# define OMAP_INT_730_MCSI 16 -# define OMAP_INT_730_uWireTX 17 -# define OMAP_INT_730_uWireRX 18 -# define OMAP_INT_730_SMC_CD 19 -# define OMAP_INT_730_SMC_IREQ 20 -# define OMAP_INT_730_HDQ_1WIRE 21 -# define OMAP_INT_730_TIMER32K 22 -# define OMAP_INT_730_MMC_SDIO 23 -# define OMAP_INT_730_UPLD 24 -# define OMAP_INT_730_USB_HHC_1 27 -# define OMAP_INT_730_USB_HHC_2 28 -# define OMAP_INT_730_USB_GENI 29 -# define OMAP_INT_730_USB_OTG 30 -# define OMAP_INT_730_CAMERA_IF 31 -# define OMAP_INT_730_RNG 32 -# define OMAP_INT_730_DUAL_MODE_TIMER 33 -# define OMAP_INT_730_DBB_RF_EN 34 -# define OMAP_INT_730_MPUIO_KEYPAD 35 -# define OMAP_INT_730_SHA1_MD5 36 -# define OMAP_INT_730_SPI_100K_2 37 -# define OMAP_INT_730_RNG_IDLE 38 -# define OMAP_INT_730_MPUIO 39 -# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 -# define OMAP_INT_730_LLPC_OE_FALLING 41 -# define OMAP_INT_730_LLPC_OE_RISING 42 -# define OMAP_INT_730_LLPC_VSYNC 43 -# define OMAP_INT_730_WAKE_UP_REQ 46 -# define OMAP_INT_730_DMA_CH6 53 -# define OMAP_INT_730_DMA_CH7 54 -# define OMAP_INT_730_DMA_CH8 55 -# define OMAP_INT_730_DMA_CH9 56 -# define OMAP_INT_730_DMA_CH10 57 -# define OMAP_INT_730_DMA_CH11 58 -# define OMAP_INT_730_DMA_CH12 59 -# define OMAP_INT_730_DMA_CH13 60 -# define OMAP_INT_730_DMA_CH14 61 -# define OMAP_INT_730_DMA_CH15 62 -# define OMAP_INT_730_NAND 63 - -/* - * OMAP-24xx common IRQ numbers - */ -# define OMAP_INT_24XX_STI 4 -# define OMAP_INT_24XX_SYS_NIRQ 7 -# define OMAP_INT_24XX_L3_IRQ 10 -# define OMAP_INT_24XX_PRCM_MPU_IRQ 11 -# define OMAP_INT_24XX_SDMA_IRQ0 12 -# define OMAP_INT_24XX_SDMA_IRQ1 13 -# define OMAP_INT_24XX_SDMA_IRQ2 14 -# define OMAP_INT_24XX_SDMA_IRQ3 15 -# define OMAP_INT_243X_MCBSP2_IRQ 16 -# define OMAP_INT_243X_MCBSP3_IRQ 17 -# define OMAP_INT_243X_MCBSP4_IRQ 18 -# define OMAP_INT_243X_MCBSP5_IRQ 19 -# define OMAP_INT_24XX_GPMC_IRQ 20 -# define OMAP_INT_24XX_GUFFAW_IRQ 21 -# define OMAP_INT_24XX_IVA_IRQ 22 -# define OMAP_INT_24XX_EAC_IRQ 23 -# define OMAP_INT_24XX_CAM_IRQ 24 -# define OMAP_INT_24XX_DSS_IRQ 25 -# define OMAP_INT_24XX_MAIL_U0_MPU 26 -# define OMAP_INT_24XX_DSP_UMA 27 -# define OMAP_INT_24XX_DSP_MMU 28 -# define OMAP_INT_24XX_GPIO_BANK1 29 -# define OMAP_INT_24XX_GPIO_BANK2 30 -# define OMAP_INT_24XX_GPIO_BANK3 31 -# define OMAP_INT_24XX_GPIO_BANK4 32 -# define OMAP_INT_243X_GPIO_BANK5 33 -# define OMAP_INT_24XX_MAIL_U3_MPU 34 -# define OMAP_INT_24XX_WDT3 35 -# define OMAP_INT_24XX_WDT4 36 -# define OMAP_INT_24XX_GPTIMER1 37 -# define OMAP_INT_24XX_GPTIMER2 38 -# define OMAP_INT_24XX_GPTIMER3 39 -# define OMAP_INT_24XX_GPTIMER4 40 -# define OMAP_INT_24XX_GPTIMER5 41 -# define OMAP_INT_24XX_GPTIMER6 42 -# define OMAP_INT_24XX_GPTIMER7 43 -# define OMAP_INT_24XX_GPTIMER8 44 -# define OMAP_INT_24XX_GPTIMER9 45 -# define OMAP_INT_24XX_GPTIMER10 46 -# define OMAP_INT_24XX_GPTIMER11 47 -# define OMAP_INT_24XX_GPTIMER12 48 -# define OMAP_INT_24XX_PKA_IRQ 50 -# define OMAP_INT_24XX_SHA1MD5_IRQ 51 -# define OMAP_INT_24XX_RNG_IRQ 52 -# define OMAP_INT_24XX_MG_IRQ 53 -# define OMAP_INT_24XX_I2C1_IRQ 56 -# define OMAP_INT_24XX_I2C2_IRQ 57 -# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 -# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 -# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 -# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 -# define OMAP_INT_243X_MCBSP1_IRQ 64 -# define OMAP_INT_24XX_MCSPI1_IRQ 65 -# define OMAP_INT_24XX_MCSPI2_IRQ 66 -# define OMAP_INT_24XX_SSI1_IRQ0 67 -# define OMAP_INT_24XX_SSI1_IRQ1 68 -# define OMAP_INT_24XX_SSI2_IRQ0 69 -# define OMAP_INT_24XX_SSI2_IRQ1 70 -# define OMAP_INT_24XX_SSI_GDD_IRQ 71 -# define OMAP_INT_24XX_UART1_IRQ 72 -# define OMAP_INT_24XX_UART2_IRQ 73 -# define OMAP_INT_24XX_UART3_IRQ 74 -# define OMAP_INT_24XX_USB_IRQ_GEN 75 -# define OMAP_INT_24XX_USB_IRQ_NISO 76 -# define OMAP_INT_24XX_USB_IRQ_ISO 77 -# define OMAP_INT_24XX_USB_IRQ_HGEN 78 -# define OMAP_INT_24XX_USB_IRQ_HSOF 79 -# define OMAP_INT_24XX_USB_IRQ_OTG 80 -# define OMAP_INT_24XX_VLYNQ_IRQ 81 -# define OMAP_INT_24XX_MMC_IRQ 83 -# define OMAP_INT_24XX_MS_IRQ 84 -# define OMAP_INT_24XX_FAC_IRQ 85 -# define OMAP_INT_24XX_MCSPI3_IRQ 91 -# define OMAP_INT_243X_HS_USB_MC 92 -# define OMAP_INT_243X_HS_USB_DMA 93 -# define OMAP_INT_243X_CARKIT 94 -# define OMAP_INT_34XX_GPTIMER12 95 - -/* omap_dma.c */ -enum omap_dma_model { - omap_dma_3_0, - omap_dma_3_1, - omap_dma_3_2, - omap_dma_4, -}; - -struct soc_dma_s; -struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, - MemoryRegion *sysmem, - qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, - enum omap_dma_model model); -struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, - MemoryRegion *sysmem, - struct omap_mpu_state_s *mpu, int fifo, - int chans, omap_clk iclk, omap_clk fclk); -void omap_dma_reset(struct soc_dma_s *s); - -struct dma_irq_map { - int ih; - int intr; -}; - -/* Only used in OMAP DMA 3.x gigacells */ -enum omap_dma_port { - emiff = 0, - emifs, - imif, /* omap16xx: ocp_t1 */ - tipb, - local, /* omap16xx: ocp_t2 */ - tipb_mpui, - __omap_dma_port_last, -}; - -typedef enum { - constant = 0, - post_incremented, - single_index, - double_index, -} omap_dma_addressing_t; - -/* Only used in OMAP DMA 3.x gigacells */ -struct omap_dma_lcd_channel_s { - enum omap_dma_port src; - hwaddr src_f1_top; - hwaddr src_f1_bottom; - hwaddr src_f2_top; - hwaddr src_f2_bottom; - - /* Used in OMAP DMA 3.2 gigacell */ - unsigned char brust_f1; - unsigned char pack_f1; - unsigned char data_type_f1; - unsigned char brust_f2; - unsigned char pack_f2; - unsigned char data_type_f2; - unsigned char end_prog; - unsigned char repeat; - unsigned char auto_init; - unsigned char priority; - unsigned char fs; - unsigned char running; - unsigned char bs; - unsigned char omap_3_1_compatible_disable; - unsigned char dst; - unsigned char lch_type; - int16_t element_index_f1; - int16_t element_index_f2; - int32_t frame_index_f1; - int32_t frame_index_f2; - uint16_t elements_f1; - uint16_t frames_f1; - uint16_t elements_f2; - uint16_t frames_f2; - omap_dma_addressing_t mode_f1; - omap_dma_addressing_t mode_f2; - - /* Destination port is fixed. */ - int interrupts; - int condition; - int dual; - - int current_frame; - hwaddr phys_framebuffer[2]; - qemu_irq irq; - struct omap_mpu_state_s *mpu; -} *omap_dma_get_lcdch(struct soc_dma_s *s); - -/* - * DMA request numbers for OMAP1 - * See /usr/include/asm-arm/arch-omap/dma.h in Linux. - */ -# define OMAP_DMA_NO_DEVICE 0 -# define OMAP_DMA_MCSI1_TX 1 -# define OMAP_DMA_MCSI1_RX 2 -# define OMAP_DMA_I2C_RX 3 -# define OMAP_DMA_I2C_TX 4 -# define OMAP_DMA_EXT_NDMA_REQ0 5 -# define OMAP_DMA_EXT_NDMA_REQ1 6 -# define OMAP_DMA_UWIRE_TX 7 -# define OMAP_DMA_MCBSP1_TX 8 -# define OMAP_DMA_MCBSP1_RX 9 -# define OMAP_DMA_MCBSP3_TX 10 -# define OMAP_DMA_MCBSP3_RX 11 -# define OMAP_DMA_UART1_TX 12 -# define OMAP_DMA_UART1_RX 13 -# define OMAP_DMA_UART2_TX 14 -# define OMAP_DMA_UART2_RX 15 -# define OMAP_DMA_MCBSP2_TX 16 -# define OMAP_DMA_MCBSP2_RX 17 -# define OMAP_DMA_UART3_TX 18 -# define OMAP_DMA_UART3_RX 19 -# define OMAP_DMA_CAMERA_IF_RX 20 -# define OMAP_DMA_MMC_TX 21 -# define OMAP_DMA_MMC_RX 22 -# define OMAP_DMA_NAND 23 /* Not in OMAP310 */ -# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ -# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ -# define OMAP_DMA_USB_W2FC_RX0 26 -# define OMAP_DMA_USB_W2FC_RX1 27 -# define OMAP_DMA_USB_W2FC_RX2 28 -# define OMAP_DMA_USB_W2FC_TX0 29 -# define OMAP_DMA_USB_W2FC_TX1 30 -# define OMAP_DMA_USB_W2FC_TX2 31 - -/* These are only for 1610 */ -# define OMAP_DMA_CRYPTO_DES_IN 32 -# define OMAP_DMA_SPI_TX 33 -# define OMAP_DMA_SPI_RX 34 -# define OMAP_DMA_CRYPTO_HASH 35 -# define OMAP_DMA_CCP_ATTN 36 -# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 -# define OMAP_DMA_CMT_APE_TX_CHAN_0 38 -# define OMAP_DMA_CMT_APE_RV_CHAN_0 39 -# define OMAP_DMA_CMT_APE_TX_CHAN_1 40 -# define OMAP_DMA_CMT_APE_RV_CHAN_1 41 -# define OMAP_DMA_CMT_APE_TX_CHAN_2 42 -# define OMAP_DMA_CMT_APE_RV_CHAN_2 43 -# define OMAP_DMA_CMT_APE_TX_CHAN_3 44 -# define OMAP_DMA_CMT_APE_RV_CHAN_3 45 -# define OMAP_DMA_CMT_APE_TX_CHAN_4 46 -# define OMAP_DMA_CMT_APE_RV_CHAN_4 47 -# define OMAP_DMA_CMT_APE_TX_CHAN_5 48 -# define OMAP_DMA_CMT_APE_RV_CHAN_5 49 -# define OMAP_DMA_CMT_APE_TX_CHAN_6 50 -# define OMAP_DMA_CMT_APE_RV_CHAN_6 51 -# define OMAP_DMA_CMT_APE_TX_CHAN_7 52 -# define OMAP_DMA_CMT_APE_RV_CHAN_7 53 -# define OMAP_DMA_MMC2_TX 54 -# define OMAP_DMA_MMC2_RX 55 -# define OMAP_DMA_CRYPTO_DES_OUT 56 - -/* - * DMA request numbers for the OMAP2 - */ -# define OMAP24XX_DMA_NO_DEVICE 0 -# define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_EXT_DMAREQ0 2 -# define OMAP24XX_DMA_EXT_DMAREQ1 3 -# define OMAP24XX_DMA_GPMC 4 -# define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_DSS 6 -# define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_EXT_DMAREQ2 14 -# define OMAP24XX_DMA_EXT_DMAREQ3 15 -# define OMAP24XX_DMA_EXT_DMAREQ4 16 -# define OMAP24XX_DMA_EAC_AC_RD 17 -# define OMAP24XX_DMA_EAC_AC_WR 18 -# define OMAP24XX_DMA_EAC_MD_UL_RD 19 -# define OMAP24XX_DMA_EAC_MD_UL_WR 20 -# define OMAP24XX_DMA_EAC_MD_DL_RD 21 -# define OMAP24XX_DMA_EAC_MD_DL_WR 22 -# define OMAP24XX_DMA_EAC_BT_UL_RD 23 -# define OMAP24XX_DMA_EAC_BT_UL_WR 24 -# define OMAP24XX_DMA_EAC_BT_DL_RD 25 -# define OMAP24XX_DMA_EAC_BT_DL_WR 26 -# define OMAP24XX_DMA_I2C1_TX 27 -# define OMAP24XX_DMA_I2C1_RX 28 -# define OMAP24XX_DMA_I2C2_TX 29 -# define OMAP24XX_DMA_I2C2_RX 30 -# define OMAP24XX_DMA_MCBSP1_TX 31 -# define OMAP24XX_DMA_MCBSP1_RX 32 -# define OMAP24XX_DMA_MCBSP2_TX 33 -# define OMAP24XX_DMA_MCBSP2_RX 34 -# define OMAP24XX_DMA_SPI1_TX0 35 -# define OMAP24XX_DMA_SPI1_RX0 36 -# define OMAP24XX_DMA_SPI1_TX1 37 -# define OMAP24XX_DMA_SPI1_RX1 38 -# define OMAP24XX_DMA_SPI1_TX2 39 -# define OMAP24XX_DMA_SPI1_RX2 40 -# define OMAP24XX_DMA_SPI1_TX3 41 -# define OMAP24XX_DMA_SPI1_RX3 42 -# define OMAP24XX_DMA_SPI2_TX0 43 -# define OMAP24XX_DMA_SPI2_RX0 44 -# define OMAP24XX_DMA_SPI2_TX1 45 -# define OMAP24XX_DMA_SPI2_RX1 46 - -# define OMAP24XX_DMA_UART1_TX 49 -# define OMAP24XX_DMA_UART1_RX 50 -# define OMAP24XX_DMA_UART2_TX 51 -# define OMAP24XX_DMA_UART2_RX 52 -# define OMAP24XX_DMA_UART3_TX 53 -# define OMAP24XX_DMA_UART3_RX 54 -# define OMAP24XX_DMA_USB_W2FC_TX0 55 -# define OMAP24XX_DMA_USB_W2FC_RX0 56 -# define OMAP24XX_DMA_USB_W2FC_TX1 57 -# define OMAP24XX_DMA_USB_W2FC_RX1 58 -# define OMAP24XX_DMA_USB_W2FC_TX2 59 -# define OMAP24XX_DMA_USB_W2FC_RX2 60 -# define OMAP24XX_DMA_MMC1_TX 61 -# define OMAP24XX_DMA_MMC1_RX 62 -# define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ -# define OMAP24XX_DMA_EXT_DMAREQ5 64 - -/* omap[123].c */ -/* OMAP2 gp timer */ -struct omap_gp_timer_s; -struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, - qemu_irq irq, omap_clk fclk, omap_clk iclk); -void omap_gp_timer_reset(struct omap_gp_timer_s *s); - -/* OMAP2 sysctimer */ -struct omap_synctimer_s; -struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, - struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); -void omap_synctimer_reset(struct omap_synctimer_s *s); - -struct omap_uart_s; -struct omap_uart_s *omap_uart_init(hwaddr base, - qemu_irq irq, omap_clk fclk, omap_clk iclk, - qemu_irq txdma, qemu_irq rxdma, - const char *label, CharDriverState *chr); -struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, - struct omap_target_agent_s *ta, - qemu_irq irq, omap_clk fclk, omap_clk iclk, - qemu_irq txdma, qemu_irq rxdma, - const char *label, CharDriverState *chr); -void omap_uart_reset(struct omap_uart_s *s); -void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); - -struct omap_mpuio_s; -qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); -void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); -void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); - -struct uWireSlave { - uint16_t (*receive)(void *opaque); - void (*send)(void *opaque, uint16_t data); - void *opaque; -}; -struct omap_uwire_s; -void omap_uwire_attach(struct omap_uwire_s *s, - uWireSlave *slave, int chipselect); - -/* OMAP2 spi */ -struct omap_mcspi_s; -struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, - qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); -void omap_mcspi_attach(struct omap_mcspi_s *s, - uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, - int chipselect); -void omap_mcspi_reset(struct omap_mcspi_s *s); - -struct I2SCodec { - void *opaque; - - /* The CPU can call this if it is generating the clock signal on the - * i2s port. The CODEC can ignore it if it is set up as a clock - * master and generates its own clock. */ - void (*set_rate)(void *opaque, int in, int out); - - void (*tx_swallow)(void *opaque); - qemu_irq rx_swallow; - qemu_irq tx_start; - - int tx_rate; - int cts; - int rx_rate; - int rts; - - struct i2s_fifo_s { - uint8_t *fifo; - int len; - int start; - int size; - } in, out; -}; -struct omap_mcbsp_s; -void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); - -void omap_tap_init(struct omap_target_agent_s *ta, - struct omap_mpu_state_s *mpu); - -/* omap_lcdc.c */ -struct omap_lcd_panel_s; -void omap_lcdc_reset(struct omap_lcd_panel_s *s); -struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, - hwaddr base, - qemu_irq irq, - struct omap_dma_lcd_channel_s *dma, - omap_clk clk); - -/* omap_dss.c */ -struct rfbi_chip_s { - void *opaque; - void (*write)(void *opaque, int dc, uint16_t value); - void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); - uint16_t (*read)(void *opaque, int dc); -}; -struct omap_dss_s; -void omap_dss_reset(struct omap_dss_s *s); -struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, - MemoryRegion *sysmem, - hwaddr l3_base, - qemu_irq irq, qemu_irq drq, - omap_clk fck1, omap_clk fck2, omap_clk ck54m, - omap_clk ick1, omap_clk ick2); -void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); - -/* omap_mmc.c */ -struct omap_mmc_s; -struct omap_mmc_s *omap_mmc_init(hwaddr base, - MemoryRegion *sysmem, - BlockBackend *blk, - qemu_irq irq, qemu_irq dma[], omap_clk clk); -struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, - BlockBackend *blk, qemu_irq irq, qemu_irq dma[], - omap_clk fclk, omap_clk iclk); -void omap_mmc_reset(struct omap_mmc_s *s); -void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); -void omap_mmc_enable(struct omap_mmc_s *s, int enable); - -/* omap_i2c.c */ -I2CBus *omap_i2c_bus(DeviceState *omap_i2c); - -# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) -# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) -# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) -# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) -# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) -# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) -# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) -# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) -# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) - -# define cpu_is_omap15xx(cpu) \ - (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) -# define cpu_is_omap16xx(cpu) \ - (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) -# define cpu_is_omap24xx(cpu) \ - (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) - -# define cpu_class_omap1(cpu) \ - (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) -# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) -# define cpu_class_omap3(cpu) \ - (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) - -struct omap_mpu_state_s { - enum omap_mpu_model { - omap310, - omap1510, - omap1610, - omap1710, - omap2410, - omap2420, - omap2422, - omap2423, - omap2430, - omap3430, - omap3630, - } mpu_model; - - ARMCPU *cpu; - - qemu_irq *drq; - - qemu_irq wakeup; - - MemoryRegion ulpd_pm_iomem; - MemoryRegion pin_cfg_iomem; - MemoryRegion id_iomem; - MemoryRegion id_iomem_e18; - MemoryRegion id_iomem_ed4; - MemoryRegion id_iomem_e20; - MemoryRegion mpui_iomem; - MemoryRegion tcmi_iomem; - MemoryRegion clkm_iomem; - MemoryRegion clkdsp_iomem; - MemoryRegion mpui_io_iomem; - MemoryRegion tap_iomem; - MemoryRegion imif_ram; - MemoryRegion emiff_ram; - MemoryRegion sdram; - MemoryRegion sram; - - struct omap_dma_port_if_s { - uint32_t (*read[3])(struct omap_mpu_state_s *s, - hwaddr offset); - void (*write[3])(struct omap_mpu_state_s *s, - hwaddr offset, uint32_t value); - int (*addr_valid)(struct omap_mpu_state_s *s, - hwaddr addr); - } port[__omap_dma_port_last]; - - unsigned long sdram_size; - unsigned long sram_size; - - /* MPUI-TIPB peripherals */ - struct omap_uart_s *uart[3]; - - DeviceState *gpio; - - struct omap_mcbsp_s *mcbsp1; - struct omap_mcbsp_s *mcbsp3; - - /* MPU public TIPB peripherals */ - struct omap_32khz_timer_s *os_timer; - - struct omap_mmc_s *mmc; - - struct omap_mpuio_s *mpuio; - - struct omap_uwire_s *microwire; - - struct omap_pwl_s *pwl; - struct omap_pwt_s *pwt; - DeviceState *i2c[2]; - - struct omap_rtc_s *rtc; - - struct omap_mcbsp_s *mcbsp2; - - struct omap_lpg_s *led[2]; - - /* MPU private TIPB peripherals */ - DeviceState *ih[2]; - - struct soc_dma_s *dma; - - struct omap_mpu_timer_s *timer[3]; - struct omap_watchdog_timer_s *wdt; - - struct omap_lcd_panel_s *lcd; - - uint32_t ulpd_pm_regs[21]; - int64_t ulpd_gauge_start; - - uint32_t func_mux_ctrl[14]; - uint32_t comp_mode_ctrl[1]; - uint32_t pull_dwn_ctrl[4]; - uint32_t gate_inh_ctrl[1]; - uint32_t voltage_ctrl[1]; - uint32_t test_dbg_ctrl[1]; - uint32_t mod_conf_ctrl[1]; - int compat1509; - - uint32_t mpui_ctrl; - - struct omap_tipb_bridge_s *private_tipb; - struct omap_tipb_bridge_s *public_tipb; - - uint32_t tcmi_regs[17]; - - struct dpll_ctl_s *dpll[3]; - - omap_clk clks; - struct { - int cold_start; - int clocking_scheme; - uint16_t arm_ckctl; - uint16_t arm_idlect1; - uint16_t arm_idlect2; - uint16_t arm_ewupct; - uint16_t arm_rstct1; - uint16_t arm_rstct2; - uint16_t arm_ckout1; - int dpll1_mode; - uint16_t dsp_idlect1; - uint16_t dsp_idlect2; - uint16_t dsp_rstct2; - } clkm; - - /* OMAP2-only peripherals */ - struct omap_l4_s *l4; - - struct omap_gp_timer_s *gptimer[12]; - struct omap_synctimer_s *synctimer; - - struct omap_prcm_s *prcm; - struct omap_sdrc_s *sdrc; - struct omap_gpmc_s *gpmc; - struct omap_sysctl_s *sysc; - - struct omap_mcspi_s *mcspi[2]; - - struct omap_dss_s *dss; - - struct omap_eac_s *eac; -}; - -/* omap1.c */ -struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, - unsigned long sdram_size, - const char *core); - -/* omap2.c */ -struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, - unsigned long sdram_size, - const char *core); - -#define OMAP_FMT_plx "%#08" HWADDR_PRIx - -uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); -void omap_badwidth_write8(void *opaque, hwaddr addr, - uint32_t value); -uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); -void omap_badwidth_write16(void *opaque, hwaddr addr, - uint32_t value); -uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); -void omap_badwidth_write32(void *opaque, hwaddr addr, - uint32_t value); - -void omap_mpu_wakeup(void *opaque, int irq, int req); - -# define OMAP_BAD_REG(paddr) \ - fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ - __FUNCTION__, paddr) -# define OMAP_RO_REG(paddr) \ - fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ - __FUNCTION__, paddr) - -/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area - (Board-specifc tags are not here) */ -#define OMAP_TAG_CLOCK 0x4f01 -#define OMAP_TAG_MMC 0x4f02 -#define OMAP_TAG_SERIAL_CONSOLE 0x4f03 -#define OMAP_TAG_USB 0x4f04 -#define OMAP_TAG_LCD 0x4f05 -#define OMAP_TAG_GPIO_SWITCH 0x4f06 -#define OMAP_TAG_UART 0x4f07 -#define OMAP_TAG_FBMEM 0x4f08 -#define OMAP_TAG_STI_CONSOLE 0x4f09 -#define OMAP_TAG_CAMERA_SENSOR 0x4f0a -#define OMAP_TAG_PARTITION 0x4f0b -#define OMAP_TAG_TEA5761 0x4f10 -#define OMAP_TAG_TMP105 0x4f11 -#define OMAP_TAG_BOOT_REASON 0x4f80 -#define OMAP_TAG_FLASH_PART_STR 0x4f81 -#define OMAP_TAG_VERSION_STR 0x4f82 - -enum { - OMAP_GPIOSW_TYPE_COVER = 0 << 4, - OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, - OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, -}; - -#define OMAP_GPIOSW_INVERTED 0x0001 -#define OMAP_GPIOSW_OUTPUT 0x0002 - -# define TCMI_VERBOSE 1 - -# ifdef TCMI_VERBOSE -# define OMAP_8B_REG(paddr) \ - fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ - __FUNCTION__, paddr) -# define OMAP_16B_REG(paddr) \ - fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ - __FUNCTION__, paddr) -# define OMAP_32B_REG(paddr) \ - fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ - __FUNCTION__, paddr) -# else -# define OMAP_8B_REG(paddr) -# define OMAP_16B_REG(paddr) -# define OMAP_32B_REG(paddr) -# endif - -# define OMAP_MPUI_REG_MASK 0x000007ff - -#endif /* hw_omap_h */ diff --git a/qemu/include/hw/arm/primecell.h b/qemu/include/hw/arm/primecell.h deleted file mode 100644 index 7337c3b3c..000000000 --- a/qemu/include/hw/arm/primecell.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef PRIMECELL_H -#define PRIMECELL_H - -/* Declarations for ARM PrimeCell based periperals. */ -/* Also includes some devices that are currently only used by the - ARM boards. */ - -/* arm_sysctl GPIO lines */ -#define ARM_SYSCTL_GPIO_MMC_WPROT 0 -#define ARM_SYSCTL_GPIO_MMC_CARDIN 1 - -#endif diff --git a/qemu/include/hw/arm/pxa.h b/qemu/include/hw/arm/pxa.h deleted file mode 100644 index 259b85249..000000000 --- a/qemu/include/hw/arm/pxa.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Intel XScale PXA255/270 processor support. - * - * Copyright (c) 2006 Openedhand Ltd. - * Written by Andrzej Zaborowski <balrog@zabor.org> - * - * This code is licensed under the GNU GPL v2. - */ -#ifndef PXA_H -# define PXA_H "pxa.h" - -#include "exec/memory.h" - -/* Interrupt numbers */ -# define PXA2XX_PIC_SSP3 0 -# define PXA2XX_PIC_USBH2 2 -# define PXA2XX_PIC_USBH1 3 -# define PXA2XX_PIC_KEYPAD 4 -# define PXA2XX_PIC_PWRI2C 6 -# define PXA25X_PIC_HWUART 7 -# define PXA27X_PIC_OST_4_11 7 -# define PXA2XX_PIC_GPIO_0 8 -# define PXA2XX_PIC_GPIO_1 9 -# define PXA2XX_PIC_GPIO_X 10 -# define PXA2XX_PIC_I2S 13 -# define PXA26X_PIC_ASSP 15 -# define PXA25X_PIC_NSSP 16 -# define PXA27X_PIC_SSP2 16 -# define PXA2XX_PIC_LCD 17 -# define PXA2XX_PIC_I2C 18 -# define PXA2XX_PIC_ICP 19 -# define PXA2XX_PIC_STUART 20 -# define PXA2XX_PIC_BTUART 21 -# define PXA2XX_PIC_FFUART 22 -# define PXA2XX_PIC_MMC 23 -# define PXA2XX_PIC_SSP 24 -# define PXA2XX_PIC_DMA 25 -# define PXA2XX_PIC_OST_0 26 -# define PXA2XX_PIC_RTC1HZ 30 -# define PXA2XX_PIC_RTCALARM 31 - -/* DMA requests */ -# define PXA2XX_RX_RQ_I2S 2 -# define PXA2XX_TX_RQ_I2S 3 -# define PXA2XX_RX_RQ_BTUART 4 -# define PXA2XX_TX_RQ_BTUART 5 -# define PXA2XX_RX_RQ_FFUART 6 -# define PXA2XX_TX_RQ_FFUART 7 -# define PXA2XX_RX_RQ_SSP1 13 -# define PXA2XX_TX_RQ_SSP1 14 -# define PXA2XX_RX_RQ_SSP2 15 -# define PXA2XX_TX_RQ_SSP2 16 -# define PXA2XX_RX_RQ_ICP 17 -# define PXA2XX_TX_RQ_ICP 18 -# define PXA2XX_RX_RQ_STUART 19 -# define PXA2XX_TX_RQ_STUART 20 -# define PXA2XX_RX_RQ_MMCI 21 -# define PXA2XX_TX_RQ_MMCI 22 -# define PXA2XX_USB_RQ(x) ((x) + 24) -# define PXA2XX_RX_RQ_SSP3 66 -# define PXA2XX_TX_RQ_SSP3 67 - -# define PXA2XX_SDRAM_BASE 0xa0000000 -# define PXA2XX_INTERNAL_BASE 0x5c000000 -# define PXA2XX_INTERNAL_SIZE 0x40000 - -/* pxa2xx_pic.c */ -DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu); - -/* pxa2xx_gpio.c */ -DeviceState *pxa2xx_gpio_init(hwaddr base, - ARMCPU *cpu, DeviceState *pic, int lines); -void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); - -/* pxa2xx_dma.c */ -DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq); -DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq); - -/* pxa2xx_lcd.c */ -typedef struct PXA2xxLCDState PXA2xxLCDState; -PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, - hwaddr base, qemu_irq irq); -void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); -void pxa2xx_lcdc_oritentation(void *opaque, int angle); - -/* pxa2xx_mmci.c */ -typedef struct PXA2xxMMCIState PXA2xxMMCIState; -PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, - hwaddr base, - BlockBackend *blk, qemu_irq irq, - qemu_irq rx_dma, qemu_irq tx_dma); -void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, - qemu_irq coverswitch); - -/* pxa2xx_pcmcia.c */ -typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, - hwaddr base); -int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); -int pxa2xx_pcmcia_detach(void *opaque); -void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); - -/* pxa2xx_keypad.c */ -struct keymap { - int8_t column; - int8_t row; -}; -typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; -PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem, - hwaddr base, - qemu_irq irq); -void pxa27x_register_keypad(PXA2xxKeyPadState *kp, - const struct keymap *map, int size); - -/* pxa2xx.c */ -typedef struct PXA2xxI2CState PXA2xxI2CState; -PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, - qemu_irq irq, uint32_t page_size); -I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s); - -typedef struct PXA2xxI2SState PXA2xxI2SState; -typedef struct PXA2xxFIrState PXA2xxFIrState; - -typedef struct { - ARMCPU *cpu; - DeviceState *pic; - qemu_irq reset; - MemoryRegion sdram; - MemoryRegion internal; - MemoryRegion cm_iomem; - MemoryRegion mm_iomem; - MemoryRegion pm_iomem; - DeviceState *dma; - DeviceState *gpio; - PXA2xxLCDState *lcd; - SSIBus **ssp; - PXA2xxI2CState *i2c[2]; - PXA2xxMMCIState *mmc; - PXA2xxPCMCIAState *pcmcia[2]; - PXA2xxI2SState *i2s; - PXA2xxFIrState *fir; - PXA2xxKeyPadState *kp; - - /* Power management */ - hwaddr pm_base; - uint32_t pm_regs[0x40]; - - /* Clock management */ - hwaddr cm_base; - uint32_t cm_regs[4]; - uint32_t clkcfg; - - /* Memory management */ - hwaddr mm_base; - uint32_t mm_regs[0x1a]; - - /* Performance monitoring */ - uint32_t pmnc; -} PXA2xxState; - -struct PXA2xxI2SState { - MemoryRegion iomem; - qemu_irq irq; - qemu_irq rx_dma; - qemu_irq tx_dma; - void (*data_req)(void *, int, int); - - uint32_t control[2]; - uint32_t status; - uint32_t mask; - uint32_t clk; - - int enable; - int rx_len; - int tx_len; - void (*codec_out)(void *, uint32_t); - uint32_t (*codec_in)(void *); - void *opaque; - - int fifo_len; - uint32_t fifo[16]; -}; - -# define PA_FMT "0x%08lx" -# define REG_FMT "0x" TARGET_FMT_plx - -PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, - const char *revision); -PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size); - -#endif /* PXA_H */ diff --git a/qemu/include/hw/arm/raspi_platform.h b/qemu/include/hw/arm/raspi_platform.h deleted file mode 100644 index 6467e88ae..000000000 --- a/qemu/include/hw/arm/raspi_platform.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines - * - * These definitions are derived from those in Raspbian Linux at - * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h - * where they carry the following notice: - * - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define MCORE_OFFSET 0x0000 /* Fake frame buffer device - * (the multicore sync block) */ -#define IC0_OFFSET 0x2000 -#define ST_OFFSET 0x3000 /* System Timer */ -#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */ -#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */ -#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */ -#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) -#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */ -#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ -#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores - * Doorbells & Mailboxes */ -#define PM_OFFSET 0x100000 /* Power Management, Reset controller - * and Watchdog registers */ -#define PCM_CLOCK_OFFSET 0x101098 -#define RNG_OFFSET 0x104000 -#define GPIO_OFFSET 0x200000 -#define UART0_OFFSET 0x201000 -#define MMCI0_OFFSET 0x202000 -#define I2S_OFFSET 0x203000 -#define SPI0_OFFSET 0x204000 -#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ -#define UART1_OFFSET 0x215000 -#define EMMC_OFFSET 0x300000 -#define SMI_OFFSET 0x600000 -#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */ -#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */ -#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */ - -/* GPU interrupts */ -#define INTERRUPT_TIMER0 0 -#define INTERRUPT_TIMER1 1 -#define INTERRUPT_TIMER2 2 -#define INTERRUPT_TIMER3 3 -#define INTERRUPT_CODEC0 4 -#define INTERRUPT_CODEC1 5 -#define INTERRUPT_CODEC2 6 -#define INTERRUPT_JPEG 7 -#define INTERRUPT_ISP 8 -#define INTERRUPT_USB 9 -#define INTERRUPT_3D 10 -#define INTERRUPT_TRANSPOSER 11 -#define INTERRUPT_MULTICORESYNC0 12 -#define INTERRUPT_MULTICORESYNC1 13 -#define INTERRUPT_MULTICORESYNC2 14 -#define INTERRUPT_MULTICORESYNC3 15 -#define INTERRUPT_DMA0 16 -#define INTERRUPT_DMA1 17 -#define INTERRUPT_DMA2 18 -#define INTERRUPT_DMA3 19 -#define INTERRUPT_DMA4 20 -#define INTERRUPT_DMA5 21 -#define INTERRUPT_DMA6 22 -#define INTERRUPT_DMA7 23 -#define INTERRUPT_DMA8 24 -#define INTERRUPT_DMA9 25 -#define INTERRUPT_DMA10 26 -#define INTERRUPT_DMA11 27 -#define INTERRUPT_DMA12 28 -#define INTERRUPT_AUX 29 -#define INTERRUPT_ARM 30 -#define INTERRUPT_VPUDMA 31 -#define INTERRUPT_HOSTPORT 32 -#define INTERRUPT_VIDEOSCALER 33 -#define INTERRUPT_CCP2TX 34 -#define INTERRUPT_SDC 35 -#define INTERRUPT_DSI0 36 -#define INTERRUPT_AVE 37 -#define INTERRUPT_CAM0 38 -#define INTERRUPT_CAM1 39 -#define INTERRUPT_HDMI0 40 -#define INTERRUPT_HDMI1 41 -#define INTERRUPT_PIXELVALVE1 42 -#define INTERRUPT_I2CSPISLV 43 -#define INTERRUPT_DSI1 44 -#define INTERRUPT_PWA0 45 -#define INTERRUPT_PWA1 46 -#define INTERRUPT_CPR 47 -#define INTERRUPT_SMI 48 -#define INTERRUPT_GPIO0 49 -#define INTERRUPT_GPIO1 50 -#define INTERRUPT_GPIO2 51 -#define INTERRUPT_GPIO3 52 -#define INTERRUPT_I2C 53 -#define INTERRUPT_SPI 54 -#define INTERRUPT_I2SPCM 55 -#define INTERRUPT_SDIO 56 -#define INTERRUPT_UART 57 -#define INTERRUPT_SLIMBUS 58 -#define INTERRUPT_VEC 59 -#define INTERRUPT_CPG 60 -#define INTERRUPT_RNG 61 -#define INTERRUPT_ARASANSDIO 62 -#define INTERRUPT_AVSPMON 63 - -/* ARM CPU IRQs use a private number space */ -#define INTERRUPT_ARM_TIMER 0 -#define INTERRUPT_ARM_MAILBOX 1 -#define INTERRUPT_ARM_DOORBELL_0 2 -#define INTERRUPT_ARM_DOORBELL_1 3 -#define INTERRUPT_VPU0_HALTED 4 -#define INTERRUPT_VPU1_HALTED 5 -#define INTERRUPT_ILLEGAL_TYPE0 6 -#define INTERRUPT_ILLEGAL_TYPE1 7 diff --git a/qemu/include/hw/arm/sharpsl.h b/qemu/include/hw/arm/sharpsl.h deleted file mode 100644 index 13981a6d0..000000000 --- a/qemu/include/hw/arm/sharpsl.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Common declarations for the Zaurii. - * - * This file is licensed under the GNU GPL. - */ -#ifndef QEMU_SHARPSL_H -#define QEMU_SHARPSL_H - -#define zaurus_printf(format, ...) \ - fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__) - -/* zaurus.c */ - -#define SL_PXA_PARAM_BASE 0xa0000a00 -void sl_bootparam_write(hwaddr ptr); - -#endif diff --git a/qemu/include/hw/arm/soc_dma.h b/qemu/include/hw/arm/soc_dma.h deleted file mode 100644 index 7379731af..000000000 --- a/qemu/include/hw/arm/soc_dma.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * On-chip DMA controller framework. - * - * Copyright (C) 2008 Nokia Corporation - * Written by Andrzej Zaborowski <andrew@openedhand.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 or - * (at your option) version 3 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef HW_SOC_DMA_H -#define HW_SOC_DMA_H 1 - - -#include "exec/memory.h" -#include "hw/irq.h" - -struct soc_dma_s; -struct soc_dma_ch_s; -typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len); -typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch); - -enum soc_dma_port_type { - soc_dma_port_mem, - soc_dma_port_fifo, - soc_dma_port_other, -}; - -enum soc_dma_access_type { - soc_dma_access_const, - soc_dma_access_linear, - soc_dma_access_other, -}; - -struct soc_dma_ch_s { - /* Private */ - struct soc_dma_s *dma; - int num; - QEMUTimer *timer; - - /* Set by soc_dma.c */ - int enable; - int update; - - /* This should be set by dma->setup_fn(). */ - int bytes; - /* Initialised by the DMA module, call soc_dma_ch_update after writing. */ - enum soc_dma_access_type type[2]; - hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ - /* Private */ - void *paddr[2]; - soc_dma_io_t io_fn[2]; - void *io_opaque[2]; - - int running; - soc_dma_transfer_t transfer_fn; - - /* Set and used by the DMA module. */ - void *opaque; -}; - -struct soc_dma_s { - /* Following fields are set by the SoC DMA module and can be used - * by anybody. */ - uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ - qemu_irq *drq; - void *opaque; - int64_t freq; - soc_dma_transfer_t transfer_fn; - soc_dma_transfer_t setup_fn; - /* Set by soc_dma_init() for use by the DMA module. */ - struct soc_dma_ch_s *ch; -}; - -/* Call to activate or stop a DMA channel. */ -void soc_dma_set_request(struct soc_dma_ch_s *ch, int level); -/* Call after every write to one of the following fields and before - * calling soc_dma_set_request(ch, 1): - * ch->type[0...1], - * ch->vaddr[0...1], - * ch->paddr[0...1], - * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */ -void soc_dma_ch_update(struct soc_dma_ch_s *ch); - -/* The SoC should call this when the DMA module is being reset. */ -void soc_dma_reset(struct soc_dma_s *s); -struct soc_dma_s *soc_dma_init(int n); - -void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base, - soc_dma_io_t fn, void *opaque, int out); -void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base, - hwaddr virt_base, size_t size); - -static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, - hwaddr virt_base, soc_dma_io_t fn, void *opaque) -{ - return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); -} - -static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, - hwaddr virt_base, soc_dma_io_t fn, void *opaque) -{ - return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); -} - -#endif diff --git a/qemu/include/hw/arm/stm32f205_soc.h b/qemu/include/hw/arm/stm32f205_soc.h deleted file mode 100644 index 0390eff80..000000000 --- a/qemu/include/hw/arm/stm32f205_soc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * STM32F205 SoC - * - * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef HW_ARM_STM32F205SOC_H -#define HW_ARM_STM32F205SOC_H - -#include "hw/misc/stm32f2xx_syscfg.h" -#include "hw/timer/stm32f2xx_timer.h" -#include "hw/char/stm32f2xx_usart.h" - -#define TYPE_STM32F205_SOC "stm32f205-soc" -#define STM32F205_SOC(obj) \ - OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC) - -#define STM_NUM_USARTS 6 -#define STM_NUM_TIMERS 4 - -#define FLASH_BASE_ADDRESS 0x08000000 -#define FLASH_SIZE (1024 * 1024) -#define SRAM_BASE_ADDRESS 0x20000000 -#define SRAM_SIZE (128 * 1024) - -typedef struct STM32F205State { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - char *kernel_filename; - char *cpu_model; - - STM32F2XXSyscfgState syscfg; - STM32F2XXUsartState usart[STM_NUM_USARTS]; - STM32F2XXTimerState timer[STM_NUM_TIMERS]; -} STM32F205State; - -#endif diff --git a/qemu/include/hw/arm/sysbus-fdt.h b/qemu/include/hw/arm/sysbus-fdt.h deleted file mode 100644 index e15bb8180..000000000 --- a/qemu/include/hw/arm/sysbus-fdt.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Dynamic sysbus device tree node generation API - * - * Copyright Linaro Limited, 2014 - * - * Authors: - * Alex Graf <agraf@suse.de> - * Eric Auger <eric.auger@linaro.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - * - */ - -#ifndef HW_ARM_SYSBUS_FDT_H -#define HW_ARM_SYSBUS_FDT_H - -#include "hw/arm/arm.h" -#include "qemu-common.h" -#include "hw/sysbus.h" - -/* - * struct that contains dimensioning parameters of the platform bus - */ -typedef struct { - hwaddr platform_bus_base; /* start address of the bus */ - hwaddr platform_bus_size; /* size of the bus */ - int platform_bus_first_irq; /* first hwirq assigned to the bus */ - int platform_bus_num_irqs; /* number of hwirq assigned to the bus */ -} ARMPlatformBusSystemParams; - -/* - * struct that contains all relevant info to build the fdt nodes of - * platform bus and attached dynamic sysbus devices - * in the future might be augmented with additional info - * such as PHY, CLK handles ... - */ -typedef struct { - const ARMPlatformBusSystemParams *system_params; - struct arm_boot_info *binfo; - const char *intc; /* parent interrupt controller name */ -} ARMPlatformBusFDTParams; - -/** - * arm_register_platform_bus_fdt_creator - register a machine init done - * notifier that creates the device tree nodes of the platform bus and - * associated dynamic sysbus devices - */ -void arm_register_platform_bus_fdt_creator(ARMPlatformBusFDTParams *fdt_params); - -#endif diff --git a/qemu/include/hw/arm/virt-acpi-build.h b/qemu/include/hw/arm/virt-acpi-build.h deleted file mode 100644 index 7d3700ebf..000000000 --- a/qemu/include/hw/arm/virt-acpi-build.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * - * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. - * - * Author: Shannon Zhao <zhaoshenglong@huawei.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef QEMU_VIRT_ACPI_BUILD_H -#define QEMU_VIRT_ACPI_BUILD_H - -#include "qemu-common.h" -#include "hw/arm/virt.h" - -#define ACPI_GICC_ENABLED 1 - -typedef struct VirtGuestInfo { - int smp_cpus; - FWCfgState *fw_cfg; - const MemMapEntry *memmap; - const int *irqmap; - bool use_highmem; - int gic_version; -} VirtGuestInfo; - - -typedef struct VirtGuestInfoState { - VirtGuestInfo info; - Notifier machine_done; -} VirtGuestInfoState; - -void virt_acpi_setup(VirtGuestInfo *guest_info); - -#endif diff --git a/qemu/include/hw/arm/virt.h b/qemu/include/hw/arm/virt.h deleted file mode 100644 index ecd858960..000000000 --- a/qemu/include/hw/arm/virt.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * - * Copyright (c) 2015 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - * - * Emulate a virtual board which works by passing Linux all the information - * it needs about what devices are present via the device tree. - * There are some restrictions about what we can do here: - * + we can only present devices whose Linux drivers will work based - * purely on the device tree with no platform data at all - * + we want to present a very stripped-down minimalist platform, - * both because this reduces the security attack surface from the guest - * and also because it reduces our exposure to being broken when - * the kernel updates its device tree bindings and requires further - * information in a device binding that we aren't providing. - * This is essentially the same approach kvmtool uses. - */ - -#ifndef QEMU_ARM_VIRT_H -#define QEMU_ARM_VIRT_H - -#include "qemu-common.h" - -#define NUM_GICV2M_SPIS 64 -#define NUM_VIRTIO_TRANSPORTS 32 - -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 - -enum { - VIRT_FLASH, - VIRT_MEM, - VIRT_CPUPERIPHS, - VIRT_GIC_DIST, - VIRT_GIC_CPU, - VIRT_GIC_V2M, - VIRT_GIC_ITS, - VIRT_GIC_REDIST, - VIRT_UART, - VIRT_MMIO, - VIRT_RTC, - VIRT_FW_CFG, - VIRT_PCIE, - VIRT_PCIE_MMIO, - VIRT_PCIE_PIO, - VIRT_PCIE_ECAM, - VIRT_PLATFORM_BUS, - VIRT_PCIE_MMIO_HIGH, - VIRT_GPIO, - VIRT_SECURE_UART, - VIRT_SECURE_MEM, -}; - -typedef struct MemMapEntry { - hwaddr base; - hwaddr size; -} MemMapEntry; - - -#endif diff --git a/qemu/include/hw/arm/xlnx-zynqmp.h b/qemu/include/hw/arm/xlnx-zynqmp.h deleted file mode 100644 index 2332596b4..000000000 --- a/qemu/include/hw/arm/xlnx-zynqmp.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Xilinx Zynq MPSoC emulation - * - * Copyright (C) 2015 Xilinx Inc - * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#ifndef XLNX_ZYNQMP_H - -#include "qemu-common.h" -#include "hw/arm/arm.h" -#include "hw/intc/arm_gic.h" -#include "hw/net/cadence_gem.h" -#include "hw/char/cadence_uart.h" -#include "hw/ide/pci.h" -#include "hw/ide/ahci.h" -#include "hw/sd/sdhci.h" -#include "hw/ssi/xilinx_spips.h" - -#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" -#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ - TYPE_XLNX_ZYNQMP) - -#define XLNX_ZYNQMP_NUM_APU_CPUS 4 -#define XLNX_ZYNQMP_NUM_RPU_CPUS 2 -#define XLNX_ZYNQMP_NUM_GEMS 4 -#define XLNX_ZYNQMP_NUM_UARTS 2 -#define XLNX_ZYNQMP_NUM_SDHCI 2 -#define XLNX_ZYNQMP_NUM_SPIS 2 - -#define XLNX_ZYNQMP_NUM_OCM_BANKS 4 -#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 -#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 - -#define XLNX_ZYNQMP_GIC_REGIONS 2 - -/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets - * and under-decodes the 64k region. This mirrors the 4k regions to every 4k - * aligned address in the 64k region. To implement each GIC region needs a - * number of memory region aliases. - */ - -#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 -#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) - -#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull - -#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull -#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull - -#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ - XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) - -typedef struct XlnxZynqMPState { - /*< private >*/ - DeviceState parent_obj; - - /*< public >*/ - ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; - ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; - GICState gic; - MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; - - MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; - - MemoryRegion *ddr_ram; - MemoryRegion ddr_ram_low, ddr_ram_high; - - CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; - CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; - SysbusAHCIState sata; - SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; - XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; - - char *boot_cpu; - ARMCPU *boot_cpu_ptr; -} XlnxZynqMPState; - -#define XLNX_ZYNQMP_H -#endif |