diff options
author | 2017-04-25 03:31:15 -0700 | |
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committer | 2017-05-22 06:48:08 +0000 | |
commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/include/hw/arm/xlnx-zynqmp.h | |
parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/include/hw/arm/xlnx-zynqmp.h')
-rw-r--r-- | qemu/include/hw/arm/xlnx-zynqmp.h | 90 |
1 files changed, 0 insertions, 90 deletions
diff --git a/qemu/include/hw/arm/xlnx-zynqmp.h b/qemu/include/hw/arm/xlnx-zynqmp.h deleted file mode 100644 index 2332596b4..000000000 --- a/qemu/include/hw/arm/xlnx-zynqmp.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Xilinx Zynq MPSoC emulation - * - * Copyright (C) 2015 Xilinx Inc - * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#ifndef XLNX_ZYNQMP_H - -#include "qemu-common.h" -#include "hw/arm/arm.h" -#include "hw/intc/arm_gic.h" -#include "hw/net/cadence_gem.h" -#include "hw/char/cadence_uart.h" -#include "hw/ide/pci.h" -#include "hw/ide/ahci.h" -#include "hw/sd/sdhci.h" -#include "hw/ssi/xilinx_spips.h" - -#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" -#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ - TYPE_XLNX_ZYNQMP) - -#define XLNX_ZYNQMP_NUM_APU_CPUS 4 -#define XLNX_ZYNQMP_NUM_RPU_CPUS 2 -#define XLNX_ZYNQMP_NUM_GEMS 4 -#define XLNX_ZYNQMP_NUM_UARTS 2 -#define XLNX_ZYNQMP_NUM_SDHCI 2 -#define XLNX_ZYNQMP_NUM_SPIS 2 - -#define XLNX_ZYNQMP_NUM_OCM_BANKS 4 -#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 -#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 - -#define XLNX_ZYNQMP_GIC_REGIONS 2 - -/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets - * and under-decodes the 64k region. This mirrors the 4k regions to every 4k - * aligned address in the 64k region. To implement each GIC region needs a - * number of memory region aliases. - */ - -#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 -#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) - -#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull - -#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull -#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull - -#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ - XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) - -typedef struct XlnxZynqMPState { - /*< private >*/ - DeviceState parent_obj; - - /*< public >*/ - ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; - ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; - GICState gic; - MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; - - MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; - - MemoryRegion *ddr_ram; - MemoryRegion ddr_ram_low, ddr_ram_high; - - CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; - CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; - SysbusAHCIState sata; - SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; - XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; - - char *boot_cpu; - ARMCPU *boot_cpu_ptr; -} XlnxZynqMPState; - -#define XLNX_ZYNQMP_H -#endif |