diff options
author | 2017-04-25 03:31:15 -0700 | |
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committer | 2017-05-22 06:48:08 +0000 | |
commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/hw/timer/aspeed_timer.c | |
parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/hw/timer/aspeed_timer.c')
-rw-r--r-- | qemu/hw/timer/aspeed_timer.c | 449 |
1 files changed, 0 insertions, 449 deletions
diff --git a/qemu/hw/timer/aspeed_timer.c b/qemu/hw/timer/aspeed_timer.c deleted file mode 100644 index 51e8303cd..000000000 --- a/qemu/hw/timer/aspeed_timer.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * ASPEED AST2400 Timer - * - * Andrew Jeffery <andrew@aj.id.au> - * - * Copyright (C) 2016 IBM Corp. - * - * This code is licensed under the GPL version 2 or later. See - * the COPYING file in the top-level directory. - */ - -#include "qemu/osdep.h" -#include "hw/ptimer.h" -#include "hw/sysbus.h" -#include "hw/timer/aspeed_timer.h" -#include "qemu-common.h" -#include "qemu/bitops.h" -#include "qemu/main-loop.h" -#include "qemu/timer.h" -#include "trace.h" - -#define TIMER_NR_REGS 4 - -#define TIMER_CTRL_BITS 4 -#define TIMER_CTRL_MASK ((1 << TIMER_CTRL_BITS) - 1) - -#define TIMER_CLOCK_USE_EXT true -#define TIMER_CLOCK_EXT_HZ 1000000 -#define TIMER_CLOCK_USE_APB false -#define TIMER_CLOCK_APB_HZ 24000000 - -#define TIMER_REG_STATUS 0 -#define TIMER_REG_RELOAD 1 -#define TIMER_REG_MATCH_FIRST 2 -#define TIMER_REG_MATCH_SECOND 3 - -#define TIMER_FIRST_CAP_PULSE 4 - -enum timer_ctrl_op { - op_enable = 0, - op_external_clock, - op_overflow_interrupt, - op_pulse_enable -}; - -/** - * Avoid mutual references between AspeedTimerCtrlState and AspeedTimer - * structs, as it's a waste of memory. The ptimer BH callback needs to know - * whether a specific AspeedTimer is enabled, but this information is held in - * AspeedTimerCtrlState. So, provide a helper to hoist ourselves from an - * arbitrary AspeedTimer to AspeedTimerCtrlState. - */ -static inline AspeedTimerCtrlState *timer_to_ctrl(AspeedTimer *t) -{ - const AspeedTimer (*timers)[] = (void *)t - (t->id * sizeof(*t)); - return container_of(timers, AspeedTimerCtrlState, timers); -} - -static inline bool timer_ctrl_status(AspeedTimer *t, enum timer_ctrl_op op) -{ - return !!(timer_to_ctrl(t)->ctrl & BIT(t->id * TIMER_CTRL_BITS + op)); -} - -static inline bool timer_enabled(AspeedTimer *t) -{ - return timer_ctrl_status(t, op_enable); -} - -static inline bool timer_overflow_interrupt(AspeedTimer *t) -{ - return timer_ctrl_status(t, op_overflow_interrupt); -} - -static inline bool timer_can_pulse(AspeedTimer *t) -{ - return t->id >= TIMER_FIRST_CAP_PULSE; -} - -static void aspeed_timer_expire(void *opaque) -{ - AspeedTimer *t = opaque; - - /* Only support interrupts on match values of zero for the moment - this is - * sufficient to boot an aspeed_defconfig Linux kernel. - * - * TODO: matching on arbitrary values (see e.g. hw/timer/a9gtimer.c) - */ - bool match = !(t->match[0] && t->match[1]); - bool interrupt = timer_overflow_interrupt(t) || match; - if (timer_enabled(t) && interrupt) { - t->level = !t->level; - qemu_set_irq(t->irq, t->level); - } -} - -static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) -{ - uint64_t value; - - switch (reg) { - case TIMER_REG_STATUS: - value = ptimer_get_count(t->timer); - break; - case TIMER_REG_RELOAD: - value = t->reload; - break; - case TIMER_REG_MATCH_FIRST: - case TIMER_REG_MATCH_SECOND: - value = t->match[reg - 2]; - break; - default: - qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n", - __func__, reg); - value = 0; - break; - } - return value; -} - -static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size) -{ - AspeedTimerCtrlState *s = opaque; - const int reg = (offset & 0xf) / 4; - uint64_t value; - - switch (offset) { - case 0x30: /* Control Register */ - value = s->ctrl; - break; - case 0x34: /* Control Register 2 */ - value = s->ctrl2; - break; - case 0x00 ... 0x2c: /* Timers 1 - 4 */ - value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); - break; - case 0x40 ... 0x8c: /* Timers 5 - 8 */ - value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); - break; - /* Illegal */ - case 0x38: - case 0x3C: - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", - __func__, offset); - value = 0; - break; - } - trace_aspeed_timer_read(offset, size, value); - return value; -} - -static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, - uint32_t value) -{ - AspeedTimer *t; - - trace_aspeed_timer_set_value(timer, reg, value); - t = &s->timers[timer]; - switch (reg) { - case TIMER_REG_STATUS: - if (timer_enabled(t)) { - ptimer_set_count(t->timer, value); - } - break; - case TIMER_REG_RELOAD: - t->reload = value; - ptimer_set_limit(t->timer, value, 1); - break; - case TIMER_REG_MATCH_FIRST: - case TIMER_REG_MATCH_SECOND: - if (value) { - /* Non-zero match values are unsupported. As such an interrupt will - * always be triggered when the timer reaches zero even if the - * overflow interrupt control bit is clear. - */ - qemu_log_mask(LOG_UNIMP, "%s: Match value unsupported by device: " - "0x%" PRIx32 "\n", __func__, value); - } else { - t->match[reg - 2] = value; - } - break; - default: - qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n", - __func__, reg); - break; - } -} - -/* Control register operations are broken out into helpers that can be - * explictly called on aspeed_timer_reset(), but also from - * aspeed_timer_ctrl_op(). - */ - -static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable) -{ - trace_aspeed_timer_ctrl_enable(t->id, enable); - if (enable) { - ptimer_run(t->timer, 0); - } else { - ptimer_stop(t->timer); - ptimer_set_limit(t->timer, t->reload, 1); - } -} - -static void aspeed_timer_ctrl_external_clock(AspeedTimer *t, bool enable) -{ - trace_aspeed_timer_ctrl_external_clock(t->id, enable); - if (enable) { - ptimer_set_freq(t->timer, TIMER_CLOCK_EXT_HZ); - } else { - ptimer_set_freq(t->timer, TIMER_CLOCK_APB_HZ); - } -} - -static void aspeed_timer_ctrl_overflow_interrupt(AspeedTimer *t, bool enable) -{ - trace_aspeed_timer_ctrl_overflow_interrupt(t->id, enable); -} - -static void aspeed_timer_ctrl_pulse_enable(AspeedTimer *t, bool enable) -{ - if (timer_can_pulse(t)) { - trace_aspeed_timer_ctrl_pulse_enable(t->id, enable); - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Timer does not support pulse mode\n", __func__); - } -} - -/** - * Given the actions are fixed in number and completely described in helper - * functions, dispatch with a lookup table rather than manage control flow with - * a switch statement. - */ -static void (*const ctrl_ops[])(AspeedTimer *, bool) = { - [op_enable] = aspeed_timer_ctrl_enable, - [op_external_clock] = aspeed_timer_ctrl_external_clock, - [op_overflow_interrupt] = aspeed_timer_ctrl_overflow_interrupt, - [op_pulse_enable] = aspeed_timer_ctrl_pulse_enable, -}; - -/** - * Conditionally affect changes chosen by a timer's control bit. - * - * The aspeed_timer_ctrl_op() interface is convenient for the - * aspeed_timer_set_ctrl() function as the "no change" early exit can be - * calculated for all operations, which cleans up the caller code. However the - * interface isn't convenient for the reset function where we want to enter a - * specific state without artificially constructing old and new values that - * will fall through the change guard (and motivates extracting the actions - * out to helper functions). - * - * @t: The timer to manipulate - * @op: The type of operation to be performed - * @old: The old state of the timer's control bits - * @new: The incoming state for the timer's control bits - */ -static void aspeed_timer_ctrl_op(AspeedTimer *t, enum timer_ctrl_op op, - uint8_t old, uint8_t new) -{ - const uint8_t mask = BIT(op); - const bool enable = !!(new & mask); - const bool changed = ((old ^ new) & mask); - if (!changed) { - return; - } - ctrl_ops[op](t, enable); -} - -static void aspeed_timer_set_ctrl(AspeedTimerCtrlState *s, uint32_t reg) -{ - int i; - int shift; - uint8_t t_old, t_new; - AspeedTimer *t; - const uint8_t enable_mask = BIT(op_enable); - - /* Handle a dependency between the 'enable' and remaining three - * configuration bits - i.e. if more than one bit in the control set has - * changed, including the 'enable' bit, then we want either disable the - * timer and perform configuration, or perform configuration and then - * enable the timer - */ - for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - t = &s->timers[i]; - shift = (i * TIMER_CTRL_BITS); - t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; - t_new = (reg >> shift) & TIMER_CTRL_MASK; - - /* If we are disabling, do so first */ - if ((t_old & enable_mask) && !(t_new & enable_mask)) { - aspeed_timer_ctrl_enable(t, false); - } - aspeed_timer_ctrl_op(t, op_external_clock, t_old, t_new); - aspeed_timer_ctrl_op(t, op_overflow_interrupt, t_old, t_new); - aspeed_timer_ctrl_op(t, op_pulse_enable, t_old, t_new); - /* If we are enabling, do so last */ - if (!(t_old & enable_mask) && (t_new & enable_mask)) { - aspeed_timer_ctrl_enable(t, true); - } - } - s->ctrl = reg; -} - -static void aspeed_timer_set_ctrl2(AspeedTimerCtrlState *s, uint32_t value) -{ - trace_aspeed_timer_set_ctrl2(value); -} - -static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) -{ - const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); - const int reg = (offset & 0xf) / 4; - AspeedTimerCtrlState *s = opaque; - - switch (offset) { - /* Control Registers */ - case 0x30: - aspeed_timer_set_ctrl(s, tv); - break; - case 0x34: - aspeed_timer_set_ctrl2(s, tv); - break; - /* Timer Registers */ - case 0x00 ... 0x2c: - aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv); - break; - case 0x40 ... 0x8c: - aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv); - break; - /* Illegal */ - case 0x38: - case 0x3C: - default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", - __func__, offset); - break; - } -} - -static const MemoryRegionOps aspeed_timer_ops = { - .read = aspeed_timer_read, - .write = aspeed_timer_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid.min_access_size = 4, - .valid.max_access_size = 4, - .valid.unaligned = false, -}; - -static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) -{ - QEMUBH *bh; - AspeedTimer *t = &s->timers[id]; - - t->id = id; - bh = qemu_bh_new(aspeed_timer_expire, t); - t->timer = ptimer_init(bh); -} - -static void aspeed_timer_realize(DeviceState *dev, Error **errp) -{ - int i; - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - AspeedTimerCtrlState *s = ASPEED_TIMER(dev); - - for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - aspeed_init_one_timer(s, i); - sysbus_init_irq(sbd, &s->timers[i].irq); - } - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_timer_ops, s, - TYPE_ASPEED_TIMER, 0x1000); - sysbus_init_mmio(sbd, &s->iomem); -} - -static void aspeed_timer_reset(DeviceState *dev) -{ - int i; - AspeedTimerCtrlState *s = ASPEED_TIMER(dev); - - for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { - AspeedTimer *t = &s->timers[i]; - /* Explictly call helpers to avoid any conditional behaviour through - * aspeed_timer_set_ctrl(). - */ - aspeed_timer_ctrl_enable(t, false); - aspeed_timer_ctrl_external_clock(t, TIMER_CLOCK_USE_APB); - aspeed_timer_ctrl_overflow_interrupt(t, false); - aspeed_timer_ctrl_pulse_enable(t, false); - t->level = 0; - t->reload = 0; - t->match[0] = 0; - t->match[1] = 0; - } - s->ctrl = 0; - s->ctrl2 = 0; -} - -static const VMStateDescription vmstate_aspeed_timer = { - .name = "aspeed.timer", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT8(id, AspeedTimer), - VMSTATE_INT32(level, AspeedTimer), - VMSTATE_PTIMER(timer, AspeedTimer), - VMSTATE_UINT32(reload, AspeedTimer), - VMSTATE_UINT32_ARRAY(match, AspeedTimer, 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_aspeed_timer_state = { - .name = "aspeed.timerctrl", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), - VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), - VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, - ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer, - AspeedTimer), - VMSTATE_END_OF_LIST() - } -}; - -static void timer_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = aspeed_timer_realize; - dc->reset = aspeed_timer_reset; - dc->desc = "ASPEED Timer"; - dc->vmsd = &vmstate_aspeed_timer_state; -} - -static const TypeInfo aspeed_timer_info = { - .name = TYPE_ASPEED_TIMER, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AspeedTimerCtrlState), - .class_init = timer_class_init, -}; - -static void aspeed_timer_register_types(void) -{ - type_register_static(&aspeed_timer_info); -} - -type_init(aspeed_timer_register_types) |