diff options
author | 2017-04-25 03:31:15 -0700 | |
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committer | 2017-05-22 06:48:08 +0000 | |
commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/hw/char/stm32f2xx_usart.c | |
parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/hw/char/stm32f2xx_usart.c')
-rw-r--r-- | qemu/hw/char/stm32f2xx_usart.c | 233 |
1 files changed, 0 insertions, 233 deletions
diff --git a/qemu/hw/char/stm32f2xx_usart.c b/qemu/hw/char/stm32f2xx_usart.c deleted file mode 100644 index a94d61ceb..000000000 --- a/qemu/hw/char/stm32f2xx_usart.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * STM32F2XX USART - * - * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/char/stm32f2xx_usart.h" - -#ifndef STM_USART_ERR_DEBUG -#define STM_USART_ERR_DEBUG 0 -#endif - -#define DB_PRINT_L(lvl, fmt, args...) do { \ - if (STM_USART_ERR_DEBUG >= lvl) { \ - qemu_log("%s: " fmt, __func__, ## args); \ - } \ -} while (0); - -#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) - -static int stm32f2xx_usart_can_receive(void *opaque) -{ - STM32F2XXUsartState *s = opaque; - - if (!(s->usart_sr & USART_SR_RXNE)) { - return 1; - } - - return 0; -} - -static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size) -{ - STM32F2XXUsartState *s = opaque; - - s->usart_dr = *buf; - - if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) { - /* USART not enabled - drop the chars */ - DB_PRINT("Dropping the chars\n"); - return; - } - - s->usart_sr |= USART_SR_RXNE; - - if (s->usart_cr1 & USART_CR1_RXNEIE) { - qemu_set_irq(s->irq, 1); - } - - DB_PRINT("Receiving: %c\n", s->usart_dr); -} - -static void stm32f2xx_usart_reset(DeviceState *dev) -{ - STM32F2XXUsartState *s = STM32F2XX_USART(dev); - - s->usart_sr = USART_SR_RESET; - s->usart_dr = 0x00000000; - s->usart_brr = 0x00000000; - s->usart_cr1 = 0x00000000; - s->usart_cr2 = 0x00000000; - s->usart_cr3 = 0x00000000; - s->usart_gtpr = 0x00000000; - - qemu_set_irq(s->irq, 0); -} - -static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, - unsigned int size) -{ - STM32F2XXUsartState *s = opaque; - uint64_t retvalue; - - DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); - - switch (addr) { - case USART_SR: - retvalue = s->usart_sr; - s->usart_sr &= ~USART_SR_TC; - if (s->chr) { - qemu_chr_accept_input(s->chr); - } - return retvalue; - case USART_DR: - DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); - s->usart_sr |= USART_SR_TXE; - s->usart_sr &= ~USART_SR_RXNE; - if (s->chr) { - qemu_chr_accept_input(s->chr); - } - qemu_set_irq(s->irq, 0); - return s->usart_dr & 0x3FF; - case USART_BRR: - return s->usart_brr; - case USART_CR1: - return s->usart_cr1; - case USART_CR2: - return s->usart_cr2; - case USART_CR3: - return s->usart_cr3; - case USART_GTPR: - return s->usart_gtpr; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); - return 0; - } - - return 0; -} - -static void stm32f2xx_usart_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) -{ - STM32F2XXUsartState *s = opaque; - uint32_t value = val64; - unsigned char ch; - - DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr); - - switch (addr) { - case USART_SR: - if (value <= 0x3FF) { - s->usart_sr = value; - } else { - s->usart_sr &= value; - } - if (!(s->usart_sr & USART_SR_RXNE)) { - qemu_set_irq(s->irq, 0); - } - return; - case USART_DR: - if (value < 0xF000) { - ch = value; - if (s->chr) { - qemu_chr_fe_write_all(s->chr, &ch, 1); - } - s->usart_sr |= USART_SR_TC; - s->usart_sr &= ~USART_SR_TXE; - } - return; - case USART_BRR: - s->usart_brr = value; - return; - case USART_CR1: - s->usart_cr1 = value; - if (s->usart_cr1 & USART_CR1_RXNEIE && - s->usart_sr & USART_SR_RXNE) { - qemu_set_irq(s->irq, 1); - } - return; - case USART_CR2: - s->usart_cr2 = value; - return; - case USART_CR3: - s->usart_cr3 = value; - return; - case USART_GTPR: - s->usart_gtpr = value; - return; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); - } -} - -static const MemoryRegionOps stm32f2xx_usart_ops = { - .read = stm32f2xx_usart_read, - .write = stm32f2xx_usart_write, - .endianness = DEVICE_NATIVE_ENDIAN, -}; - -static void stm32f2xx_usart_init(Object *obj) -{ - STM32F2XXUsartState *s = STM32F2XX_USART(obj); - - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, - TYPE_STM32F2XX_USART, 0x2000); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); - - /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */ - s->chr = qemu_char_get_next_serial(); - - if (s->chr) { - qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive, - stm32f2xx_usart_receive, NULL, s); - } -} - -static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->reset = stm32f2xx_usart_reset; - /* Reason: instance_init() method uses qemu_char_get_next_serial() */ - dc->cannot_instantiate_with_device_add_yet = true; -} - -static const TypeInfo stm32f2xx_usart_info = { - .name = TYPE_STM32F2XX_USART, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(STM32F2XXUsartState), - .instance_init = stm32f2xx_usart_init, - .class_init = stm32f2xx_usart_class_init, -}; - -static void stm32f2xx_usart_register_types(void) -{ - type_register_static(&stm32f2xx_usart_info); -} - -type_init(stm32f2xx_usart_register_types) |