diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/gdb-xml/arm-vfp3.xml | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/gdb-xml/arm-vfp3.xml')
| -rw-r--r-- | qemu/gdb-xml/arm-vfp3.xml | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/qemu/gdb-xml/arm-vfp3.xml b/qemu/gdb-xml/arm-vfp3.xml new file mode 100644 index 000000000..227afd801 --- /dev/null +++ b/qemu/gdb-xml/arm-vfp3.xml @@ -0,0 +1,45 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2008 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.arm.vfp"> + <reg name="d0" bitsize="64" type="float"/> + <reg name="d1" bitsize="64" type="float"/> + <reg name="d2" bitsize="64" type="float"/> + <reg name="d3" bitsize="64" type="float"/> + <reg name="d4" bitsize="64" type="float"/> + <reg name="d5" bitsize="64" type="float"/> + <reg name="d6" bitsize="64" type="float"/> + <reg name="d7" bitsize="64" type="float"/> + <reg name="d8" bitsize="64" type="float"/> + <reg name="d9" bitsize="64" type="float"/> + <reg name="d10" bitsize="64" type="float"/> + <reg name="d11" bitsize="64" type="float"/> + <reg name="d12" bitsize="64" type="float"/> + <reg name="d13" bitsize="64" type="float"/> + <reg name="d14" bitsize="64" type="float"/> + <reg name="d15" bitsize="64" type="float"/> + <reg name="d16" bitsize="64" type="float"/> + <reg name="d17" bitsize="64" type="float"/> + <reg name="d18" bitsize="64" type="float"/> + <reg name="d19" bitsize="64" type="float"/> + <reg name="d20" bitsize="64" type="float"/> + <reg name="d21" bitsize="64" type="float"/> + <reg name="d22" bitsize="64" type="float"/> + <reg name="d23" bitsize="64" type="float"/> + <reg name="d24" bitsize="64" type="float"/> + <reg name="d25" bitsize="64" type="float"/> + <reg name="d26" bitsize="64" type="float"/> + <reg name="d27" bitsize="64" type="float"/> + <reg name="d28" bitsize="64" type="float"/> + <reg name="d29" bitsize="64" type="float"/> + <reg name="d30" bitsize="64" type="float"/> + <reg name="d31" bitsize="64" type="float"/> + + <reg name="fpsid" bitsize="32" type="int" group="float"/> + <reg name="fpscr" bitsize="32" type="int" group="float"/> + <reg name="fpexc" bitsize="32" type="int" group="float"/> +</feature> |