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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/dtc/tests/base01.dts
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/dtc/tests/base01.dts')
-rw-r--r--qemu/dtc/tests/base01.dts33
1 files changed, 33 insertions, 0 deletions
diff --git a/qemu/dtc/tests/base01.dts b/qemu/dtc/tests/base01.dts
new file mode 100644
index 000000000..97a5dd50b
--- /dev/null
+++ b/qemu/dtc/tests/base01.dts
@@ -0,0 +1,33 @@
+/dts-v1/;
+
+/ {
+ model = "SomeModel";
+ compatible = "Nothing";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ d10 = < 10>; // hex: 0xa
+ d23 = < 23>; // hex: 0x17
+ b101 = < 0x5>; // hex: 0x5
+ o17 = < 017>; // hex: 0xf
+ hd00d = < 0xd00d>; // hex: 0xd00d
+
+ // hex: 0x4d2 0x163e 0x2334 0xd80
+ stuff = < 1234 5678 9012 3456>;
+
+
+ bad-d-1 = < 0>; // Hrm. 0
+ bad-d-2 = < 123456789012345>;
+ bad-o-1 = < 00>;
+ bad-o-2 = < 0123456123456>;
+ };
+
+};