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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/docs/specs/standard-vga.txt
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
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+
+QEMU Standard VGA
+=================
+
+Exists in two variants, for isa and pci.
+
+command line switches:
+ -vga std [ picks isa for -M isapc, otherwise pci ]
+ -device VGA [ pci variant ]
+ -device isa-vga [ isa variant ]
+ -device secondary-vga [ legacy-free pci variant ]
+
+
+PCI spec
+--------
+
+Applies to the pci variant only for obvious reasons.
+
+PCI ID: 1234:1111
+
+PCI Region 0:
+ Framebuffer memory, 16 MB in size (by default).
+ Size is tunable via vga_mem_mb property.
+
+PCI Region 1:
+ Reserved (so we have the option to make the framebuffer bar 64bit).
+
+PCI Region 2:
+ MMIO bar, 4096 bytes in size (qemu 1.3+)
+
+PCI ROM Region:
+ Holds the vgabios (qemu 0.14+).
+
+
+The legacy-free variant has no ROM and has PCI_CLASS_DISPLAY_OTHER
+instead of PCI_CLASS_DISPLAY_VGA.
+
+
+IO ports used
+-------------
+
+Doesn't apply to the legacy-free pci variant, use the MMIO bar instead.
+
+03c0 - 03df : standard vga ports
+01ce : bochs vbe interface index port
+01cf : bochs vbe interface data port (x86 only)
+01d0 : bochs vbe interface data port
+
+
+Memory regions used
+-------------------
+
+0xe0000000 : Framebuffer memory, isa variant only.
+
+The pci variant used to mirror the framebuffer bar here, qemu 0.14+
+stops doing that (except when in -M pc-$old compat mode).
+
+
+MMIO area spec
+--------------
+
+Likewise applies to the pci variant only for obvious reasons.
+
+0000 - 03ff : reserved, for possible virtio extension.
+0400 - 041f : vga ioports (0x3c0 -> 0x3df), remapped 1:1.
+ word access is supported, bytes are written
+ in little endia order (aka index port first),
+ so indexed registers can be updated with a
+ single mmio write (and thus only one vmexit).
+0500 - 0515 : bochs dispi interface registers, mapped flat
+ without index/data ports. Use (index << 1)
+ as offset for (16bit) register access.
+
+0600 - 0607 : qemu extended registers. qemu 2.2+ only.
+ The pci revision is 2 (or greater) when
+ these registers are present. The registers
+ are 32bit.
+ 0600 : qemu extended register region size, in bytes.
+ 0604 : framebuffer endianness register.
+ - 0xbebebebe indicates big endian.
+ - 0x1e1e1e1e indicates little endian.