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| author |   Don Dugger <n0ano@n0ano.com> | 2016-06-03 03:33:22 +0000 |
|---|---|---|
| committer |   Gerrit Code Review <gerrit@172.30.200.206> | 2016-06-03 03:33:23 +0000 |
| commit | da27230f80795d0028333713f036d44c53cb0e68 (patch) | |
| tree | b3d379eaf000adf72b36cb01cdf4d79c3e3f064c /qemu/disas/mips.c | |
| parent | 0e68cb048bb8aadb14675f5d4286d8ab2fc35449 (diff) | |
| parent | 437fd90c0250dee670290f9b714253671a990160 (diff) | |
Merge "These changes are the raw update to qemu-2.6."
Diffstat (limited to 'qemu/disas/mips.c')
| -rw-r--r-- | qemu/disas/mips.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/qemu/disas/mips.c b/qemu/disas/mips.c index 01336a838..249931b73 100644 --- a/qemu/disas/mips.c +++ b/qemu/disas/mips.c @@ -19,6 +19,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ +#include "qemu/osdep.h" #include "disas/bfd.h" /* mips.h. Mips opcode list for GDB, the GNU debugger. @@ -1404,6 +1405,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, {"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, {"cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, +{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I32R6}, +{"dvp", "t", 0x41600024, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, +{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I32R6}, +{"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, /* MSA */ {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, @@ -2420,9 +2425,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, +{"jr", "s", 0x00000009, 0xfc1fffff, UBD|RD_s, 0, I32R6 }, /* jalr */ /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with the same hazard barrier effect. */ {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, +{"jr.hb", "s", 0x00000409, 0xfc1fffff, UBD|RD_s, 0, I32R6 }, /* jalr.hb */ {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ /* SVR4 PIC code requires special handling for j, so it must be a macro. */ |