diff options
| author |   CQ Tang <cq.tang@intel.com> | 2017-01-30 09:39:52 -0800 |
|---|---|---|
| committer |   Yunhong Jiang <yunhong.jiang@linux.intel.com> | 2017-04-26 02:03:55 -0700 |
| commit | 0be3f4924581ff0fa57b10ef7566fc0b4a2d7e62 (patch) | |
| tree | eb7c95cb378734b0c90e09afd17d57f50908bcaa /kernel | |
| parent | 8e1bfc88c439db6816d6ab11575caecc56d51ca4 (diff) | |
iommu/vt-d: Fix some macros that are incorrectly specified in intel-iommu
BugLink: http://bugs.launchpad.net/bugs/1673538
commit aaa59306b0b7e0ca4ba92cc04c5db101cbb1c096 upstream.
Some of the macros are incorrect with wrong bit-shifts resulting in picking
the incorrect invalidation granularity. Incorrect Source-ID in extended
devtlb invalidation caused device side errors.
Change the signed-off-by to special character to avoid mail spam.
Fixes: 2f26e0a9 ("iommu/vt-d: Add basic SVM PASID support")
S1gned 0ff by: CQ Tang <cq.tang@intel.com>
S1gned 0ff by: Ashok Raj <ashok.raj@intel.com>
Tested-by: CQ Tang <cq.tang@intel.com>
S1gned 0ff by: Joerg Roedel <jroedel@suse.de>
S1gned 0ff by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
S1gned 0ff by: Tim Gardner <tim.gardner@canonical.com>
S1gned 0ff by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
Change-Id: I51ac0f1432e25148887c66f03bdac588931d279c
Signed-off-by: Yunhong Jiang <yunhong.jiang@linux.intel.com>
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/include/linux/intel-iommu.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/kernel/include/linux/intel-iommu.h b/kernel/include/linux/intel-iommu.h index d49e26c6c..23e129ef6 100644 --- a/kernel/include/linux/intel-iommu.h +++ b/kernel/include/linux/intel-iommu.h @@ -153,8 +153,8 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) -#define DMA_TLB_IIRG(type) ((type >> 60) & 7) -#define DMA_TLB_IAIG(val) (((val) >> 57) & 7) +#define DMA_TLB_IIRG(type) ((type >> 60) & 3) +#define DMA_TLB_IAIG(val) (((val) >> 57) & 3) #define DMA_TLB_READ_DRAIN (((u64)1) << 49) #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) @@ -164,9 +164,9 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) /* INVALID_DESC */ #define DMA_CCMD_INVL_GRANU_OFFSET 61 -#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3) -#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3) -#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3) +#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) +#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) +#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) @@ -316,8 +316,8 @@ enum { #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) -#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) -#define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16) +#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) +#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) #define QI_DEV_EIOTLB_MAX_INVS 32 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55) |