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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/firmware/dsp56k/bootstrap.asm
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/firmware/dsp56k/bootstrap.asm')
-rw-r--r--kernel/firmware/dsp56k/bootstrap.asm98
1 files changed, 98 insertions, 0 deletions
diff --git a/kernel/firmware/dsp56k/bootstrap.asm b/kernel/firmware/dsp56k/bootstrap.asm
new file mode 100644
index 000000000..a411047e6
--- /dev/null
+++ b/kernel/firmware/dsp56k/bootstrap.asm
@@ -0,0 +1,98 @@
+; Author: Frederik Noring <noring@nocrew.org>
+;
+; This file is subject to the terms and conditions of the GNU General Public
+; License. See the file COPYING in the main directory of this archive
+; for more details.
+
+; DSP56k loader
+
+; Host Interface
+M_BCR EQU $FFFE ; Port A Bus Control Register
+M_PBC EQU $FFE0 ; Port B Control Register
+M_PBDDR EQU $FFE2 ; Port B Data Direction Register
+M_PBD EQU $FFE4 ; Port B Data Register
+M_PCC EQU $FFE1 ; Port C Control Register
+M_PCDDR EQU $FFE3 ; Port C Data Direction Register
+M_PCD EQU $FFE5 ; Port C Data Register
+
+M_HCR EQU $FFE8 ; Host Control Register
+M_HSR EQU $FFE9 ; Host Status Register
+M_HRX EQU $FFEB ; Host Receive Data Register
+M_HTX EQU $FFEB ; Host Transmit Data Register
+
+; SSI, Synchronous Serial Interface
+M_RX EQU $FFEF ; Serial Receive Data Register
+M_TX EQU $FFEF ; Serial Transmit Data Register
+M_CRA EQU $FFEC ; SSI Control Register A
+M_CRB EQU $FFED ; SSI Control Register B
+M_SR EQU $FFEE ; SSI Status Register
+M_TSR EQU $FFEE ; SSI Time Slot Register
+
+; Exception Processing
+M_IPR EQU $FFFF ; Interrupt Priority Register
+
+ org P:$0
+start jmp <$40
+
+ org P:$40
+; ; Zero 16384 DSP X and Y words
+; clr A #0,r0
+; clr B #0,r4
+; do #64,<_block1
+; rep #256
+; move A,X:(r0)+ B,Y:(r4)+
+;_block1 ; Zero (32768-512) Program words
+; clr A #512,r0
+; do #126,<_block2
+; rep #256
+; move A,P:(r0)+
+;_block2
+
+ ; Copy DSP program control
+ move #real,r0
+ move #upload,r1
+ do #upload_end-upload,_copy
+ movem P:(r0)+,x0
+ movem x0,P:(r1)+
+_copy movep #4,X:<<M_HCR
+ movep #$c00,X:<<M_IPR
+ and #<$fe,mr
+ jmp upload
+
+real
+ org P:$7ea9
+upload
+ movep #1,X:<<M_PBC
+ movep #0,X:<<M_BCR
+
+next jclr #0,X:<<M_HSR,*
+ movep X:<<M_HRX,A
+ move #>3,x0
+ cmp x0,A #>1,x0
+ jeq <$0
+_get_address
+ jclr #0,X:<<M_HSR,_get_address
+ movep X:<<M_HRX,r0
+_get_length
+ jclr #0,X:<<M_HSR,_get_length
+ movep X:<<M_HRX,y0
+ cmp x0,A #>2,x0
+ jeq load_X
+ cmp x0,A
+ jeq load_Y
+
+load_P do y0,_load_P
+ jclr #0,X:<<M_HSR,*
+ movep X:<<M_HRX,P:(r0)+
+_load_P jmp next
+load_X do y0,_load_X
+ jclr #0,X:<<M_HSR,*
+ movep X:<<M_HRX,X:(r0)+
+_load_X jmp next
+load_Y do y0,_load_Y
+ jclr #0,X:<<M_HSR,*
+ movep X:<<M_HRX,Y:(r0)+
+_load_Y jmp next
+
+upload_end
+ end