diff options
author | 2015-08-04 12:17:53 -0700 | |
---|---|---|
committer | 2015-08-04 15:44:42 -0700 | |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/drivers/staging/vt6655 | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/drivers/staging/vt6655')
32 files changed, 12599 insertions, 0 deletions
diff --git a/kernel/drivers/staging/vt6655/Kconfig b/kernel/drivers/staging/vt6655/Kconfig new file mode 100644 index 000000000..77cfc708c --- /dev/null +++ b/kernel/drivers/staging/vt6655/Kconfig @@ -0,0 +1,6 @@ +config VT6655 + tristate "VIA Technologies VT6655 support" + depends on PCI && MAC80211 && m + ---help--- + This is a vendor-written driver for VIA VT6655. + diff --git a/kernel/drivers/staging/vt6655/Makefile b/kernel/drivers/staging/vt6655/Makefile new file mode 100644 index 000000000..115b951bf --- /dev/null +++ b/kernel/drivers/staging/vt6655/Makefile @@ -0,0 +1,18 @@ +# TODO: all of these should be removed +ccflags-y := -DLINUX -D__KERNEL__ -D__NO_VERSION__ +ccflags-y += -DHOSTAP + +vt6655_stage-y += device_main.o \ + card.o \ + channel.o \ + mac.o \ + baseband.o \ + rxtx.o \ + dpc.o \ + power.o \ + srom.o \ + mib.o \ + key.o \ + rf.o + +obj-$(CONFIG_VT6655) += vt6655_stage.o diff --git a/kernel/drivers/staging/vt6655/TODO b/kernel/drivers/staging/vt6655/TODO new file mode 100644 index 000000000..63607ef9c --- /dev/null +++ b/kernel/drivers/staging/vt6655/TODO @@ -0,0 +1,21 @@ +TODO: +- remove __cplusplus ifdefs -- done +- prepare for merge with vt6656 driver: + - rename DEVICE_PRT() to DBG_PRT() -- done + - share 80211*.h includes + - split rf.c + - remove dead code + - abstract VT3253 chipset specific code +- add common vt665x infrastructure +- kill ttype.h +- switch to use LIB80211 +- switch to use MAC80211 +- verify unsigned long usage for x86-64 arch +- reduce .data footprint +- use kernel coding style +- checkpatch.pl fixes +- sparse fixes +- integrate with drivers/net/wireless + +Please send any patches to Greg Kroah-Hartman <greg@kroah.com> +and Forest Bond <forest@alittletooquiet.net>. diff --git a/kernel/drivers/staging/vt6655/baseband.c b/kernel/drivers/staging/vt6655/baseband.c new file mode 100644 index 000000000..b0ea38f19 --- /dev/null +++ b/kernel/drivers/staging/vt6655/baseband.c @@ -0,0 +1,2397 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: baseband.c + * + * Purpose: Implement functions to access baseband + * + * Author: Kyle Hsu + * + * Date: Aug.22, 2002 + * + * Functions: + * BBuGetFrameTime - Calculate data frame transmitting time + * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal + * parameter for baseband Tx + * BBbReadEmbedded - Embedded read baseband register via MAC + * BBbWriteEmbedded - Embedded write baseband register via MAC + * BBbVT3253Init - VIA VT3253 baseband chip init code + * + * Revision History: + * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. + * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support. + * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter(). + * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init(). + * Add the comments. + * 09-01-2003 Bryan YC Fan: RF & BB tables updated. + * Modified BBvLoopbackOn & BBvLoopbackOff(). + * + * + */ + +#include "tmacro.h" +#include "mac.h" +#include "baseband.h" +#include "srom.h" +#include "rf.h" + +/*--------------------- Static Classes ----------------------------*/ + +/*--------------------- Static Variables --------------------------*/ + +/*--------------------- Static Functions --------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Static Definitions -------------------------*/ + +/*--------------------- Static Classes ----------------------------*/ + +/*--------------------- Static Variables --------------------------*/ + +#define CB_VT3253_INIT_FOR_RFMD 446 +static unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = { + {0x00, 0x30}, + {0x01, 0x00}, + {0x02, 0x00}, + {0x03, 0x00}, + {0x04, 0x00}, + {0x05, 0x00}, + {0x06, 0x00}, + {0x07, 0x00}, + {0x08, 0x70}, + {0x09, 0x45}, + {0x0a, 0x2a}, + {0x0b, 0x76}, + {0x0c, 0x00}, + {0x0d, 0x01}, + {0x0e, 0x80}, + {0x0f, 0x00}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x00}, + {0x13, 0x00}, + {0x14, 0x00}, + {0x15, 0x00}, + {0x16, 0x00}, + {0x17, 0x00}, + {0x18, 0x00}, + {0x19, 0x00}, + {0x1a, 0x00}, + {0x1b, 0x9d}, + {0x1c, 0x05}, + {0x1d, 0x00}, + {0x1e, 0x00}, + {0x1f, 0x00}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x00}, + {0x25, 0x4a}, + {0x26, 0x00}, + {0x27, 0x00}, + {0x28, 0x00}, + {0x29, 0x00}, + {0x2a, 0x00}, + {0x2b, 0x00}, + {0x2c, 0x00}, + {0x2d, 0xa8}, + {0x2e, 0x1a}, + {0x2f, 0x0c}, + {0x30, 0x26}, + {0x31, 0x5b}, + {0x32, 0x00}, + {0x33, 0x00}, + {0x34, 0x00}, + {0x35, 0x00}, + {0x36, 0xaa}, + {0x37, 0xaa}, + {0x38, 0xff}, + {0x39, 0xff}, + {0x3a, 0x00}, + {0x3b, 0x00}, + {0x3c, 0x00}, + {0x3d, 0x0d}, + {0x3e, 0x51}, + {0x3f, 0x04}, + {0x40, 0x00}, + {0x41, 0x08}, + {0x42, 0x00}, + {0x43, 0x08}, + {0x44, 0x06}, + {0x45, 0x14}, + {0x46, 0x05}, + {0x47, 0x08}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4a, 0x00}, + {0x4b, 0x00}, + {0x4c, 0x09}, + {0x4d, 0x80}, + {0x4e, 0x00}, + {0x4f, 0xc5}, + {0x50, 0x14}, + {0x51, 0x19}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x00}, + {0x56, 0x00}, + {0x57, 0x00}, + {0x58, 0x00}, + {0x59, 0xb0}, + {0x5a, 0x00}, + {0x5b, 0x00}, + {0x5c, 0x00}, + {0x5d, 0x00}, + {0x5e, 0x00}, + {0x5f, 0x00}, + {0x60, 0x44}, + {0x61, 0x04}, + {0x62, 0x00}, + {0x63, 0x00}, + {0x64, 0x00}, + {0x65, 0x00}, + {0x66, 0x04}, + {0x67, 0xb7}, + {0x68, 0x00}, + {0x69, 0x00}, + {0x6a, 0x00}, + {0x6b, 0x00}, + {0x6c, 0x00}, + {0x6d, 0x03}, + {0x6e, 0x01}, + {0x6f, 0x00}, + {0x70, 0x00}, + {0x71, 0x00}, + {0x72, 0x00}, + {0x73, 0x00}, + {0x74, 0x00}, + {0x75, 0x00}, + {0x76, 0x00}, + {0x77, 0x00}, + {0x78, 0x00}, + {0x79, 0x00}, + {0x7a, 0x00}, + {0x7b, 0x00}, + {0x7c, 0x00}, + {0x7d, 0x00}, + {0x7e, 0x00}, + {0x7f, 0x00}, + {0x80, 0x0b}, + {0x81, 0x00}, + {0x82, 0x3c}, + {0x83, 0x00}, + {0x84, 0x00}, + {0x85, 0x00}, + {0x86, 0x00}, + {0x87, 0x00}, + {0x88, 0x08}, + {0x89, 0x00}, + {0x8a, 0x08}, + {0x8b, 0xa6}, + {0x8c, 0x84}, + {0x8d, 0x47}, + {0x8e, 0xbb}, + {0x8f, 0x02}, + {0x90, 0x21}, + {0x91, 0x0c}, + {0x92, 0x04}, + {0x93, 0x22}, + {0x94, 0x00}, + {0x95, 0x00}, + {0x96, 0x00}, + {0x97, 0xeb}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x9a, 0x00}, + {0x9b, 0x00}, + {0x9c, 0x00}, + {0x9d, 0x00}, + {0x9e, 0x00}, + {0x9f, 0x00}, + {0xa0, 0x00}, + {0xa1, 0x00}, + {0xa2, 0x00}, + {0xa3, 0x00}, + {0xa4, 0x00}, + {0xa5, 0x00}, + {0xa6, 0x10}, + {0xa7, 0x04}, + {0xa8, 0x10}, + {0xa9, 0x00}, + {0xaa, 0x8f}, + {0xab, 0x00}, + {0xac, 0x00}, + {0xad, 0x00}, + {0xae, 0x00}, + {0xaf, 0x80}, + {0xb0, 0x38}, + {0xb1, 0x00}, + {0xb2, 0x00}, + {0xb3, 0x00}, + {0xb4, 0xee}, + {0xb5, 0xff}, + {0xb6, 0x10}, + {0xb7, 0x00}, + {0xb8, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x03}, + {0xbc, 0x00}, + {0xbd, 0x00}, + {0xbe, 0x00}, + {0xbf, 0x00}, + {0xc0, 0x10}, + {0xc1, 0x10}, + {0xc2, 0x18}, + {0xc3, 0x20}, + {0xc4, 0x10}, + {0xc5, 0x00}, + {0xc6, 0x22}, + {0xc7, 0x14}, + {0xc8, 0x0f}, + {0xc9, 0x08}, + {0xca, 0xa4}, + {0xcb, 0xa7}, + {0xcc, 0x3c}, + {0xcd, 0x10}, + {0xce, 0x20}, + {0xcf, 0x00}, + {0xd0, 0x00}, + {0xd1, 0x10}, + {0xd2, 0x00}, + {0xd3, 0x00}, + {0xd4, 0x10}, + {0xd5, 0x33}, + {0xd6, 0x70}, + {0xd7, 0x01}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xdc, 0x00}, + {0xdd, 0x00}, + {0xde, 0x00}, + {0xdf, 0x00}, + {0xe0, 0x00}, + {0xe1, 0x00}, + {0xe2, 0xcc}, + {0xe3, 0x04}, + {0xe4, 0x08}, + {0xe5, 0x10}, + {0xe6, 0x00}, + {0xe7, 0x0e}, + {0xe8, 0x88}, + {0xe9, 0xd4}, + {0xea, 0x05}, + {0xeb, 0xf0}, + {0xec, 0x79}, + {0xed, 0x0f}, + {0xee, 0x04}, + {0xef, 0x04}, + {0xf0, 0x00}, + {0xf1, 0x00}, + {0xf2, 0x00}, + {0xf3, 0x00}, + {0xf4, 0x00}, + {0xf5, 0x00}, + {0xf6, 0x00}, + {0xf7, 0x00}, + {0xf8, 0x00}, + {0xf9, 0x00}, + {0xF0, 0x00}, + {0xF1, 0xF8}, + {0xF0, 0x80}, + {0xF0, 0x00}, + {0xF1, 0xF4}, + {0xF0, 0x81}, + {0xF0, 0x01}, + {0xF1, 0xF0}, + {0xF0, 0x82}, + {0xF0, 0x02}, + {0xF1, 0xEC}, + {0xF0, 0x83}, + {0xF0, 0x03}, + {0xF1, 0xE8}, + {0xF0, 0x84}, + {0xF0, 0x04}, + {0xF1, 0xE4}, + {0xF0, 0x85}, + {0xF0, 0x05}, + {0xF1, 0xE0}, + {0xF0, 0x86}, + {0xF0, 0x06}, + {0xF1, 0xDC}, + {0xF0, 0x87}, + {0xF0, 0x07}, + {0xF1, 0xD8}, + {0xF0, 0x88}, + {0xF0, 0x08}, + {0xF1, 0xD4}, + {0xF0, 0x89}, + {0xF0, 0x09}, + {0xF1, 0xD0}, + {0xF0, 0x8A}, + {0xF0, 0x0A}, + {0xF1, 0xCC}, + {0xF0, 0x8B}, + {0xF0, 0x0B}, + {0xF1, 0xC8}, + {0xF0, 0x8C}, + {0xF0, 0x0C}, + {0xF1, 0xC4}, + {0xF0, 0x8D}, + {0xF0, 0x0D}, + {0xF1, 0xC0}, + {0xF0, 0x8E}, + {0xF0, 0x0E}, + {0xF1, 0xBC}, + {0xF0, 0x8F}, + {0xF0, 0x0F}, + {0xF1, 0xB8}, + {0xF0, 0x90}, + {0xF0, 0x10}, + {0xF1, 0xB4}, + {0xF0, 0x91}, + {0xF0, 0x11}, + {0xF1, 0xB0}, + {0xF0, 0x92}, + {0xF0, 0x12}, + {0xF1, 0xAC}, + {0xF0, 0x93}, + {0xF0, 0x13}, + {0xF1, 0xA8}, + {0xF0, 0x94}, + {0xF0, 0x14}, + {0xF1, 0xA4}, + {0xF0, 0x95}, + {0xF0, 0x15}, + {0xF1, 0xA0}, + {0xF0, 0x96}, + {0xF0, 0x16}, + {0xF1, 0x9C}, + {0xF0, 0x97}, + {0xF0, 0x17}, + {0xF1, 0x98}, + {0xF0, 0x98}, + {0xF0, 0x18}, + {0xF1, 0x94}, + {0xF0, 0x99}, + {0xF0, 0x19}, + {0xF1, 0x90}, + {0xF0, 0x9A}, + {0xF0, 0x1A}, + {0xF1, 0x8C}, + {0xF0, 0x9B}, + {0xF0, 0x1B}, + {0xF1, 0x88}, + {0xF0, 0x9C}, + {0xF0, 0x1C}, + {0xF1, 0x84}, + {0xF0, 0x9D}, + {0xF0, 0x1D}, + {0xF1, 0x80}, + {0xF0, 0x9E}, + {0xF0, 0x1E}, + {0xF1, 0x7C}, + {0xF0, 0x9F}, + {0xF0, 0x1F}, + {0xF1, 0x78}, + {0xF0, 0xA0}, + {0xF0, 0x20}, + {0xF1, 0x74}, + {0xF0, 0xA1}, + {0xF0, 0x21}, + {0xF1, 0x70}, + {0xF0, 0xA2}, + {0xF0, 0x22}, + {0xF1, 0x6C}, + {0xF0, 0xA3}, + {0xF0, 0x23}, + {0xF1, 0x68}, + {0xF0, 0xA4}, + {0xF0, 0x24}, + {0xF1, 0x64}, + {0xF0, 0xA5}, + {0xF0, 0x25}, + {0xF1, 0x60}, + {0xF0, 0xA6}, + {0xF0, 0x26}, + {0xF1, 0x5C}, + {0xF0, 0xA7}, + {0xF0, 0x27}, + {0xF1, 0x58}, + {0xF0, 0xA8}, + {0xF0, 0x28}, + {0xF1, 0x54}, + {0xF0, 0xA9}, + {0xF0, 0x29}, + {0xF1, 0x50}, + {0xF0, 0xAA}, + {0xF0, 0x2A}, + {0xF1, 0x4C}, + {0xF0, 0xAB}, + {0xF0, 0x2B}, + {0xF1, 0x48}, + {0xF0, 0xAC}, + {0xF0, 0x2C}, + {0xF1, 0x44}, + {0xF0, 0xAD}, + {0xF0, 0x2D}, + {0xF1, 0x40}, + {0xF0, 0xAE}, + {0xF0, 0x2E}, + {0xF1, 0x3C}, + {0xF0, 0xAF}, + {0xF0, 0x2F}, + {0xF1, 0x38}, + {0xF0, 0xB0}, + {0xF0, 0x30}, + {0xF1, 0x34}, + {0xF0, 0xB1}, + {0xF0, 0x31}, + {0xF1, 0x30}, + {0xF0, 0xB2}, + {0xF0, 0x32}, + {0xF1, 0x2C}, + {0xF0, 0xB3}, + {0xF0, 0x33}, + {0xF1, 0x28}, + {0xF0, 0xB4}, + {0xF0, 0x34}, + {0xF1, 0x24}, + {0xF0, 0xB5}, + {0xF0, 0x35}, + {0xF1, 0x20}, + {0xF0, 0xB6}, + {0xF0, 0x36}, + {0xF1, 0x1C}, + {0xF0, 0xB7}, + {0xF0, 0x37}, + {0xF1, 0x18}, + {0xF0, 0xB8}, + {0xF0, 0x38}, + {0xF1, 0x14}, + {0xF0, 0xB9}, + {0xF0, 0x39}, + {0xF1, 0x10}, + {0xF0, 0xBA}, + {0xF0, 0x3A}, + {0xF1, 0x0C}, + {0xF0, 0xBB}, + {0xF0, 0x3B}, + {0xF1, 0x08}, + {0xF0, 0x00}, + {0xF0, 0x3C}, + {0xF1, 0x04}, + {0xF0, 0xBD}, + {0xF0, 0x3D}, + {0xF1, 0x00}, + {0xF0, 0xBE}, + {0xF0, 0x3E}, + {0xF1, 0x00}, + {0xF0, 0xBF}, + {0xF0, 0x3F}, + {0xF1, 0x00}, + {0xF0, 0xC0}, + {0xF0, 0x00}, +}; + +#define CB_VT3253B0_INIT_FOR_RFMD 256 +static unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = { + {0x00, 0x31}, + {0x01, 0x00}, + {0x02, 0x00}, + {0x03, 0x00}, + {0x04, 0x00}, + {0x05, 0x81}, + {0x06, 0x00}, + {0x07, 0x00}, + {0x08, 0x38}, + {0x09, 0x45}, + {0x0a, 0x2a}, + {0x0b, 0x76}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0x0e, 0x80}, + {0x0f, 0x00}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x00}, + {0x13, 0x00}, + {0x14, 0x00}, + {0x15, 0x00}, + {0x16, 0x00}, + {0x17, 0x00}, + {0x18, 0x00}, + {0x19, 0x00}, + {0x1a, 0x00}, + {0x1b, 0x8e}, + {0x1c, 0x06}, + {0x1d, 0x00}, + {0x1e, 0x00}, + {0x1f, 0x00}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x00}, + {0x25, 0x4a}, + {0x26, 0x00}, + {0x27, 0x00}, + {0x28, 0x00}, + {0x29, 0x00}, + {0x2a, 0x00}, + {0x2b, 0x00}, + {0x2c, 0x00}, + {0x2d, 0x34}, + {0x2e, 0x18}, + {0x2f, 0x0c}, + {0x30, 0x26}, + {0x31, 0x5b}, + {0x32, 0x00}, + {0x33, 0x00}, + {0x34, 0x00}, + {0x35, 0x00}, + {0x36, 0xaa}, + {0x37, 0xaa}, + {0x38, 0xff}, + {0x39, 0xff}, + {0x3a, 0xf8}, + {0x3b, 0x00}, + {0x3c, 0x00}, + {0x3d, 0x09}, + {0x3e, 0x0d}, + {0x3f, 0x04}, + {0x40, 0x00}, + {0x41, 0x08}, + {0x42, 0x00}, + {0x43, 0x08}, + {0x44, 0x08}, + {0x45, 0x14}, + {0x46, 0x05}, + {0x47, 0x08}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4a, 0x00}, + {0x4b, 0x00}, + {0x4c, 0x09}, + {0x4d, 0x80}, + {0x4e, 0x00}, + {0x4f, 0xc5}, + {0x50, 0x14}, + {0x51, 0x19}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x00}, + {0x56, 0x00}, + {0x57, 0x00}, + {0x58, 0x00}, + {0x59, 0xb0}, + {0x5a, 0x00}, + {0x5b, 0x00}, + {0x5c, 0x00}, + {0x5d, 0x00}, + {0x5e, 0x00}, + {0x5f, 0x00}, + {0x60, 0x39}, + {0x61, 0x83}, + {0x62, 0x00}, + {0x63, 0x00}, + {0x64, 0x00}, + {0x65, 0x00}, + {0x66, 0xc0}, + {0x67, 0x49}, + {0x68, 0x00}, + {0x69, 0x00}, + {0x6a, 0x00}, + {0x6b, 0x00}, + {0x6c, 0x00}, + {0x6d, 0x03}, + {0x6e, 0x01}, + {0x6f, 0x00}, + {0x70, 0x00}, + {0x71, 0x00}, + {0x72, 0x00}, + {0x73, 0x00}, + {0x74, 0x00}, + {0x75, 0x00}, + {0x76, 0x00}, + {0x77, 0x00}, + {0x78, 0x00}, + {0x79, 0x00}, + {0x7a, 0x00}, + {0x7b, 0x00}, + {0x7c, 0x00}, + {0x7d, 0x00}, + {0x7e, 0x00}, + {0x7f, 0x00}, + {0x80, 0x89}, + {0x81, 0x00}, + {0x82, 0x0e}, + {0x83, 0x00}, + {0x84, 0x00}, + {0x85, 0x00}, + {0x86, 0x00}, + {0x87, 0x00}, + {0x88, 0x08}, + {0x89, 0x00}, + {0x8a, 0x0e}, + {0x8b, 0xa7}, + {0x8c, 0x88}, + {0x8d, 0x47}, + {0x8e, 0xaa}, + {0x8f, 0x02}, + {0x90, 0x23}, + {0x91, 0x0c}, + {0x92, 0x06}, + {0x93, 0x08}, + {0x94, 0x00}, + {0x95, 0x00}, + {0x96, 0x00}, + {0x97, 0xeb}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x9a, 0x00}, + {0x9b, 0x00}, + {0x9c, 0x00}, + {0x9d, 0x00}, + {0x9e, 0x00}, + {0x9f, 0x00}, + {0xa0, 0x00}, + {0xa1, 0x00}, + {0xa2, 0x00}, + {0xa3, 0xcd}, + {0xa4, 0x07}, + {0xa5, 0x33}, + {0xa6, 0x18}, + {0xa7, 0x00}, + {0xa8, 0x18}, + {0xa9, 0x00}, + {0xaa, 0x28}, + {0xab, 0x00}, + {0xac, 0x00}, + {0xad, 0x00}, + {0xae, 0x00}, + {0xaf, 0x18}, + {0xb0, 0x38}, + {0xb1, 0x30}, + {0xb2, 0x00}, + {0xb3, 0x00}, + {0xb4, 0x00}, + {0xb5, 0x00}, + {0xb6, 0x84}, + {0xb7, 0xfd}, + {0xb8, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x03}, + {0xbc, 0x00}, + {0xbd, 0x00}, + {0xbe, 0x00}, + {0xbf, 0x00}, + {0xc0, 0x10}, + {0xc1, 0x20}, + {0xc2, 0x18}, + {0xc3, 0x20}, + {0xc4, 0x10}, + {0xc5, 0x2c}, + {0xc6, 0x1e}, + {0xc7, 0x10}, + {0xc8, 0x12}, + {0xc9, 0x01}, + {0xca, 0x6f}, + {0xcb, 0xa7}, + {0xcc, 0x3c}, + {0xcd, 0x10}, + {0xce, 0x00}, + {0xcf, 0x22}, + {0xd0, 0x00}, + {0xd1, 0x10}, + {0xd2, 0x00}, + {0xd3, 0x00}, + {0xd4, 0x10}, + {0xd5, 0x33}, + {0xd6, 0x80}, + {0xd7, 0x21}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xdc, 0x00}, + {0xdd, 0x00}, + {0xde, 0x00}, + {0xdf, 0x00}, + {0xe0, 0x00}, + {0xe1, 0xB3}, + {0xe2, 0x00}, + {0xe3, 0x00}, + {0xe4, 0x00}, + {0xe5, 0x10}, + {0xe6, 0x00}, + {0xe7, 0x18}, + {0xe8, 0x08}, + {0xe9, 0xd4}, + {0xea, 0x00}, + {0xeb, 0xff}, + {0xec, 0x79}, + {0xed, 0x10}, + {0xee, 0x30}, + {0xef, 0x02}, + {0xf0, 0x00}, + {0xf1, 0x09}, + {0xf2, 0x00}, + {0xf3, 0x00}, + {0xf4, 0x00}, + {0xf5, 0x00}, + {0xf6, 0x00}, + {0xf7, 0x00}, + {0xf8, 0x00}, + {0xf9, 0x00}, + {0xfa, 0x00}, + {0xfb, 0x00}, + {0xfc, 0x00}, + {0xfd, 0x00}, + {0xfe, 0x00}, + {0xff, 0x00}, +}; + +#define CB_VT3253B0_AGC_FOR_RFMD2959 195 +/* For RFMD2959 */ +static unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = { + {0xF0, 0x00}, + {0xF1, 0x3E}, + {0xF0, 0x80}, + {0xF0, 0x00}, + {0xF1, 0x3E}, + {0xF0, 0x81}, + {0xF0, 0x01}, + {0xF1, 0x3E}, + {0xF0, 0x82}, + {0xF0, 0x02}, + {0xF1, 0x3E}, + {0xF0, 0x83}, + {0xF0, 0x03}, + {0xF1, 0x3B}, + {0xF0, 0x84}, + {0xF0, 0x04}, + {0xF1, 0x39}, + {0xF0, 0x85}, + {0xF0, 0x05}, + {0xF1, 0x38}, + {0xF0, 0x86}, + {0xF0, 0x06}, + {0xF1, 0x37}, + {0xF0, 0x87}, + {0xF0, 0x07}, + {0xF1, 0x36}, + {0xF0, 0x88}, + {0xF0, 0x08}, + {0xF1, 0x35}, + {0xF0, 0x89}, + {0xF0, 0x09}, + {0xF1, 0x35}, + {0xF0, 0x8A}, + {0xF0, 0x0A}, + {0xF1, 0x34}, + {0xF0, 0x8B}, + {0xF0, 0x0B}, + {0xF1, 0x34}, + {0xF0, 0x8C}, + {0xF0, 0x0C}, + {0xF1, 0x33}, + {0xF0, 0x8D}, + {0xF0, 0x0D}, + {0xF1, 0x32}, + {0xF0, 0x8E}, + {0xF0, 0x0E}, + {0xF1, 0x31}, + {0xF0, 0x8F}, + {0xF0, 0x0F}, + {0xF1, 0x30}, + {0xF0, 0x90}, + {0xF0, 0x10}, + {0xF1, 0x2F}, + {0xF0, 0x91}, + {0xF0, 0x11}, + {0xF1, 0x2F}, + {0xF0, 0x92}, + {0xF0, 0x12}, + {0xF1, 0x2E}, + {0xF0, 0x93}, + {0xF0, 0x13}, + {0xF1, 0x2D}, + {0xF0, 0x94}, + {0xF0, 0x14}, + {0xF1, 0x2C}, + {0xF0, 0x95}, + {0xF0, 0x15}, + {0xF1, 0x2B}, + {0xF0, 0x96}, + {0xF0, 0x16}, + {0xF1, 0x2B}, + {0xF0, 0x97}, + {0xF0, 0x17}, + {0xF1, 0x2A}, + {0xF0, 0x98}, + {0xF0, 0x18}, + {0xF1, 0x29}, + {0xF0, 0x99}, + {0xF0, 0x19}, + {0xF1, 0x28}, + {0xF0, 0x9A}, + {0xF0, 0x1A}, + {0xF1, 0x27}, + {0xF0, 0x9B}, + {0xF0, 0x1B}, + {0xF1, 0x26}, + {0xF0, 0x9C}, + {0xF0, 0x1C}, + {0xF1, 0x25}, + {0xF0, 0x9D}, + {0xF0, 0x1D}, + {0xF1, 0x24}, + {0xF0, 0x9E}, + {0xF0, 0x1E}, + {0xF1, 0x24}, + {0xF0, 0x9F}, + {0xF0, 0x1F}, + {0xF1, 0x23}, + {0xF0, 0xA0}, + {0xF0, 0x20}, + {0xF1, 0x22}, + {0xF0, 0xA1}, + {0xF0, 0x21}, + {0xF1, 0x21}, + {0xF0, 0xA2}, + {0xF0, 0x22}, + {0xF1, 0x20}, + {0xF0, 0xA3}, + {0xF0, 0x23}, + {0xF1, 0x20}, + {0xF0, 0xA4}, + {0xF0, 0x24}, + {0xF1, 0x1F}, + {0xF0, 0xA5}, + {0xF0, 0x25}, + {0xF1, 0x1E}, + {0xF0, 0xA6}, + {0xF0, 0x26}, + {0xF1, 0x1D}, + {0xF0, 0xA7}, + {0xF0, 0x27}, + {0xF1, 0x1C}, + {0xF0, 0xA8}, + {0xF0, 0x28}, + {0xF1, 0x1B}, + {0xF0, 0xA9}, + {0xF0, 0x29}, + {0xF1, 0x1B}, + {0xF0, 0xAA}, + {0xF0, 0x2A}, + {0xF1, 0x1A}, + {0xF0, 0xAB}, + {0xF0, 0x2B}, + {0xF1, 0x1A}, + {0xF0, 0xAC}, + {0xF0, 0x2C}, + {0xF1, 0x19}, + {0xF0, 0xAD}, + {0xF0, 0x2D}, + {0xF1, 0x18}, + {0xF0, 0xAE}, + {0xF0, 0x2E}, + {0xF1, 0x17}, + {0xF0, 0xAF}, + {0xF0, 0x2F}, + {0xF1, 0x16}, + {0xF0, 0xB0}, + {0xF0, 0x30}, + {0xF1, 0x15}, + {0xF0, 0xB1}, + {0xF0, 0x31}, + {0xF1, 0x15}, + {0xF0, 0xB2}, + {0xF0, 0x32}, + {0xF1, 0x15}, + {0xF0, 0xB3}, + {0xF0, 0x33}, + {0xF1, 0x14}, + {0xF0, 0xB4}, + {0xF0, 0x34}, + {0xF1, 0x13}, + {0xF0, 0xB5}, + {0xF0, 0x35}, + {0xF1, 0x12}, + {0xF0, 0xB6}, + {0xF0, 0x36}, + {0xF1, 0x11}, + {0xF0, 0xB7}, + {0xF0, 0x37}, + {0xF1, 0x10}, + {0xF0, 0xB8}, + {0xF0, 0x38}, + {0xF1, 0x0F}, + {0xF0, 0xB9}, + {0xF0, 0x39}, + {0xF1, 0x0E}, + {0xF0, 0xBA}, + {0xF0, 0x3A}, + {0xF1, 0x0D}, + {0xF0, 0xBB}, + {0xF0, 0x3B}, + {0xF1, 0x0C}, + {0xF0, 0xBC}, + {0xF0, 0x3C}, + {0xF1, 0x0B}, + {0xF0, 0xBD}, + {0xF0, 0x3D}, + {0xF1, 0x0B}, + {0xF0, 0xBE}, + {0xF0, 0x3E}, + {0xF1, 0x0A}, + {0xF0, 0xBF}, + {0xF0, 0x3F}, + {0xF1, 0x09}, + {0xF0, 0x00}, +}; + +#define CB_VT3253B0_INIT_FOR_AIROHA2230 256 +/* For AIROHA */ +static unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = { + {0x00, 0x31}, + {0x01, 0x00}, + {0x02, 0x00}, + {0x03, 0x00}, + {0x04, 0x00}, + {0x05, 0x80}, + {0x06, 0x00}, + {0x07, 0x00}, + {0x08, 0x70}, + {0x09, 0x41}, + {0x0a, 0x2A}, + {0x0b, 0x76}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0x0e, 0x80}, + {0x0f, 0x00}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x00}, + {0x13, 0x00}, + {0x14, 0x00}, + {0x15, 0x00}, + {0x16, 0x00}, + {0x17, 0x00}, + {0x18, 0x00}, + {0x19, 0x00}, + {0x1a, 0x00}, + {0x1b, 0x8f}, + {0x1c, 0x09}, + {0x1d, 0x00}, + {0x1e, 0x00}, + {0x1f, 0x00}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x00}, + {0x25, 0x4a}, + {0x26, 0x00}, + {0x27, 0x00}, + {0x28, 0x00}, + {0x29, 0x00}, + {0x2a, 0x00}, + {0x2b, 0x00}, + {0x2c, 0x00}, + {0x2d, 0x4a}, + {0x2e, 0x00}, + {0x2f, 0x0a}, + {0x30, 0x26}, + {0x31, 0x5b}, + {0x32, 0x00}, + {0x33, 0x00}, + {0x34, 0x00}, + {0x35, 0x00}, + {0x36, 0xaa}, + {0x37, 0xaa}, + {0x38, 0xff}, + {0x39, 0xff}, + {0x3a, 0x79}, + {0x3b, 0x00}, + {0x3c, 0x00}, + {0x3d, 0x0b}, + {0x3e, 0x48}, + {0x3f, 0x04}, + {0x40, 0x00}, + {0x41, 0x08}, + {0x42, 0x00}, + {0x43, 0x08}, + {0x44, 0x08}, + {0x45, 0x14}, + {0x46, 0x05}, + {0x47, 0x09}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4a, 0x00}, + {0x4b, 0x00}, + {0x4c, 0x09}, + {0x4d, 0x73}, + {0x4e, 0x00}, + {0x4f, 0xc5}, + {0x50, 0x15}, + {0x51, 0x19}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x00}, + {0x56, 0x00}, + {0x57, 0x00}, + {0x58, 0x00}, + {0x59, 0xb0}, + {0x5a, 0x00}, + {0x5b, 0x00}, + {0x5c, 0x00}, + {0x5d, 0x00}, + {0x5e, 0x00}, + {0x5f, 0x00}, + {0x60, 0xe4}, + {0x61, 0x80}, + {0x62, 0x00}, + {0x63, 0x00}, + {0x64, 0x00}, + {0x65, 0x00}, + {0x66, 0x98}, + {0x67, 0x0a}, + {0x68, 0x00}, + {0x69, 0x00}, + {0x6a, 0x00}, + {0x6b, 0x00}, + {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */ + {0x6d, 0x03}, + {0x6e, 0x01}, + {0x6f, 0x00}, + {0x70, 0x00}, + {0x71, 0x00}, + {0x72, 0x00}, + {0x73, 0x00}, + {0x74, 0x00}, + {0x75, 0x00}, + {0x76, 0x00}, + {0x77, 0x00}, + {0x78, 0x00}, + {0x79, 0x00}, + {0x7a, 0x00}, + {0x7b, 0x00}, + {0x7c, 0x00}, + {0x7d, 0x00}, + {0x7e, 0x00}, + {0x7f, 0x00}, + {0x80, 0x8c}, + {0x81, 0x01}, + {0x82, 0x09}, + {0x83, 0x00}, + {0x84, 0x00}, + {0x85, 0x00}, + {0x86, 0x00}, + {0x87, 0x00}, + {0x88, 0x08}, + {0x89, 0x00}, + {0x8a, 0x0f}, + {0x8b, 0xb7}, + {0x8c, 0x88}, + {0x8d, 0x47}, + {0x8e, 0xaa}, + {0x8f, 0x02}, + {0x90, 0x22}, + {0x91, 0x00}, + {0x92, 0x00}, + {0x93, 0x00}, + {0x94, 0x00}, + {0x95, 0x00}, + {0x96, 0x00}, + {0x97, 0xeb}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x9a, 0x00}, + {0x9b, 0x00}, + {0x9c, 0x00}, + {0x9d, 0x00}, + {0x9e, 0x00}, + {0x9f, 0x01}, + {0xa0, 0x00}, + {0xa1, 0x00}, + {0xa2, 0x00}, + {0xa3, 0x00}, + {0xa4, 0x00}, + {0xa5, 0x00}, + {0xa6, 0x10}, + {0xa7, 0x00}, + {0xa8, 0x18}, + {0xa9, 0x00}, + {0xaa, 0x00}, + {0xab, 0x00}, + {0xac, 0x00}, + {0xad, 0x00}, + {0xae, 0x00}, + {0xaf, 0x18}, + {0xb0, 0x38}, + {0xb1, 0x30}, + {0xb2, 0x00}, + {0xb3, 0x00}, + {0xb4, 0xff}, + {0xb5, 0x0f}, + {0xb6, 0xe4}, + {0xb7, 0xe2}, + {0xb8, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x03}, + {0xbc, 0x01}, + {0xbd, 0x00}, + {0xbe, 0x00}, + {0xbf, 0x00}, + {0xc0, 0x18}, + {0xc1, 0x20}, + {0xc2, 0x07}, + {0xc3, 0x18}, + {0xc4, 0xff}, + {0xc5, 0x2c}, + {0xc6, 0x0c}, + {0xc7, 0x0a}, + {0xc8, 0x0e}, + {0xc9, 0x01}, + {0xca, 0x68}, + {0xcb, 0xa7}, + {0xcc, 0x3c}, + {0xcd, 0x10}, + {0xce, 0x00}, + {0xcf, 0x25}, + {0xd0, 0x40}, + {0xd1, 0x12}, + {0xd2, 0x00}, + {0xd3, 0x00}, + {0xd4, 0x10}, + {0xd5, 0x28}, + {0xd6, 0x80}, + {0xd7, 0x2A}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xdc, 0x00}, + {0xdd, 0x00}, + {0xde, 0x00}, + {0xdf, 0x00}, + {0xe0, 0x00}, + {0xe1, 0xB3}, + {0xe2, 0x00}, + {0xe3, 0x00}, + {0xe4, 0x00}, + {0xe5, 0x10}, + {0xe6, 0x00}, + {0xe7, 0x1C}, + {0xe8, 0x00}, + {0xe9, 0xf4}, + {0xea, 0x00}, + {0xeb, 0xff}, + {0xec, 0x79}, + {0xed, 0x20}, + {0xee, 0x30}, + {0xef, 0x01}, + {0xf0, 0x00}, + {0xf1, 0x3e}, + {0xf2, 0x00}, + {0xf3, 0x00}, + {0xf4, 0x00}, + {0xf5, 0x00}, + {0xf6, 0x00}, + {0xf7, 0x00}, + {0xf8, 0x00}, + {0xf9, 0x00}, + {0xfa, 0x00}, + {0xfb, 0x00}, + {0xfc, 0x00}, + {0xfd, 0x00}, + {0xfe, 0x00}, + {0xff, 0x00}, +}; + +#define CB_VT3253B0_INIT_FOR_UW2451 256 +/* For UW2451 */ +static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = { + {0x00, 0x31}, + {0x01, 0x00}, + {0x02, 0x00}, + {0x03, 0x00}, + {0x04, 0x00}, + {0x05, 0x81}, + {0x06, 0x00}, + {0x07, 0x00}, + {0x08, 0x38}, + {0x09, 0x45}, + {0x0a, 0x28}, + {0x0b, 0x76}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0x0e, 0x80}, + {0x0f, 0x00}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x00}, + {0x13, 0x00}, + {0x14, 0x00}, + {0x15, 0x00}, + {0x16, 0x00}, + {0x17, 0x00}, + {0x18, 0x00}, + {0x19, 0x00}, + {0x1a, 0x00}, + {0x1b, 0x8f}, + {0x1c, 0x0f}, + {0x1d, 0x00}, + {0x1e, 0x00}, + {0x1f, 0x00}, + {0x20, 0x00}, + {0x21, 0x00}, + {0x22, 0x00}, + {0x23, 0x00}, + {0x24, 0x00}, + {0x25, 0x4a}, + {0x26, 0x00}, + {0x27, 0x00}, + {0x28, 0x00}, + {0x29, 0x00}, + {0x2a, 0x00}, + {0x2b, 0x00}, + {0x2c, 0x00}, + {0x2d, 0x18}, + {0x2e, 0x00}, + {0x2f, 0x0a}, + {0x30, 0x26}, + {0x31, 0x5b}, + {0x32, 0x00}, + {0x33, 0x00}, + {0x34, 0x00}, + {0x35, 0x00}, + {0x36, 0xaa}, + {0x37, 0xaa}, + {0x38, 0xff}, + {0x39, 0xff}, + {0x3a, 0x00}, + {0x3b, 0x00}, + {0x3c, 0x00}, + {0x3d, 0x03}, + {0x3e, 0x1d}, + {0x3f, 0x04}, + {0x40, 0x00}, + {0x41, 0x08}, + {0x42, 0x00}, + {0x43, 0x08}, + {0x44, 0x08}, + {0x45, 0x14}, + {0x46, 0x05}, + {0x47, 0x09}, + {0x48, 0x00}, + {0x49, 0x00}, + {0x4a, 0x00}, + {0x4b, 0x00}, + {0x4c, 0x09}, + {0x4d, 0x90}, + {0x4e, 0x00}, + {0x4f, 0xc5}, + {0x50, 0x15}, + {0x51, 0x19}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x54, 0x00}, + {0x55, 0x00}, + {0x56, 0x00}, + {0x57, 0x00}, + {0x58, 0x00}, + {0x59, 0xb0}, + {0x5a, 0x00}, + {0x5b, 0x00}, + {0x5c, 0x00}, + {0x5d, 0x00}, + {0x5e, 0x00}, + {0x5f, 0x00}, + {0x60, 0xb3}, + {0x61, 0x81}, + {0x62, 0x00}, + {0x63, 0x00}, + {0x64, 0x00}, + {0x65, 0x00}, + {0x66, 0x57}, + {0x67, 0x6c}, + {0x68, 0x00}, + {0x69, 0x00}, + {0x6a, 0x00}, + {0x6b, 0x00}, + {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */ + {0x6d, 0x03}, + {0x6e, 0x01}, + {0x6f, 0x00}, + {0x70, 0x00}, + {0x71, 0x00}, + {0x72, 0x00}, + {0x73, 0x00}, + {0x74, 0x00}, + {0x75, 0x00}, + {0x76, 0x00}, + {0x77, 0x00}, + {0x78, 0x00}, + {0x79, 0x00}, + {0x7a, 0x00}, + {0x7b, 0x00}, + {0x7c, 0x00}, + {0x7d, 0x00}, + {0x7e, 0x00}, + {0x7f, 0x00}, + {0x80, 0x8c}, + {0x81, 0x00}, + {0x82, 0x0e}, + {0x83, 0x00}, + {0x84, 0x00}, + {0x85, 0x00}, + {0x86, 0x00}, + {0x87, 0x00}, + {0x88, 0x08}, + {0x89, 0x00}, + {0x8a, 0x0e}, + {0x8b, 0xa7}, + {0x8c, 0x88}, + {0x8d, 0x47}, + {0x8e, 0xaa}, + {0x8f, 0x02}, + {0x90, 0x00}, + {0x91, 0x00}, + {0x92, 0x00}, + {0x93, 0x00}, + {0x94, 0x00}, + {0x95, 0x00}, + {0x96, 0x00}, + {0x97, 0xe3}, + {0x98, 0x00}, + {0x99, 0x00}, + {0x9a, 0x00}, + {0x9b, 0x00}, + {0x9c, 0x00}, + {0x9d, 0x00}, + {0x9e, 0x00}, + {0x9f, 0x00}, + {0xa0, 0x00}, + {0xa1, 0x00}, + {0xa2, 0x00}, + {0xa3, 0x00}, + {0xa4, 0x00}, + {0xa5, 0x00}, + {0xa6, 0x10}, + {0xa7, 0x00}, + {0xa8, 0x18}, + {0xa9, 0x00}, + {0xaa, 0x00}, + {0xab, 0x00}, + {0xac, 0x00}, + {0xad, 0x00}, + {0xae, 0x00}, + {0xaf, 0x18}, + {0xb0, 0x18}, + {0xb1, 0x30}, + {0xb2, 0x00}, + {0xb3, 0x00}, + {0xb4, 0x00}, + {0xb5, 0x00}, + {0xb6, 0x00}, + {0xb7, 0x00}, + {0xb8, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x03}, + {0xbc, 0x01}, + {0xbd, 0x00}, + {0xbe, 0x00}, + {0xbf, 0x00}, + {0xc0, 0x10}, + {0xc1, 0x20}, + {0xc2, 0x00}, + {0xc3, 0x20}, + {0xc4, 0x00}, + {0xc5, 0x2c}, + {0xc6, 0x1c}, + {0xc7, 0x10}, + {0xc8, 0x10}, + {0xc9, 0x01}, + {0xca, 0x68}, + {0xcb, 0xa7}, + {0xcc, 0x3c}, + {0xcd, 0x09}, + {0xce, 0x00}, + {0xcf, 0x20}, + {0xd0, 0x40}, + {0xd1, 0x10}, + {0xd2, 0x00}, + {0xd3, 0x00}, + {0xd4, 0x20}, + {0xd5, 0x28}, + {0xd6, 0xa0}, + {0xd7, 0x2a}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xdc, 0x00}, + {0xdd, 0x00}, + {0xde, 0x00}, + {0xdf, 0x00}, + {0xe0, 0x00}, + {0xe1, 0xd3}, + {0xe2, 0xc0}, + {0xe3, 0x00}, + {0xe4, 0x00}, + {0xe5, 0x10}, + {0xe6, 0x00}, + {0xe7, 0x12}, + {0xe8, 0x12}, + {0xe9, 0x34}, + {0xea, 0x00}, + {0xeb, 0xff}, + {0xec, 0x79}, + {0xed, 0x20}, + {0xee, 0x30}, + {0xef, 0x01}, + {0xf0, 0x00}, + {0xf1, 0x3e}, + {0xf2, 0x00}, + {0xf3, 0x00}, + {0xf4, 0x00}, + {0xf5, 0x00}, + {0xf6, 0x00}, + {0xf7, 0x00}, + {0xf8, 0x00}, + {0xf9, 0x00}, + {0xfa, 0x00}, + {0xfb, 0x00}, + {0xfc, 0x00}, + {0xfd, 0x00}, + {0xfe, 0x00}, + {0xff, 0x00}, +}; + +#define CB_VT3253B0_AGC 193 +/* For AIROHA */ +static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = { + {0xF0, 0x00}, + {0xF1, 0x00}, + {0xF0, 0x80}, + {0xF0, 0x01}, + {0xF1, 0x00}, + {0xF0, 0x81}, + {0xF0, 0x02}, + {0xF1, 0x02}, + {0xF0, 0x82}, + {0xF0, 0x03}, + {0xF1, 0x04}, + {0xF0, 0x83}, + {0xF0, 0x03}, + {0xF1, 0x04}, + {0xF0, 0x84}, + {0xF0, 0x04}, + {0xF1, 0x06}, + {0xF0, 0x85}, + {0xF0, 0x05}, + {0xF1, 0x06}, + {0xF0, 0x86}, + {0xF0, 0x06}, + {0xF1, 0x06}, + {0xF0, 0x87}, + {0xF0, 0x07}, + {0xF1, 0x08}, + {0xF0, 0x88}, + {0xF0, 0x08}, + {0xF1, 0x08}, + {0xF0, 0x89}, + {0xF0, 0x09}, + {0xF1, 0x0A}, + {0xF0, 0x8A}, + {0xF0, 0x0A}, + {0xF1, 0x0A}, + {0xF0, 0x8B}, + {0xF0, 0x0B}, + {0xF1, 0x0C}, + {0xF0, 0x8C}, + {0xF0, 0x0C}, + {0xF1, 0x0C}, + {0xF0, 0x8D}, + {0xF0, 0x0D}, + {0xF1, 0x0E}, + {0xF0, 0x8E}, + {0xF0, 0x0E}, + {0xF1, 0x0E}, + {0xF0, 0x8F}, + {0xF0, 0x0F}, + {0xF1, 0x10}, + {0xF0, 0x90}, + {0xF0, 0x10}, + {0xF1, 0x10}, + {0xF0, 0x91}, + {0xF0, 0x11}, + {0xF1, 0x12}, + {0xF0, 0x92}, + {0xF0, 0x12}, + {0xF1, 0x12}, + {0xF0, 0x93}, + {0xF0, 0x13}, + {0xF1, 0x14}, + {0xF0, 0x94}, + {0xF0, 0x14}, + {0xF1, 0x14}, + {0xF0, 0x95}, + {0xF0, 0x15}, + {0xF1, 0x16}, + {0xF0, 0x96}, + {0xF0, 0x16}, + {0xF1, 0x16}, + {0xF0, 0x97}, + {0xF0, 0x17}, + {0xF1, 0x18}, + {0xF0, 0x98}, + {0xF0, 0x18}, + {0xF1, 0x18}, + {0xF0, 0x99}, + {0xF0, 0x19}, + {0xF1, 0x1A}, + {0xF0, 0x9A}, + {0xF0, 0x1A}, + {0xF1, 0x1A}, + {0xF0, 0x9B}, + {0xF0, 0x1B}, + {0xF1, 0x1C}, + {0xF0, 0x9C}, + {0xF0, 0x1C}, + {0xF1, 0x1C}, + {0xF0, 0x9D}, + {0xF0, 0x1D}, + {0xF1, 0x1E}, + {0xF0, 0x9E}, + {0xF0, 0x1E}, + {0xF1, 0x1E}, + {0xF0, 0x9F}, + {0xF0, 0x1F}, + {0xF1, 0x20}, + {0xF0, 0xA0}, + {0xF0, 0x20}, + {0xF1, 0x20}, + {0xF0, 0xA1}, + {0xF0, 0x21}, + {0xF1, 0x22}, + {0xF0, 0xA2}, + {0xF0, 0x22}, + {0xF1, 0x22}, + {0xF0, 0xA3}, + {0xF0, 0x23}, + {0xF1, 0x24}, + {0xF0, 0xA4}, + {0xF0, 0x24}, + {0xF1, 0x24}, + {0xF0, 0xA5}, + {0xF0, 0x25}, + {0xF1, 0x26}, + {0xF0, 0xA6}, + {0xF0, 0x26}, + {0xF1, 0x26}, + {0xF0, 0xA7}, + {0xF0, 0x27}, + {0xF1, 0x28}, + {0xF0, 0xA8}, + {0xF0, 0x28}, + {0xF1, 0x28}, + {0xF0, 0xA9}, + {0xF0, 0x29}, + {0xF1, 0x2A}, + {0xF0, 0xAA}, + {0xF0, 0x2A}, + {0xF1, 0x2A}, + {0xF0, 0xAB}, + {0xF0, 0x2B}, + {0xF1, 0x2C}, + {0xF0, 0xAC}, + {0xF0, 0x2C}, + {0xF1, 0x2C}, + {0xF0, 0xAD}, + {0xF0, 0x2D}, + {0xF1, 0x2E}, + {0xF0, 0xAE}, + {0xF0, 0x2E}, + {0xF1, 0x2E}, + {0xF0, 0xAF}, + {0xF0, 0x2F}, + {0xF1, 0x30}, + {0xF0, 0xB0}, + {0xF0, 0x30}, + {0xF1, 0x30}, + {0xF0, 0xB1}, + {0xF0, 0x31}, + {0xF1, 0x32}, + {0xF0, 0xB2}, + {0xF0, 0x32}, + {0xF1, 0x32}, + {0xF0, 0xB3}, + {0xF0, 0x33}, + {0xF1, 0x34}, + {0xF0, 0xB4}, + {0xF0, 0x34}, + {0xF1, 0x34}, + {0xF0, 0xB5}, + {0xF0, 0x35}, + {0xF1, 0x36}, + {0xF0, 0xB6}, + {0xF0, 0x36}, + {0xF1, 0x36}, + {0xF0, 0xB7}, + {0xF0, 0x37}, + {0xF1, 0x38}, + {0xF0, 0xB8}, + {0xF0, 0x38}, + {0xF1, 0x38}, + {0xF0, 0xB9}, + {0xF0, 0x39}, + {0xF1, 0x3A}, + {0xF0, 0xBA}, + {0xF0, 0x3A}, + {0xF1, 0x3A}, + {0xF0, 0xBB}, + {0xF0, 0x3B}, + {0xF1, 0x3C}, + {0xF0, 0xBC}, + {0xF0, 0x3C}, + {0xF1, 0x3C}, + {0xF0, 0xBD}, + {0xF0, 0x3D}, + {0xF1, 0x3E}, + {0xF0, 0xBE}, + {0xF0, 0x3E}, + {0xF1, 0x3E}, + {0xF0, 0xBF}, + {0xF0, 0x00}, +}; + +static const unsigned short awcFrameTime[MAX_RATE] = { + 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216 +}; + +/*--------------------- Export Variables --------------------------*/ +/* + * Description: Calculate data frame transmitting time + * + * Parameters: + * In: + * byPreambleType - Preamble Type + * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA + * cbFrameLength - Baseband Type + * wRate - Tx Rate + * Out: + * + * Return Value: FrameTime + * + */ +unsigned int +BBuGetFrameTime( + unsigned char byPreambleType, + unsigned char byPktType, + unsigned int cbFrameLength, + unsigned short wRate +) +{ + unsigned int uFrameTime; + unsigned int uPreamble; + unsigned int uTmp; + unsigned int uRateIdx = (unsigned int) wRate; + unsigned int uRate = 0; + + if (uRateIdx > RATE_54M) { + ASSERT(0); + return 0; + } + + uRate = (unsigned int)awcFrameTime[uRateIdx]; + + if (uRateIdx <= 3) { /* CCK mode */ + if (byPreambleType == 1) /* Short */ + uPreamble = 96; + else + uPreamble = 192; + + uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */ + uTmp = (uFrameTime * uRate) / 80; + if (cbFrameLength != uTmp) + uFrameTime++; + + return uPreamble + uFrameTime; + } + uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */ + uTmp = ((uFrameTime * uRate) - 22) / 8; + if (cbFrameLength != uTmp) + uFrameTime++; + + uFrameTime = uFrameTime * 4; /* ??????? */ + if (byPktType != PK_TYPE_11A) + uFrameTime += 6; /* ?????? */ + + return 20 + uFrameTime; /* ?????? */ +} + +/* + * Description: Calculate Length, Service, and Signal fields of Phy for Tx + * + * Parameters: + * In: + * priv - Device Structure + * frame_length - Tx Frame Length + * tx_rate - Tx Rate + * Out: + * struct vnt_phy_field *phy + * - pointer to Phy Length field + * - pointer to Phy Service field + * - pointer to Phy Signal field + * + * Return Value: none + * + */ +void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, + u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy) +{ + u32 bit_count; + u32 count = 0; + u32 tmp; + int ext_bit; + u8 preamble_type = priv->byPreambleType; + + bit_count = frame_length * 8; + ext_bit = false; + + switch (tx_rate) { + case RATE_1M: + count = bit_count; + + phy->signal = 0x00; + + break; + case RATE_2M: + count = bit_count / 2; + + if (preamble_type == 1) + phy->signal = 0x09; + else + phy->signal = 0x01; + + break; + case RATE_5M: + count = (bit_count * 10) / 55; + tmp = (count * 55) / 10; + + if (tmp != bit_count) + count++; + + if (preamble_type == 1) + phy->signal = 0x0a; + else + phy->signal = 0x02; + + break; + case RATE_11M: + count = bit_count / 11; + tmp = count * 11; + + if (tmp != bit_count) { + count++; + + if ((bit_count - tmp) <= 3) + ext_bit = true; + } + + if (preamble_type == 1) + phy->signal = 0x0b; + else + phy->signal = 0x03; + + break; + case RATE_6M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9b; + else + phy->signal = 0x8b; + + break; + case RATE_9M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9f; + else + phy->signal = 0x8f; + + break; + case RATE_12M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9a; + else + phy->signal = 0x8a; + + break; + case RATE_18M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9e; + else + phy->signal = 0x8e; + + break; + case RATE_24M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x99; + else + phy->signal = 0x89; + + break; + case RATE_36M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9d; + else + phy->signal = 0x8d; + + break; + case RATE_48M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x98; + else + phy->signal = 0x88; + + break; + case RATE_54M: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9c; + else + phy->signal = 0x8c; + break; + default: + if (pkt_type == PK_TYPE_11A) + phy->signal = 0x9c; + else + phy->signal = 0x8c; + break; + } + + if (pkt_type == PK_TYPE_11B) { + phy->service = 0x00; + if (ext_bit) + phy->service |= 0x80; + phy->len = cpu_to_le16((u16)count); + } else { + phy->service = 0x00; + phy->len = cpu_to_le16((u16)frame_length); + } +} + +/* + * Description: Read a byte from BASEBAND, by embedded programming + * + * Parameters: + * In: + * dwIoBase - I/O base address + * byBBAddr - address of register in Baseband + * Out: + * pbyData - data read + * + * Return Value: true if succeeded; false if failed. + * + */ +bool BBbReadEmbedded(struct vnt_private *priv, + unsigned char byBBAddr, unsigned char *pbyData) +{ + void __iomem *dwIoBase = priv->PortOffset; + unsigned short ww; + unsigned char byValue; + + /* BB reg offset */ + VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr); + + /* turn on REGR */ + MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR); + /* W_MAX_TIMEOUT is the timeout period */ + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue); + if (byValue & BBREGCTL_DONE) + break; + } + + /* get BB data */ + VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData); + + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x30); + pr_debug(" DBG_PORT80(0x30)\n"); + return false; + } + return true; +} + +/* + * Description: Write a Byte to BASEBAND, by embedded programming + * + * Parameters: + * In: + * dwIoBase - I/O base address + * byBBAddr - address of register in Baseband + * byData - data to write + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +bool BBbWriteEmbedded(struct vnt_private *priv, + unsigned char byBBAddr, unsigned char byData) +{ + void __iomem *dwIoBase = priv->PortOffset; + unsigned short ww; + unsigned char byValue; + + /* BB reg offset */ + VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr); + /* set BB data */ + VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData); + + /* turn on BBREGCTL_REGW */ + MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW); + /* W_MAX_TIMEOUT is the timeout period */ + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue); + if (byValue & BBREGCTL_DONE) + break; + } + + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x31); + pr_debug(" DBG_PORT80(0x31)\n"); + return false; + } + return true; +} + +/* + * Description: VIA VT3253 Baseband chip init function + * + * Parameters: + * In: + * dwIoBase - I/O base address + * byRevId - Revision ID + * byRFType - RF type + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ + +bool BBbVT3253Init(struct vnt_private *priv) +{ + bool bResult = true; + int ii; + void __iomem *dwIoBase = priv->PortOffset; + unsigned char byRFType = priv->byRFType; + unsigned char byLocalID = priv->byLocalID; + + if (byRFType == RF_RFMD2959) { + if (byLocalID <= REV_ID_VT3253_A1) { + for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253InitTab_RFMD[ii][0], + byVT3253InitTab_RFMD[ii][1]); + + } else { + for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_RFMD[ii][0], + byVT3253B0_RFMD[ii][1]); + + for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AGC4_RFMD2959[ii][0], + byVT3253B0_AGC4_RFMD2959[ii][1]); + + VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23); + MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0)); + } + priv->abyBBVGA[0] = 0x18; + priv->abyBBVGA[1] = 0x0A; + priv->abyBBVGA[2] = 0x0; + priv->abyBBVGA[3] = 0x0; + priv->ldBmThreshold[0] = -70; + priv->ldBmThreshold[1] = -50; + priv->ldBmThreshold[2] = 0; + priv->ldBmThreshold[3] = 0; + } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) { + for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AIROHA2230[ii][0], + byVT3253B0_AIROHA2230[ii][1]); + + for (ii = 0; ii < CB_VT3253B0_AGC; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + + priv->abyBBVGA[0] = 0x1C; + priv->abyBBVGA[1] = 0x10; + priv->abyBBVGA[2] = 0x0; + priv->abyBBVGA[3] = 0x0; + priv->ldBmThreshold[0] = -70; + priv->ldBmThreshold[1] = -48; + priv->ldBmThreshold[2] = 0; + priv->ldBmThreshold[3] = 0; + } else if (byRFType == RF_UW2451) { + for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_UW2451[ii][0], + byVT3253B0_UW2451[ii][1]); + + for (ii = 0; ii < CB_VT3253B0_AGC; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AGC[ii][0], + byVT3253B0_AGC[ii][1]); + + VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); + MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0)); + + priv->abyBBVGA[0] = 0x14; + priv->abyBBVGA[1] = 0x0A; + priv->abyBBVGA[2] = 0x0; + priv->abyBBVGA[3] = 0x0; + priv->ldBmThreshold[0] = -60; + priv->ldBmThreshold[1] = -50; + priv->ldBmThreshold[2] = 0; + priv->ldBmThreshold[3] = 0; + } else if (byRFType == RF_UW2452) { + for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_UW2451[ii][0], + byVT3253B0_UW2451[ii][1]); + + /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ + /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/ + /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ + /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/ + /* Select VC1/VC2, CR215 = 0x02->0x06 */ + bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); + + /* {{RobertYu:20050125, request by Jack */ + bResult &= BBbWriteEmbedded(priv, 0x90, 0x20); + bResult &= BBbWriteEmbedded(priv, 0x97, 0xeb); + /* }} */ + + /* {{RobertYu:20050221, request by Jack */ + bResult &= BBbWriteEmbedded(priv, 0xa6, 0x00); + bResult &= BBbWriteEmbedded(priv, 0xa8, 0x30); + /* }} */ + bResult &= BBbWriteEmbedded(priv, 0xb0, 0x58); + + for (ii = 0; ii < CB_VT3253B0_AGC; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + + priv->abyBBVGA[0] = 0x14; + priv->abyBBVGA[1] = 0x0A; + priv->abyBBVGA[2] = 0x0; + priv->abyBBVGA[3] = 0x0; + priv->ldBmThreshold[0] = -60; + priv->ldBmThreshold[1] = -50; + priv->ldBmThreshold[2] = 0; + priv->ldBmThreshold[3] = 0; + /* }} RobertYu */ + + } else if (byRFType == RF_VT3226) { + for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AIROHA2230[ii][0], + byVT3253B0_AIROHA2230[ii][1]); + + for (ii = 0; ii < CB_VT3253B0_AGC; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + + priv->abyBBVGA[0] = 0x1C; + priv->abyBBVGA[1] = 0x10; + priv->abyBBVGA[2] = 0x0; + priv->abyBBVGA[3] = 0x0; + priv->ldBmThreshold[0] = -70; + priv->ldBmThreshold[1] = -48; + priv->ldBmThreshold[2] = 0; + priv->ldBmThreshold[3] = 0; + /* Fix VT3226 DFC system timing issue */ + MACvSetRFLE_LatchBase(dwIoBase); + /* {{ RobertYu: 20050104 */ + } else if (byRFType == RF_AIROHA7230) { + for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AIROHA2230[ii][0], + byVT3253B0_AIROHA2230[ii][1]); + + + /* {{ RobertYu:20050223, request by JerryChung */ + /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ + /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/ + /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ + /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/ + /* Select VC1/VC2, CR215 = 0x02->0x06 */ + bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); + /* }} */ + + for (ii = 0; ii < CB_VT3253B0_AGC; ii++) + bResult &= BBbWriteEmbedded(priv, + byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); + + priv->abyBBVGA[0] = 0x1C; + priv->abyBBVGA[1] = 0x10; + priv->abyBBVGA[2] = 0x0; + priv->abyBBVGA[3] = 0x0; + priv->ldBmThreshold[0] = -70; + priv->ldBmThreshold[1] = -48; + priv->ldBmThreshold[2] = 0; + priv->ldBmThreshold[3] = 0; + /* }} RobertYu */ + } else { + /* No VGA Table now */ + priv->bUpdateBBVGA = false; + priv->abyBBVGA[0] = 0x1C; + } + + if (byLocalID > REV_ID_VT3253_A1) { + BBbWriteEmbedded(priv, 0x04, 0x7F); + BBbWriteEmbedded(priv, 0x0D, 0x01); + } + + return bResult; +} + +/* + * Description: Set ShortSlotTime mode + * + * Parameters: + * In: + * priv - Device Structure + * Out: + * none + * + * Return Value: none + * + */ +void +BBvSetShortSlotTime(struct vnt_private *priv) +{ + unsigned char byBBRxConf = 0; + unsigned char byBBVGA = 0; + + BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */ + + if (priv->bShortSlotTime) + byBBRxConf &= 0xDF; /* 1101 1111 */ + else + byBBRxConf |= 0x20; /* 0010 0000 */ + + /* patch for 3253B0 Baseband with Cardbus module */ + BBbReadEmbedded(priv, 0xE7, &byBBVGA); + if (byBBVGA == priv->abyBBVGA[0]) + byBBRxConf |= 0x20; /* 0010 0000 */ + + BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */ +} + +void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData) +{ + unsigned char byBBRxConf = 0; + + BBbWriteEmbedded(priv, 0xE7, byData); + + BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */ + /* patch for 3253B0 Baseband with Cardbus module */ + if (byData == priv->abyBBVGA[0]) + byBBRxConf |= 0x20; /* 0010 0000 */ + else if (priv->bShortSlotTime) + byBBRxConf &= 0xDF; /* 1101 1111 */ + else + byBBRxConf |= 0x20; /* 0010 0000 */ + priv->byBBVGACurrent = byData; + BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */ +} + +/* + * Description: Baseband SoftwareReset + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * none + * + * Return Value: none + * + */ +void +BBvSoftwareReset(struct vnt_private *priv) +{ + BBbWriteEmbedded(priv, 0x50, 0x40); + BBbWriteEmbedded(priv, 0x50, 0); + BBbWriteEmbedded(priv, 0x9C, 0x01); + BBbWriteEmbedded(priv, 0x9C, 0); +} + +/* + * Description: Baseband Power Save Mode ON + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * none + * + * Return Value: none + * + */ +void +BBvPowerSaveModeON(struct vnt_private *priv) +{ + unsigned char byOrgData; + + BBbReadEmbedded(priv, 0x0D, &byOrgData); + byOrgData |= BIT(0); + BBbWriteEmbedded(priv, 0x0D, byOrgData); +} + +/* + * Description: Baseband Power Save Mode OFF + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * none + * + * Return Value: none + * + */ +void +BBvPowerSaveModeOFF(struct vnt_private *priv) +{ + unsigned char byOrgData; + + BBbReadEmbedded(priv, 0x0D, &byOrgData); + byOrgData &= ~(BIT(0)); + BBbWriteEmbedded(priv, 0x0D, byOrgData); +} + +/* + * Description: Set Tx Antenna mode + * + * Parameters: + * In: + * priv - Device Structure + * byAntennaMode - Antenna Mode + * Out: + * none + * + * Return Value: none + * + */ + +void +BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) +{ + unsigned char byBBTxConf; + + BBbReadEmbedded(priv, 0x09, &byBBTxConf); /* CR09 */ + if (byAntennaMode == ANT_DIVERSITY) { + /* bit 1 is diversity */ + byBBTxConf |= 0x02; + } else if (byAntennaMode == ANT_A) { + /* bit 2 is ANTSEL */ + byBBTxConf &= 0xF9; /* 1111 1001 */ + } else if (byAntennaMode == ANT_B) { + byBBTxConf &= 0xFD; /* 1111 1101 */ + byBBTxConf |= 0x04; + } + BBbWriteEmbedded(priv, 0x09, byBBTxConf); /* CR09 */ +} + +/* + * Description: Set Rx Antenna mode + * + * Parameters: + * In: + * priv - Device Structure + * byAntennaMode - Antenna Mode + * Out: + * none + * + * Return Value: none + * + */ + +void +BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode) +{ + unsigned char byBBRxConf; + + BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */ + if (byAntennaMode == ANT_DIVERSITY) { + byBBRxConf |= 0x01; + + } else if (byAntennaMode == ANT_A) { + byBBRxConf &= 0xFC; /* 1111 1100 */ + } else if (byAntennaMode == ANT_B) { + byBBRxConf &= 0xFE; /* 1111 1110 */ + byBBRxConf |= 0x02; + } + BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */ +} + +/* + * Description: BBvSetDeepSleep + * + * Parameters: + * In: + * priv - Device Structure + * Out: + * none + * + * Return Value: none + * + */ +void +BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID) +{ + BBbWriteEmbedded(priv, 0x0C, 0x17); /* CR12 */ + BBbWriteEmbedded(priv, 0x0D, 0xB9); /* CR13 */ +} + +void +BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID) +{ + BBbWriteEmbedded(priv, 0x0C, 0x00); /* CR12 */ + BBbWriteEmbedded(priv, 0x0D, 0x01); /* CR13 */ +} diff --git a/kernel/drivers/staging/vt6655/baseband.h b/kernel/drivers/staging/vt6655/baseband.h new file mode 100644 index 000000000..43a4fb1f3 --- /dev/null +++ b/kernel/drivers/staging/vt6655/baseband.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: baseband.h + * + * Purpose: Implement functions to access baseband + * + * Author: Jerry Chen + * + * Date: Jun. 5, 2002 + * + */ + +#ifndef __BASEBAND_H__ +#define __BASEBAND_H__ + +#include "device.h" + +/* + * Registers in the BASEBAND + */ +#define BB_MAX_CONTEXT_SIZE 256 + +/* + * Baseband RF pair definition in eeprom (Bits 6..0) + */ + +#define PREAMBLE_LONG 0 +#define PREAMBLE_SHORT 1 + +#define F5G 0 +#define F2_4G 1 + +#define TOP_RATE_54M 0x80000000 +#define TOP_RATE_48M 0x40000000 +#define TOP_RATE_36M 0x20000000 +#define TOP_RATE_24M 0x10000000 +#define TOP_RATE_18M 0x08000000 +#define TOP_RATE_12M 0x04000000 +#define TOP_RATE_11M 0x02000000 +#define TOP_RATE_9M 0x01000000 +#define TOP_RATE_6M 0x00800000 +#define TOP_RATE_55M 0x00400000 +#define TOP_RATE_2M 0x00200000 +#define TOP_RATE_1M 0x00100000 + +#define BBvClearFOE(dwIoBase) \ + BBbWriteEmbedded(dwIoBase, 0xB1, 0) + +#define BBvSetFOE(dwIoBase) \ + BBbWriteEmbedded(dwIoBase, 0xB1, 0x0C) + +unsigned int +BBuGetFrameTime( + unsigned char byPreambleType, + unsigned char byPktType, + unsigned int cbFrameLength, + unsigned short wRate +); + +void vnt_get_phy_field(struct vnt_private *, u32 frame_length, + u16 tx_rate, u8 pkt_type, struct vnt_phy_field *); + +bool BBbReadEmbedded(struct vnt_private *, unsigned char byBBAddr, unsigned char *pbyData); +bool BBbWriteEmbedded(struct vnt_private *, unsigned char byBBAddr, unsigned char byData); + +void BBvSetShortSlotTime(struct vnt_private *); +void BBvSetVGAGainOffset(struct vnt_private *, unsigned char byData); + +/* VT3253 Baseband */ +bool BBbVT3253Init(struct vnt_private *); +void BBvSoftwareReset(struct vnt_private *); +void BBvPowerSaveModeON(struct vnt_private *); +void BBvPowerSaveModeOFF(struct vnt_private *); +void BBvSetTxAntennaMode(struct vnt_private *, unsigned char byAntennaMode); +void BBvSetRxAntennaMode(struct vnt_private *, unsigned char byAntennaMode); +void BBvSetDeepSleep(struct vnt_private *, unsigned char byLocalID); +void BBvExitDeepSleep(struct vnt_private *, unsigned char byLocalID); + +#endif /* __BASEBAND_H__ */ diff --git a/kernel/drivers/staging/vt6655/card.c b/kernel/drivers/staging/vt6655/card.c new file mode 100644 index 000000000..e00c0605d --- /dev/null +++ b/kernel/drivers/staging/vt6655/card.c @@ -0,0 +1,1017 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: card.c + * Purpose: Provide functions to setup NIC operation mode + * Functions: + * s_vSafeResetTx - Rest Tx + * CARDvSetRSPINF - Set RSPINF + * CARDvUpdateBasicTopRate - Update BasicTopRate + * CARDbAddBasicRate - Add to BasicRateSet + * CARDbIsOFDMinBasicRate - Check if any OFDM rate is in BasicRateSet + * CARDvSetLoopbackMode - Set Loopback mode + * CARDbSoftwareReset - Sortware reset NIC + * CARDqGetTSFOffset - Calculate TSFOffset + * CARDbGetCurrentTSF - Read Current NIC TSF counter + * CARDqGetNextTBTT - Calculate Next Beacon TSF counter + * CARDvSetFirstNextTBTT - Set NIC Beacon time + * CARDvUpdateNextTBTT - Sync. NIC Beacon time + * CARDbRadioPowerOff - Turn Off NIC Radio Power + * CARDbRadioPowerOn - Turn On NIC Radio Power + * + * Revision History: + * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. + * 08-26-2003 Kyle Hsu: Modify the defination type of dwIoBase. + * 09-01-2003 Bryan YC Fan: Add vUpdateIFS(). + * + */ + +#include "tmacro.h" +#include "card.h" +#include "baseband.h" +#include "mac.h" +#include "desc.h" +#include "rf.h" +#include "power.h" + +/*--------------------- Static Definitions -------------------------*/ + +#define C_SIFS_A 16 /* micro sec. */ +#define C_SIFS_BG 10 + +#define C_EIFS 80 /* micro sec. */ + +#define C_SLOT_SHORT 9 /* micro sec. */ +#define C_SLOT_LONG 20 + +#define C_CWMIN_A 15 /* slot time */ +#define C_CWMIN_B 31 + +#define C_CWMAX 1023 /* slot time */ + +#define WAIT_BEACON_TX_DOWN_TMO 3 /* Times */ + +/*--------------------- Static Variables --------------------------*/ + +static const unsigned short cwRXBCNTSFOff[MAX_RATE] = { + 17, 17, 17, 17, 34, 23, 17, 11, 8, 5, 4, 3}; + +/*--------------------- Static Functions --------------------------*/ + +static +void +s_vCalculateOFDMRParameter( + unsigned char byRate, + u8 bb_type, + unsigned char *pbyTxRate, + unsigned char *pbyRsvTime +); + +/*--------------------- Export Functions --------------------------*/ + +/* + * Description: Calculate TxRate and RsvTime fields for RSPINF in OFDM mode. + * + * Parameters: + * In: + * wRate - Tx Rate + * byPktType - Tx Packet type + * Out: + * pbyTxRate - pointer to RSPINF TxRate field + * pbyRsvTime - pointer to RSPINF RsvTime field + * + * Return Value: none + */ +static +void +s_vCalculateOFDMRParameter( + unsigned char byRate, + u8 bb_type, + unsigned char *pbyTxRate, + unsigned char *pbyRsvTime +) +{ + switch (byRate) { + case RATE_6M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x9B; + *pbyRsvTime = 44; + } else { + *pbyTxRate = 0x8B; + *pbyRsvTime = 50; + } + break; + + case RATE_9M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x9F; + *pbyRsvTime = 36; + } else { + *pbyTxRate = 0x8F; + *pbyRsvTime = 42; + } + break; + + case RATE_12M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x9A; + *pbyRsvTime = 32; + } else { + *pbyTxRate = 0x8A; + *pbyRsvTime = 38; + } + break; + + case RATE_18M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x9E; + *pbyRsvTime = 28; + } else { + *pbyTxRate = 0x8E; + *pbyRsvTime = 34; + } + break; + + case RATE_36M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x9D; + *pbyRsvTime = 24; + } else { + *pbyTxRate = 0x8D; + *pbyRsvTime = 30; + } + break; + + case RATE_48M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x98; + *pbyRsvTime = 24; + } else { + *pbyTxRate = 0x88; + *pbyRsvTime = 30; + } + break; + + case RATE_54M: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x9C; + *pbyRsvTime = 24; + } else { + *pbyTxRate = 0x8C; + *pbyRsvTime = 30; + } + break; + + case RATE_24M: + default: + if (bb_type == BB_TYPE_11A) { /* 5GHZ */ + *pbyTxRate = 0x99; + *pbyRsvTime = 28; + } else { + *pbyTxRate = 0x89; + *pbyRsvTime = 34; + } + break; + } +} + +/*--------------------- Export Functions --------------------------*/ + +/* + * Description: Update IFS + * + * Parameters: + * In: + * pDevice - The adapter to be set + * Out: + * none + * + * Return Value: None. + */ +bool CARDbSetPhyParameter(struct vnt_private *pDevice, u8 bb_type) +{ + unsigned char byCWMaxMin = 0; + unsigned char bySlot = 0; + unsigned char bySIFS = 0; + unsigned char byDIFS = 0; + unsigned char byData; + int i; + + /* Set SIFS, DIFS, EIFS, SlotTime, CwMin */ + if (bb_type == BB_TYPE_11A) { + if (pDevice->byRFType == RF_AIROHA7230) { + /* AL7230 use single PAPE and connect to PAPE_2.4G */ + MACvSetBBType(pDevice->PortOffset, BB_TYPE_11G); + pDevice->abyBBVGA[0] = 0x20; + pDevice->abyBBVGA[2] = 0x10; + pDevice->abyBBVGA[3] = 0x10; + BBbReadEmbedded(pDevice, 0xE7, &byData); + if (byData == 0x1C) + BBbWriteEmbedded(pDevice, 0xE7, pDevice->abyBBVGA[0]); + + } else if (pDevice->byRFType == RF_UW2452) { + MACvSetBBType(pDevice->PortOffset, BB_TYPE_11A); + pDevice->abyBBVGA[0] = 0x18; + BBbReadEmbedded(pDevice, 0xE7, &byData); + if (byData == 0x14) { + BBbWriteEmbedded(pDevice, 0xE7, pDevice->abyBBVGA[0]); + BBbWriteEmbedded(pDevice, 0xE1, 0x57); + } + } else { + MACvSetBBType(pDevice->PortOffset, BB_TYPE_11A); + } + BBbWriteEmbedded(pDevice, 0x88, 0x03); + bySlot = C_SLOT_SHORT; + bySIFS = C_SIFS_A; + byDIFS = C_SIFS_A + 2*C_SLOT_SHORT; + byCWMaxMin = 0xA4; + } else if (bb_type == BB_TYPE_11B) { + MACvSetBBType(pDevice->PortOffset, BB_TYPE_11B); + if (pDevice->byRFType == RF_AIROHA7230) { + pDevice->abyBBVGA[0] = 0x1C; + pDevice->abyBBVGA[2] = 0x00; + pDevice->abyBBVGA[3] = 0x00; + BBbReadEmbedded(pDevice, 0xE7, &byData); + if (byData == 0x20) + BBbWriteEmbedded(pDevice, 0xE7, pDevice->abyBBVGA[0]); + + } else if (pDevice->byRFType == RF_UW2452) { + pDevice->abyBBVGA[0] = 0x14; + BBbReadEmbedded(pDevice, 0xE7, &byData); + if (byData == 0x18) { + BBbWriteEmbedded(pDevice, 0xE7, pDevice->abyBBVGA[0]); + BBbWriteEmbedded(pDevice, 0xE1, 0xD3); + } + } + BBbWriteEmbedded(pDevice, 0x88, 0x02); + bySlot = C_SLOT_LONG; + bySIFS = C_SIFS_BG; + byDIFS = C_SIFS_BG + 2*C_SLOT_LONG; + byCWMaxMin = 0xA5; + } else { /* PK_TYPE_11GA & PK_TYPE_11GB */ + MACvSetBBType(pDevice->PortOffset, BB_TYPE_11G); + if (pDevice->byRFType == RF_AIROHA7230) { + pDevice->abyBBVGA[0] = 0x1C; + pDevice->abyBBVGA[2] = 0x00; + pDevice->abyBBVGA[3] = 0x00; + BBbReadEmbedded(pDevice, 0xE7, &byData); + if (byData == 0x20) + BBbWriteEmbedded(pDevice, 0xE7, pDevice->abyBBVGA[0]); + + } else if (pDevice->byRFType == RF_UW2452) { + pDevice->abyBBVGA[0] = 0x14; + BBbReadEmbedded(pDevice, 0xE7, &byData); + if (byData == 0x18) { + BBbWriteEmbedded(pDevice, 0xE7, pDevice->abyBBVGA[0]); + BBbWriteEmbedded(pDevice, 0xE1, 0xD3); + } + } + BBbWriteEmbedded(pDevice, 0x88, 0x08); + bySIFS = C_SIFS_BG; + + if (pDevice->bShortSlotTime) { + bySlot = C_SLOT_SHORT; + byDIFS = C_SIFS_BG + 2*C_SLOT_SHORT; + } else { + bySlot = C_SLOT_LONG; + byDIFS = C_SIFS_BG + 2*C_SLOT_LONG; + } + + byCWMaxMin = 0xa4; + + for (i = RATE_54M; i >= RATE_6M; i--) { + if (pDevice->basic_rates & ((u32)(0x1 << i))) { + byCWMaxMin |= 0x1; + break; + } + } + } + + if (pDevice->byRFType == RF_RFMD2959) { + /* + * bcs TX_PE will reserve 3 us hardware's processing + * time here is 2 us. + */ + bySIFS -= 3; + byDIFS -= 3; + /* + * TX_PE will reserve 3 us for MAX2829 A mode only, it is for + * better TX throughput; MAC will need 2 us to process, so the + * SIFS, DIFS can be shorter by 2 us. + */ + } + + if (pDevice->bySIFS != bySIFS) { + pDevice->bySIFS = bySIFS; + VNSvOutPortB(pDevice->PortOffset + MAC_REG_SIFS, pDevice->bySIFS); + } + if (pDevice->byDIFS != byDIFS) { + pDevice->byDIFS = byDIFS; + VNSvOutPortB(pDevice->PortOffset + MAC_REG_DIFS, pDevice->byDIFS); + } + if (pDevice->byEIFS != C_EIFS) { + pDevice->byEIFS = C_EIFS; + VNSvOutPortB(pDevice->PortOffset + MAC_REG_EIFS, pDevice->byEIFS); + } + if (pDevice->bySlot != bySlot) { + pDevice->bySlot = bySlot; + VNSvOutPortB(pDevice->PortOffset + MAC_REG_SLOT, pDevice->bySlot); + + BBvSetShortSlotTime(pDevice); + } + if (pDevice->byCWMaxMin != byCWMaxMin) { + pDevice->byCWMaxMin = byCWMaxMin; + VNSvOutPortB(pDevice->PortOffset + MAC_REG_CWMAXMIN0, pDevice->byCWMaxMin); + } + + pDevice->byPacketType = CARDbyGetPktType(pDevice); + + CARDvSetRSPINF(pDevice, bb_type); + + return true; +} + +/* + * Description: Sync. TSF counter to BSS + * Get TSF offset and write to HW + * + * Parameters: + * In: + * pDevice - The adapter to be sync. + * byRxRate - data rate of receive beacon + * qwBSSTimestamp - Rx BCN's TSF + * qwLocalTSF - Local TSF + * Out: + * none + * + * Return Value: none + */ +bool CARDbUpdateTSF(struct vnt_private *pDevice, unsigned char byRxRate, + u64 qwBSSTimestamp) +{ + u64 local_tsf; + u64 qwTSFOffset = 0; + + CARDbGetCurrentTSF(pDevice, &local_tsf); + + if (qwBSSTimestamp != local_tsf) { + qwTSFOffset = CARDqGetTSFOffset(byRxRate, qwBSSTimestamp, + local_tsf); + /* adjust TSF, HW's TSF add TSF Offset reg */ + VNSvOutPortD(pDevice->PortOffset + MAC_REG_TSFOFST, (u32)qwTSFOffset); + VNSvOutPortD(pDevice->PortOffset + MAC_REG_TSFOFST + 4, (u32)(qwTSFOffset >> 32)); + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_TFTCTL, TFTCTL_TSFSYNCEN); + } + return true; +} + +/* + * Description: Set NIC TSF counter for first Beacon time + * Get NEXTTBTT from adjusted TSF and Beacon Interval + * + * Parameters: + * In: + * pDevice - The adapter to be set. + * wBeaconInterval - Beacon Interval + * Out: + * none + * + * Return Value: true if succeed; otherwise false + */ +bool CARDbSetBeaconPeriod(struct vnt_private *pDevice, + unsigned short wBeaconInterval) +{ + u64 qwNextTBTT = 0; + + CARDbGetCurrentTSF(pDevice, &qwNextTBTT); /* Get Local TSF counter */ + + qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval); + + /* set HW beacon interval */ + VNSvOutPortW(pDevice->PortOffset + MAC_REG_BI, wBeaconInterval); + pDevice->wBeaconInterval = wBeaconInterval; + /* Set NextTBTT */ + VNSvOutPortD(pDevice->PortOffset + MAC_REG_NEXTTBTT, (u32)qwNextTBTT); + VNSvOutPortD(pDevice->PortOffset + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32)); + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); + + return true; +} + +/* + * Description: Turn off Radio power + * + * Parameters: + * In: + * pDevice - The adapter to be turned off + * Out: + * none + * + * Return Value: true if success; otherwise false + */ +bool CARDbRadioPowerOff(struct vnt_private *pDevice) +{ + bool bResult = true; + + if (pDevice->bRadioOff == true) + return true; + + switch (pDevice->byRFType) { + case RF_RFMD2959: + MACvWordRegBitsOff(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_TXPEINV); + MACvWordRegBitsOn(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE1); + break; + + case RF_AIROHA: + case RF_AL2230S: + case RF_AIROHA7230: + MACvWordRegBitsOff(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE2); + MACvWordRegBitsOff(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + break; + + } + + MACvRegBitsOff(pDevice->PortOffset, MAC_REG_HOSTCR, HOSTCR_RXON); + + BBvSetDeepSleep(pDevice, pDevice->byLocalID); + + pDevice->bRadioOff = true; + pr_debug("chester power off\n"); + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_GPIOCTL0, LED_ACTSET); /* LED issue */ + return bResult; +} + +/* + * Description: Turn on Radio power + * + * Parameters: + * In: + * pDevice - The adapter to be turned on + * Out: + * none + * + * Return Value: true if success; otherwise false + */ +bool CARDbRadioPowerOn(struct vnt_private *pDevice) +{ + bool bResult = true; + + pr_debug("chester power on\n"); + if (pDevice->bRadioControlOff == true) { + if (pDevice->bHWRadioOff == true) + pr_debug("chester bHWRadioOff\n"); + if (pDevice->bRadioControlOff == true) + pr_debug("chester bRadioControlOff\n"); + return false; } + + if (pDevice->bRadioOff == false) { + pr_debug("chester pbRadioOff\n"); + return true; } + + BBvExitDeepSleep(pDevice, pDevice->byLocalID); + + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_HOSTCR, HOSTCR_RXON); + + switch (pDevice->byRFType) { + case RF_RFMD2959: + MACvWordRegBitsOn(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_TXPEINV); + MACvWordRegBitsOff(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE1); + break; + + case RF_AIROHA: + case RF_AL2230S: + case RF_AIROHA7230: + MACvWordRegBitsOn(pDevice->PortOffset, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE2 | + SOFTPWRCTL_SWPE3)); + break; + + } + + pDevice->bRadioOff = false; + pr_debug("chester power on\n"); + MACvRegBitsOff(pDevice->PortOffset, MAC_REG_GPIOCTL0, LED_ACTSET); /* LED issue */ + return bResult; +} + +void +CARDvSafeResetTx( + struct vnt_private *pDevice +) +{ + unsigned int uu; + PSTxDesc pCurrTD; + + /* initialize TD index */ + pDevice->apTailTD[0] = pDevice->apCurrTD[0] = &(pDevice->apTD0Rings[0]); + pDevice->apTailTD[1] = pDevice->apCurrTD[1] = &(pDevice->apTD1Rings[0]); + + for (uu = 0; uu < TYPE_MAXTD; uu++) + pDevice->iTDUsed[uu] = 0; + + for (uu = 0; uu < pDevice->sOpts.nTxDescs[0]; uu++) { + pCurrTD = &(pDevice->apTD0Rings[uu]); + pCurrTD->m_td0TD0.f1Owner = OWNED_BY_HOST; + /* init all Tx Packet pointer to NULL */ + } + for (uu = 0; uu < pDevice->sOpts.nTxDescs[1]; uu++) { + pCurrTD = &(pDevice->apTD1Rings[uu]); + pCurrTD->m_td0TD0.f1Owner = OWNED_BY_HOST; + /* init all Tx Packet pointer to NULL */ + } + + /* set MAC TD pointer */ + MACvSetCurrTXDescAddr(TYPE_TXDMA0, pDevice->PortOffset, + (pDevice->td0_pool_dma)); + + MACvSetCurrTXDescAddr(TYPE_AC0DMA, pDevice->PortOffset, + (pDevice->td1_pool_dma)); + + /* set MAC Beacon TX pointer */ + MACvSetCurrBCNTxDescAddr(pDevice->PortOffset, + (pDevice->tx_beacon_dma)); +} + +/* + * Description: + * Reset Rx + * + * Parameters: + * In: + * pDevice - Pointer to the adapter + * Out: + * none + * + * Return Value: none + */ +void +CARDvSafeResetRx( + struct vnt_private *pDevice +) +{ + unsigned int uu; + PSRxDesc pDesc; + + /* initialize RD index */ + pDevice->pCurrRD[0] = &(pDevice->aRD0Ring[0]); + pDevice->pCurrRD[1] = &(pDevice->aRD1Ring[0]); + + /* init state, all RD is chip's */ + for (uu = 0; uu < pDevice->sOpts.nRxDescs0; uu++) { + pDesc = &(pDevice->aRD0Ring[uu]); + pDesc->m_rd0RD0.wResCount = (unsigned short)(pDevice->rx_buf_sz); + pDesc->m_rd0RD0.f1Owner = OWNED_BY_NIC; + pDesc->m_rd1RD1.wReqCount = (unsigned short)(pDevice->rx_buf_sz); + } + + /* init state, all RD is chip's */ + for (uu = 0; uu < pDevice->sOpts.nRxDescs1; uu++) { + pDesc = &(pDevice->aRD1Ring[uu]); + pDesc->m_rd0RD0.wResCount = (unsigned short)(pDevice->rx_buf_sz); + pDesc->m_rd0RD0.f1Owner = OWNED_BY_NIC; + pDesc->m_rd1RD1.wReqCount = (unsigned short)(pDevice->rx_buf_sz); + } + + /* set perPkt mode */ + MACvRx0PerPktMode(pDevice->PortOffset); + MACvRx1PerPktMode(pDevice->PortOffset); + /* set MAC RD pointer */ + MACvSetCurrRx0DescAddr(pDevice->PortOffset, + pDevice->rd0_pool_dma); + + MACvSetCurrRx1DescAddr(pDevice->PortOffset, + pDevice->rd1_pool_dma); +} + +/* + * Description: Get response Control frame rate in CCK mode + * + * Parameters: + * In: + * pDevice - The adapter to be set + * wRateIdx - Receiving data rate + * Out: + * none + * + * Return Value: response Control frame rate + */ +static unsigned short CARDwGetCCKControlRate(struct vnt_private *pDevice, + unsigned short wRateIdx) +{ + unsigned int ui = (unsigned int) wRateIdx; + + while (ui > RATE_1M) { + if (pDevice->basic_rates & ((u32)0x1 << ui)) + return (unsigned short)ui; + + ui--; + } + return (unsigned short)RATE_1M; +} + +/* + * Description: Get response Control frame rate in OFDM mode + * + * Parameters: + * In: + * pDevice - The adapter to be set + * wRateIdx - Receiving data rate + * Out: + * none + * + * Return Value: response Control frame rate + */ +static unsigned short CARDwGetOFDMControlRate(struct vnt_private *pDevice, + unsigned short wRateIdx) +{ + unsigned int ui = (unsigned int) wRateIdx; + + pr_debug("BASIC RATE: %X\n", pDevice->basic_rates); + + if (!CARDbIsOFDMinBasicRate((void *)pDevice)) { + pr_debug("CARDwGetOFDMControlRate:(NO OFDM) %d\n", wRateIdx); + if (wRateIdx > RATE_24M) + wRateIdx = RATE_24M; + return wRateIdx; + } + while (ui > RATE_11M) { + if (pDevice->basic_rates & ((u32)0x1 << ui)) { + pr_debug("CARDwGetOFDMControlRate : %d\n", ui); + return (unsigned short)ui; + } + ui--; + } + pr_debug("CARDwGetOFDMControlRate: 6M\n"); + return (unsigned short)RATE_24M; +} + +/* + * Description: Set RSPINF + * + * Parameters: + * In: + * pDevice - The adapter to be set + * Out: + * none + * + * Return Value: None. + */ +void CARDvSetRSPINF(struct vnt_private *pDevice, u8 bb_type) +{ + union vnt_phy_field_swap phy; + unsigned char byTxRate, byRsvTime; /* For OFDM */ + unsigned long flags; + + spin_lock_irqsave(&pDevice->lock, flags); + + /* Set to Page1 */ + MACvSelectPage1(pDevice->PortOffset); + + /* RSPINF_b_1 */ + vnt_get_phy_field(pDevice, 14, + CARDwGetCCKControlRate(pDevice, RATE_1M), + PK_TYPE_11B, &phy.field_read); + + /* swap over to get correct write order */ + swap(phy.swap[0], phy.swap[1]); + + VNSvOutPortD(pDevice->PortOffset + MAC_REG_RSPINF_B_1, phy.field_write); + + /* RSPINF_b_2 */ + vnt_get_phy_field(pDevice, 14, + CARDwGetCCKControlRate(pDevice, RATE_2M), + PK_TYPE_11B, &phy.field_read); + + swap(phy.swap[0], phy.swap[1]); + + VNSvOutPortD(pDevice->PortOffset + MAC_REG_RSPINF_B_2, phy.field_write); + + /* RSPINF_b_5 */ + vnt_get_phy_field(pDevice, 14, + CARDwGetCCKControlRate(pDevice, RATE_5M), + PK_TYPE_11B, &phy.field_read); + + swap(phy.swap[0], phy.swap[1]); + + VNSvOutPortD(pDevice->PortOffset + MAC_REG_RSPINF_B_5, phy.field_write); + + /* RSPINF_b_11 */ + vnt_get_phy_field(pDevice, 14, + CARDwGetCCKControlRate(pDevice, RATE_11M), + PK_TYPE_11B, &phy.field_read); + + swap(phy.swap[0], phy.swap[1]); + + VNSvOutPortD(pDevice->PortOffset + MAC_REG_RSPINF_B_11, phy.field_write); + + /* RSPINF_a_6 */ + s_vCalculateOFDMRParameter(RATE_6M, + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_6, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_9 */ + s_vCalculateOFDMRParameter(RATE_9M, + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_9, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_12 */ + s_vCalculateOFDMRParameter(RATE_12M, + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_12, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_18 */ + s_vCalculateOFDMRParameter(RATE_18M, + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_18, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_24 */ + s_vCalculateOFDMRParameter(RATE_24M, + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_24, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_36 */ + s_vCalculateOFDMRParameter(CARDwGetOFDMControlRate((void *)pDevice, RATE_36M), + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_36, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_48 */ + s_vCalculateOFDMRParameter(CARDwGetOFDMControlRate((void *)pDevice, RATE_48M), + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_48, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_54 */ + s_vCalculateOFDMRParameter(CARDwGetOFDMControlRate((void *)pDevice, RATE_54M), + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_54, MAKEWORD(byTxRate, byRsvTime)); + /* RSPINF_a_72 */ + s_vCalculateOFDMRParameter(CARDwGetOFDMControlRate((void *)pDevice, RATE_54M), + bb_type, + &byTxRate, + &byRsvTime); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_RSPINF_A_72, MAKEWORD(byTxRate, byRsvTime)); + /* Set to Page0 */ + MACvSelectPage0(pDevice->PortOffset); + + spin_unlock_irqrestore(&pDevice->lock, flags); +} + +void CARDvUpdateBasicTopRate(struct vnt_private *pDevice) +{ + unsigned char byTopOFDM = RATE_24M, byTopCCK = RATE_1M; + unsigned char ii; + + /* Determines the highest basic rate. */ + for (ii = RATE_54M; ii >= RATE_6M; ii--) { + if ((pDevice->basic_rates) & ((u32)(1 << ii))) { + byTopOFDM = ii; + break; + } + } + pDevice->byTopOFDMBasicRate = byTopOFDM; + + for (ii = RATE_11M;; ii--) { + if ((pDevice->basic_rates) & ((u32)(1 << ii))) { + byTopCCK = ii; + break; + } + if (ii == RATE_1M) + break; + } + pDevice->byTopCCKBasicRate = byTopCCK; +} + +bool CARDbIsOFDMinBasicRate(struct vnt_private *pDevice) +{ + int ii; + + for (ii = RATE_54M; ii >= RATE_6M; ii--) { + if ((pDevice->basic_rates) & ((u32)(1 << ii))) + return true; + } + return false; +} + +unsigned char CARDbyGetPktType(struct vnt_private *pDevice) +{ + + if (pDevice->byBBType == BB_TYPE_11A || pDevice->byBBType == BB_TYPE_11B) + return (unsigned char)pDevice->byBBType; + else if (CARDbIsOFDMinBasicRate((void *)pDevice)) + return PK_TYPE_11GA; + else + return PK_TYPE_11GB; +} + +/* + * Description: Set NIC Loopback mode + * + * Parameters: + * In: + * pDevice - The adapter to be set + * wLoopbackMode - Loopback mode to be set + * Out: + * none + * + * Return Value: none + */ +void CARDvSetLoopbackMode(struct vnt_private *priv, unsigned short wLoopbackMode) +{ + void __iomem *dwIoBase = priv->PortOffset; + + switch (wLoopbackMode) { + case CARD_LB_NONE: + case CARD_LB_MAC: + case CARD_LB_PHY: + break; + default: + ASSERT(false); + break; + } + /* set MAC loopback */ + MACvSetLoopbackMode(dwIoBase, LOBYTE(wLoopbackMode)); + /* set Baseband loopback */ +} + +/* + * Description: Software Reset NIC + * + * Parameters: + * In: + * pDevice - The adapter to be reset + * Out: + * none + * + * Return Value: none + */ +bool CARDbSoftwareReset(struct vnt_private *pDevice) +{ + + /* reset MAC */ + if (!MACbSafeSoftwareReset(pDevice->PortOffset)) + return false; + + return true; +} + +/* + * Description: Calculate TSF offset of two TSF input + * Get TSF Offset from RxBCN's TSF and local TSF + * + * Parameters: + * In: + * pDevice - The adapter to be sync. + * qwTSF1 - Rx BCN's TSF + * qwTSF2 - Local TSF + * Out: + * none + * + * Return Value: TSF Offset value + */ +u64 CARDqGetTSFOffset(unsigned char byRxRate, u64 qwTSF1, u64 qwTSF2) +{ + u64 qwTSFOffset = 0; + unsigned short wRxBcnTSFOffst = 0; + + wRxBcnTSFOffst = cwRXBCNTSFOff[byRxRate%MAX_RATE]; + + qwTSF2 += (u64)wRxBcnTSFOffst; + + qwTSFOffset = qwTSF1 - qwTSF2; + + return qwTSFOffset; +} + +/* + * Description: Read NIC TSF counter + * Get local TSF counter + * + * Parameters: + * In: + * pDevice - The adapter to be read + * Out: + * qwCurrTSF - Current TSF counter + * + * Return Value: true if success; otherwise false + */ +bool CARDbGetCurrentTSF(struct vnt_private *priv, u64 *pqwCurrTSF) +{ + void __iomem *dwIoBase = priv->PortOffset; + unsigned short ww; + unsigned char byData; + + MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TSFCNTRRD); + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_TFTCTL, &byData); + if (!(byData & TFTCTL_TSFCNTRRD)) + break; + } + if (ww == W_MAX_TIMEOUT) + return false; + VNSvInPortD(dwIoBase + MAC_REG_TSFCNTR, (u32 *)pqwCurrTSF); + VNSvInPortD(dwIoBase + MAC_REG_TSFCNTR + 4, (u32 *)pqwCurrTSF + 1); + + return true; +} + +/* + * Description: Read NIC TSF counter + * Get NEXTTBTT from adjusted TSF and Beacon Interval + * + * Parameters: + * In: + * qwTSF - Current TSF counter + * wbeaconInterval - Beacon Interval + * Out: + * qwCurrTSF - Current TSF counter + * + * Return Value: TSF value of next Beacon + */ +u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval) +{ + u32 beacon_int; + + beacon_int = wBeaconInterval * 1024; + if (beacon_int) { + do_div(qwTSF, beacon_int); + qwTSF += 1; + qwTSF *= beacon_int; + } + + return qwTSF; +} + +/* + * Description: Set NIC TSF counter for first Beacon time + * Get NEXTTBTT from adjusted TSF and Beacon Interval + * + * Parameters: + * In: + * dwIoBase - IO Base + * wBeaconInterval - Beacon Interval + * Out: + * none + * + * Return Value: none + */ +void CARDvSetFirstNextTBTT(struct vnt_private *priv, unsigned short wBeaconInterval) +{ + void __iomem *dwIoBase = priv->PortOffset; + u64 qwNextTBTT = 0; + + CARDbGetCurrentTSF(priv, &qwNextTBTT); /* Get Local TSF counter */ + + qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval); + /* Set NextTBTT */ + VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT); + VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32)); + MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); +} + +/* + * Description: Sync NIC TSF counter for Beacon time + * Get NEXTTBTT and write to HW + * + * Parameters: + * In: + * pDevice - The adapter to be set + * qwTSF - Current TSF counter + * wBeaconInterval - Beacon Interval + * Out: + * none + * + * Return Value: none + */ +void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF, unsigned short wBeaconInterval) +{ + void __iomem *dwIoBase = priv->PortOffset; + + qwTSF = CARDqGetNextTBTT(qwTSF, wBeaconInterval); + /* Set NextTBTT */ + VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT, (u32)qwTSF); + VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32)); + MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); + pr_debug("Card:Update Next TBTT[%8llx]\n", qwTSF); +} diff --git a/kernel/drivers/staging/vt6655/card.h b/kernel/drivers/staging/vt6655/card.h new file mode 100644 index 000000000..16cca49e6 --- /dev/null +++ b/kernel/drivers/staging/vt6655/card.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: card.h + * + * Purpose: Provide functions to setup NIC operation mode + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + */ + +#ifndef __CARD_H__ +#define __CARD_H__ + +#include <linux/types.h> +#include <linux/nl80211.h> + +/* + * Loopback mode + * + * LOBYTE is MAC LB mode, HIBYTE is MII LB mode + */ +#define CARD_LB_NONE MAKEWORD(MAC_LB_NONE, 0) +#define CARD_LB_MAC MAKEWORD(MAC_LB_INTERNAL, 0) /* PHY must ISO, avoid MAC loopback packet go out */ +#define CARD_LB_PHY MAKEWORD(MAC_LB_EXT, 0) + +#define DEFAULT_MSDU_LIFETIME 512 /* ms */ +#define DEFAULT_MSDU_LIFETIME_RES_64us 8000 /* 64us */ + +#define DEFAULT_MGN_LIFETIME 8 /* ms */ +#define DEFAULT_MGN_LIFETIME_RES_64us 125 /* 64us */ + +#define CB_MAX_CHANNEL_24G 14 +#define CB_MAX_CHANNEL_5G 42 +#define CB_MAX_CHANNEL (CB_MAX_CHANNEL_24G+CB_MAX_CHANNEL_5G) + +typedef enum _CARD_PKT_TYPE { + PKT_TYPE_802_11_BCN, + PKT_TYPE_802_11_MNG, + PKT_TYPE_802_11_DATA, + PKT_TYPE_802_11_ALL +} CARD_PKT_TYPE, *PCARD_PKT_TYPE; + +typedef enum _CARD_STATUS_TYPE { + CARD_STATUS_MEDIA_CONNECT, + CARD_STATUS_MEDIA_DISCONNECT, + CARD_STATUS_PMKID +} CARD_STATUS_TYPE, *PCARD_STATUS_TYPE; + +struct vnt_private; + +void CARDvSetRSPINF(struct vnt_private *, u8); +void CARDvUpdateBasicTopRate(struct vnt_private *); +bool CARDbIsOFDMinBasicRate(struct vnt_private *); +void CARDvSetLoopbackMode(struct vnt_private *, unsigned short wLoopbackMode); +bool CARDbSoftwareReset(struct vnt_private *); +void CARDvSetFirstNextTBTT(struct vnt_private *, unsigned short wBeaconInterval); +void CARDvUpdateNextTBTT(struct vnt_private *, u64 qwTSF, unsigned short wBeaconInterval); +bool CARDbGetCurrentTSF(struct vnt_private *, u64 *pqwCurrTSF); +u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval); +u64 CARDqGetTSFOffset(unsigned char byRxRate, u64 qwTSF1, u64 qwTSF2); +unsigned char CARDbyGetPktType(struct vnt_private *); +void CARDvSafeResetTx(struct vnt_private *); +void CARDvSafeResetRx(struct vnt_private *); +bool CARDbRadioPowerOff(struct vnt_private *); +bool CARDbRadioPowerOn(struct vnt_private *); +bool CARDbSetPhyParameter(struct vnt_private *, u8); +bool CARDbUpdateTSF(struct vnt_private *, unsigned char byRxRate, + u64 qwBSSTimestamp); +bool CARDbSetBeaconPeriod(struct vnt_private *, unsigned short wBeaconInterval); + +#endif /* __CARD_H__ */ diff --git a/kernel/drivers/staging/vt6655/channel.c b/kernel/drivers/staging/vt6655/channel.c new file mode 100644 index 000000000..7a717828f --- /dev/null +++ b/kernel/drivers/staging/vt6655/channel.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: channel.c + * + */ + +#include "baseband.h" +#include "channel.h" +#include "device.h" +#include "rf.h" + +static struct ieee80211_rate vnt_rates_bg[] = { + { .bitrate = 10, .hw_value = RATE_1M }, + { .bitrate = 20, .hw_value = RATE_2M }, + { .bitrate = 55, .hw_value = RATE_5M }, + { .bitrate = 110, .hw_value = RATE_11M }, + { .bitrate = 60, .hw_value = RATE_6M }, + { .bitrate = 90, .hw_value = RATE_9M }, + { .bitrate = 120, .hw_value = RATE_12M }, + { .bitrate = 180, .hw_value = RATE_18M }, + { .bitrate = 240, .hw_value = RATE_24M }, + { .bitrate = 360, .hw_value = RATE_36M }, + { .bitrate = 480, .hw_value = RATE_48M }, + { .bitrate = 540, .hw_value = RATE_54M }, +}; + +static struct ieee80211_rate vnt_rates_a[] = { + { .bitrate = 60, .hw_value = RATE_6M }, + { .bitrate = 90, .hw_value = RATE_9M }, + { .bitrate = 120, .hw_value = RATE_12M }, + { .bitrate = 180, .hw_value = RATE_18M }, + { .bitrate = 240, .hw_value = RATE_24M }, + { .bitrate = 360, .hw_value = RATE_36M }, + { .bitrate = 480, .hw_value = RATE_48M }, + { .bitrate = 540, .hw_value = RATE_54M }, +}; + +static struct ieee80211_channel vnt_channels_2ghz[] = { + { .center_freq = 2412, .hw_value = 1 }, + { .center_freq = 2417, .hw_value = 2 }, + { .center_freq = 2422, .hw_value = 3 }, + { .center_freq = 2427, .hw_value = 4 }, + { .center_freq = 2432, .hw_value = 5 }, + { .center_freq = 2437, .hw_value = 6 }, + { .center_freq = 2442, .hw_value = 7 }, + { .center_freq = 2447, .hw_value = 8 }, + { .center_freq = 2452, .hw_value = 9 }, + { .center_freq = 2457, .hw_value = 10 }, + { .center_freq = 2462, .hw_value = 11 }, + { .center_freq = 2467, .hw_value = 12 }, + { .center_freq = 2472, .hw_value = 13 }, + { .center_freq = 2484, .hw_value = 14 } +}; + +static struct ieee80211_channel vnt_channels_5ghz[] = { + { .center_freq = 4915, .hw_value = 15 }, + { .center_freq = 4920, .hw_value = 16 }, + { .center_freq = 4925, .hw_value = 17 }, + { .center_freq = 4935, .hw_value = 18 }, + { .center_freq = 4940, .hw_value = 19 }, + { .center_freq = 4945, .hw_value = 20 }, + { .center_freq = 4960, .hw_value = 21 }, + { .center_freq = 4980, .hw_value = 22 }, + { .center_freq = 5035, .hw_value = 23 }, + { .center_freq = 5040, .hw_value = 24 }, + { .center_freq = 5045, .hw_value = 25 }, + { .center_freq = 5055, .hw_value = 26 }, + { .center_freq = 5060, .hw_value = 27 }, + { .center_freq = 5080, .hw_value = 28 }, + { .center_freq = 5170, .hw_value = 29 }, + { .center_freq = 5180, .hw_value = 30 }, + { .center_freq = 5190, .hw_value = 31 }, + { .center_freq = 5200, .hw_value = 32 }, + { .center_freq = 5210, .hw_value = 33 }, + { .center_freq = 5220, .hw_value = 34 }, + { .center_freq = 5230, .hw_value = 35 }, + { .center_freq = 5240, .hw_value = 36 }, + { .center_freq = 5260, .hw_value = 37 }, + { .center_freq = 5280, .hw_value = 38 }, + { .center_freq = 5300, .hw_value = 39 }, + { .center_freq = 5320, .hw_value = 40 }, + { .center_freq = 5500, .hw_value = 41 }, + { .center_freq = 5520, .hw_value = 42 }, + { .center_freq = 5540, .hw_value = 43 }, + { .center_freq = 5560, .hw_value = 44 }, + { .center_freq = 5580, .hw_value = 45 }, + { .center_freq = 5600, .hw_value = 46 }, + { .center_freq = 5620, .hw_value = 47 }, + { .center_freq = 5640, .hw_value = 48 }, + { .center_freq = 5660, .hw_value = 49 }, + { .center_freq = 5680, .hw_value = 50 }, + { .center_freq = 5700, .hw_value = 51 }, + { .center_freq = 5745, .hw_value = 52 }, + { .center_freq = 5765, .hw_value = 53 }, + { .center_freq = 5785, .hw_value = 54 }, + { .center_freq = 5805, .hw_value = 55 }, + { .center_freq = 5825, .hw_value = 56 } +}; + +static struct ieee80211_supported_band vnt_supported_2ghz_band = { + .channels = vnt_channels_2ghz, + .n_channels = ARRAY_SIZE(vnt_channels_2ghz), + .bitrates = vnt_rates_bg, + .n_bitrates = ARRAY_SIZE(vnt_rates_bg), +}; + +static struct ieee80211_supported_band vnt_supported_5ghz_band = { + .channels = vnt_channels_5ghz, + .n_channels = ARRAY_SIZE(vnt_channels_5ghz), + .bitrates = vnt_rates_a, + .n_bitrates = ARRAY_SIZE(vnt_rates_a), +}; + +void vnt_init_bands(struct vnt_private *priv) +{ + struct ieee80211_channel *ch; + int i; + + switch (priv->byRFType) { + case RF_AIROHA7230: + case RF_UW2452: + case RF_NOTHING: + default: + ch = vnt_channels_5ghz; + + for (i = 0; i < ARRAY_SIZE(vnt_channels_5ghz); i++) { + ch[i].max_power = 0x3f; + ch[i].flags = IEEE80211_CHAN_NO_HT40; + } + + priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = + &vnt_supported_5ghz_band; + /* fallthrough */ + case RF_RFMD2959: + case RF_AIROHA: + case RF_AL2230S: + case RF_UW2451: + case RF_VT3226: + ch = vnt_channels_2ghz; + + for (i = 0; i < ARRAY_SIZE(vnt_channels_2ghz); i++) { + ch[i].max_power = 0x3f; + ch[i].flags = IEEE80211_CHAN_NO_HT40; + } + + priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = + &vnt_supported_2ghz_band; + break; + } +} + +/** + * set_channel() - Set NIC media channel + * + * @pDeviceHandler: The adapter to be set + * @uConnectionChannel: Channel to be set + * + * Return Value: true if succeeded; false if failed. + * + */ +bool set_channel(void *pDeviceHandler, struct ieee80211_channel *ch) +{ + struct vnt_private *pDevice = pDeviceHandler; + bool bResult = true; + + if (pDevice->byCurrentCh == ch->hw_value) + return bResult; + + /* Set VGA to max sensitivity */ + if (pDevice->bUpdateBBVGA && + pDevice->byBBVGACurrent != pDevice->abyBBVGA[0]) { + pDevice->byBBVGACurrent = pDevice->abyBBVGA[0]; + + BBvSetVGAGainOffset(pDevice, pDevice->byBBVGACurrent); + } + + /* clear NAV */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_MACCR, MACCR_CLRNAV); + + /* TX_PE will reserve 3 us for MAX2829 A mode only, + it is for better TX throughput */ + + if (pDevice->byRFType == RF_AIROHA7230) + RFbAL7230SelectChannelPostProcess(pDevice, pDevice->byCurrentCh, + ch->hw_value); + + pDevice->byCurrentCh = ch->hw_value; + bResult &= RFbSelectChannel(pDevice, pDevice->byRFType, + ch->hw_value); + + /* Init Synthesizer Table */ + if (pDevice->bEnablePSMode) + RFvWriteWakeProgSyn(pDevice, pDevice->byRFType, ch->hw_value); + + BBvSoftwareReset(pDevice); + + if (pDevice->byLocalID > REV_ID_VT3253_B1) { + unsigned long flags; + + spin_lock_irqsave(&pDevice->lock, flags); + + /* set HW default power register */ + MACvSelectPage1(pDevice->PortOffset); + RFbSetPower(pDevice, RATE_1M, pDevice->byCurrentCh); + VNSvOutPortB(pDevice->PortOffset + MAC_REG_PWRCCK, + pDevice->byCurPwr); + RFbSetPower(pDevice, RATE_6M, pDevice->byCurrentCh); + VNSvOutPortB(pDevice->PortOffset + MAC_REG_PWROFDM, + pDevice->byCurPwr); + MACvSelectPage0(pDevice->PortOffset); + + spin_unlock_irqrestore(&pDevice->lock, flags); + } + + if (pDevice->byBBType == BB_TYPE_11B) + RFbSetPower(pDevice, RATE_1M, pDevice->byCurrentCh); + else + RFbSetPower(pDevice, RATE_6M, pDevice->byCurrentCh); + + return bResult; +} diff --git a/kernel/drivers/staging/vt6655/channel.h b/kernel/drivers/staging/vt6655/channel.h new file mode 100644 index 000000000..e2be6fca5 --- /dev/null +++ b/kernel/drivers/staging/vt6655/channel.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: channel.h + * + */ + +#ifndef _CHANNEL_H_ +#define _CHANNEL_H_ + +#include "card.h" + +void vnt_init_bands(struct vnt_private *); + +bool set_channel(void *pDeviceHandler, struct ieee80211_channel *); + +#endif /* _CHANNEL_H_ */ diff --git a/kernel/drivers/staging/vt6655/desc.h b/kernel/drivers/staging/vt6655/desc.h new file mode 100644 index 000000000..758eeb2af --- /dev/null +++ b/kernel/drivers/staging/vt6655/desc.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: desc.h + * + * Purpose:The header file of descriptor + * + * Revision History: + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + */ + +#ifndef __DESC_H__ +#define __DESC_H__ + +#include <linux/types.h> +#include <linux/mm.h> +#include "linux/ieee80211.h" + +#define B_OWNED_BY_CHIP 1 +#define B_OWNED_BY_HOST 0 + +/* Bits in the RSR register */ +#define RSR_ADDRBROAD 0x80 +#define RSR_ADDRMULTI 0x40 +#define RSR_ADDRUNI 0x00 +#define RSR_IVLDTYP 0x20 +#define RSR_IVLDLEN 0x10 /* invalid len (> 2312 byte) */ +#define RSR_BSSIDOK 0x08 +#define RSR_CRCOK 0x04 +#define RSR_BCNSSIDOK 0x02 +#define RSR_ADDROK 0x01 + +/* Bits in the new RSR register */ +#define NEWRSR_DECRYPTOK 0x10 +#define NEWRSR_CFPIND 0x08 +#define NEWRSR_HWUTSF 0x04 +#define NEWRSR_BCNHITAID 0x02 +#define NEWRSR_BCNHITAID0 0x01 + +/* Bits in the TSR0 register */ +#define TSR0_PWRSTS1_2 0xC0 +#define TSR0_PWRSTS7 0x20 +#define TSR0_NCR 0x1F + +/* Bits in the TSR1 register */ +#define TSR1_TERR 0x80 +#define TSR1_PWRSTS4_6 0x70 +#define TSR1_RETRYTMO 0x08 +#define TSR1_TMO 0x04 +#define TSR1_PWRSTS3 0x02 +#define ACK_DATA 0x01 + +/* Bits in the TCR register */ +#define EDMSDU 0x04 /* end of sdu */ +#define TCR_EDP 0x02 /* end of packet */ +#define TCR_STP 0x01 /* start of packet */ + +/* max transmit or receive buffer size */ +#define CB_MAX_BUF_SIZE 2900U + /* NOTE: must be multiple of 4 */ +#define CB_MAX_TX_BUF_SIZE CB_MAX_BUF_SIZE +#define CB_MAX_RX_BUF_SIZE_NORMAL CB_MAX_BUF_SIZE + +#define CB_BEACON_BUF_SIZE 512U + +#define CB_MAX_RX_DESC 128 +#define CB_MIN_RX_DESC 16 +#define CB_MAX_TX_DESC 64 +#define CB_MIN_TX_DESC 16 + +#define CB_MAX_RECEIVED_PACKETS 16 + /* + * limit our receive routine to indicating + * this many at a time for 2 reasons: + * 1. driver flow control to protocol layer + * 2. limit the time used in ISR routine + */ + +#define CB_EXTRA_RD_NUM 32 +#define CB_RD_NUM 32 +#define CB_TD_NUM 32 + +/* + * max number of physical segments in a single NDIS packet. Above this + * threshold, the packet is copied into a single physically contiguous buffer + */ +#define CB_MAX_SEGMENT 4 + +#define CB_MIN_MAP_REG_NUM 4 +#define CB_MAX_MAP_REG_NUM CB_MAX_TX_DESC + +#define CB_PROTOCOL_RESERVED_SECTION 16 + +/* + * if retrys excess 15 times , tx will abort, and if tx fifo underflow, + * tx will fail, we should try to resend it + */ +#define CB_MAX_TX_ABORT_RETRY 3 + +/* WMAC definition FIFO Control */ +#define FIFOCTL_AUTO_FB_1 0x1000 +#define FIFOCTL_AUTO_FB_0 0x0800 +#define FIFOCTL_GRPACK 0x0400 +#define FIFOCTL_11GA 0x0300 +#define FIFOCTL_11GB 0x0200 +#define FIFOCTL_11B 0x0100 +#define FIFOCTL_11A 0x0000 +#define FIFOCTL_RTS 0x0080 +#define FIFOCTL_ISDMA0 0x0040 +#define FIFOCTL_GENINT 0x0020 +#define FIFOCTL_TMOEN 0x0010 +#define FIFOCTL_LRETRY 0x0008 +#define FIFOCTL_CRCDIS 0x0004 +#define FIFOCTL_NEEDACK 0x0002 +#define FIFOCTL_LHEAD 0x0001 + +/* WMAC definition Frag Control */ +#define FRAGCTL_AES 0x0300 +#define FRAGCTL_TKIP 0x0200 +#define FRAGCTL_LEGACY 0x0100 +#define FRAGCTL_NONENCRYPT 0x0000 +#define FRAGCTL_ENDFRAG 0x0003 +#define FRAGCTL_MIDFRAG 0x0002 +#define FRAGCTL_STAFRAG 0x0001 +#define FRAGCTL_NONFRAG 0x0000 + +#define TYPE_TXDMA0 0 +#define TYPE_AC0DMA 1 +#define TYPE_ATIMDMA 2 +#define TYPE_SYNCDMA 3 +#define TYPE_MAXTD 2 + +#define TYPE_BEACONDMA 4 + +#define TYPE_RXDMA0 0 +#define TYPE_RXDMA1 1 +#define TYPE_MAXRD 2 + +/* TD_INFO flags control bit */ +#define TD_FLAGS_NETIF_SKB 0x01 /* check if need release skb */ +#define TD_FLAGS_PRIV_SKB 0x02 /* check if called from private skb (hostap) */ +#define TD_FLAGS_PS_RETRY 0x04 /* check if PS STA frame re-transmit */ + +/* + * ref_sk_buff is used for mapping the skb structure between pre-built + * driver-obj & running kernel. Since different kernel version (2.4x) may + * change skb structure, i.e. pre-built driver-obj may link to older skb that + * leads error. + */ + +typedef struct tagDEVICE_RD_INFO { + struct sk_buff *skb; + dma_addr_t skb_dma; + dma_addr_t curr_desc; +} DEVICE_RD_INFO, *PDEVICE_RD_INFO; + +#ifdef __BIG_ENDIAN + +typedef struct tagRDES0 { + volatile unsigned short wResCount; + union { + volatile u16 f15Reserved; + struct { + volatile u8 f8Reserved1; + volatile u8 f1Owner:1; + volatile u8 f7Reserved:7; + } __attribute__ ((__packed__)); + } __attribute__ ((__packed__)); +} __attribute__ ((__packed__)) +SRDES0, *PSRDES0; + +#else + +typedef struct tagRDES0 { + unsigned short wResCount; + unsigned short f15Reserved:15; + unsigned short f1Owner:1; +} __attribute__ ((__packed__)) +SRDES0; + +#endif + +typedef struct tagRDES1 { + unsigned short wReqCount; + unsigned short wReserved; +} __attribute__ ((__packed__)) +SRDES1; + +/* Rx descriptor*/ +typedef struct tagSRxDesc { + volatile SRDES0 m_rd0RD0; + volatile SRDES1 m_rd1RD1; + volatile u32 buff_addr; + volatile u32 next_desc; + struct tagSRxDesc *next __aligned(8); + volatile PDEVICE_RD_INFO pRDInfo __aligned(8); +} __attribute__ ((__packed__)) +SRxDesc, *PSRxDesc; +typedef const SRxDesc *PCSRxDesc; + +#ifdef __BIG_ENDIAN + +typedef struct tagTDES0 { + volatile unsigned char byTSR0; + volatile unsigned char byTSR1; + union { + volatile u16 f15Txtime; + struct { + volatile u8 f8Reserved1; + volatile u8 f1Owner:1; + volatile u8 f7Reserved:7; + } __attribute__ ((__packed__)); + } __attribute__ ((__packed__)); +} __attribute__ ((__packed__)) +STDES0, PSTDES0; + +#else + +typedef struct tagTDES0 { + volatile unsigned char byTSR0; + volatile unsigned char byTSR1; + volatile unsigned short f15Txtime:15; + volatile unsigned short f1Owner:1; +} __attribute__ ((__packed__)) +STDES0; + +#endif + +typedef struct tagTDES1 { + volatile unsigned short wReqCount; + volatile unsigned char byTCR; + volatile unsigned char byReserved; +} __attribute__ ((__packed__)) +STDES1; + +typedef struct tagDEVICE_TD_INFO { + void *mic_hdr; + struct sk_buff *skb; + unsigned char *buf; + dma_addr_t skb_dma; + dma_addr_t buf_dma; + dma_addr_t curr_desc; + unsigned long dwReqCount; + unsigned long dwHeaderLength; + unsigned char byFlags; +} DEVICE_TD_INFO, *PDEVICE_TD_INFO; + +/* transmit descriptor */ +typedef struct tagSTxDesc { + volatile STDES0 m_td0TD0; + volatile STDES1 m_td1TD1; + volatile u32 buff_addr; + volatile u32 next_desc; + struct tagSTxDesc *next __aligned(8); + volatile PDEVICE_TD_INFO pTDInfo __aligned(8); +} __attribute__ ((__packed__)) +STxDesc, *PSTxDesc; +typedef const STxDesc *PCSTxDesc; + +typedef struct tagSTxSyncDesc { + volatile STDES0 m_td0TD0; + volatile STDES1 m_td1TD1; + volatile u32 buff_addr; /* pointer to logical buffer */ + volatile u32 next_desc; /* pointer to next logical descriptor */ + volatile unsigned short m_wFIFOCtl; + volatile unsigned short m_wTimeStamp; + struct tagSTxSyncDesc *next __aligned(8); + volatile PDEVICE_TD_INFO pTDInfo __aligned(8); +} __attribute__ ((__packed__)) +STxSyncDesc, *PSTxSyncDesc; +typedef const STxSyncDesc *PCSTxSyncDesc; + +/* RsvTime buffer header */ +typedef struct tagSRrvTime_atim { + unsigned short wCTSTxRrvTime_ba; + unsigned short wTxRrvTime_a; +} __attribute__ ((__packed__)) +SRrvTime_atim, *PSRrvTime_atim; +typedef const SRrvTime_atim *PCSRrvTime_atim; + +/* Length, Service, and Signal fields of Phy for Tx */ +struct vnt_phy_field { + u8 signal; + u8 service; + __le16 len; +} __packed; + +union vnt_phy_field_swap { + struct vnt_phy_field field_read; + u16 swap[2]; + u32 field_write; +}; + +/* Tx FIFO header */ +typedef struct tagSTxBufHead { + u32 adwTxKey[4]; + unsigned short wFIFOCtl; + unsigned short wTimeStamp; + unsigned short wFragCtl; + unsigned char byTxPower; + unsigned char wReserved; +} __attribute__ ((__packed__)) +STxBufHead, *PSTxBufHead; +typedef const STxBufHead *PCSTxBufHead; + +typedef struct tagSBEACONCtl { + u32 BufReady:1; + u32 TSF:15; + u32 BufLen:11; + u32 Reserved:5; +} __attribute__ ((__packed__)) +SBEACONCtl; + +typedef struct tagSSecretKey { + u32 dwLowDword; + unsigned char byHighByte; +} __attribute__ ((__packed__)) +SSecretKey; + +typedef struct tagSKeyEntry { + unsigned char abyAddrHi[2]; + unsigned short wKCTL; + unsigned char abyAddrLo[4]; + u32 dwKey0[4]; + u32 dwKey1[4]; + u32 dwKey2[4]; + u32 dwKey3[4]; + u32 dwKey4[4]; +} __attribute__ ((__packed__)) +SKeyEntry; + +#endif /* __DESC_H__ */ diff --git a/kernel/drivers/staging/vt6655/device.h b/kernel/drivers/staging/vt6655/device.h new file mode 100644 index 000000000..440537e47 --- /dev/null +++ b/kernel/drivers/staging/vt6655/device.h @@ -0,0 +1,424 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: device.h + * + * Purpose: MAC Data structure + * + * Author: Tevin Chen + * + * Date: Mar 17, 1997 + * + */ + +#ifndef __DEVICE_H__ +#define __DEVICE_H__ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/mm.h> +#include <linux/errno.h> +#include <linux/ioport.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/netdevice.h> +#include <linux/etherdevice.h> +#include <linux/skbuff.h> +#include <linux/delay.h> +#include <linux/timer.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/string.h> +#include <linux/wait.h> +#include <linux/if_arp.h> +#include <linux/sched.h> +#include <linux/io.h> +#include <linux/if.h> +#include <linux/crc32.h> +#include <linux/uaccess.h> +#include <linux/proc_fs.h> +#include <linux/inetdevice.h> +#include <linux/reboot.h> +#include <linux/ethtool.h> +/* Include Wireless Extension definition and check version - Jean II */ +#include <net/mac80211.h> +#include <linux/wireless.h> +#include <net/iw_handler.h> /* New driver API */ + +#ifndef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT +#define WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT +#endif + +/* device specific */ + +#include "device_cfg.h" +#include "card.h" +#include "mib.h" +#include "srom.h" +#include "desc.h" +#include "key.h" +#include "mac.h" + +/*--------------------- Export Definitions -------------------------*/ + +#define RATE_1M 0 +#define RATE_2M 1 +#define RATE_5M 2 +#define RATE_11M 3 +#define RATE_6M 4 +#define RATE_9M 5 +#define RATE_12M 6 +#define RATE_18M 7 +#define RATE_24M 8 +#define RATE_36M 9 +#define RATE_48M 10 +#define RATE_54M 11 +#define RATE_AUTO 12 +#define MAX_RATE 12 + +#define MAC_MAX_CONTEXT_REG (256+128) + +#define MAX_MULTICAST_ADDRESS_NUM 32 +#define MULTICAST_ADDRESS_LIST_SIZE (MAX_MULTICAST_ADDRESS_NUM * ETH_ALEN) + +#define DUPLICATE_RX_CACHE_LENGTH 5 + +#define NUM_KEY_ENTRY 11 + +#define TX_WEP_NONE 0 +#define TX_WEP_OTF 1 +#define TX_WEP_SW 2 +#define TX_WEP_SWOTP 3 +#define TX_WEP_OTPSW 4 +#define TX_WEP_SW232 5 + +#define KEYSEL_WEP40 0 +#define KEYSEL_WEP104 1 +#define KEYSEL_TKIP 2 +#define KEYSEL_CCMP 3 + +#define AUTO_FB_NONE 0 +#define AUTO_FB_0 1 +#define AUTO_FB_1 2 + +#define FB_RATE0 0 +#define FB_RATE1 1 + +/* Antenna Mode */ +#define ANT_A 0 +#define ANT_B 1 +#define ANT_DIVERSITY 2 +#define ANT_RXD_TXA 3 +#define ANT_RXD_TXB 4 +#define ANT_UNKNOWN 0xFF + +#define MAXCHECKHANGCNT 4 + +#define BB_VGA_LEVEL 4 +#define BB_VGA_CHANGE_THRESHOLD 16 + +#ifndef RUN_AT +#define RUN_AT(x) (jiffies+(x)) +#endif + +#define MAKE_BEACON_RESERVED 10 /* (us) */ + +/* DMA related */ +#define RESERV_AC0DMA 4 + +/* BUILD OBJ mode */ + +#define AVAIL_TD(p, q) ((p)->sOpts.nTxDescs[(q)] - ((p)->iTDUsed[(q)])) + +#define NUM 64 + +/* 0:11A 1:11B 2:11G */ +#define BB_TYPE_11A 0 +#define BB_TYPE_11B 1 +#define BB_TYPE_11G 2 + +/* 0:11a, 1:11b, 2:11gb (only CCK in BasicRate), 3:11ga (OFDM in BasicRate) */ +#define PK_TYPE_11A 0 +#define PK_TYPE_11B 1 +#define PK_TYPE_11GB 2 +#define PK_TYPE_11GA 3 + +typedef struct __chip_info_tbl { + CHIP_TYPE chip_id; + char *name; + int io_size; + int nTxQueue; + u32 flags; +} CHIP_INFO, *PCHIP_INFO; + +typedef enum { + OWNED_BY_HOST = 0, + OWNED_BY_NIC = 1 +} DEVICE_OWNER_TYPE, *PDEVICE_OWNER_TYPE; + +/* flags for options */ +#define DEVICE_FLAGS_IP_ALIGN 0x00000001UL +#define DEVICE_FLAGS_PREAMBLE_TYPE 0x00000002UL +#define DEVICE_FLAGS_OP_MODE 0x00000004UL +#define DEVICE_FLAGS_PS_MODE 0x00000008UL +#define DEVICE_FLAGS_80211h_MODE 0x00000010UL +#define DEVICE_FLAGS_DiversityANT 0x00000020UL + +/* flags for driver status */ +#define DEVICE_FLAGS_OPENED 0x00010000UL +#define DEVICE_FLAGS_WOL_ENABLED 0x00080000UL +/* flags for capabilities */ +#define DEVICE_FLAGS_TX_ALIGN 0x01000000UL +#define DEVICE_FLAGS_HAVE_CAM 0x02000000UL +#define DEVICE_FLAGS_FLOW_CTRL 0x04000000UL + +/* flags for MII status */ +#define DEVICE_LINK_FAIL 0x00000001UL +#define DEVICE_SPEED_10 0x00000002UL +#define DEVICE_SPEED_100 0x00000004UL +#define DEVICE_SPEED_1000 0x00000008UL +#define DEVICE_DUPLEX_FULL 0x00000010UL +#define DEVICE_AUTONEG_ENABLE 0x00000020UL +#define DEVICE_FORCED_BY_EEPROM 0x00000040UL +/* for device_set_media_duplex */ +#define DEVICE_LINK_CHANGE 0x00000001UL + +typedef struct __device_opt { + int nRxDescs0; /* Number of RX descriptors0 */ + int nRxDescs1; /* Number of RX descriptors1 */ + int nTxDescs[2]; /* Number of TX descriptors 0, 1 */ + int int_works; /* interrupt limits */ + int short_retry; + int long_retry; + int bbp_type; + u32 flags; +} OPTIONS, *POPTIONS; + +struct vnt_private { + struct pci_dev *pcid; + /* mac80211 */ + struct ieee80211_hw *hw; + struct ieee80211_vif *vif; + unsigned long key_entry_inuse; + u32 basic_rates; + u16 current_aid; + int mc_list_count; + u8 mac_hw; + +/* dma addr, rx/tx pool */ + dma_addr_t pool_dma; + dma_addr_t rd0_pool_dma; + dma_addr_t rd1_pool_dma; + + dma_addr_t td0_pool_dma; + dma_addr_t td1_pool_dma; + + dma_addr_t tx_bufs_dma0; + dma_addr_t tx_bufs_dma1; + dma_addr_t tx_beacon_dma; + + unsigned char *tx0_bufs; + unsigned char *tx1_bufs; + unsigned char *tx_beacon_bufs; + + CHIP_TYPE chip_id; + + void __iomem *PortOffset; + unsigned long dwIsr; + u32 memaddr; + u32 ioaddr; + u32 io_size; + + unsigned char byRevId; + unsigned char byRxMode; + unsigned short SubSystemID; + unsigned short SubVendorID; + + spinlock_t lock; + + int nTxQueues; + volatile int iTDUsed[TYPE_MAXTD]; + + volatile PSTxDesc apCurrTD[TYPE_MAXTD]; + volatile PSTxDesc apTailTD[TYPE_MAXTD]; + + volatile PSTxDesc apTD0Rings; + volatile PSTxDesc apTD1Rings; + + volatile PSRxDesc aRD0Ring; + volatile PSRxDesc aRD1Ring; + volatile PSRxDesc pCurrRD[TYPE_MAXRD]; + + OPTIONS sOpts; + + u32 flags; + + u32 rx_buf_sz; + u8 rx_rate; + int multicast_limit; + + u32 rx_bytes; + + /* Version control */ + unsigned char byLocalID; + unsigned char byRFType; + + unsigned char byMaxPwrLevel; + unsigned char byZoneType; + bool bZoneRegExist; + unsigned char byOriginalZonetype; + + unsigned char abyCurrentNetAddr[ETH_ALEN]; __aligned(2) + bool bLinkPass; /* link status: OK or fail */ + + /* Adapter statistics */ + SStatCounter scStatistic; + /* 802.11 counter */ + SDot11Counters s802_11Counter; + + unsigned int uCurrRSSI; + unsigned char byCurrSQ; + + unsigned long dwTxAntennaSel; + unsigned long dwRxAntennaSel; + unsigned char byAntennaCount; + unsigned char byRxAntennaMode; + unsigned char byTxAntennaMode; + bool bTxRxAntInv; + + unsigned char *pbyTmpBuff; + unsigned int uSIFS; /* Current SIFS */ + unsigned int uDIFS; /* Current DIFS */ + unsigned int uEIFS; /* Current EIFS */ + unsigned int uSlot; /* Current SlotTime */ + unsigned int uCwMin; /* Current CwMin */ + unsigned int uCwMax; /* CwMax is fixed on 1023. */ + /* PHY parameter */ + unsigned char bySIFS; + unsigned char byDIFS; + unsigned char byEIFS; + unsigned char bySlot; + unsigned char byCWMaxMin; + + u8 byBBType; /* 0:11A, 1:11B, 2:11G */ + u8 byPacketType; /* + * 0:11a,1:11b,2:11gb (only CCK + * in BasicRate), 3:11ga (OFDM in + * Basic Rate) + */ + unsigned short wBasicRate; + unsigned char byACKRate; + unsigned char byTopOFDMBasicRate; + unsigned char byTopCCKBasicRate; + + unsigned char byMinChannel; + unsigned char byMaxChannel; + + unsigned char byPreambleType; + unsigned char byShortPreamble; + + unsigned short wCurrentRate; + unsigned char byShortRetryLimit; + unsigned char byLongRetryLimit; + enum nl80211_iftype op_mode; + bool bBSSIDFilter; + unsigned short wMaxTransmitMSDULifetime; + + bool bEncryptionEnable; + bool bLongHeader; + bool bShortSlotTime; + bool bProtectMode; + bool bNonERPPresent; + bool bBarkerPreambleMd; + + bool bRadioControlOff; + bool bRadioOff; + bool bEnablePSMode; + unsigned short wListenInterval; + bool bPWBitOn; + + /* GPIO Radio Control */ + unsigned char byRadioCtl; + unsigned char byGPIO; + bool bHWRadioOff; + bool bPrvActive4RadioOFF; + bool bGPIOBlockRead; + + /* Beacon related */ + unsigned short wSeqCounter; + unsigned short wBCNBufLen; + bool bBeaconBufReady; + bool bBeaconSent; + bool bIsBeaconBufReadySet; + unsigned int cbBeaconBufReadySetCnt; + bool bFixRate; + u16 byCurrentCh; + + bool bAES; + + unsigned char byAutoFBCtrl; + + /* For Update BaseBand VGA Gain Offset */ + bool bUpdateBBVGA; + unsigned int uBBVGADiffCount; + unsigned char byBBVGANew; + unsigned char byBBVGACurrent; + unsigned char abyBBVGA[BB_VGA_LEVEL]; + long ldBmThreshold[BB_VGA_LEVEL]; + + unsigned char byBBPreEDRSSI; + unsigned char byBBPreEDIndex; + + unsigned long dwDiagRefCount; + + /* For FOE Tuning */ + unsigned char byFOETuning; + + /* For RF Power table */ + unsigned char byCCKPwr; + unsigned char byOFDMPwrG; + unsigned char byCurPwr; + char byCurPwrdBm; + unsigned char abyCCKPwrTbl[CB_MAX_CHANNEL_24G+1]; + unsigned char abyOFDMPwrTbl[CB_MAX_CHANNEL+1]; + char abyCCKDefaultPwr[CB_MAX_CHANNEL_24G+1]; + char abyOFDMDefaultPwr[CB_MAX_CHANNEL+1]; + char abyRegPwr[CB_MAX_CHANNEL+1]; + char abyLocalPwr[CB_MAX_CHANNEL+1]; + + /* BaseBand Loopback Use */ + unsigned char byBBCR4d; + unsigned char byBBCRc9; + unsigned char byBBCR88; + unsigned char byBBCR09; + + unsigned char abyEEPROM[EEP_MAX_CONTEXT_SIZE]; /* unsigned long alignment */ + + unsigned short wBeaconInterval; +}; + +static inline PDEVICE_RD_INFO alloc_rd_info(void) +{ + return kzalloc(sizeof(DEVICE_RD_INFO), GFP_ATOMIC); +} + +static inline PDEVICE_TD_INFO alloc_td_info(void) +{ + return kzalloc(sizeof(DEVICE_TD_INFO), GFP_ATOMIC); +} +#endif diff --git a/kernel/drivers/staging/vt6655/device_cfg.h b/kernel/drivers/staging/vt6655/device_cfg.h new file mode 100644 index 000000000..a4a8a8489 --- /dev/null +++ b/kernel/drivers/staging/vt6655/device_cfg.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: device_cfg.h + * + * Purpose: Driver configuration header + * Author: Lyndon Chen + * + * Date: Dec 17, 2002 + * + */ +#ifndef __DEVICE_CONFIG_H +#define __DEVICE_CONFIG_H + +#include <linux/types.h> + +typedef +struct _version { + unsigned char major; + unsigned char minor; + unsigned char build; +} version_t, *pversion_t; + +#define VID_TABLE_SIZE 64 +#define MCAST_TABLE_SIZE 64 +#define MCAM_SIZE 32 +#define VCAM_SIZE 32 +#define TX_QUEUE_NO 8 + +#define DEVICE_NAME "vt6655" +#define DEVICE_FULL_DRV_NAM "VIA Networking Solomon-A/B/G Wireless LAN Adapter Driver" + +#ifndef MAJOR_VERSION +#define MAJOR_VERSION 1 +#endif + +#ifndef MINOR_VERSION +#define MINOR_VERSION 17 +#endif + +#ifndef DEVICE_VERSION +#define DEVICE_VERSION "1.19.12" +#endif + +#include <linux/fs.h> +#include <linux/fcntl.h> +#ifndef CONFIG_PATH +#define CONFIG_PATH "/etc/vntconfiguration.dat" +#endif + +#define PKT_BUF_SZ 2390 + +typedef enum _chip_type { + VT3253 = 1 +} CHIP_TYPE, *PCHIP_TYPE; + +#ifdef VIAWET_DEBUG +#define ASSERT(x) \ +do { \ + if (!(x)) { \ + pr_err("assertion %s failed: file %s line %d\n", \ + #x, __func__, __LINE__); \ + *(int *)0 = 0; \ + } \ +} while (0) +#define DBG_PORT80(value) outb(value, 0x80) +#else +#define ASSERT(x) +#define DBG_PORT80(value) +#endif + +#endif diff --git a/kernel/drivers/staging/vt6655/device_main.c b/kernel/drivers/staging/vt6655/device_main.c new file mode 100644 index 000000000..0343ae386 --- /dev/null +++ b/kernel/drivers/staging/vt6655/device_main.c @@ -0,0 +1,1910 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: device_main.c + * + * Purpose: driver entry for initial, open, close, tx and rx. + * + * Author: Lyndon Chen + * + * Date: Jan 8, 2003 + * + * Functions: + * + * vt6655_probe - module initial (insmod) driver entry + * vt6655_remove - module remove entry + * vt6655_init_info - device structure resource allocation function + * device_free_info - device structure resource free function + * device_get_pci_info - get allocated pci io/mem resource + * device_print_info - print out resource + * device_intr - interrupt handle function + * device_rx_srv - rx service function + * device_alloc_rx_buf - rx buffer pre-allocated function + * device_free_tx_buf - free tx buffer function + * device_init_rd0_ring- initial rd dma0 ring + * device_init_rd1_ring- initial rd dma1 ring + * device_init_td0_ring- initial tx dma0 ring buffer + * device_init_td1_ring- initial tx dma1 ring buffer + * device_init_registers- initial MAC & BBP & RF internal registers. + * device_init_rings- initial tx/rx ring buffer + * device_free_rings- free all allocated ring buffer + * device_tx_srv- tx interrupt service function + * + * Revision History: + */ +#undef __NO_VERSION__ + +#include <linux/file.h> +#include "device.h" +#include "card.h" +#include "channel.h" +#include "baseband.h" +#include "mac.h" +#include "power.h" +#include "rxtx.h" +#include "dpc.h" +#include "rf.h" +#include <linux/delay.h> +#include <linux/kthread.h> +#include <linux/slab.h> + +/*--------------------- Static Definitions -------------------------*/ +/* + * Define module options + */ +MODULE_AUTHOR("VIA Networking Technologies, Inc., <lyndonchen@vntek.com.tw>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("VIA Networking Solomon-A/B/G Wireless LAN Adapter Driver"); + +#define DEVICE_PARAM(N, D) + +#define RX_DESC_MIN0 16 +#define RX_DESC_MAX0 128 +#define RX_DESC_DEF0 32 +DEVICE_PARAM(RxDescriptors0, "Number of receive descriptors0"); + +#define RX_DESC_MIN1 16 +#define RX_DESC_MAX1 128 +#define RX_DESC_DEF1 32 +DEVICE_PARAM(RxDescriptors1, "Number of receive descriptors1"); + +#define TX_DESC_MIN0 16 +#define TX_DESC_MAX0 128 +#define TX_DESC_DEF0 32 +DEVICE_PARAM(TxDescriptors0, "Number of transmit descriptors0"); + +#define TX_DESC_MIN1 16 +#define TX_DESC_MAX1 128 +#define TX_DESC_DEF1 64 +DEVICE_PARAM(TxDescriptors1, "Number of transmit descriptors1"); + +#define INT_WORKS_DEF 20 +#define INT_WORKS_MIN 10 +#define INT_WORKS_MAX 64 + +DEVICE_PARAM(int_works, "Number of packets per interrupt services"); + +#define RTS_THRESH_DEF 2347 + +#define FRAG_THRESH_DEF 2346 + +#define SHORT_RETRY_MIN 0 +#define SHORT_RETRY_MAX 31 +#define SHORT_RETRY_DEF 8 + +DEVICE_PARAM(ShortRetryLimit, "Short frame retry limits"); + +#define LONG_RETRY_MIN 0 +#define LONG_RETRY_MAX 15 +#define LONG_RETRY_DEF 4 + +DEVICE_PARAM(LongRetryLimit, "long frame retry limits"); + +/* BasebandType[] baseband type selected + 0: indicate 802.11a type + 1: indicate 802.11b type + 2: indicate 802.11g type +*/ +#define BBP_TYPE_MIN 0 +#define BBP_TYPE_MAX 2 +#define BBP_TYPE_DEF 2 + +DEVICE_PARAM(BasebandType, "baseband type"); + +/* + * Static vars definitions + */ +static CHIP_INFO chip_info_table[] = { + { VT3253, "VIA Networking Solomon-A/B/G Wireless LAN Adapter ", + 256, 1, DEVICE_FLAGS_IP_ALIGN|DEVICE_FLAGS_TX_ALIGN }, + {0, NULL} +}; + +static const struct pci_device_id vt6655_pci_id_table[] = { + { PCI_VDEVICE(VIA, 0x3253), (kernel_ulong_t)chip_info_table}, + { 0, } +}; + +/*--------------------- Static Functions --------------------------*/ + +static int vt6655_probe(struct pci_dev *pcid, const struct pci_device_id *ent); +static void vt6655_init_info(struct pci_dev *pcid, + struct vnt_private **ppDevice, PCHIP_INFO); +static void device_free_info(struct vnt_private *pDevice); +static bool device_get_pci_info(struct vnt_private *, struct pci_dev *pcid); +static void device_print_info(struct vnt_private *pDevice); +static irqreturn_t device_intr(int irq, void *dev_instance); + +#ifdef CONFIG_PM +static int device_notify_reboot(struct notifier_block *, unsigned long event, void *ptr); +static struct notifier_block device_notifier = { + .notifier_call = device_notify_reboot, + .next = NULL, + .priority = 0, +}; +#endif + +static void device_init_rd0_ring(struct vnt_private *pDevice); +static void device_init_rd1_ring(struct vnt_private *pDevice); +static void device_init_td0_ring(struct vnt_private *pDevice); +static void device_init_td1_ring(struct vnt_private *pDevice); + +static int device_rx_srv(struct vnt_private *pDevice, unsigned int uIdx); +static int device_tx_srv(struct vnt_private *pDevice, unsigned int uIdx); +static bool device_alloc_rx_buf(struct vnt_private *pDevice, PSRxDesc pDesc); +static void device_init_registers(struct vnt_private *pDevice); +static void device_free_tx_buf(struct vnt_private *pDevice, PSTxDesc pDesc); +static void device_free_td0_ring(struct vnt_private *pDevice); +static void device_free_td1_ring(struct vnt_private *pDevice); +static void device_free_rd0_ring(struct vnt_private *pDevice); +static void device_free_rd1_ring(struct vnt_private *pDevice); +static void device_free_rings(struct vnt_private *pDevice); + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +static char *get_chip_name(int chip_id) +{ + int i; + + for (i = 0; chip_info_table[i].name != NULL; i++) + if (chip_info_table[i].chip_id == chip_id) + break; + return chip_info_table[i].name; +} + +static void vt6655_remove(struct pci_dev *pcid) +{ + struct vnt_private *pDevice = pci_get_drvdata(pcid); + + if (pDevice == NULL) + return; + device_free_info(pDevice); +} + +static void device_get_options(struct vnt_private *pDevice) +{ + POPTIONS pOpts = &(pDevice->sOpts); + + pOpts->nRxDescs0 = RX_DESC_DEF0; + pOpts->nRxDescs1 = RX_DESC_DEF1; + pOpts->nTxDescs[0] = TX_DESC_DEF0; + pOpts->nTxDescs[1] = TX_DESC_DEF1; + pOpts->int_works = INT_WORKS_DEF; + + pOpts->short_retry = SHORT_RETRY_DEF; + pOpts->long_retry = LONG_RETRY_DEF; + pOpts->bbp_type = BBP_TYPE_DEF; +} + +static void +device_set_options(struct vnt_private *pDevice) +{ + pDevice->byShortRetryLimit = pDevice->sOpts.short_retry; + pDevice->byLongRetryLimit = pDevice->sOpts.long_retry; + pDevice->byBBType = pDevice->sOpts.bbp_type; + pDevice->byPacketType = pDevice->byBBType; + pDevice->byAutoFBCtrl = AUTO_FB_0; + pDevice->bUpdateBBVGA = true; + pDevice->byPreambleType = 0; + + pr_debug(" byShortRetryLimit= %d\n", (int)pDevice->byShortRetryLimit); + pr_debug(" byLongRetryLimit= %d\n", (int)pDevice->byLongRetryLimit); + pr_debug(" byPreambleType= %d\n", (int)pDevice->byPreambleType); + pr_debug(" byShortPreamble= %d\n", (int)pDevice->byShortPreamble); + pr_debug(" byBBType= %d\n", (int)pDevice->byBBType); +} + +/* + * Initialisation of MAC & BBP registers + */ + +static void device_init_registers(struct vnt_private *pDevice) +{ + unsigned long flags; + unsigned int ii; + unsigned char byValue; + unsigned char byCCKPwrdBm = 0; + unsigned char byOFDMPwrdBm = 0; + + MACbShutdown(pDevice->PortOffset); + BBvSoftwareReset(pDevice); + + /* Do MACbSoftwareReset in MACvInitialize */ + MACbSoftwareReset(pDevice->PortOffset); + + pDevice->bAES = false; + + /* Only used in 11g type, sync with ERP IE */ + pDevice->bProtectMode = false; + + pDevice->bNonERPPresent = false; + pDevice->bBarkerPreambleMd = false; + pDevice->wCurrentRate = RATE_1M; + pDevice->byTopOFDMBasicRate = RATE_24M; + pDevice->byTopCCKBasicRate = RATE_1M; + + /* Target to IF pin while programming to RF chip. */ + pDevice->byRevId = 0; + + /* init MAC */ + MACvInitialize(pDevice->PortOffset); + + /* Get Local ID */ + VNSvInPortB(pDevice->PortOffset + MAC_REG_LOCALID, &pDevice->byLocalID); + + spin_lock_irqsave(&pDevice->lock, flags); + + SROMvReadAllContents(pDevice->PortOffset, pDevice->abyEEPROM); + + spin_unlock_irqrestore(&pDevice->lock, flags); + + /* Get Channel range */ + pDevice->byMinChannel = 1; + pDevice->byMaxChannel = CB_MAX_CHANNEL; + + /* Get Antena */ + byValue = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_ANTENNA); + if (byValue & EEP_ANTINV) + pDevice->bTxRxAntInv = true; + else + pDevice->bTxRxAntInv = false; + + byValue &= (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN); + /* if not set default is All */ + if (byValue == 0) + byValue = (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN); + + if (byValue == (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN)) { + pDevice->byAntennaCount = 2; + pDevice->byTxAntennaMode = ANT_B; + pDevice->dwTxAntennaSel = 1; + pDevice->dwRxAntennaSel = 1; + + if (pDevice->bTxRxAntInv) + pDevice->byRxAntennaMode = ANT_A; + else + pDevice->byRxAntennaMode = ANT_B; + } else { + pDevice->byAntennaCount = 1; + pDevice->dwTxAntennaSel = 0; + pDevice->dwRxAntennaSel = 0; + + if (byValue & EEP_ANTENNA_AUX) { + pDevice->byTxAntennaMode = ANT_A; + + if (pDevice->bTxRxAntInv) + pDevice->byRxAntennaMode = ANT_B; + else + pDevice->byRxAntennaMode = ANT_A; + } else { + pDevice->byTxAntennaMode = ANT_B; + + if (pDevice->bTxRxAntInv) + pDevice->byRxAntennaMode = ANT_A; + else + pDevice->byRxAntennaMode = ANT_B; + } + } + + /* Set initial antenna mode */ + BBvSetTxAntennaMode(pDevice, pDevice->byTxAntennaMode); + BBvSetRxAntennaMode(pDevice, pDevice->byRxAntennaMode); + + /* zonetype initial */ + pDevice->byOriginalZonetype = pDevice->abyEEPROM[EEP_OFS_ZONETYPE]; + + if (!pDevice->bZoneRegExist) + pDevice->byZoneType = pDevice->abyEEPROM[EEP_OFS_ZONETYPE]; + + pr_debug("pDevice->byZoneType = %x\n", pDevice->byZoneType); + + /* Init RF module */ + RFbInit(pDevice); + + /* Get Desire Power Value */ + pDevice->byCurPwr = 0xFF; + pDevice->byCCKPwr = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_PWR_CCK); + pDevice->byOFDMPwrG = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_PWR_OFDMG); + + /* Load power Table */ + for (ii = 0; ii < CB_MAX_CHANNEL_24G; ii++) { + pDevice->abyCCKPwrTbl[ii + 1] = + SROMbyReadEmbedded(pDevice->PortOffset, + (unsigned char)(ii + EEP_OFS_CCK_PWR_TBL)); + if (pDevice->abyCCKPwrTbl[ii + 1] == 0) + pDevice->abyCCKPwrTbl[ii+1] = pDevice->byCCKPwr; + + pDevice->abyOFDMPwrTbl[ii + 1] = + SROMbyReadEmbedded(pDevice->PortOffset, + (unsigned char)(ii + EEP_OFS_OFDM_PWR_TBL)); + if (pDevice->abyOFDMPwrTbl[ii + 1] == 0) + pDevice->abyOFDMPwrTbl[ii + 1] = pDevice->byOFDMPwrG; + + pDevice->abyCCKDefaultPwr[ii + 1] = byCCKPwrdBm; + pDevice->abyOFDMDefaultPwr[ii + 1] = byOFDMPwrdBm; + } + + /* recover 12,13 ,14channel for EUROPE by 11 channel */ + for (ii = 11; ii < 14; ii++) { + pDevice->abyCCKPwrTbl[ii] = pDevice->abyCCKPwrTbl[10]; + pDevice->abyOFDMPwrTbl[ii] = pDevice->abyOFDMPwrTbl[10]; + } + + /* Load OFDM A Power Table */ + for (ii = 0; ii < CB_MAX_CHANNEL_5G; ii++) { + pDevice->abyOFDMPwrTbl[ii + CB_MAX_CHANNEL_24G + 1] = + SROMbyReadEmbedded(pDevice->PortOffset, + (unsigned char)(ii + EEP_OFS_OFDMA_PWR_TBL)); + + pDevice->abyOFDMDefaultPwr[ii + CB_MAX_CHANNEL_24G + 1] = + SROMbyReadEmbedded(pDevice->PortOffset, + (unsigned char)(ii + EEP_OFS_OFDMA_PWR_dBm)); + } + + if (pDevice->byLocalID > REV_ID_VT3253_B1) { + MACvSelectPage1(pDevice->PortOffset); + + VNSvOutPortB(pDevice->PortOffset + MAC_REG_MSRCTL + 1, + (MSRCTL1_TXPWR | MSRCTL1_CSAPAREN)); + + MACvSelectPage0(pDevice->PortOffset); + } + + /* use relative tx timeout and 802.11i D4 */ + MACvWordRegBitsOn(pDevice->PortOffset, + MAC_REG_CFG, (CFG_TKIPOPT | CFG_NOTXTIMEOUT)); + + /* set performance parameter by registry */ + MACvSetShortRetryLimit(pDevice->PortOffset, pDevice->byShortRetryLimit); + MACvSetLongRetryLimit(pDevice->PortOffset, pDevice->byLongRetryLimit); + + /* reset TSF counter */ + VNSvOutPortB(pDevice->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST); + /* enable TSF counter */ + VNSvOutPortB(pDevice->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); + + /* initialize BBP registers */ + BBbVT3253Init(pDevice); + + if (pDevice->bUpdateBBVGA) { + pDevice->byBBVGACurrent = pDevice->abyBBVGA[0]; + pDevice->byBBVGANew = pDevice->byBBVGACurrent; + BBvSetVGAGainOffset(pDevice, pDevice->abyBBVGA[0]); + } + + BBvSetRxAntennaMode(pDevice, pDevice->byRxAntennaMode); + BBvSetTxAntennaMode(pDevice, pDevice->byTxAntennaMode); + + /* Set BB and packet type at the same time. */ + /* Set Short Slot Time, xIFS, and RSPINF. */ + pDevice->wCurrentRate = RATE_54M; + + pDevice->bRadioOff = false; + + pDevice->byRadioCtl = SROMbyReadEmbedded(pDevice->PortOffset, + EEP_OFS_RADIOCTL); + pDevice->bHWRadioOff = false; + + if (pDevice->byRadioCtl & EEP_RADIOCTL_ENABLE) { + /* Get GPIO */ + MACvGPIOIn(pDevice->PortOffset, &pDevice->byGPIO); + + if (((pDevice->byGPIO & GPIO0_DATA) && + !(pDevice->byRadioCtl & EEP_RADIOCTL_INV)) || + (!(pDevice->byGPIO & GPIO0_DATA) && + (pDevice->byRadioCtl & EEP_RADIOCTL_INV))) + pDevice->bHWRadioOff = true; + } + + if (pDevice->bHWRadioOff || pDevice->bRadioControlOff) + CARDbRadioPowerOff(pDevice); + + /* get Permanent network address */ + SROMvReadEtherAddress(pDevice->PortOffset, pDevice->abyCurrentNetAddr); + pr_debug("Network address = %pM\n", pDevice->abyCurrentNetAddr); + + /* reset Tx pointer */ + CARDvSafeResetRx(pDevice); + /* reset Rx pointer */ + CARDvSafeResetTx(pDevice); + + if (pDevice->byLocalID <= REV_ID_VT3253_A1) + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_RCR, RCR_WPAERR); + + /* Turn On Rx DMA */ + MACvReceive0(pDevice->PortOffset); + MACvReceive1(pDevice->PortOffset); + + /* start the adapter */ + MACvStart(pDevice->PortOffset); +} + +static void device_print_info(struct vnt_private *pDevice) +{ + dev_info(&pDevice->pcid->dev, "%s\n", get_chip_name(pDevice->chip_id)); + + dev_info(&pDevice->pcid->dev, "MAC=%pM IO=0x%lx Mem=0x%lx IRQ=%d\n", + pDevice->abyCurrentNetAddr, (unsigned long)pDevice->ioaddr, + (unsigned long)pDevice->PortOffset, pDevice->pcid->irq); +} + +static void vt6655_init_info(struct pci_dev *pcid, + struct vnt_private **ppDevice, + PCHIP_INFO pChip_info) +{ + memset(*ppDevice, 0, sizeof(**ppDevice)); + + (*ppDevice)->pcid = pcid; + (*ppDevice)->chip_id = pChip_info->chip_id; + (*ppDevice)->io_size = pChip_info->io_size; + (*ppDevice)->nTxQueues = pChip_info->nTxQueue; + (*ppDevice)->multicast_limit = 32; + + spin_lock_init(&((*ppDevice)->lock)); +} + +static bool device_get_pci_info(struct vnt_private *pDevice, + struct pci_dev *pcid) +{ + u16 pci_cmd; + u8 b; + unsigned int cis_addr; + + pci_read_config_byte(pcid, PCI_REVISION_ID, &pDevice->byRevId); + pci_read_config_word(pcid, PCI_SUBSYSTEM_ID, &pDevice->SubSystemID); + pci_read_config_word(pcid, PCI_SUBSYSTEM_VENDOR_ID, &pDevice->SubVendorID); + pci_read_config_word(pcid, PCI_COMMAND, (u16 *)&(pci_cmd)); + + pci_set_master(pcid); + + pDevice->memaddr = pci_resource_start(pcid, 0); + pDevice->ioaddr = pci_resource_start(pcid, 1); + + cis_addr = pci_resource_start(pcid, 2); + + pDevice->pcid = pcid; + + pci_read_config_byte(pcid, PCI_COMMAND, &b); + pci_write_config_byte(pcid, PCI_COMMAND, (b|PCI_COMMAND_MASTER)); + + return true; +} + +static void device_free_info(struct vnt_private *pDevice) +{ + if (!pDevice) + return; + + if (pDevice->mac_hw) + ieee80211_unregister_hw(pDevice->hw); + + if (pDevice->PortOffset) + iounmap(pDevice->PortOffset); + + if (pDevice->pcid) + pci_release_regions(pDevice->pcid); + + if (pDevice->hw) + ieee80211_free_hw(pDevice->hw); +} + +static bool device_init_rings(struct vnt_private *pDevice) +{ + void *vir_pool; + + /*allocate all RD/TD rings a single pool*/ + vir_pool = dma_zalloc_coherent(&pDevice->pcid->dev, + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc) + + pDevice->sOpts.nRxDescs1 * sizeof(SRxDesc) + + pDevice->sOpts.nTxDescs[0] * sizeof(STxDesc) + + pDevice->sOpts.nTxDescs[1] * sizeof(STxDesc), + &pDevice->pool_dma, GFP_ATOMIC); + if (vir_pool == NULL) { + dev_err(&pDevice->pcid->dev, "allocate desc dma memory failed\n"); + return false; + } + + pDevice->aRD0Ring = vir_pool; + pDevice->aRD1Ring = vir_pool + + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc); + + pDevice->rd0_pool_dma = pDevice->pool_dma; + pDevice->rd1_pool_dma = pDevice->rd0_pool_dma + + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc); + + pDevice->tx0_bufs = dma_zalloc_coherent(&pDevice->pcid->dev, + pDevice->sOpts.nTxDescs[0] * PKT_BUF_SZ + + pDevice->sOpts.nTxDescs[1] * PKT_BUF_SZ + + CB_BEACON_BUF_SIZE + + CB_MAX_BUF_SIZE, + &pDevice->tx_bufs_dma0, + GFP_ATOMIC); + if (pDevice->tx0_bufs == NULL) { + dev_err(&pDevice->pcid->dev, "allocate buf dma memory failed\n"); + + dma_free_coherent(&pDevice->pcid->dev, + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc) + + pDevice->sOpts.nRxDescs1 * sizeof(SRxDesc) + + pDevice->sOpts.nTxDescs[0] * sizeof(STxDesc) + + pDevice->sOpts.nTxDescs[1] * sizeof(STxDesc), + vir_pool, pDevice->pool_dma + ); + return false; + } + + pDevice->td0_pool_dma = pDevice->rd1_pool_dma + + pDevice->sOpts.nRxDescs1 * sizeof(SRxDesc); + + pDevice->td1_pool_dma = pDevice->td0_pool_dma + + pDevice->sOpts.nTxDescs[0] * sizeof(STxDesc); + + /* vir_pool: pvoid type */ + pDevice->apTD0Rings = vir_pool + + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc) + + pDevice->sOpts.nRxDescs1 * sizeof(SRxDesc); + + pDevice->apTD1Rings = vir_pool + + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc) + + pDevice->sOpts.nRxDescs1 * sizeof(SRxDesc) + + pDevice->sOpts.nTxDescs[0] * sizeof(STxDesc); + + pDevice->tx1_bufs = pDevice->tx0_bufs + + pDevice->sOpts.nTxDescs[0] * PKT_BUF_SZ; + + pDevice->tx_beacon_bufs = pDevice->tx1_bufs + + pDevice->sOpts.nTxDescs[1] * PKT_BUF_SZ; + + pDevice->pbyTmpBuff = pDevice->tx_beacon_bufs + + CB_BEACON_BUF_SIZE; + + pDevice->tx_bufs_dma1 = pDevice->tx_bufs_dma0 + + pDevice->sOpts.nTxDescs[0] * PKT_BUF_SZ; + + pDevice->tx_beacon_dma = pDevice->tx_bufs_dma1 + + pDevice->sOpts.nTxDescs[1] * PKT_BUF_SZ; + + return true; +} + +static void device_free_rings(struct vnt_private *pDevice) +{ + dma_free_coherent(&pDevice->pcid->dev, + pDevice->sOpts.nRxDescs0 * sizeof(SRxDesc) + + pDevice->sOpts.nRxDescs1 * sizeof(SRxDesc) + + pDevice->sOpts.nTxDescs[0] * sizeof(STxDesc) + + pDevice->sOpts.nTxDescs[1] * sizeof(STxDesc) + , + pDevice->aRD0Ring, pDevice->pool_dma + ); + + if (pDevice->tx0_bufs) + dma_free_coherent(&pDevice->pcid->dev, + pDevice->sOpts.nTxDescs[0] * PKT_BUF_SZ + + pDevice->sOpts.nTxDescs[1] * PKT_BUF_SZ + + CB_BEACON_BUF_SIZE + + CB_MAX_BUF_SIZE, + pDevice->tx0_bufs, pDevice->tx_bufs_dma0 + ); +} + +static void device_init_rd0_ring(struct vnt_private *pDevice) +{ + int i; + dma_addr_t curr = pDevice->rd0_pool_dma; + PSRxDesc pDesc; + + /* Init the RD0 ring entries */ + for (i = 0; i < pDevice->sOpts.nRxDescs0; i ++, curr += sizeof(SRxDesc)) { + pDesc = &(pDevice->aRD0Ring[i]); + pDesc->pRDInfo = alloc_rd_info(); + ASSERT(pDesc->pRDInfo); + if (!device_alloc_rx_buf(pDevice, pDesc)) + dev_err(&pDevice->pcid->dev, "can not alloc rx bufs\n"); + + pDesc->next = &(pDevice->aRD0Ring[(i+1) % pDevice->sOpts.nRxDescs0]); + pDesc->pRDInfo->curr_desc = cpu_to_le32(curr); + pDesc->next_desc = cpu_to_le32(curr + sizeof(SRxDesc)); + } + + if (i > 0) + pDevice->aRD0Ring[i-1].next_desc = cpu_to_le32(pDevice->rd0_pool_dma); + pDevice->pCurrRD[0] = &(pDevice->aRD0Ring[0]); +} + +static void device_init_rd1_ring(struct vnt_private *pDevice) +{ + int i; + dma_addr_t curr = pDevice->rd1_pool_dma; + PSRxDesc pDesc; + + /* Init the RD1 ring entries */ + for (i = 0; i < pDevice->sOpts.nRxDescs1; i ++, curr += sizeof(SRxDesc)) { + pDesc = &(pDevice->aRD1Ring[i]); + pDesc->pRDInfo = alloc_rd_info(); + ASSERT(pDesc->pRDInfo); + if (!device_alloc_rx_buf(pDevice, pDesc)) + dev_err(&pDevice->pcid->dev, "can not alloc rx bufs\n"); + + pDesc->next = &(pDevice->aRD1Ring[(i+1) % pDevice->sOpts.nRxDescs1]); + pDesc->pRDInfo->curr_desc = cpu_to_le32(curr); + pDesc->next_desc = cpu_to_le32(curr + sizeof(SRxDesc)); + } + + if (i > 0) + pDevice->aRD1Ring[i-1].next_desc = cpu_to_le32(pDevice->rd1_pool_dma); + pDevice->pCurrRD[1] = &(pDevice->aRD1Ring[0]); +} + +static void device_free_rd0_ring(struct vnt_private *pDevice) +{ + int i; + + for (i = 0; i < pDevice->sOpts.nRxDescs0; i++) { + PSRxDesc pDesc = &(pDevice->aRD0Ring[i]); + PDEVICE_RD_INFO pRDInfo = pDesc->pRDInfo; + + dma_unmap_single(&pDevice->pcid->dev, pRDInfo->skb_dma, + pDevice->rx_buf_sz, DMA_FROM_DEVICE); + + dev_kfree_skb(pRDInfo->skb); + + kfree(pDesc->pRDInfo); + } +} + +static void device_free_rd1_ring(struct vnt_private *pDevice) +{ + int i; + + for (i = 0; i < pDevice->sOpts.nRxDescs1; i++) { + PSRxDesc pDesc = &(pDevice->aRD1Ring[i]); + PDEVICE_RD_INFO pRDInfo = pDesc->pRDInfo; + + dma_unmap_single(&pDevice->pcid->dev, pRDInfo->skb_dma, + pDevice->rx_buf_sz, DMA_FROM_DEVICE); + + dev_kfree_skb(pRDInfo->skb); + + kfree(pDesc->pRDInfo); + } +} + +static void device_init_td0_ring(struct vnt_private *pDevice) +{ + int i; + dma_addr_t curr; + PSTxDesc pDesc; + + curr = pDevice->td0_pool_dma; + for (i = 0; i < pDevice->sOpts.nTxDescs[0]; i++, curr += sizeof(STxDesc)) { + pDesc = &(pDevice->apTD0Rings[i]); + pDesc->pTDInfo = alloc_td_info(); + ASSERT(pDesc->pTDInfo); + if (pDevice->flags & DEVICE_FLAGS_TX_ALIGN) { + pDesc->pTDInfo->buf = pDevice->tx0_bufs + (i)*PKT_BUF_SZ; + pDesc->pTDInfo->buf_dma = pDevice->tx_bufs_dma0 + (i)*PKT_BUF_SZ; + } + pDesc->next = &(pDevice->apTD0Rings[(i+1) % pDevice->sOpts.nTxDescs[0]]); + pDesc->pTDInfo->curr_desc = cpu_to_le32(curr); + pDesc->next_desc = cpu_to_le32(curr+sizeof(STxDesc)); + } + + if (i > 0) + pDevice->apTD0Rings[i-1].next_desc = cpu_to_le32(pDevice->td0_pool_dma); + pDevice->apTailTD[0] = pDevice->apCurrTD[0] = &(pDevice->apTD0Rings[0]); +} + +static void device_init_td1_ring(struct vnt_private *pDevice) +{ + int i; + dma_addr_t curr; + PSTxDesc pDesc; + + /* Init the TD ring entries */ + curr = pDevice->td1_pool_dma; + for (i = 0; i < pDevice->sOpts.nTxDescs[1]; i++, curr += sizeof(STxDesc)) { + pDesc = &(pDevice->apTD1Rings[i]); + pDesc->pTDInfo = alloc_td_info(); + ASSERT(pDesc->pTDInfo); + if (pDevice->flags & DEVICE_FLAGS_TX_ALIGN) { + pDesc->pTDInfo->buf = pDevice->tx1_bufs + (i) * PKT_BUF_SZ; + pDesc->pTDInfo->buf_dma = pDevice->tx_bufs_dma1 + (i) * PKT_BUF_SZ; + } + pDesc->next = &(pDevice->apTD1Rings[(i + 1) % pDevice->sOpts.nTxDescs[1]]); + pDesc->pTDInfo->curr_desc = cpu_to_le32(curr); + pDesc->next_desc = cpu_to_le32(curr+sizeof(STxDesc)); + } + + if (i > 0) + pDevice->apTD1Rings[i-1].next_desc = cpu_to_le32(pDevice->td1_pool_dma); + pDevice->apTailTD[1] = pDevice->apCurrTD[1] = &(pDevice->apTD1Rings[0]); +} + +static void device_free_td0_ring(struct vnt_private *pDevice) +{ + int i; + + for (i = 0; i < pDevice->sOpts.nTxDescs[0]; i++) { + PSTxDesc pDesc = &(pDevice->apTD0Rings[i]); + PDEVICE_TD_INFO pTDInfo = pDesc->pTDInfo; + + if (pTDInfo->skb_dma && (pTDInfo->skb_dma != pTDInfo->buf_dma)) + dma_unmap_single(&pDevice->pcid->dev, pTDInfo->skb_dma, + pTDInfo->skb->len, DMA_TO_DEVICE); + + if (pTDInfo->skb) + dev_kfree_skb(pTDInfo->skb); + + kfree(pDesc->pTDInfo); + } +} + +static void device_free_td1_ring(struct vnt_private *pDevice) +{ + int i; + + for (i = 0; i < pDevice->sOpts.nTxDescs[1]; i++) { + PSTxDesc pDesc = &(pDevice->apTD1Rings[i]); + PDEVICE_TD_INFO pTDInfo = pDesc->pTDInfo; + + if (pTDInfo->skb_dma && (pTDInfo->skb_dma != pTDInfo->buf_dma)) + dma_unmap_single(&pDevice->pcid->dev, pTDInfo->skb_dma, + pTDInfo->skb->len, DMA_TO_DEVICE); + + if (pTDInfo->skb) + dev_kfree_skb(pTDInfo->skb); + + kfree(pDesc->pTDInfo); + } +} + +/*-----------------------------------------------------------------*/ + +static int device_rx_srv(struct vnt_private *pDevice, unsigned int uIdx) +{ + PSRxDesc pRD; + int works = 0; + + for (pRD = pDevice->pCurrRD[uIdx]; + pRD->m_rd0RD0.f1Owner == OWNED_BY_HOST; + pRD = pRD->next) { + if (works++ > 15) + break; + if (vnt_receive_frame(pDevice, pRD)) { + if (!device_alloc_rx_buf(pDevice, pRD)) { + dev_err(&pDevice->pcid->dev, + "can not allocate rx buf\n"); + break; + } + } + pRD->m_rd0RD0.f1Owner = OWNED_BY_NIC; + } + + pDevice->pCurrRD[uIdx] = pRD; + + return works; +} + +static bool device_alloc_rx_buf(struct vnt_private *pDevice, PSRxDesc pRD) +{ + PDEVICE_RD_INFO pRDInfo = pRD->pRDInfo; + + pRDInfo->skb = dev_alloc_skb((int)pDevice->rx_buf_sz); + if (pRDInfo->skb == NULL) + return false; + ASSERT(pRDInfo->skb); + + pRDInfo->skb_dma = + dma_map_single(&pDevice->pcid->dev, + skb_put(pRDInfo->skb, skb_tailroom(pRDInfo->skb)), + pDevice->rx_buf_sz, DMA_FROM_DEVICE); + + *((unsigned int *)&(pRD->m_rd0RD0)) = 0; /* FIX cast */ + + pRD->m_rd0RD0.wResCount = cpu_to_le16(pDevice->rx_buf_sz); + pRD->m_rd0RD0.f1Owner = OWNED_BY_NIC; + pRD->m_rd1RD1.wReqCount = cpu_to_le16(pDevice->rx_buf_sz); + pRD->buff_addr = cpu_to_le32(pRDInfo->skb_dma); + + return true; +} + +static const u8 fallback_rate0[5][5] = { + {RATE_18M, RATE_18M, RATE_12M, RATE_12M, RATE_12M}, + {RATE_24M, RATE_24M, RATE_18M, RATE_12M, RATE_12M}, + {RATE_36M, RATE_36M, RATE_24M, RATE_18M, RATE_18M}, + {RATE_48M, RATE_48M, RATE_36M, RATE_24M, RATE_24M}, + {RATE_54M, RATE_54M, RATE_48M, RATE_36M, RATE_36M} +}; + +static const u8 fallback_rate1[5][5] = { + {RATE_18M, RATE_18M, RATE_12M, RATE_6M, RATE_6M}, + {RATE_24M, RATE_24M, RATE_18M, RATE_6M, RATE_6M}, + {RATE_36M, RATE_36M, RATE_24M, RATE_12M, RATE_12M}, + {RATE_48M, RATE_48M, RATE_24M, RATE_12M, RATE_12M}, + {RATE_54M, RATE_54M, RATE_36M, RATE_18M, RATE_18M} +}; + +static int vnt_int_report_rate(struct vnt_private *priv, + PDEVICE_TD_INFO context, u8 tsr0, u8 tsr1) +{ + struct vnt_tx_fifo_head *fifo_head; + struct ieee80211_tx_info *info; + struct ieee80211_rate *rate; + u16 fb_option; + u8 tx_retry = (tsr0 & TSR0_NCR); + s8 idx; + + if (!context) + return -ENOMEM; + + if (!context->skb) + return -EINVAL; + + fifo_head = (struct vnt_tx_fifo_head *)context->buf; + fb_option = (le16_to_cpu(fifo_head->fifo_ctl) & + (FIFOCTL_AUTO_FB_0 | FIFOCTL_AUTO_FB_1)); + + info = IEEE80211_SKB_CB(context->skb); + idx = info->control.rates[0].idx; + + if (fb_option && !(tsr1 & TSR1_TERR)) { + u8 tx_rate; + u8 retry = tx_retry; + + rate = ieee80211_get_tx_rate(priv->hw, info); + tx_rate = rate->hw_value - RATE_18M; + + if (retry > 4) + retry = 4; + + if (fb_option & FIFOCTL_AUTO_FB_0) + tx_rate = fallback_rate0[tx_rate][retry]; + else if (fb_option & FIFOCTL_AUTO_FB_1) + tx_rate = fallback_rate1[tx_rate][retry]; + + if (info->band == IEEE80211_BAND_5GHZ) + idx = tx_rate - RATE_6M; + else + idx = tx_rate; + } + + ieee80211_tx_info_clear_status(info); + + info->status.rates[0].count = tx_retry; + + if (!(tsr1 & TSR1_TERR)) { + info->status.rates[0].idx = idx; + + if (info->flags & IEEE80211_TX_CTL_NO_ACK) + info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; + else + info->flags |= IEEE80211_TX_STAT_ACK; + } + + return 0; +} + +static int device_tx_srv(struct vnt_private *pDevice, unsigned int uIdx) +{ + PSTxDesc pTD; + int works = 0; + unsigned char byTsr0; + unsigned char byTsr1; + + for (pTD = pDevice->apTailTD[uIdx]; pDevice->iTDUsed[uIdx] > 0; pTD = pTD->next) { + if (pTD->m_td0TD0.f1Owner == OWNED_BY_NIC) + break; + if (works++ > 15) + break; + + byTsr0 = pTD->m_td0TD0.byTSR0; + byTsr1 = pTD->m_td0TD0.byTSR1; + + /* Only the status of first TD in the chain is correct */ + if (pTD->m_td1TD1.byTCR & TCR_STP) { + if ((pTD->pTDInfo->byFlags & TD_FLAGS_NETIF_SKB) != 0) { + if (!(byTsr1 & TSR1_TERR)) { + if (byTsr0 != 0) { + pr_debug(" Tx[%d] OK but has error. tsr1[%02X] tsr0[%02X]\n", + (int)uIdx, byTsr1, + byTsr0); + } + } else { + pr_debug(" Tx[%d] dropped & tsr1[%02X] tsr0[%02X]\n", + (int)uIdx, byTsr1, byTsr0); + } + } + + if (byTsr1 & TSR1_TERR) { + if ((pTD->pTDInfo->byFlags & TD_FLAGS_PRIV_SKB) != 0) { + pr_debug(" Tx[%d] fail has error. tsr1[%02X] tsr0[%02X]\n", + (int)uIdx, byTsr1, byTsr0); + } + } + + vnt_int_report_rate(pDevice, pTD->pTDInfo, byTsr0, byTsr1); + + device_free_tx_buf(pDevice, pTD); + pDevice->iTDUsed[uIdx]--; + } + } + + pDevice->apTailTD[uIdx] = pTD; + + return works; +} + +static void device_error(struct vnt_private *pDevice, unsigned short status) +{ + if (status & ISR_FETALERR) { + dev_err(&pDevice->pcid->dev, "Hardware fatal error\n"); + + MACbShutdown(pDevice->PortOffset); + return; + } +} + +static void device_free_tx_buf(struct vnt_private *pDevice, PSTxDesc pDesc) +{ + PDEVICE_TD_INFO pTDInfo = pDesc->pTDInfo; + struct sk_buff *skb = pTDInfo->skb; + + /* pre-allocated buf_dma can't be unmapped. */ + if (pTDInfo->skb_dma && (pTDInfo->skb_dma != pTDInfo->buf_dma)) { + dma_unmap_single(&pDevice->pcid->dev, pTDInfo->skb_dma, + skb->len, DMA_TO_DEVICE); + } + + if (skb) + ieee80211_tx_status_irqsafe(pDevice->hw, skb); + + pTDInfo->skb_dma = 0; + pTDInfo->skb = NULL; + pTDInfo->byFlags = 0; +} + +static void vnt_check_bb_vga(struct vnt_private *priv) +{ + long dbm; + int i; + + if (!priv->bUpdateBBVGA) + return; + + if (priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) + return; + + if (!(priv->vif->bss_conf.assoc && priv->uCurrRSSI)) + return; + + RFvRSSITodBm(priv, (u8)priv->uCurrRSSI, &dbm); + + for (i = 0; i < BB_VGA_LEVEL; i++) { + if (dbm < priv->ldBmThreshold[i]) { + priv->byBBVGANew = priv->abyBBVGA[i]; + break; + } + } + + if (priv->byBBVGANew == priv->byBBVGACurrent) { + priv->uBBVGADiffCount = 1; + return; + } + + priv->uBBVGADiffCount++; + + if (priv->uBBVGADiffCount == 1) { + /* first VGA diff gain */ + BBvSetVGAGainOffset(priv, priv->byBBVGANew); + + dev_dbg(&priv->pcid->dev, + "First RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n", + (int)dbm, priv->byBBVGANew, + priv->byBBVGACurrent, + (int)priv->uBBVGADiffCount); + } + + if (priv->uBBVGADiffCount >= BB_VGA_CHANGE_THRESHOLD) { + dev_dbg(&priv->pcid->dev, + "RSSI[%d] NewGain[%d] OldGain[%d] Count[%d]\n", + (int)dbm, priv->byBBVGANew, + priv->byBBVGACurrent, + (int)priv->uBBVGADiffCount); + + BBvSetVGAGainOffset(priv, priv->byBBVGANew); + } +} + +static irqreturn_t device_intr(int irq, void *dev_instance) +{ + struct vnt_private *pDevice = dev_instance; + int max_count = 0; + unsigned long dwMIBCounter = 0; + unsigned char byOrgPageSel = 0; + int handled = 0; + unsigned long flags; + + MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr); + + if (pDevice->dwIsr == 0) + return IRQ_RETVAL(handled); + + if (pDevice->dwIsr == 0xffffffff) { + pr_debug("dwIsr = 0xffff\n"); + return IRQ_RETVAL(handled); + } + + handled = 1; + MACvIntDisable(pDevice->PortOffset); + + spin_lock_irqsave(&pDevice->lock, flags); + + /* Make sure current page is 0 */ + VNSvInPortB(pDevice->PortOffset + MAC_REG_PAGE1SEL, &byOrgPageSel); + if (byOrgPageSel == 1) + MACvSelectPage0(pDevice->PortOffset); + else + byOrgPageSel = 0; + + MACvReadMIBCounter(pDevice->PortOffset, &dwMIBCounter); + /* + * TBD.... + * Must do this after doing rx/tx, cause ISR bit is slow + * than RD/TD write back + * update ISR counter + */ + STAvUpdate802_11Counter(&pDevice->s802_11Counter, &pDevice->scStatistic, dwMIBCounter); + while (pDevice->dwIsr != 0) { + STAvUpdateIsrStatCounter(&pDevice->scStatistic, pDevice->dwIsr); + MACvWriteISR(pDevice->PortOffset, pDevice->dwIsr); + + if (pDevice->dwIsr & ISR_FETALERR) { + pr_debug(" ISR_FETALERR\n"); + VNSvOutPortB(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, 0); + VNSvOutPortW(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI); + device_error(pDevice, pDevice->dwIsr); + } + + if (pDevice->dwIsr & ISR_TBTT) { + if (pDevice->vif && + pDevice->op_mode != NL80211_IFTYPE_ADHOC) + vnt_check_bb_vga(pDevice); + + pDevice->bBeaconSent = false; + if (pDevice->bEnablePSMode) + PSbIsNextTBTTWakeUp((void *)pDevice); + + if ((pDevice->op_mode == NL80211_IFTYPE_AP || + pDevice->op_mode == NL80211_IFTYPE_ADHOC) && + pDevice->vif->bss_conf.enable_beacon) { + MACvOneShotTimer1MicroSec(pDevice->PortOffset, + (pDevice->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10); + } + + /* TODO: adhoc PS mode */ + + } + + if (pDevice->dwIsr & ISR_BNTX) { + if (pDevice->op_mode == NL80211_IFTYPE_ADHOC) { + pDevice->bIsBeaconBufReadySet = false; + pDevice->cbBeaconBufReadySetCnt = 0; + } + + pDevice->bBeaconSent = true; + } + + if (pDevice->dwIsr & ISR_RXDMA0) + max_count += device_rx_srv(pDevice, TYPE_RXDMA0); + + if (pDevice->dwIsr & ISR_RXDMA1) + max_count += device_rx_srv(pDevice, TYPE_RXDMA1); + + if (pDevice->dwIsr & ISR_TXDMA0) + max_count += device_tx_srv(pDevice, TYPE_TXDMA0); + + if (pDevice->dwIsr & ISR_AC0DMA) + max_count += device_tx_srv(pDevice, TYPE_AC0DMA); + + if (pDevice->dwIsr & ISR_SOFTTIMER1) { + if (pDevice->vif) { + if (pDevice->vif->bss_conf.enable_beacon) + vnt_beacon_make(pDevice, pDevice->vif); + } + } + + /* If both buffers available wake the queue */ + if (pDevice->vif) { + if (AVAIL_TD(pDevice, TYPE_TXDMA0) && + AVAIL_TD(pDevice, TYPE_AC0DMA) && + ieee80211_queue_stopped(pDevice->hw, 0)) + ieee80211_wake_queues(pDevice->hw); + } + + MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr); + + MACvReceive0(pDevice->PortOffset); + MACvReceive1(pDevice->PortOffset); + + if (max_count > pDevice->sOpts.int_works) + break; + } + + if (byOrgPageSel == 1) + MACvSelectPage1(pDevice->PortOffset); + + spin_unlock_irqrestore(&pDevice->lock, flags); + + MACvIntEnable(pDevice->PortOffset, IMR_MASK_VALUE); + + return IRQ_RETVAL(handled); +} + +static int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + PSTxDesc head_td; + u32 dma_idx; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (ieee80211_is_data(hdr->frame_control)) + dma_idx = TYPE_AC0DMA; + else + dma_idx = TYPE_TXDMA0; + + if (AVAIL_TD(priv, dma_idx) < 1) { + spin_unlock_irqrestore(&priv->lock, flags); + return -ENOMEM; + } + + head_td = priv->apCurrTD[dma_idx]; + + head_td->m_td1TD1.byTCR = 0; + + head_td->pTDInfo->skb = skb; + + if (dma_idx == TYPE_AC0DMA) + head_td->pTDInfo->byFlags = TD_FLAGS_NETIF_SKB; + + priv->apCurrTD[dma_idx] = head_td->next; + + spin_unlock_irqrestore(&priv->lock, flags); + + vnt_generate_fifo_header(priv, dma_idx, head_td, skb); + + if (MACbIsRegBitsOn(priv->PortOffset, MAC_REG_PSCTL, PSCTL_PS)) + MACbPSWakeup(priv->PortOffset); + + spin_lock_irqsave(&priv->lock, flags); + + priv->bPWBitOn = false; + + /* Set TSR1 & ReqCount in TxDescHead */ + head_td->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU); + head_td->m_td1TD1.wReqCount = + cpu_to_le16((u16)head_td->pTDInfo->dwReqCount); + + head_td->buff_addr = cpu_to_le32(head_td->pTDInfo->skb_dma); + + /* Poll Transmit the adapter */ + wmb(); + head_td->m_td0TD0.f1Owner = OWNED_BY_NIC; + wmb(); /* second memory barrier */ + + if (head_td->pTDInfo->byFlags & TD_FLAGS_NETIF_SKB) + MACvTransmitAC0(priv->PortOffset); + else + MACvTransmit0(priv->PortOffset); + + priv->iTDUsed[dma_idx]++; + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static void vnt_tx_80211(struct ieee80211_hw *hw, + struct ieee80211_tx_control *control, + struct sk_buff *skb) +{ + struct vnt_private *priv = hw->priv; + + ieee80211_stop_queues(hw); + + if (vnt_tx_packet(priv, skb)) { + ieee80211_free_txskb(hw, skb); + + ieee80211_wake_queues(hw); + } +} + +static int vnt_start(struct ieee80211_hw *hw) +{ + struct vnt_private *priv = hw->priv; + int ret; + + priv->rx_buf_sz = PKT_BUF_SZ; + if (!device_init_rings(priv)) + return -ENOMEM; + + ret = request_irq(priv->pcid->irq, &device_intr, + IRQF_SHARED, "vt6655", priv); + if (ret) { + dev_dbg(&priv->pcid->dev, "failed to start irq\n"); + return ret; + } + + dev_dbg(&priv->pcid->dev, "call device init rd0 ring\n"); + device_init_rd0_ring(priv); + device_init_rd1_ring(priv); + device_init_td0_ring(priv); + device_init_td1_ring(priv); + + device_init_registers(priv); + + dev_dbg(&priv->pcid->dev, "call MACvIntEnable\n"); + MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE); + + ieee80211_wake_queues(hw); + + return 0; +} + +static void vnt_stop(struct ieee80211_hw *hw) +{ + struct vnt_private *priv = hw->priv; + + ieee80211_stop_queues(hw); + + MACbShutdown(priv->PortOffset); + MACbSoftwareReset(priv->PortOffset); + CARDbRadioPowerOff(priv); + + device_free_td0_ring(priv); + device_free_td1_ring(priv); + device_free_rd0_ring(priv); + device_free_rd1_ring(priv); + device_free_rings(priv); + + free_irq(priv->pcid->irq, priv); +} + +static int vnt_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct vnt_private *priv = hw->priv; + + priv->vif = vif; + + switch (vif->type) { + case NL80211_IFTYPE_STATION: + break; + case NL80211_IFTYPE_ADHOC: + MACvRegBitsOff(priv->PortOffset, MAC_REG_RCR, RCR_UNICAST); + + MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_ADHOC); + + break; + case NL80211_IFTYPE_AP: + MACvRegBitsOff(priv->PortOffset, MAC_REG_RCR, RCR_UNICAST); + + MACvRegBitsOn(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_AP); + + break; + default: + return -EOPNOTSUPP; + } + + priv->op_mode = vif->type; + + return 0; +} + +static void vnt_remove_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct vnt_private *priv = hw->priv; + + switch (vif->type) { + case NL80211_IFTYPE_STATION: + break; + case NL80211_IFTYPE_ADHOC: + MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX); + MACvRegBitsOff(priv->PortOffset, + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); + MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_ADHOC); + break; + case NL80211_IFTYPE_AP: + MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX); + MACvRegBitsOff(priv->PortOffset, + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); + MACvRegBitsOff(priv->PortOffset, MAC_REG_HOSTCR, HOSTCR_AP); + break; + default: + break; + } + + priv->op_mode = NL80211_IFTYPE_UNSPECIFIED; +} + + +static int vnt_config(struct ieee80211_hw *hw, u32 changed) +{ + struct vnt_private *priv = hw->priv; + struct ieee80211_conf *conf = &hw->conf; + u8 bb_type; + + if (changed & IEEE80211_CONF_CHANGE_PS) { + if (conf->flags & IEEE80211_CONF_PS) + PSvEnablePowerSaving(priv, conf->listen_interval); + else + PSvDisablePowerSaving(priv); + } + + if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || + (conf->flags & IEEE80211_CONF_OFFCHANNEL)) { + set_channel(priv, conf->chandef.chan); + + if (conf->chandef.chan->band == IEEE80211_BAND_5GHZ) + bb_type = BB_TYPE_11A; + else + bb_type = BB_TYPE_11G; + + if (priv->byBBType != bb_type) { + priv->byBBType = bb_type; + + CARDbSetPhyParameter(priv, priv->byBBType); + } + } + + if (changed & IEEE80211_CONF_CHANGE_POWER) { + if (priv->byBBType == BB_TYPE_11B) + priv->wCurrentRate = RATE_1M; + else + priv->wCurrentRate = RATE_54M; + + RFbSetPower(priv, priv->wCurrentRate, + conf->chandef.chan->hw_value); + } + + return 0; +} + +static void vnt_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, struct ieee80211_bss_conf *conf, + u32 changed) +{ + struct vnt_private *priv = hw->priv; + + priv->current_aid = conf->aid; + + if (changed & BSS_CHANGED_BSSID) { + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + MACvWriteBSSIDAddress(priv->PortOffset, (u8 *)conf->bssid); + + spin_unlock_irqrestore(&priv->lock, flags); + } + + if (changed & BSS_CHANGED_BASIC_RATES) { + priv->basic_rates = conf->basic_rates; + + CARDvUpdateBasicTopRate(priv); + + dev_dbg(&priv->pcid->dev, + "basic rates %x\n", conf->basic_rates); + } + + if (changed & BSS_CHANGED_ERP_PREAMBLE) { + if (conf->use_short_preamble) { + MACvEnableBarkerPreambleMd(priv->PortOffset); + priv->byPreambleType = true; + } else { + MACvDisableBarkerPreambleMd(priv->PortOffset); + priv->byPreambleType = false; + } + } + + if (changed & BSS_CHANGED_ERP_CTS_PROT) { + if (conf->use_cts_prot) + MACvEnableProtectMD(priv->PortOffset); + else + MACvDisableProtectMD(priv->PortOffset); + } + + if (changed & BSS_CHANGED_ERP_SLOT) { + if (conf->use_short_slot) + priv->bShortSlotTime = true; + else + priv->bShortSlotTime = false; + + CARDbSetPhyParameter(priv, priv->byBBType); + BBvSetVGAGainOffset(priv, priv->abyBBVGA[0]); + } + + if (changed & BSS_CHANGED_TXPOWER) + RFbSetPower(priv, priv->wCurrentRate, + conf->chandef.chan->hw_value); + + if (changed & BSS_CHANGED_BEACON_ENABLED) { + dev_dbg(&priv->pcid->dev, + "Beacon enable %d\n", conf->enable_beacon); + + if (conf->enable_beacon) { + vnt_beacon_enable(priv, vif, conf); + + MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR, + TCR_AUTOBCNTX); + } else { + MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR, + TCR_AUTOBCNTX); + } + } + + if (changed & BSS_CHANGED_ASSOC && priv->op_mode != NL80211_IFTYPE_AP) { + if (conf->assoc) { + CARDbUpdateTSF(priv, conf->beacon_rate->hw_value, + conf->sync_tsf); + + CARDbSetBeaconPeriod(priv, conf->beacon_int); + + CARDvSetFirstNextTBTT(priv, conf->beacon_int); + } else { + VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, + TFTCTL_TSFCNTRST); + VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, + TFTCTL_TSFCNTREN); + } + } +} + +static u64 vnt_prepare_multicast(struct ieee80211_hw *hw, + struct netdev_hw_addr_list *mc_list) +{ + struct vnt_private *priv = hw->priv; + struct netdev_hw_addr *ha; + u64 mc_filter = 0; + u32 bit_nr = 0; + + netdev_hw_addr_list_for_each(ha, mc_list) { + bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; + + mc_filter |= 1ULL << (bit_nr & 0x3f); + } + + priv->mc_list_count = mc_list->count; + + return mc_filter; +} + +static void vnt_configure(struct ieee80211_hw *hw, + unsigned int changed_flags, unsigned int *total_flags, u64 multicast) +{ + struct vnt_private *priv = hw->priv; + u8 rx_mode = 0; + + *total_flags &= FIF_ALLMULTI | FIF_OTHER_BSS | FIF_PROMISC_IN_BSS | + FIF_BCN_PRBRESP_PROMISC; + + VNSvInPortB(priv->PortOffset + MAC_REG_RCR, &rx_mode); + + dev_dbg(&priv->pcid->dev, "rx mode in = %x\n", rx_mode); + + if (changed_flags & FIF_PROMISC_IN_BSS) { + /* unconditionally log net taps */ + if (*total_flags & FIF_PROMISC_IN_BSS) + rx_mode |= RCR_UNICAST; + else + rx_mode &= ~RCR_UNICAST; + } + + if (changed_flags & FIF_ALLMULTI) { + if (*total_flags & FIF_ALLMULTI) { + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + if (priv->mc_list_count > 2) { + MACvSelectPage1(priv->PortOffset); + + VNSvOutPortD(priv->PortOffset + + MAC_REG_MAR0, 0xffffffff); + VNSvOutPortD(priv->PortOffset + + MAC_REG_MAR0 + 4, 0xffffffff); + + MACvSelectPage0(priv->PortOffset); + } else { + MACvSelectPage1(priv->PortOffset); + + VNSvOutPortD(priv->PortOffset + + MAC_REG_MAR0, (u32)multicast); + VNSvOutPortD(priv->PortOffset + + MAC_REG_MAR0 + 4, + (u32)(multicast >> 32)); + + MACvSelectPage0(priv->PortOffset); + } + + spin_unlock_irqrestore(&priv->lock, flags); + + rx_mode |= RCR_MULTICAST | RCR_BROADCAST; + } else { + rx_mode &= ~(RCR_MULTICAST | RCR_BROADCAST); + } + } + + if (changed_flags & (FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC)) { + rx_mode |= RCR_MULTICAST | RCR_BROADCAST; + + if (*total_flags & (FIF_OTHER_BSS | FIF_BCN_PRBRESP_PROMISC)) + rx_mode &= ~RCR_BSSID; + else + rx_mode |= RCR_BSSID; + } + + VNSvOutPortB(priv->PortOffset + MAC_REG_RCR, rx_mode); + + dev_dbg(&priv->pcid->dev, "rx mode out= %x\n", rx_mode); +} + +static int vnt_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, + struct ieee80211_vif *vif, struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + struct vnt_private *priv = hw->priv; + + switch (cmd) { + case SET_KEY: + if (vnt_set_keys(hw, sta, vif, key)) + return -EOPNOTSUPP; + break; + case DISABLE_KEY: + if (test_bit(key->hw_key_idx, &priv->key_entry_inuse)) + clear_bit(key->hw_key_idx, &priv->key_entry_inuse); + default: + break; + } + + return 0; +} + +static u64 vnt_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct vnt_private *priv = hw->priv; + u64 tsf; + + CARDbGetCurrentTSF(priv, &tsf); + + return tsf; +} + +static void vnt_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u64 tsf) +{ + struct vnt_private *priv = hw->priv; + + CARDvUpdateNextTBTT(priv, tsf, vif->bss_conf.beacon_int); +} + +static void vnt_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) +{ + struct vnt_private *priv = hw->priv; + + /* reset TSF counter */ + VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST); +} + +static const struct ieee80211_ops vnt_mac_ops = { + .tx = vnt_tx_80211, + .start = vnt_start, + .stop = vnt_stop, + .add_interface = vnt_add_interface, + .remove_interface = vnt_remove_interface, + .config = vnt_config, + .bss_info_changed = vnt_bss_info_changed, + .prepare_multicast = vnt_prepare_multicast, + .configure_filter = vnt_configure, + .set_key = vnt_set_key, + .get_tsf = vnt_get_tsf, + .set_tsf = vnt_set_tsf, + .reset_tsf = vnt_reset_tsf, +}; + +static int vnt_init(struct vnt_private *priv) +{ + SET_IEEE80211_PERM_ADDR(priv->hw, priv->abyCurrentNetAddr); + + vnt_init_bands(priv); + + if (ieee80211_register_hw(priv->hw)) + return -ENODEV; + + priv->mac_hw = true; + + CARDbRadioPowerOff(priv); + + return 0; +} + +static int +vt6655_probe(struct pci_dev *pcid, const struct pci_device_id *ent) +{ + PCHIP_INFO pChip_info = (PCHIP_INFO)ent->driver_data; + struct vnt_private *priv; + struct ieee80211_hw *hw; + struct wiphy *wiphy; + int rc; + + dev_notice(&pcid->dev, + "%s Ver. %s\n", DEVICE_FULL_DRV_NAM, DEVICE_VERSION); + + dev_notice(&pcid->dev, + "Copyright (c) 2003 VIA Networking Technologies, Inc.\n"); + + hw = ieee80211_alloc_hw(sizeof(*priv), &vnt_mac_ops); + if (!hw) { + dev_err(&pcid->dev, "could not register ieee80211_hw\n"); + return -ENOMEM; + } + + priv = hw->priv; + + vt6655_init_info(pcid, &priv, pChip_info); + + priv->hw = hw; + + SET_IEEE80211_DEV(priv->hw, &pcid->dev); + + if (pci_enable_device(pcid)) { + device_free_info(priv); + return -ENODEV; + } + + dev_dbg(&pcid->dev, + "Before get pci_info memaddr is %x\n", priv->memaddr); + + if (!device_get_pci_info(priv, pcid)) { + dev_err(&pcid->dev, ": Failed to find PCI device.\n"); + device_free_info(priv); + return -ENODEV; + } + +#ifdef DEBUG + dev_dbg(&pcid->dev, + "after get pci_info memaddr is %x, io addr is %x,io_size is %d\n", + priv->memaddr, priv->ioaddr, priv->io_size); + { + int i; + u32 bar, len; + u32 address[] = { + PCI_BASE_ADDRESS_0, + PCI_BASE_ADDRESS_1, + PCI_BASE_ADDRESS_2, + PCI_BASE_ADDRESS_3, + PCI_BASE_ADDRESS_4, + PCI_BASE_ADDRESS_5, + 0}; + for (i = 0; address[i]; i++) { + pci_read_config_dword(pcid, address[i], &bar); + + dev_dbg(&pcid->dev, "bar %d is %x\n", i, bar); + + if (!bar) { + dev_dbg(&pcid->dev, + "bar %d not implemented\n", i); + continue; + } + + if (bar & PCI_BASE_ADDRESS_SPACE_IO) { + /* This is IO */ + + len = bar & (PCI_BASE_ADDRESS_IO_MASK & 0xffff); + len = len & ~(len - 1); + + dev_dbg(&pcid->dev, + "IO space: len in IO %x, BAR %d\n", + len, i); + } else { + len = bar & 0xfffffff0; + len = ~len + 1; + + dev_dbg(&pcid->dev, + "len in MEM %x, BAR %d\n", len, i); + } + } + } +#endif + + priv->PortOffset = ioremap(priv->memaddr & PCI_BASE_ADDRESS_MEM_MASK, + priv->io_size); + if (!priv->PortOffset) { + dev_err(&pcid->dev, ": Failed to IO remapping ..\n"); + device_free_info(priv); + return -ENODEV; + } + + rc = pci_request_regions(pcid, DEVICE_NAME); + if (rc) { + dev_err(&pcid->dev, ": Failed to find PCI device\n"); + device_free_info(priv); + return -ENODEV; + } + + /* do reset */ + if (!MACbSoftwareReset(priv->PortOffset)) { + dev_err(&pcid->dev, ": Failed to access MAC hardware..\n"); + device_free_info(priv); + return -ENODEV; + } + /* initial to reload eeprom */ + MACvInitialize(priv->PortOffset); + MACvReadEtherAddress(priv->PortOffset, priv->abyCurrentNetAddr); + + /* Get RFType */ + priv->byRFType = SROMbyReadEmbedded(priv->PortOffset, EEP_OFS_RFTYPE); + priv->byRFType &= RF_MASK; + + dev_dbg(&pcid->dev, "RF Type = %x\n", priv->byRFType); + + device_get_options(priv); + device_set_options(priv); + /* Mask out the options cannot be set to the chip */ + priv->sOpts.flags &= pChip_info->flags; + + /* Enable the chip specified capabilities */ + priv->flags = priv->sOpts.flags | (pChip_info->flags & 0xff000000UL); + + wiphy = priv->hw->wiphy; + + wiphy->frag_threshold = FRAG_THRESH_DEF; + wiphy->rts_threshold = RTS_THRESH_DEF; + wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); + + priv->hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | + IEEE80211_HW_REPORTS_TX_ACK_STATUS | + IEEE80211_HW_SIGNAL_DBM | + IEEE80211_HW_TIMING_BEACON_ONLY; + + priv->hw->max_signal = 100; + + if (vnt_init(priv)) + return -ENODEV; + + device_print_info(priv); + pci_set_drvdata(pcid, priv); + + return 0; +} + +/*------------------------------------------------------------------*/ + +#ifdef CONFIG_PM +static int vt6655_suspend(struct pci_dev *pcid, pm_message_t state) +{ + struct vnt_private *priv = pci_get_drvdata(pcid); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + pci_save_state(pcid); + + MACbShutdown(priv->PortOffset); + + pci_disable_device(pcid); + pci_set_power_state(pcid, pci_choose_state(pcid, state)); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int vt6655_resume(struct pci_dev *pcid) +{ + + pci_set_power_state(pcid, PCI_D0); + pci_enable_wake(pcid, PCI_D0, 0); + pci_restore_state(pcid); + + return 0; +} +#endif + +MODULE_DEVICE_TABLE(pci, vt6655_pci_id_table); + +static struct pci_driver device_driver = { + .name = DEVICE_NAME, + .id_table = vt6655_pci_id_table, + .probe = vt6655_probe, + .remove = vt6655_remove, +#ifdef CONFIG_PM + .suspend = vt6655_suspend, + .resume = vt6655_resume, +#endif +}; + +static int __init vt6655_init_module(void) +{ + int ret; + + ret = pci_register_driver(&device_driver); +#ifdef CONFIG_PM + if (ret >= 0) + register_reboot_notifier(&device_notifier); +#endif + + return ret; +} + +static void __exit vt6655_cleanup_module(void) +{ +#ifdef CONFIG_PM + unregister_reboot_notifier(&device_notifier); +#endif + pci_unregister_driver(&device_driver); +} + +module_init(vt6655_init_module); +module_exit(vt6655_cleanup_module); + +#ifdef CONFIG_PM +static int +device_notify_reboot(struct notifier_block *nb, unsigned long event, void *p) +{ + struct pci_dev *pdev = NULL; + + switch (event) { + case SYS_DOWN: + case SYS_HALT: + case SYS_POWER_OFF: + for_each_pci_dev(pdev) { + if (pci_dev_driver(pdev) == &device_driver) { + if (pci_get_drvdata(pdev)) + vt6655_suspend(pdev, PMSG_HIBERNATE); + } + } + } + return NOTIFY_DONE; +} +#endif diff --git a/kernel/drivers/staging/vt6655/dpc.c b/kernel/drivers/staging/vt6655/dpc.c new file mode 100644 index 000000000..b25ee9625 --- /dev/null +++ b/kernel/drivers/staging/vt6655/dpc.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: dpc.c + * + * Purpose: handle dpc rx functions + * + * Author: Lyndon Chen + * + * Date: May 20, 2003 + * + * Functions: + * + * Revision History: + * + */ + +#include "device.h" +#include "baseband.h" +#include "rf.h" +#include "dpc.h" + +static bool vnt_rx_data(struct vnt_private *priv, struct sk_buff *skb, + u16 bytes_received) +{ + struct ieee80211_hw *hw = priv->hw; + struct ieee80211_supported_band *sband; + struct ieee80211_rx_status rx_status = { 0 }; + struct ieee80211_hdr *hdr; + __le16 fc; + u8 *rsr, *new_rsr, *rssi; + __le64 *tsf_time; + u16 frame_size; + int ii, r; + u8 *rx_sts, *rx_rate, *sq; + u8 *skb_data; + u8 rate_idx = 0; + u8 rate[MAX_RATE] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108}; + long rx_dbm; + + /* [31:16]RcvByteCount ( not include 4-byte Status ) */ + frame_size = le16_to_cpu(*((__le16 *)(skb->data + 2))); + if (frame_size > 2346 || frame_size < 14) { + dev_dbg(&priv->pcid->dev, "------- WRONG Length 1\n"); + return false; + } + + skb_data = (u8 *)skb->data; + + rx_sts = skb_data; + rx_rate = skb_data + 1; + + sband = hw->wiphy->bands[hw->conf.chandef.chan->band]; + + for (r = RATE_1M; r < MAX_RATE; r++) { + if (*rx_rate == rate[r]) + break; + } + + priv->rx_rate = r; + + for (ii = 0; ii < sband->n_bitrates; ii++) { + if (sband->bitrates[ii].hw_value == r) { + rate_idx = ii; + break; + } + } + + if (ii == sband->n_bitrates) { + dev_dbg(&priv->pcid->dev, "Wrong RxRate %x\n", *rx_rate); + return false; + } + + tsf_time = (__le64 *)(skb_data + bytes_received - 12); + sq = skb_data + bytes_received - 4; + new_rsr = skb_data + bytes_received - 3; + rssi = skb_data + bytes_received - 2; + rsr = skb_data + bytes_received - 1; + if (*rsr & (RSR_IVLDTYP | RSR_IVLDLEN)) + return false; + + RFvRSSITodBm(priv, *rssi, &rx_dbm); + + priv->byBBPreEDRSSI = (u8)rx_dbm + 1; + priv->uCurrRSSI = *rssi; + + skb_pull(skb, 4); + skb_trim(skb, frame_size); + + rx_status.mactime = le64_to_cpu(*tsf_time); + rx_status.band = hw->conf.chandef.chan->band; + rx_status.signal = rx_dbm; + rx_status.flag = 0; + rx_status.freq = hw->conf.chandef.chan->center_freq; + + if (!(*rsr & RSR_CRCOK)) + rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; + + hdr = (struct ieee80211_hdr *)(skb->data); + fc = hdr->frame_control; + + rx_status.rate_idx = rate_idx; + + if (ieee80211_has_protected(fc)) { + if (priv->byLocalID > REV_ID_VT3253_A1) + rx_status.flag |= RX_FLAG_DECRYPTED; + + /* Drop packet */ + if (!(*new_rsr & NEWRSR_DECRYPTOK)) + return false; + } + + memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); + + ieee80211_rx_irqsafe(priv->hw, skb); + + return true; +} + +bool vnt_receive_frame(struct vnt_private *priv, PSRxDesc curr_rd) +{ + PDEVICE_RD_INFO rd_info = curr_rd->pRDInfo; + struct sk_buff *skb; + u16 frame_size; + + skb = rd_info->skb; + + dma_unmap_single(&priv->pcid->dev, rd_info->skb_dma, + priv->rx_buf_sz, DMA_FROM_DEVICE); + + frame_size = le16_to_cpu(curr_rd->m_rd1RD1.wReqCount) + - cpu_to_le16(curr_rd->m_rd0RD0.wResCount); + + if ((frame_size > 2364) || (frame_size < 33)) { + /* Frame Size error drop this packet.*/ + dev_dbg(&priv->pcid->dev, "Wrong frame size %d\n", frame_size); + dev_kfree_skb_irq(skb); + return true; + } + + if (vnt_rx_data(priv, skb, frame_size)) + return true; + + dev_kfree_skb_irq(skb); + + return true; +} diff --git a/kernel/drivers/staging/vt6655/dpc.h b/kernel/drivers/staging/vt6655/dpc.h new file mode 100644 index 000000000..ad495719a --- /dev/null +++ b/kernel/drivers/staging/vt6655/dpc.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: dpc.h + * + * Purpose: + * + * Author: Jerry Chen + * + * Date: Jun. 27, 2002 + * + */ + +#ifndef __DPC_H__ +#define __DPC_H__ + +#include "device.h" + +bool vnt_receive_frame(struct vnt_private *priv, PSRxDesc curr_rd); + +#endif /* __RXTX_H__ */ diff --git a/kernel/drivers/staging/vt6655/key.c b/kernel/drivers/staging/vt6655/key.c new file mode 100644 index 000000000..f2b3fea90 --- /dev/null +++ b/kernel/drivers/staging/vt6655/key.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: key.c + * + * Purpose: Implement functions for 802.11i Key management + * + * Author: Jerry Chen + * + * Date: May 29, 2003 + * + */ + +#include "tmacro.h" +#include "key.h" +#include "mac.h" + +int vnt_key_init_table(struct vnt_private *priv) +{ + u32 i; + + for (i = 0; i < MAX_KEY_TABLE; i++) + MACvDisableKeyEntry(priv->PortOffset, i); + + return 0; +} + +static int vnt_set_keymode(struct ieee80211_hw *hw, u8 *mac_addr, + struct ieee80211_key_conf *key, u32 key_type, u32 mode, + bool onfly_latch) +{ + struct vnt_private *priv = hw->priv; + u8 broadcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u16 key_mode = 0; + u32 entry = 0; + u8 *bssid; + u8 key_inx = key->keyidx; + u8 i; + + if (mac_addr) + bssid = mac_addr; + else + bssid = &broadcast[0]; + + if (key_type != VNT_KEY_DEFAULTKEY) { + for (i = 0; i < (MAX_KEY_TABLE - 1); i++) { + if (!test_bit(i, &priv->key_entry_inuse)) { + set_bit(i, &priv->key_entry_inuse); + + key->hw_key_idx = i; + entry = key->hw_key_idx; + break; + } + } + } + + switch (key_type) { + /* fallthrough */ + case VNT_KEY_DEFAULTKEY: + /* default key last entry */ + entry = MAX_KEY_TABLE - 1; + key->hw_key_idx = entry; + case VNT_KEY_ALLGROUP: + key_mode |= VNT_KEY_ALLGROUP; + if (onfly_latch) + key_mode |= VNT_KEY_ONFLY_ALL; + case VNT_KEY_GROUP_ADDRESS: + key_mode |= mode; + case VNT_KEY_GROUP: + key_mode |= (mode << 4); + key_mode |= VNT_KEY_GROUP; + break; + case VNT_KEY_PAIRWISE: + key_mode |= mode; + key_inx = 4; + break; + default: + return -EINVAL; + } + + if (onfly_latch) + key_mode |= VNT_KEY_ONFLY; + + if (mode == KEY_CTL_WEP) { + if (key->keylen == WLAN_KEY_LEN_WEP40) + key->key[15] &= 0x7f; + if (key->keylen == WLAN_KEY_LEN_WEP104) + key->key[15] |= 0x80; + } + + MACvSetKeyEntry(priv->PortOffset, key_mode, entry, key_inx, + bssid, (u32 *)key->key, priv->byLocalID); + + return 0; +} + +int vnt_set_keys(struct ieee80211_hw *hw, struct ieee80211_sta *sta, + struct ieee80211_vif *vif, struct ieee80211_key_conf *key) +{ + struct ieee80211_bss_conf *conf = &vif->bss_conf; + struct vnt_private *priv = hw->priv; + u8 *mac_addr = NULL; + u8 key_dec_mode = 0; + int ret = 0; + u32 u; + + if (sta) + mac_addr = &sta->addr[0]; + + switch (key->cipher) { + case 0: + for (u = 0 ; u < MAX_KEY_TABLE; u++) + MACvDisableKeyEntry(priv->PortOffset, u); + return ret; + + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + for (u = 0; u < MAX_KEY_TABLE; u++) + MACvDisableKeyEntry(priv->PortOffset, u); + + vnt_set_keymode(hw, mac_addr, + key, VNT_KEY_DEFAULTKEY, KEY_CTL_WEP, true); + + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; + + return ret; + case WLAN_CIPHER_SUITE_TKIP: + key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; + + key_dec_mode = KEY_CTL_TKIP; + + break; + case WLAN_CIPHER_SUITE_CCMP: + key_dec_mode = KEY_CTL_CCMP; + + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; + } + + if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { + vnt_set_keymode(hw, mac_addr, + key, VNT_KEY_PAIRWISE, key_dec_mode, true); + } else { + vnt_set_keymode(hw, mac_addr, + key, VNT_KEY_DEFAULTKEY, key_dec_mode, true); + + vnt_set_keymode(hw, (u8 *)conf->bssid, + key, VNT_KEY_GROUP_ADDRESS, key_dec_mode, true); + } + + return 0; +} diff --git a/kernel/drivers/staging/vt6655/key.h b/kernel/drivers/staging/vt6655/key.h new file mode 100644 index 000000000..261f8181d --- /dev/null +++ b/kernel/drivers/staging/vt6655/key.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: key.h + * + * Purpose: Implement functions for 802.11i Key management + * + * Author: Jerry Chen + * + * Date: May 29, 2003 + * + */ + +#ifndef __KEY_H__ +#define __KEY_H__ + +#include <net/mac80211.h> + +/*--------------------- Export Definitions -------------------------*/ +#define MAX_GROUP_KEY 4 +#define MAX_KEY_TABLE 11 +#define MAX_KEY_LEN 32 +#define AES_KEY_LEN 16 + +#define AUTHENTICATOR_KEY 0x10000000 +#define USE_KEYRSC 0x20000000 +#define PAIRWISE_KEY 0x40000000 +#define TRANSMIT_KEY 0x80000000 + +#define GROUP_KEY 0x00000000 + +#define KEY_CTL_WEP 0x00 +#define KEY_CTL_NONE 0x01 +#define KEY_CTL_TKIP 0x02 +#define KEY_CTL_CCMP 0x03 +#define KEY_CTL_INVALID 0xFF + +#define VNT_KEY_DEFAULTKEY 0x1 +#define VNT_KEY_GROUP_ADDRESS 0x2 +#define VNT_KEY_ALLGROUP 0x4 +#define VNT_KEY_GROUP 0x40 +#define VNT_KEY_PAIRWISE 0x00 +#define VNT_KEY_ONFLY 0x8000 +#define VNT_KEY_ONFLY_ALL 0x4000 + +struct vnt_private; + +int vnt_key_init_table(struct vnt_private *); + +int vnt_set_keys(struct ieee80211_hw *hw, struct ieee80211_sta *sta, + struct ieee80211_vif *vif, struct ieee80211_key_conf *key); + +#endif /* __KEY_H__ */ diff --git a/kernel/drivers/staging/vt6655/mac.c b/kernel/drivers/staging/vt6655/mac.c new file mode 100644 index 000000000..8048b3263 --- /dev/null +++ b/kernel/drivers/staging/vt6655/mac.c @@ -0,0 +1,895 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: mac.c + * + * Purpose: MAC routines + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + * Functions: + * MACbIsRegBitsOn - Test if All test Bits On + * MACbIsRegBitsOff - Test if All test Bits Off + * MACbIsIntDisable - Test if MAC interrupt disable + * MACvSetShortRetryLimit - Set 802.11 Short Retry limit + * MACvSetLongRetryLimit - Set 802.11 Long Retry limit + * MACvSetLoopbackMode - Set MAC Loopback Mode + * MACvSaveContext - Save Context of MAC Registers + * MACvRestoreContext - Restore Context of MAC Registers + * MACbSoftwareReset - Software Reset MAC + * MACbSafeRxOff - Turn Off MAC Rx + * MACbSafeTxOff - Turn Off MAC Tx + * MACbSafeStop - Stop MAC function + * MACbShutdown - Shut down MAC + * MACvInitialize - Initialize MAC + * MACvSetCurrRxDescAddr - Set Rx Descriptors Address + * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address + * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address + * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC + * + * Revision History: + * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53 + * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()& MACvEnableBusSusEn() + * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry + * + */ + +#include "tmacro.h" +#include "mac.h" + +/* + * Description: + * Test if all test bits on + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * byRegOfs - Offset of MAC Register + * byTestBits - Test bits + * Out: + * none + * + * Return Value: true if all test bits On; otherwise false + * + */ +bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits) +{ + unsigned char byData; + + VNSvInPortB(dwIoBase + byRegOfs, &byData); + return (byData & byTestBits) == byTestBits; +} + +/* + * Description: + * Test if all test bits off + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * byRegOfs - Offset of MAC Register + * byTestBits - Test bits + * Out: + * none + * + * Return Value: true if all test bits Off; otherwise false + * + */ +bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits) +{ + unsigned char byData; + + VNSvInPortB(dwIoBase + byRegOfs, &byData); + return !(byData & byTestBits); +} + +/* + * Description: + * Test if MAC interrupt disable + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if interrupt is disable; otherwise false + * + */ +bool MACbIsIntDisable(void __iomem *dwIoBase) +{ + unsigned long dwData; + + VNSvInPortD(dwIoBase + MAC_REG_IMR, &dwData); + if (dwData != 0) + return false; + + return true; +} + +/* + * Description: + * Set 802.11 Short Retry Limit + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * byRetryLimit- Retry Limit + * Out: + * none + * + * Return Value: none + * + */ +void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit) +{ + /* set SRT */ + VNSvOutPortB(dwIoBase + MAC_REG_SRT, byRetryLimit); +} + + +/* + * Description: + * Set 802.11 Long Retry Limit + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * byRetryLimit- Retry Limit + * Out: + * none + * + * Return Value: none + * + */ +void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit) +{ + /* set LRT */ + VNSvOutPortB(dwIoBase + MAC_REG_LRT, byRetryLimit); +} + +/* + * Description: + * Set MAC Loopback mode + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * byLoopbackMode - Loopback Mode + * Out: + * none + * + * Return Value: none + * + */ +void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode) +{ + unsigned char byOrgValue; + + ASSERT(byLoopbackMode < 3); + byLoopbackMode <<= 6; + /* set TCR */ + VNSvInPortB(dwIoBase + MAC_REG_TEST, &byOrgValue); + byOrgValue = byOrgValue & 0x3F; + byOrgValue = byOrgValue | byLoopbackMode; + VNSvOutPortB(dwIoBase + MAC_REG_TEST, byOrgValue); +} + +/* + * Description: + * Save MAC registers to context buffer + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * pbyCxtBuf - Context buffer + * + * Return Value: none + * + */ +void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf) +{ + int ii; + + /* read page0 register */ + for (ii = 0; ii < MAC_MAX_CONTEXT_SIZE_PAGE0; ii++) + VNSvInPortB((dwIoBase + ii), (pbyCxtBuf + ii)); + + MACvSelectPage1(dwIoBase); + + /* read page1 register */ + for (ii = 0; ii < MAC_MAX_CONTEXT_SIZE_PAGE1; ii++) + VNSvInPortB((dwIoBase + ii), (pbyCxtBuf + MAC_MAX_CONTEXT_SIZE_PAGE0 + ii)); + + MACvSelectPage0(dwIoBase); +} + +/* + * Description: + * Restore MAC registers from context buffer + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * pbyCxtBuf - Context buffer + * Out: + * none + * + * Return Value: none + * + */ +void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf) +{ + int ii; + + MACvSelectPage1(dwIoBase); + /* restore page1 */ + for (ii = 0; ii < MAC_MAX_CONTEXT_SIZE_PAGE1; ii++) + VNSvOutPortB((dwIoBase + ii), *(pbyCxtBuf + MAC_MAX_CONTEXT_SIZE_PAGE0 + ii)); + + MACvSelectPage0(dwIoBase); + + /* restore RCR,TCR,IMR... */ + for (ii = MAC_REG_RCR; ii < MAC_REG_ISR; ii++) + VNSvOutPortB(dwIoBase + ii, *(pbyCxtBuf + ii)); + + /* restore MAC Config. */ + for (ii = MAC_REG_LRT; ii < MAC_REG_PAGE1SEL; ii++) + VNSvOutPortB(dwIoBase + ii, *(pbyCxtBuf + ii)); + + VNSvOutPortB(dwIoBase + MAC_REG_CFG, *(pbyCxtBuf + MAC_REG_CFG)); + + /* restore PS Config. */ + for (ii = MAC_REG_PSCFG; ii < MAC_REG_BBREGCTL; ii++) + VNSvOutPortB(dwIoBase + ii, *(pbyCxtBuf + ii)); + + /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */ + VNSvOutPortD(dwIoBase + MAC_REG_TXDMAPTR0, *(unsigned long *)(pbyCxtBuf + MAC_REG_TXDMAPTR0)); + VNSvOutPortD(dwIoBase + MAC_REG_AC0DMAPTR, *(unsigned long *)(pbyCxtBuf + MAC_REG_AC0DMAPTR)); + VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, *(unsigned long *)(pbyCxtBuf + MAC_REG_BCNDMAPTR)); + + VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR0, *(unsigned long *)(pbyCxtBuf + MAC_REG_RXDMAPTR0)); + + VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR1, *(unsigned long *)(pbyCxtBuf + MAC_REG_RXDMAPTR1)); +} + +/* + * Description: + * Software Reset MAC + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if Reset Success; otherwise false + * + */ +bool MACbSoftwareReset(void __iomem *dwIoBase) +{ + unsigned char byData; + unsigned short ww; + + /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */ + VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, 0x01); + + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData); + if (!(byData & HOSTCR_SOFTRST)) + break; + } + if (ww == W_MAX_TIMEOUT) + return false; + return true; +} + +/* + * Description: + * save some important register's value, then do reset, then restore register's value + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if success; otherwise false + * + */ +bool MACbSafeSoftwareReset(void __iomem *dwIoBase) +{ + unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0+MAC_MAX_CONTEXT_SIZE_PAGE1]; + bool bRetVal; + + /* PATCH.... + * save some important register's value, then do + * reset, then restore register's value + */ + /* save MAC context */ + MACvSaveContext(dwIoBase, abyTmpRegData); + /* do reset */ + bRetVal = MACbSoftwareReset(dwIoBase); + /* restore MAC context, except CR0 */ + MACvRestoreContext(dwIoBase, abyTmpRegData); + + return bRetVal; +} + +/* + * Description: + * Turn Off MAC Rx + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if success; otherwise false + * + */ +bool MACbSafeRxOff(void __iomem *dwIoBase) +{ + unsigned short ww; + unsigned long dwData; + unsigned char byData; + + /* turn off wow temp for turn off Rx safely */ + + /* Clear RX DMA0,1 */ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_CLRRUN); + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_CLRRUN); + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); + if (!(dwData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x10); + pr_debug(" DBG_PORT80(0x10)\n"); + return false; + } + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); + if (!(dwData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x11); + pr_debug(" DBG_PORT80(0x11)\n"); + return false; + } + + /* try to safe shutdown RX */ + MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON); + /* W_MAX_TIMEOUT is the timeout period */ + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData); + if (!(byData & HOSTCR_RXONST)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x12); + pr_debug(" DBG_PORT80(0x12)\n"); + return false; + } + return true; +} + +/* + * Description: + * Turn Off MAC Tx + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if success; otherwise false + * + */ +bool MACbSafeTxOff(void __iomem *dwIoBase) +{ + unsigned short ww; + unsigned long dwData; + unsigned char byData; + + /* Clear TX DMA */ + /* Tx0 */ + VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_CLRRUN); + /* AC0 */ + VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_CLRRUN); + + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); + if (!(dwData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x20); + pr_debug(" DBG_PORT80(0x20)\n"); + return false; + } + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); + if (!(dwData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x21); + pr_debug(" DBG_PORT80(0x21)\n"); + return false; + } + + /* try to safe shutdown TX */ + MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON); + + /* W_MAX_TIMEOUT is the timeout period */ + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData); + if (!(byData & HOSTCR_TXONST)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x24); + pr_debug(" DBG_PORT80(0x24)\n"); + return false; + } + return true; +} + +/* + * Description: + * Stop MAC function + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if success; otherwise false + * + */ +bool MACbSafeStop(void __iomem *dwIoBase) +{ + MACvRegBitsOff(dwIoBase, MAC_REG_TCR, TCR_AUTOBCNTX); + + if (!MACbSafeRxOff(dwIoBase)) { + DBG_PORT80(0xA1); + pr_debug(" MACbSafeRxOff == false)\n"); + MACbSafeSoftwareReset(dwIoBase); + return false; + } + if (!MACbSafeTxOff(dwIoBase)) { + DBG_PORT80(0xA2); + pr_debug(" MACbSafeTxOff == false)\n"); + MACbSafeSoftwareReset(dwIoBase); + return false; + } + + MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_MACEN); + + return true; +} + +/* + * Description: + * Shut Down MAC + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: true if success; otherwise false + * + */ +bool MACbShutdown(void __iomem *dwIoBase) +{ + /* disable MAC IMR */ + MACvIntDisable(dwIoBase); + MACvSetLoopbackMode(dwIoBase, MAC_LB_INTERNAL); + /* stop the adapter */ + if (!MACbSafeStop(dwIoBase)) { + MACvSetLoopbackMode(dwIoBase, MAC_LB_NONE); + return false; + } + MACvSetLoopbackMode(dwIoBase, MAC_LB_NONE); + return true; +} + +/* + * Description: + * Initialize MAC + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * Out: + * none + * + * Return Value: none + * + */ +void MACvInitialize(void __iomem *dwIoBase) +{ + /* clear sticky bits */ + MACvClearStckDS(dwIoBase); + /* disable force PME-enable */ + VNSvOutPortB(dwIoBase + MAC_REG_PMC1, PME_OVR); + /* only 3253 A */ + + /* do reset */ + MACbSoftwareReset(dwIoBase); + + /* reset TSF counter */ + VNSvOutPortB(dwIoBase + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST); + /* enable TSF counter */ + VNSvOutPortB(dwIoBase + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); +} + +/* + * Description: + * Set the chip with current rx descriptor address + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * dwCurrDescAddr - Descriptor Address + * Out: + * none + * + * Return Value: none + * + */ +void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr) +{ + unsigned short ww; + unsigned char byData; + unsigned char byOrgDMACtl; + + VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byOrgDMACtl); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0+2, DMACTL_RUN); + + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL0, &byData); + if (!(byData & DMACTL_RUN)) + break; + } + + if (ww == W_MAX_TIMEOUT) + DBG_PORT80(0x13); + + VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR0, dwCurrDescAddr); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); +} + +/* + * Description: + * Set the chip with current rx descriptor address + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * dwCurrDescAddr - Descriptor Address + * Out: + * none + * + * Return Value: none + * + */ +void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr) +{ + unsigned short ww; + unsigned char byData; + unsigned char byOrgDMACtl; + + VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byOrgDMACtl); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1+2, DMACTL_RUN); + + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_RXDMACTL1, &byData); + if (!(byData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) + DBG_PORT80(0x14); + + VNSvOutPortD(dwIoBase + MAC_REG_RXDMAPTR1, dwCurrDescAddr); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); + +} + +/* + * Description: + * Set the chip with current tx0 descriptor address + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * dwCurrDescAddr - Descriptor Address + * Out: + * none + * + * Return Value: none + * + */ +void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr) +{ + unsigned short ww; + unsigned char byData; + unsigned char byOrgDMACtl; + + VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byOrgDMACtl); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0+2, DMACTL_RUN); + + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_TXDMACTL0, &byData); + if (!(byData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) + DBG_PORT80(0x25); + + VNSvOutPortD(dwIoBase + MAC_REG_TXDMAPTR0, dwCurrDescAddr); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); +} + +/* + * Description: + * Set the chip with current AC0 descriptor address + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * dwCurrDescAddr - Descriptor Address + * Out: + * none + * + * Return Value: none + * + */ +/* TxDMA1 = AC0DMA */ +void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr) +{ + unsigned short ww; + unsigned char byData; + unsigned char byOrgDMACtl; + + VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byOrgDMACtl); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL+2, DMACTL_RUN); + + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_AC0DMACTL, &byData); + if (!(byData & DMACTL_RUN)) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x26); + pr_debug(" DBG_PORT80(0x26)\n"); + } + VNSvOutPortD(dwIoBase + MAC_REG_AC0DMAPTR, dwCurrDescAddr); + if (byOrgDMACtl & DMACTL_RUN) + VNSvOutPortB(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); +} + +void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase, unsigned long dwCurrDescAddr) +{ + if (iTxType == TYPE_AC0DMA) + MACvSetCurrAC0DescAddrEx(dwIoBase, dwCurrDescAddr); + else if (iTxType == TYPE_TXDMA0) + MACvSetCurrTx0DescAddrEx(dwIoBase, dwCurrDescAddr); +} + +/* + * Description: + * Micro Second Delay via MAC + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * uDelay - Delay time (timer resolution is 4 us) + * Out: + * none + * + * Return Value: none + * + */ +void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay) +{ + unsigned char byValue; + unsigned int uu, ii; + + VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0); + VNSvOutPortD(dwIoBase + MAC_REG_TMDATA0, uDelay); + VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, (TMCTL_TMD | TMCTL_TE)); + for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */ + for (uu = 0; uu < uDelay; uu++) { + VNSvInPortB(dwIoBase + MAC_REG_TMCTL0, &byValue); + if ((byValue == 0) || + (byValue & TMCTL_TSUSP)) { + VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0); + return; + } + } + } + VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0); +} + +/* + * Description: + * Micro Second One shot timer via MAC + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * uDelay - Delay time + * Out: + * none + * + * Return Value: none + * + */ +void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime) +{ + VNSvOutPortB(dwIoBase + MAC_REG_TMCTL1, 0); + VNSvOutPortD(dwIoBase + MAC_REG_TMDATA1, uDelayTime); + VNSvOutPortB(dwIoBase + MAC_REG_TMCTL1, (TMCTL_TMD | TMCTL_TE)); +} + +void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, unsigned long dwData) +{ + if (wOffset > 273) + return; + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset); + VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData); + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE); +} + +bool MACbPSWakeup(void __iomem *dwIoBase) +{ + unsigned char byOrgValue; + unsigned int ww; + /* Read PSCTL */ + if (MACbIsRegBitsOff(dwIoBase, MAC_REG_PSCTL, PSCTL_PS)) + return true; + + /* Disable PS */ + MACvRegBitsOff(dwIoBase, MAC_REG_PSCTL, PSCTL_PSEN); + + /* Check if SyncFlushOK */ + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortB(dwIoBase + MAC_REG_PSCTL, &byOrgValue); + if (byOrgValue & PSCTL_WAKEDONE) + break; + } + if (ww == W_MAX_TIMEOUT) { + DBG_PORT80(0x36); + pr_debug(" DBG_PORT80(0x33)\n"); + return false; + } + return true; +} + +/* + * Description: + * Set the Key by MISCFIFO + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * + * Out: + * none + * + * Return Value: none + * + */ + +void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, + unsigned int uKeyIdx, unsigned char *pbyAddr, u32 *pdwKey, unsigned char byLocalID) +{ + unsigned short wOffset; + u32 dwData; + int ii; + + if (byLocalID <= 1) + return; + + pr_debug("MACvSetKeyEntry\n"); + wOffset = MISCFIFO_KEYETRY0; + wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); + + dwData = 0; + dwData |= wKeyCtl; + dwData <<= 16; + dwData |= MAKEWORD(*(pbyAddr+4), *(pbyAddr+5)); + pr_debug("1. wOffset: %d, Data: %X, KeyCtl:%X\n", + wOffset, dwData, wKeyCtl); + + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset); + VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData); + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE); + wOffset++; + + dwData = 0; + dwData |= *(pbyAddr+3); + dwData <<= 8; + dwData |= *(pbyAddr+2); + dwData <<= 8; + dwData |= *(pbyAddr+1); + dwData <<= 8; + dwData |= *(pbyAddr+0); + pr_debug("2. wOffset: %d, Data: %X\n", wOffset, dwData); + + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset); + VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, dwData); + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE); + wOffset++; + + wOffset += (uKeyIdx * 4); + for (ii = 0; ii < 4; ii++) { + /* always push 128 bits */ + pr_debug("3.(%d) wOffset: %d, Data: %X\n", + ii, wOffset+ii, *pdwKey); + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset+ii); + VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, *pdwKey++); + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE); + } +} + +/* + * Description: + * Disable the Key Entry by MISCFIFO + * + * Parameters: + * In: + * dwIoBase - Base Address for MAC + * + * Out: + * none + * + * Return Value: none + * + */ +void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx) +{ + unsigned short wOffset; + + wOffset = MISCFIFO_KEYETRY0; + wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); + + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, wOffset); + VNSvOutPortD(dwIoBase + MAC_REG_MISCFFDATA, 0); + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE); +} diff --git a/kernel/drivers/staging/vt6655/mac.h b/kernel/drivers/staging/vt6655/mac.h new file mode 100644 index 000000000..8e0200a78 --- /dev/null +++ b/kernel/drivers/staging/vt6655/mac.h @@ -0,0 +1,946 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: mac.h + * + * Purpose: MAC routines + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + * Revision History: + * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. + * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. + * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD + */ + +#ifndef __MAC_H__ +#define __MAC_H__ + +#include "tmacro.h" +#include "upc.h" + +/*--------------------- Export Definitions -------------------------*/ +/* Registers in the MAC */ +#define MAC_MAX_CONTEXT_SIZE_PAGE0 256 +#define MAC_MAX_CONTEXT_SIZE_PAGE1 128 + +/* Registers not related to 802.11b */ +#define MAC_REG_BCFG0 0x00 +#define MAC_REG_BCFG1 0x01 +#define MAC_REG_FCR0 0x02 +#define MAC_REG_FCR1 0x03 +#define MAC_REG_BISTCMD 0x04 +#define MAC_REG_BISTSR0 0x05 +#define MAC_REG_BISTSR1 0x06 +#define MAC_REG_BISTSR2 0x07 +#define MAC_REG_I2MCSR 0x08 +#define MAC_REG_I2MTGID 0x09 +#define MAC_REG_I2MTGAD 0x0A +#define MAC_REG_I2MCFG 0x0B +#define MAC_REG_I2MDIPT 0x0C +#define MAC_REG_I2MDOPT 0x0E +#define MAC_REG_PMC0 0x10 +#define MAC_REG_PMC1 0x11 +#define MAC_REG_STICKHW 0x12 +#define MAC_REG_LOCALID 0x14 +#define MAC_REG_TESTCFG 0x15 +#define MAC_REG_JUMPER0 0x16 +#define MAC_REG_JUMPER1 0x17 +#define MAC_REG_TMCTL0 0x18 +#define MAC_REG_TMCTL1 0x19 +#define MAC_REG_TMDATA0 0x1C + +/* MAC Parameter related */ +#define MAC_REG_LRT 0x20 +#define MAC_REG_SRT 0x21 +#define MAC_REG_SIFS 0x22 +#define MAC_REG_DIFS 0x23 +#define MAC_REG_EIFS 0x24 +#define MAC_REG_SLOT 0x25 +#define MAC_REG_BI 0x26 +#define MAC_REG_CWMAXMIN0 0x28 +#define MAC_REG_LINKOFFTOTM 0x2A +#define MAC_REG_SWTMOT 0x2B +#define MAC_REG_MIBCNTR 0x2C +#define MAC_REG_RTSOKCNT 0x2C +#define MAC_REG_RTSFAILCNT 0x2D +#define MAC_REG_ACKFAILCNT 0x2E +#define MAC_REG_FCSERRCNT 0x2F + +/* TSF Related */ +#define MAC_REG_TSFCNTR 0x30 +#define MAC_REG_NEXTTBTT 0x38 +#define MAC_REG_TSFOFST 0x40 +#define MAC_REG_TFTCTL 0x48 + +/* WMAC Control/Status Related */ +#define MAC_REG_ENCFG 0x4C +#define MAC_REG_PAGE1SEL 0x4F +#define MAC_REG_CFG 0x50 +#define MAC_REG_TEST 0x52 +#define MAC_REG_HOSTCR 0x54 +#define MAC_REG_MACCR 0x55 +#define MAC_REG_RCR 0x56 +#define MAC_REG_TCR 0x57 +#define MAC_REG_IMR 0x58 +#define MAC_REG_ISR 0x5C + +/* Power Saving Related */ +#define MAC_REG_PSCFG 0x60 +#define MAC_REG_PSCTL 0x61 +#define MAC_REG_PSPWRSIG 0x62 +#define MAC_REG_BBCR13 0x63 +#define MAC_REG_AIDATIM 0x64 +#define MAC_REG_PWBT 0x66 +#define MAC_REG_WAKEOKTMR 0x68 +#define MAC_REG_CALTMR 0x69 +#define MAC_REG_SYNSPACCNT 0x6A +#define MAC_REG_WAKSYNOPT 0x6B + +/* Baseband/IF Control Group */ +#define MAC_REG_BBREGCTL 0x6C +#define MAC_REG_CHANNEL 0x6D +#define MAC_REG_BBREGADR 0x6E +#define MAC_REG_BBREGDATA 0x6F +#define MAC_REG_IFREGCTL 0x70 +#define MAC_REG_IFDATA 0x71 +#define MAC_REG_ITRTMSET 0x74 +#define MAC_REG_PAPEDELAY 0x77 +#define MAC_REG_SOFTPWRCTL 0x78 +#define MAC_REG_GPIOCTL0 0x7A +#define MAC_REG_GPIOCTL1 0x7B + +/* MAC DMA Related Group */ +#define MAC_REG_TXDMACTL0 0x7C +#define MAC_REG_TXDMAPTR0 0x80 +#define MAC_REG_AC0DMACTL 0x84 +#define MAC_REG_AC0DMAPTR 0x88 +#define MAC_REG_BCNDMACTL 0x8C +#define MAC_REG_BCNDMAPTR 0x90 +#define MAC_REG_RXDMACTL0 0x94 +#define MAC_REG_RXDMAPTR0 0x98 +#define MAC_REG_RXDMACTL1 0x9C +#define MAC_REG_RXDMAPTR1 0xA0 +#define MAC_REG_SYNCDMACTL 0xA4 +#define MAC_REG_SYNCDMAPTR 0xA8 +#define MAC_REG_ATIMDMACTL 0xAC +#define MAC_REG_ATIMDMAPTR 0xB0 + +/* MiscFF PIO related */ +#define MAC_REG_MISCFFNDEX 0xB4 +#define MAC_REG_MISCFFCTL 0xB6 +#define MAC_REG_MISCFFDATA 0xB8 + +/* Extend SW Timer */ +#define MAC_REG_TMDATA1 0xBC + +/* WOW Related Group */ +#define MAC_REG_WAKEUPEN0 0xC0 +#define MAC_REG_WAKEUPEN1 0xC1 +#define MAC_REG_WAKEUPSR0 0xC2 +#define MAC_REG_WAKEUPSR1 0xC3 +#define MAC_REG_WAKE128_0 0xC4 +#define MAC_REG_WAKE128_1 0xD4 +#define MAC_REG_WAKE128_2 0xE4 +#define MAC_REG_WAKE128_3 0xF4 + +/************** Page 1 ******************/ +#define MAC_REG_CRC_128_0 0x04 +#define MAC_REG_CRC_128_1 0x06 +#define MAC_REG_CRC_128_2 0x08 +#define MAC_REG_CRC_128_3 0x0A + +/* MAC Configuration Group */ +#define MAC_REG_PAR0 0x0C +#define MAC_REG_PAR4 0x10 +#define MAC_REG_BSSID0 0x14 +#define MAC_REG_BSSID4 0x18 +#define MAC_REG_MAR0 0x1C +#define MAC_REG_MAR4 0x20 + +/* MAC RSPPKT INFO Group */ +#define MAC_REG_RSPINF_B_1 0x24 +#define MAC_REG_RSPINF_B_2 0x28 +#define MAC_REG_RSPINF_B_5 0x2C +#define MAC_REG_RSPINF_B_11 0x30 +#define MAC_REG_RSPINF_A_6 0x34 +#define MAC_REG_RSPINF_A_9 0x36 +#define MAC_REG_RSPINF_A_12 0x38 +#define MAC_REG_RSPINF_A_18 0x3A +#define MAC_REG_RSPINF_A_24 0x3C +#define MAC_REG_RSPINF_A_36 0x3E +#define MAC_REG_RSPINF_A_48 0x40 +#define MAC_REG_RSPINF_A_54 0x42 +#define MAC_REG_RSPINF_A_72 0x44 + +/* 802.11h relative */ +#define MAC_REG_QUIETINIT 0x60 +#define MAC_REG_QUIETGAP 0x62 +#define MAC_REG_QUIETDUR 0x64 +#define MAC_REG_MSRCTL 0x66 +#define MAC_REG_MSRBBSTS 0x67 +#define MAC_REG_MSRSTART 0x68 +#define MAC_REG_MSRDURATION 0x70 +#define MAC_REG_CCAFRACTION 0x72 +#define MAC_REG_PWRCCK 0x73 +#define MAC_REG_PWROFDM 0x7C + +/* Bits in the BCFG0 register */ +#define BCFG0_PERROFF 0x40 +#define BCFG0_MRDMDIS 0x20 +#define BCFG0_MRDLDIS 0x10 +#define BCFG0_MWMEN 0x08 +#define BCFG0_VSERREN 0x02 +#define BCFG0_LATMEN 0x01 + +/* Bits in the BCFG1 register */ +#define BCFG1_CFUNOPT 0x80 +#define BCFG1_CREQOPT 0x40 +#define BCFG1_DMA8 0x10 +#define BCFG1_ARBITOPT 0x08 +#define BCFG1_PCIMEN 0x04 +#define BCFG1_MIOEN 0x02 +#define BCFG1_CISDLYEN 0x01 + +/* Bits in RAMBIST registers */ +#define BISTCMD_TSTPAT5 0x00 +#define BISTCMD_TSTPATA 0x80 +#define BISTCMD_TSTERR 0x20 +#define BISTCMD_TSTPATF 0x18 +#define BISTCMD_TSTPAT0 0x10 +#define BISTCMD_TSTMODE 0x04 +#define BISTCMD_TSTITTX 0x03 +#define BISTCMD_TSTATRX 0x02 +#define BISTCMD_TSTATTX 0x01 +#define BISTCMD_TSTRX 0x00 +#define BISTSR0_BISTGO 0x01 +#define BISTSR1_TSTSR 0x01 +#define BISTSR2_CMDPRTEN 0x02 +#define BISTSR2_RAMTSTEN 0x01 + +/* Bits in the I2MCFG EEPROM register */ +#define I2MCFG_BOUNDCTL 0x80 +#define I2MCFG_WAITCTL 0x20 +#define I2MCFG_SCLOECTL 0x10 +#define I2MCFG_WBUSYCTL 0x08 +#define I2MCFG_NORETRY 0x04 +#define I2MCFG_I2MLDSEQ 0x02 +#define I2MCFG_I2CMFAST 0x01 + +/* Bits in the I2MCSR EEPROM register */ +#define I2MCSR_EEMW 0x80 +#define I2MCSR_EEMR 0x40 +#define I2MCSR_AUTOLD 0x08 +#define I2MCSR_NACK 0x02 +#define I2MCSR_DONE 0x01 + +/* Bits in the PMC1 register */ +#define SPS_RST 0x80 +#define PCISTIKY 0x40 +#define PME_OVR 0x02 + +/* Bits in the STICKYHW register */ +#define STICKHW_DS1_SHADOW 0x02 +#define STICKHW_DS0_SHADOW 0x01 + +/* Bits in the TMCTL register */ +#define TMCTL_TSUSP 0x04 +#define TMCTL_TMD 0x02 +#define TMCTL_TE 0x01 + +/* Bits in the TFTCTL register */ +#define TFTCTL_HWUTSF 0x80 +#define TFTCTL_TBTTSYNC 0x40 +#define TFTCTL_HWUTSFEN 0x20 +#define TFTCTL_TSFCNTRRD 0x10 +#define TFTCTL_TBTTSYNCEN 0x08 +#define TFTCTL_TSFSYNCEN 0x04 +#define TFTCTL_TSFCNTRST 0x02 +#define TFTCTL_TSFCNTREN 0x01 + +/* Bits in the EnhanceCFG register */ +#define EnCFG_BarkerPream 0x00020000 +#define EnCFG_NXTBTTCFPSTR 0x00010000 +#define EnCFG_BcnSusClr 0x00000200 +#define EnCFG_BcnSusInd 0x00000100 +#define EnCFG_CFP_ProtectEn 0x00000040 +#define EnCFG_ProtectMd 0x00000020 +#define EnCFG_HwParCFP 0x00000010 +#define EnCFG_CFNULRSP 0x00000004 +#define EnCFG_BBType_MASK 0x00000003 +#define EnCFG_BBType_g 0x00000002 +#define EnCFG_BBType_b 0x00000001 +#define EnCFG_BBType_a 0x00000000 + +/* Bits in the Page1Sel register */ +#define PAGE1_SEL 0x01 + +/* Bits in the CFG register */ +#define CFG_TKIPOPT 0x80 +#define CFG_RXDMAOPT 0x40 +#define CFG_TMOT_SW 0x20 +#define CFG_TMOT_HWLONG 0x10 +#define CFG_TMOT_HW 0x00 +#define CFG_CFPENDOPT 0x08 +#define CFG_BCNSUSEN 0x04 +#define CFG_NOTXTIMEOUT 0x02 +#define CFG_NOBUFOPT 0x01 + +/* Bits in the TEST register */ +#define TEST_LBEXT 0x80 +#define TEST_LBINT 0x40 +#define TEST_LBNONE 0x00 +#define TEST_SOFTINT 0x20 +#define TEST_CONTTX 0x10 +#define TEST_TXPE 0x08 +#define TEST_NAVDIS 0x04 +#define TEST_NOCTS 0x02 +#define TEST_NOACK 0x01 + +/* Bits in the HOSTCR register */ +#define HOSTCR_TXONST 0x80 +#define HOSTCR_RXONST 0x40 +#define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */ +#define HOSTCR_AP 0x10 /* Port Type 1 = AP */ +#define HOSTCR_TXON 0x08 /* 0000 1000 */ +#define HOSTCR_RXON 0x04 /* 0000 0100 */ +#define HOSTCR_MACEN 0x02 /* 0000 0010 */ +#define HOSTCR_SOFTRST 0x01 /* 0000 0001 */ + +/* Bits in the MACCR register */ +#define MACCR_SYNCFLUSHOK 0x04 +#define MACCR_SYNCFLUSH 0x02 +#define MACCR_CLRNAV 0x01 + +/* Bits in the MAC_REG_GPIOCTL0 register */ +#define LED_ACTSET 0x01 +#define LED_RFOFF 0x02 +#define LED_NOCONNECT 0x04 + +/* Bits in the RCR register */ +#define RCR_SSID 0x80 +#define RCR_RXALLTYPE 0x40 +#define RCR_UNICAST 0x20 +#define RCR_BROADCAST 0x10 +#define RCR_MULTICAST 0x08 +#define RCR_WPAERR 0x04 +#define RCR_ERRCRC 0x02 +#define RCR_BSSID 0x01 + +/* Bits in the TCR register */ +#define TCR_SYNCDCFOPT 0x02 +#define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */ + +/* Bits in the IMR register */ +#define IMR_MEASURESTART 0x80000000 +#define IMR_QUIETSTART 0x20000000 +#define IMR_RADARDETECT 0x10000000 +#define IMR_MEASUREEND 0x08000000 +#define IMR_SOFTTIMER1 0x00200000 +#define IMR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ +#define IMR_RXNOBUF 0x00000800 +#define IMR_MIBNEARFULL 0x00000400 +#define IMR_SOFTINT 0x00000200 +#define IMR_FETALERR 0x00000100 +#define IMR_WATCHDOG 0x00000080 +#define IMR_SOFTTIMER 0x00000040 +#define IMR_GPIO 0x00000020 +#define IMR_TBTT 0x00000010 +#define IMR_RXDMA0 0x00000008 +#define IMR_BNTX 0x00000004 +#define IMR_AC0DMA 0x00000002 +#define IMR_TXDMA0 0x00000001 + +/* Bits in the ISR register */ +#define ISR_MEASURESTART 0x80000000 +#define ISR_QUIETSTART 0x20000000 +#define ISR_RADARDETECT 0x10000000 +#define ISR_MEASUREEND 0x08000000 +#define ISR_SOFTTIMER1 0x00200000 +#define ISR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ +#define ISR_RXNOBUF 0x00000800 /* 0000 0000 0000 1000 0000 0000 */ +#define ISR_MIBNEARFULL 0x00000400 /* 0000 0000 0000 0100 0000 0000 */ +#define ISR_SOFTINT 0x00000200 +#define ISR_FETALERR 0x00000100 +#define ISR_WATCHDOG 0x00000080 +#define ISR_SOFTTIMER 0x00000040 +#define ISR_GPIO 0x00000020 +#define ISR_TBTT 0x00000010 +#define ISR_RXDMA0 0x00000008 +#define ISR_BNTX 0x00000004 +#define ISR_AC0DMA 0x00000002 +#define ISR_TXDMA0 0x00000001 + +/* Bits in the PSCFG register */ +#define PSCFG_PHILIPMD 0x40 +#define PSCFG_WAKECALEN 0x20 +#define PSCFG_WAKETMREN 0x10 +#define PSCFG_BBPSPROG 0x08 +#define PSCFG_WAKESYN 0x04 +#define PSCFG_SLEEPSYN 0x02 +#define PSCFG_AUTOSLEEP 0x01 + +/* Bits in the PSCTL register */ +#define PSCTL_WAKEDONE 0x20 +#define PSCTL_PS 0x10 +#define PSCTL_GO2DOZE 0x08 +#define PSCTL_LNBCN 0x04 +#define PSCTL_ALBCN 0x02 +#define PSCTL_PSEN 0x01 + +/* Bits in the PSPWSIG register */ +#define PSSIG_WPE3 0x80 +#define PSSIG_WPE2 0x40 +#define PSSIG_WPE1 0x20 +#define PSSIG_WRADIOPE 0x10 +#define PSSIG_SPE3 0x08 +#define PSSIG_SPE2 0x04 +#define PSSIG_SPE1 0x02 +#define PSSIG_SRADIOPE 0x01 + +/* Bits in the BBREGCTL register */ +#define BBREGCTL_DONE 0x04 +#define BBREGCTL_REGR 0x02 +#define BBREGCTL_REGW 0x01 + +/* Bits in the IFREGCTL register */ +#define IFREGCTL_DONE 0x04 +#define IFREGCTL_IFRF 0x02 +#define IFREGCTL_REGW 0x01 + +/* Bits in the SOFTPWRCTL register */ +#define SOFTPWRCTL_RFLEOPT 0x0800 +#define SOFTPWRCTL_TXPEINV 0x0200 +#define SOFTPWRCTL_SWPECTI 0x0100 +#define SOFTPWRCTL_SWPAPE 0x0020 +#define SOFTPWRCTL_SWCALEN 0x0010 +#define SOFTPWRCTL_SWRADIO_PE 0x0008 +#define SOFTPWRCTL_SWPE2 0x0004 +#define SOFTPWRCTL_SWPE1 0x0002 +#define SOFTPWRCTL_SWPE3 0x0001 + +/* Bits in the GPIOCTL1 register */ +#define GPIO1_DATA1 0x20 +#define GPIO1_MD1 0x10 +#define GPIO1_DATA0 0x02 +#define GPIO1_MD0 0x01 + +/* Bits in the DMACTL register */ +#define DMACTL_CLRRUN 0x00080000 +#define DMACTL_RUN 0x00000008 +#define DMACTL_WAKE 0x00000004 +#define DMACTL_DEAD 0x00000002 +#define DMACTL_ACTIVE 0x00000001 + +/* Bits in the RXDMACTL0 register */ +#define RX_PERPKT 0x00000100 +#define RX_PERPKTCLR 0x01000000 + +/* Bits in the BCNDMACTL register */ +#define BEACON_READY 0x01 + +/* Bits in the MISCFFCTL register */ +#define MISCFFCTL_WRITE 0x0001 + +/* Bits in WAKEUPEN0 */ +#define WAKEUPEN0_DIRPKT 0x10 +#define WAKEUPEN0_LINKOFF 0x08 +#define WAKEUPEN0_ATIMEN 0x04 +#define WAKEUPEN0_TIMEN 0x02 +#define WAKEUPEN0_MAGICEN 0x01 + +/* Bits in WAKEUPEN1 */ +#define WAKEUPEN1_128_3 0x08 +#define WAKEUPEN1_128_2 0x04 +#define WAKEUPEN1_128_1 0x02 +#define WAKEUPEN1_128_0 0x01 + +/* Bits in WAKEUPSR0 */ +#define WAKEUPSR0_DIRPKT 0x10 +#define WAKEUPSR0_LINKOFF 0x08 +#define WAKEUPSR0_ATIMEN 0x04 +#define WAKEUPSR0_TIMEN 0x02 +#define WAKEUPSR0_MAGICEN 0x01 + +/* Bits in WAKEUPSR1 */ +#define WAKEUPSR1_128_3 0x08 +#define WAKEUPSR1_128_2 0x04 +#define WAKEUPSR1_128_1 0x02 +#define WAKEUPSR1_128_0 0x01 + +/* Bits in the MAC_REG_GPIOCTL register */ +#define GPIO0_MD 0x01 +#define GPIO0_DATA 0x02 +#define GPIO0_INTMD 0x04 +#define GPIO1_MD 0x10 +#define GPIO1_DATA 0x20 + +/* Bits in the MSRCTL register */ +#define MSRCTL_FINISH 0x80 +#define MSRCTL_READY 0x40 +#define MSRCTL_RADARDETECT 0x20 +#define MSRCTL_EN 0x10 +#define MSRCTL_QUIETTXCHK 0x08 +#define MSRCTL_QUIETRPT 0x04 +#define MSRCTL_QUIETINT 0x02 +#define MSRCTL_QUIETEN 0x01 + +/* Bits in the MSRCTL1 register */ +#define MSRCTL1_TXPWR 0x08 +#define MSRCTL1_CSAPAREN 0x04 +#define MSRCTL1_TXPAUSE 0x01 + +/* Loopback mode */ +#define MAC_LB_EXT 0x02 +#define MAC_LB_INTERNAL 0x01 +#define MAC_LB_NONE 0x00 + +#define Default_BI 0x200 + +/* MiscFIFO Offset */ +#define MISCFIFO_KEYETRY0 32 +#define MISCFIFO_KEYENTRYSIZE 22 +#define MISCFIFO_SYNINFO_IDX 10 +#define MISCFIFO_SYNDATA_IDX 11 +#define MISCFIFO_SYNDATASIZE 21 + +/* enabled mask value of irq */ +#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \ + IMR_RXDMA1 | \ + IMR_RXNOBUF | \ + IMR_MIBNEARFULL | \ + IMR_SOFTINT | \ + IMR_FETALERR | \ + IMR_WATCHDOG | \ + IMR_SOFTTIMER | \ + IMR_GPIO | \ + IMR_TBTT | \ + IMR_RXDMA0 | \ + IMR_BNTX | \ + IMR_AC0DMA | \ + IMR_TXDMA0) + +/* max time out delay time */ +#define W_MAX_TIMEOUT 0xFFF0U + +/* wait time within loop */ +#define CB_DELAY_LOOP_WAIT 10 /* 10ms */ + +/* revision id */ +#define REV_ID_VT3253_A0 0x00 +#define REV_ID_VT3253_A1 0x01 +#define REV_ID_VT3253_B0 0x08 +#define REV_ID_VT3253_B1 0x09 + +/*--------------------- Export Types ------------------------------*/ + +/*--------------------- Export Macros ------------------------------*/ + +#define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \ +do { \ + unsigned char byData; \ + VNSvInPortB(dwIoBase + byRegOfs, &byData); \ + VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ +} while (0) + +#define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \ +do { \ + unsigned short wData; \ + VNSvInPortW(dwIoBase + byRegOfs, &wData); \ + VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \ +} while (0) + +#define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ + VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \ +} while (0) + +#define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \ +do { \ + unsigned char byData; \ + VNSvInPortB(dwIoBase + byRegOfs, &byData); \ + byData &= byMask; \ + VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ +} while (0) + +#define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \ +do { \ + unsigned char byData; \ + VNSvInPortB(dwIoBase + byRegOfs, &byData); \ + VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \ +} while (0) + +#define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \ +do { \ + unsigned short wData; \ + VNSvInPortW(dwIoBase + byRegOfs, &wData); \ + VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \ +} while (0) + +#define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ + VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \ +} while (0) + +#define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \ + VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \ + (unsigned long *)pdwCurrDescAddr) + +#define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \ + VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \ + (unsigned long *)pdwCurrDescAddr) + +#define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \ + VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \ + (unsigned long *)pdwCurrDescAddr) + +#define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \ + VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \ + (unsigned long *)pdwCurrDescAddr) + +#define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \ + VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \ + (unsigned long *)pdwCurrDescAddr) + +#define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \ + VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \ + (unsigned long *)pdwCurrDescAddr) + +/* set the chip with current BCN tx descriptor address */ +#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \ + VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \ + dwCurrDescAddr) + +/* set the chip with current BCN length */ +#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \ + VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \ + wCurrBCNLength) + +#define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \ +do { \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ + VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \ + (unsigned char *)pbyEtherAddr); \ + VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ + pbyEtherAddr + 1); \ + VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ + pbyEtherAddr + 2); \ + VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ + pbyEtherAddr + 3); \ + VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ + pbyEtherAddr + 4); \ + VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ + pbyEtherAddr + 5); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ +} while (0) + +#define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \ +do { \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ + VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \ + *(pbyEtherAddr)); \ + VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ + *(pbyEtherAddr + 1)); \ + VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ + *(pbyEtherAddr + 2)); \ + VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ + *(pbyEtherAddr + 3)); \ + VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ + *(pbyEtherAddr + 4)); \ + VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ + *(pbyEtherAddr + 5)); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ +} while (0) + +#define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \ +do { \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ + VNSvInPortB(dwIoBase + MAC_REG_PAR0, \ + (unsigned char *)pbyEtherAddr); \ + VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \ + pbyEtherAddr + 1); \ + VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \ + pbyEtherAddr + 2); \ + VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \ + pbyEtherAddr + 3); \ + VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \ + pbyEtherAddr + 4); \ + VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \ + pbyEtherAddr + 5); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ +} while (0) + +#define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \ +do { \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \ + *pbyEtherAddr); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \ + *(pbyEtherAddr + 1)); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \ + *(pbyEtherAddr + 2)); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \ + *(pbyEtherAddr + 3)); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \ + *(pbyEtherAddr + 4)); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \ + *(pbyEtherAddr + 5)); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ +} while (0) + +#define MACvClearISR(dwIoBase) \ + VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE) + +#define MACvStart(dwIoBase) \ + VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \ + (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)) + +#define MACvRx0PerPktMode(dwIoBase) \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT) + +#define MACvRx0BufferFillMode(dwIoBase) \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR) + +#define MACvRx1PerPktMode(dwIoBase) \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT) + +#define MACvRx1BufferFillMode(dwIoBase) \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR) + +#define MACvRxOn(dwIoBase) \ + MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON) + +#define MACvReceive0(dwIoBase) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \ + if (dwData & DMACTL_RUN) \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \ + else \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \ +} while (0) + +#define MACvReceive1(dwIoBase) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \ + if (dwData & DMACTL_RUN) \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \ + else \ + VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \ +} while (0) + +#define MACvTxOn(dwIoBase) \ + MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON) + +#define MACvTransmit0(dwIoBase) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \ + if (dwData & DMACTL_RUN) \ + VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \ + else \ + VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \ +} while (0) + +#define MACvTransmitAC0(dwIoBase) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \ + if (dwData & DMACTL_RUN) \ + VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \ + else \ + VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \ +} while (0) + +#define MACvTransmitSYNC(dwIoBase) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \ + if (dwData & DMACTL_RUN) \ + VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \ + else \ + VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \ +} while (0) + +#define MACvTransmitATIM(dwIoBase) \ +do { \ + unsigned long dwData; \ + VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \ + if (dwData & DMACTL_RUN) \ + VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \ + else \ + VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \ +} while (0) + +#define MACvTransmitBCN(dwIoBase) \ + VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY) + +#define MACvClearStckDS(dwIoBase) \ +do { \ + unsigned char byOrgValue; \ + VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \ + byOrgValue = byOrgValue & 0xFC; \ + VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \ +} while (0) + +#define MACvReadISR(dwIoBase, pdwValue) \ + VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue) + +#define MACvWriteISR(dwIoBase, dwValue) \ + VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue) + +#define MACvIntEnable(dwIoBase, dwMask) \ + VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask) + +#define MACvIntDisable(dwIoBase) \ + VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0) + +#define MACvSelectPage0(dwIoBase) \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0) + +#define MACvSelectPage1(dwIoBase) \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1) + +#define MACvReadMIBCounter(dwIoBase, pdwCounter) \ + VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR, pdwCounter) + +#define MACvPwrEvntDisable(dwIoBase) \ + VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000) + +#define MACvEnableProtectMD(dwIoBase) \ +do { \ + unsigned long dwOrgValue; \ + VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \ + VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ +} while (0) + +#define MACvDisableProtectMD(dwIoBase) \ +do { \ + unsigned long dwOrgValue; \ + VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \ + VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ +} while (0) + +#define MACvEnableBarkerPreambleMd(dwIoBase) \ +do { \ + unsigned long dwOrgValue; \ + VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \ + VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ +} while (0) + +#define MACvDisableBarkerPreambleMd(dwIoBase) \ +do { \ + unsigned long dwOrgValue; \ + VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \ + VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ +} while (0) + +#define MACvSetBBType(dwIoBase, byTyp) \ +do { \ + unsigned long dwOrgValue; \ + VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \ + dwOrgValue = dwOrgValue | (unsigned long)byTyp; \ + VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ +} while (0) + +#define MACvReadATIMW(dwIoBase, pwCounter) \ + VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter) + +#define MACvWriteATIMW(dwIoBase, wCounter) \ + VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter) + +#define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \ +do { \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ + VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \ + VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ +} while (0) + +#define MACvGPIOIn(dwIoBase, pbyValue) \ + VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue) + +#define MACvSetRFLE_LatchBase(dwIoBase) \ + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT) + +bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs, + unsigned char byTestBits); +bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs, + unsigned char byTestBits); + +bool MACbIsIntDisable(void __iomem *dwIoBase); + +void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit); + +void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit); +void MACvGetLongRetryLimit(void __iomem *dwIoBase, + unsigned char *pbyRetryLimit); + +void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode); + +void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf); +void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf); + +bool MACbSoftwareReset(void __iomem *dwIoBase); +bool MACbSafeSoftwareReset(void __iomem *dwIoBase); +bool MACbSafeRxOff(void __iomem *dwIoBase); +bool MACbSafeTxOff(void __iomem *dwIoBase); +bool MACbSafeStop(void __iomem *dwIoBase); +bool MACbShutdown(void __iomem *dwIoBase); +void MACvInitialize(void __iomem *dwIoBase); +void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvSetCurrSyncDescAddrEx(void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvSetCurrATIMDescAddrEx(void __iomem *dwIoBase, + unsigned long dwCurrDescAddr); +void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay); +void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime); + +void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, + unsigned long dwData); + +bool MACbPSWakeup(void __iomem *dwIoBase); + +void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl, + unsigned int uEntryIdx, unsigned int uKeyIdx, + unsigned char *pbyAddr, u32 *pdwKey, + unsigned char byLocalID); +void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx); + +#endif /* __MAC_H__ */ diff --git a/kernel/drivers/staging/vt6655/mib.c b/kernel/drivers/staging/vt6655/mib.c new file mode 100644 index 000000000..d55c76202 --- /dev/null +++ b/kernel/drivers/staging/vt6655/mib.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: mib.c + * + * Purpose: Implement MIB Data Structure + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + * Functions: + * STAvUpdateIstStatCounter - Update ISR statistic counter + * STAvUpdate802_11Counter - Update 802.11 mib counter + * + * Revision History: + * + */ + +#include "mac.h" +#include "mib.h" + +/*--------------------- Static Classes ----------------------------*/ + +/*--------------------- Static Variables --------------------------*/ + +/*--------------------- Static Functions --------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +/* + * Description: Update Isr Statistic Counter + * + * Parameters: + * In: + * pStatistic - Pointer to Statistic Counter Data Structure + * wisr - Interrupt status + * Out: + * none + * + * Return Value: none + * + */ +void STAvUpdateIsrStatCounter(PSStatCounter pStatistic, unsigned long dwIsr) +{ + /**********************/ + /* ABNORMAL interrupt */ + /**********************/ + /* not any IMR bit invoke irq */ + + if (dwIsr == 0) { + pStatistic->ISRStat.dwIsrUnknown++; + return; + } + +/* Added by Kyle */ + if (dwIsr & ISR_TXDMA0) /* ISR, bit0 */ + pStatistic->ISRStat.dwIsrTx0OK++; /* TXDMA0 successful */ + + if (dwIsr & ISR_AC0DMA) /* ISR, bit1 */ + pStatistic->ISRStat.dwIsrAC0TxOK++; /* AC0DMA successful */ + + if (dwIsr & ISR_BNTX) /* ISR, bit2 */ + pStatistic->ISRStat.dwIsrBeaconTxOK++; /* BeaconTx successful */ + + if (dwIsr & ISR_RXDMA0) /* ISR, bit3 */ + pStatistic->ISRStat.dwIsrRx0OK++; /* Rx0 successful */ + + if (dwIsr & ISR_TBTT) /* ISR, bit4 */ + pStatistic->ISRStat.dwIsrTBTTInt++; /* TBTT successful */ + + if (dwIsr & ISR_SOFTTIMER) /* ISR, bit6 */ + pStatistic->ISRStat.dwIsrSTIMERInt++; + + if (dwIsr & ISR_WATCHDOG) /* ISR, bit7 */ + pStatistic->ISRStat.dwIsrWatchDog++; + + if (dwIsr & ISR_FETALERR) /* ISR, bit8 */ + pStatistic->ISRStat.dwIsrUnrecoverableError++; + + if (dwIsr & ISR_SOFTINT) /* ISR, bit9 */ + pStatistic->ISRStat.dwIsrSoftInterrupt++; /* software interrupt */ + + if (dwIsr & ISR_MIBNEARFULL) /* ISR, bit10 */ + pStatistic->ISRStat.dwIsrMIBNearfull++; + + if (dwIsr & ISR_RXNOBUF) /* ISR, bit11 */ + pStatistic->ISRStat.dwIsrRxNoBuf++; /* Rx No Buff */ + + if (dwIsr & ISR_RXDMA1) /* ISR, bit12 */ + pStatistic->ISRStat.dwIsrRx1OK++; /* Rx1 successful */ + + if (dwIsr & ISR_SOFTTIMER1) /* ISR, bit21 */ + pStatistic->ISRStat.dwIsrSTIMER1Int++; +} + +/* + * Description: Update 802.11 mib counter + * + * Parameters: + * In: + * p802_11Counter - Pointer to 802.11 mib counter + * pStatistic - Pointer to Statistic Counter Data Structure + * dwCounter - hardware counter for 802.11 mib + * Out: + * none + * + * Return Value: none + * + */ +void +STAvUpdate802_11Counter( + PSDot11Counters p802_11Counter, + PSStatCounter pStatistic, + unsigned long dwCounter +) +{ + p802_11Counter->RTSSuccessCount += (unsigned long long) (dwCounter & 0x000000ff); + p802_11Counter->RTSFailureCount += (unsigned long long) ((dwCounter & 0x0000ff00) >> 8); + p802_11Counter->ACKFailureCount += (unsigned long long) ((dwCounter & 0x00ff0000) >> 16); + p802_11Counter->FCSErrorCount += (unsigned long long) ((dwCounter & 0xff000000) >> 24); +} diff --git a/kernel/drivers/staging/vt6655/mib.h b/kernel/drivers/staging/vt6655/mib.h new file mode 100644 index 000000000..5cb59b8a1 --- /dev/null +++ b/kernel/drivers/staging/vt6655/mib.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: mib.h + * + * Purpose: Implement MIB Data Structure + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + */ + +#ifndef __MIB_H__ +#define __MIB_H__ + +#include "desc.h" + +// +// 802.11 counter +// + +typedef struct tagSDot11Counters { + unsigned long long RTSSuccessCount; + unsigned long long RTSFailureCount; + unsigned long long ACKFailureCount; + unsigned long long FCSErrorCount; +} SDot11Counters, *PSDot11Counters; + +// +// Custom counter +// +typedef struct tagSISRCounters { + unsigned long dwIsrTx0OK; + unsigned long dwIsrAC0TxOK; + unsigned long dwIsrBeaconTxOK; + unsigned long dwIsrRx0OK; + unsigned long dwIsrTBTTInt; + unsigned long dwIsrSTIMERInt; + unsigned long dwIsrWatchDog; + unsigned long dwIsrUnrecoverableError; + unsigned long dwIsrSoftInterrupt; + unsigned long dwIsrMIBNearfull; + unsigned long dwIsrRxNoBuf; + + unsigned long dwIsrUnknown; + + unsigned long dwIsrRx1OK; + unsigned long dwIsrSTIMER1Int; +} SISRCounters, *PSISRCounters; + +// +// statistic counter +// +typedef struct tagSStatCounter { + SISRCounters ISRStat; +} SStatCounter, *PSStatCounter; + +void STAvUpdateIsrStatCounter(PSStatCounter pStatistic, unsigned long dwIsr); + +void STAvUpdate802_11Counter( + PSDot11Counters p802_11Counter, + PSStatCounter pStatistic, + unsigned long dwCounter +); + +#endif // __MIB_H__ diff --git a/kernel/drivers/staging/vt6655/power.c b/kernel/drivers/staging/vt6655/power.c new file mode 100644 index 000000000..be3c4e949 --- /dev/null +++ b/kernel/drivers/staging/vt6655/power.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: power.c + * + * Purpose: Handles 802.11 power management functions + * + * Author: Lyndon Chen + * + * Date: July 17, 2002 + * + * Functions: + * PSvEnablePowerSaving - Enable Power Saving Mode + * PSvDiasblePowerSaving - Disable Power Saving Mode + * PSbConsiderPowerDown - Decide if we can Power Down + * PSvSendPSPOLL - Send PS-POLL packet + * PSbSendNullPacket - Send Null packet + * PSbIsNextTBTTWakeUp - Decide if we need to wake up at next Beacon + * + * Revision History: + * + */ + +#include "mac.h" +#include "device.h" +#include "power.h" +#include "card.h" + +/*--------------------- Static Definitions -------------------------*/ + +/*--------------------- Static Classes ----------------------------*/ + +/*--------------------- Static Functions --------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +/*+ + * + * Routine Description: + * Enable hw power saving functions + * + * Return Value: + * None. + * + -*/ + +void +PSvEnablePowerSaving( + void *hDeviceContext, + unsigned short wListenInterval +) +{ + struct vnt_private *pDevice = hDeviceContext; + u16 wAID = pDevice->current_aid | BIT(14) | BIT(15); + + /* set period of power up before TBTT */ + VNSvOutPortW(pDevice->PortOffset + MAC_REG_PWBT, C_PWBT); + if (pDevice->op_mode != NL80211_IFTYPE_ADHOC) { + /* set AID */ + VNSvOutPortW(pDevice->PortOffset + MAC_REG_AIDATIM, wAID); + } else { + /* set ATIM Window */ +#if 0 /* TODO atim window */ + MACvWriteATIMW(pDevice->PortOffset, pMgmt->wCurrATIMWindow); +#endif + } + /* Set AutoSleep */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCFG, PSCFG_AUTOSLEEP); + /* Set HWUTSF */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_TFTCTL, TFTCTL_HWUTSF); + + if (wListenInterval >= 2) { + /* clear always listen beacon */ + MACvRegBitsOff(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN); + /* first time set listen next beacon */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_LNBCN); + } else { + /* always listen beacon */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN); + } + + /* enable power saving hw function */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_PSEN); + pDevice->bEnablePSMode = true; + + pDevice->bPWBitOn = true; + pr_debug("PS:Power Saving Mode Enable...\n"); +} + +/*+ + * + * Routine Description: + * Disable hw power saving functions + * + * Return Value: + * None. + * + -*/ + +void +PSvDisablePowerSaving( + void *hDeviceContext +) +{ + struct vnt_private *pDevice = hDeviceContext; + + /* disable power saving hw function */ + MACbPSWakeup(pDevice->PortOffset); + /* clear AutoSleep */ + MACvRegBitsOff(pDevice->PortOffset, MAC_REG_PSCFG, PSCFG_AUTOSLEEP); + /* clear HWUTSF */ + MACvRegBitsOff(pDevice->PortOffset, MAC_REG_TFTCTL, TFTCTL_HWUTSF); + /* set always listen beacon */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_ALBCN); + + pDevice->bEnablePSMode = false; + + pDevice->bPWBitOn = false; +} + + +/*+ + * + * Routine Description: + * Check if Next TBTT must wake up + * + * Return Value: + * None. + * + -*/ + +bool +PSbIsNextTBTTWakeUp( + void *hDeviceContext +) +{ + struct vnt_private *pDevice = hDeviceContext; + struct ieee80211_hw *hw = pDevice->hw; + struct ieee80211_conf *conf = &hw->conf; + bool bWakeUp = false; + + if (conf->listen_interval == 1) { + /* Turn on wake up to listen next beacon */ + MACvRegBitsOn(pDevice->PortOffset, MAC_REG_PSCTL, PSCTL_LNBCN); + bWakeUp = true; + } + + return bWakeUp; +} diff --git a/kernel/drivers/staging/vt6655/power.h b/kernel/drivers/staging/vt6655/power.h new file mode 100644 index 000000000..1083341b2 --- /dev/null +++ b/kernel/drivers/staging/vt6655/power.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: power.h + * + * Purpose: Handles 802.11 power management functions + * + * Author: Lyndon Chen + * + * Date: July 17, 2002 + * + */ + +#ifndef __POWER_H__ +#define __POWER_H__ + +#define C_PWBT 1000 // micro sec. power up before TBTT +#define PS_FAST_INTERVAL 1 // Fast power saving listen interval +#define PS_MAX_INTERVAL 4 // MAX power saving listen interval + +void +PSvDisablePowerSaving( + void *hDeviceContext +); + +void +PSvEnablePowerSaving( + void *hDeviceContext, + unsigned short wListenInterval +); + + +bool +PSbIsNextTBTTWakeUp( + void *hDeviceContext +); + +#endif //__POWER_H__ diff --git a/kernel/drivers/staging/vt6655/rf.c b/kernel/drivers/staging/vt6655/rf.c new file mode 100644 index 000000000..7626f635f --- /dev/null +++ b/kernel/drivers/staging/vt6655/rf.c @@ -0,0 +1,965 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: rf.c + * + * Purpose: rf function code + * + * Author: Jerry Chen + * + * Date: Feb. 19, 2004 + * + * Functions: + * IFRFbWriteEmbedded - Embedded write RF register via MAC + * + * Revision History: + * RobertYu 2005 + * chester 2008 + * + */ + +#include "mac.h" +#include "srom.h" +#include "rf.h" +#include "baseband.h" + +#define BY_AL2230_REG_LEN 23 //24bit +#define CB_AL2230_INIT_SEQ 15 +#define SWITCH_CHANNEL_DELAY_AL2230 200 //us +#define AL2230_PWR_IDX_LEN 64 + +#define BY_AL7230_REG_LEN 23 //24bit +#define CB_AL7230_INIT_SEQ 16 +#define SWITCH_CHANNEL_DELAY_AL7230 200 //us +#define AL7230_PWR_IDX_LEN 64 + +static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = { + 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // + 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW +}; + +static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = { + 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz + 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz + 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz + 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz + 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz + 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz + 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz + 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz + 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz + 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz + 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz + 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz + 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz + 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M +}; + +static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = { + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz + 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz + 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz + 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz + 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz + 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz + 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz + 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz + 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M +}; + +static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = { + 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, + 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW +}; + +// 40MHz reference frequency +// Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. +static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { + 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a + 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a + 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2 + 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3 + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a + // RoberYu:20050113, Rev0.47 Regsiter Setting Guide + 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55 + 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207 + 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A + 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) + // RoberYu:20050113, Rev0.47 Regsiter Setting Guide + 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C + 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF +}; + +static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = { + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g + 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g + 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g + 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g + 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113 + 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g + 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g + 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) + 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g + 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, + 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g +}; + +static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = { + 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz + 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz + 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz + 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz + 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz + 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz + 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz + 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 + 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 + 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 + 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 + 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 + 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 + 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz + + // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) + 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) + 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) + 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) + + // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, + // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) + + 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) + 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) + 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) + 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) + 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) + 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) + 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) + 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) + 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 + 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) + 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) + 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) + 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) + 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) + 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) + 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) + 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) + 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) + + 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) + 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) + 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) + 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) + 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) + 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) + 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) + 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) + 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) + 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) + 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) + 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) + 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) + 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) + 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) + 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) +}; + +static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = { + 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz + 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz + 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz + 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz + 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz + 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz + 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz + 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz + 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz + 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz + 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz + 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz + 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz + 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz + + // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) + 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) + 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) + 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) + 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) + + // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, + // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) + 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) + 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) + 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) + 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) + 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) + 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) + 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) + 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) + 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) + 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) + 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) + 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) + 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) + 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) + 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) +}; + +static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz + 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz + + // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) + + // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, + // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) + 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) + 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) +}; + +/* + * Description: AIROHA IFRF chip init function + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +static bool s_bAL7230Init(struct vnt_private *priv) +{ + void __iomem *dwIoBase = priv->PortOffset; + int ii; + bool bResult; + + bResult = true; + + /* 3-wire control for normal mode */ + VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); + + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | + SOFTPWRCTL_TXPEINV)); + BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */ + + for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]); + + /* PLL On */ + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + + /* Calibration */ + MACvTimer0MicroSDelay(dwIoBase, 150);//150us + /* TXDCOC:active, RCK:disable */ + bResult &= IFRFbWriteEmbedded(priv, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); + MACvTimer0MicroSDelay(dwIoBase, 30);//30us + /* TXDCOC:disable, RCK:active */ + bResult &= IFRFbWriteEmbedded(priv, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); + MACvTimer0MicroSDelay(dwIoBase, 30);//30us + /* TXDCOC:disable, RCK:disable */ + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); + + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | + SOFTPWRCTL_SWPE2 | + SOFTPWRCTL_SWPECTI | + SOFTPWRCTL_TXPEINV)); + + BBvPowerSaveModeON(priv); /* RobertYu:20050106 */ + + /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */ + /* 3-wire control for power saving mode */ + VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 + + return bResult; +} + +/* Need to Pull PLLON low when writing channel registers through + * 3-wire interface */ +static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel) +{ + void __iomem *dwIoBase = priv->PortOffset; + bool bResult; + + bResult = true; + + /* PLLON Off */ + MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + + bResult &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable0[byChannel - 1]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable1[byChannel - 1]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable2[byChannel - 1]); + + /* PLLOn On */ + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + + /* Set Channel[7] = 0 to tell H/W channel is changing now. */ + VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); + MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230); + /* Set Channel[7] = 1 to tell H/W channel change is done. */ + VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); + + return bResult; +} + +/* + * Description: Write to IF/RF, by embedded programming + * + * Parameters: + * In: + * dwIoBase - I/O base address + * dwData - data to write + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) +{ + void __iomem *dwIoBase = priv->PortOffset; + unsigned short ww; + unsigned long dwValue; + + VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData); + + /* W_MAX_TIMEOUT is the timeout period */ + for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { + VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue); + if (dwValue & IFREGCTL_DONE) + break; + } + + if (ww == W_MAX_TIMEOUT) + return false; + + return true; +} + +/* + * Description: AIROHA IFRF chip init function + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +static bool RFbAL2230Init(struct vnt_private *priv) +{ + void __iomem *dwIoBase = priv->PortOffset; + int ii; + bool bResult; + + bResult = true; + + /* 3-wire control for normal mode */ + VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); + + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | + SOFTPWRCTL_TXPEINV)); + /* PLL Off */ + MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + + /* patch abnormal AL2230 frequency output */ + IFRFbWriteEmbedded(priv, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); + + for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) + bResult &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[ii]); + MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us + + /* PLL On */ + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + + MACvTimer0MicroSDelay(dwIoBase, 150);//150us + bResult &= IFRFbWriteEmbedded(priv, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); + MACvTimer0MicroSDelay(dwIoBase, 30);//30us + bResult &= IFRFbWriteEmbedded(priv, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); + MACvTimer0MicroSDelay(dwIoBase, 30);//30us + bResult &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]); + + MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | + SOFTPWRCTL_SWPE2 | + SOFTPWRCTL_SWPECTI | + SOFTPWRCTL_TXPEINV)); + + /* 3-wire control for power saving mode */ + VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 + + return bResult; +} + +static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel) +{ + void __iomem *dwIoBase = priv->PortOffset; + bool bResult; + + bResult = true; + + bResult &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable0[byChannel - 1]); + bResult &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable1[byChannel - 1]); + + /* Set Channel[7] = 0 to tell H/W channel is changing now. */ + VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); + MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230); + /* Set Channel[7] = 1 to tell H/W channel change is done. */ + VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); + + return bResult; +} + +/* + * Description: RF init function + * + * Parameters: + * In: + * byBBType + * byRFType + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +bool RFbInit( + struct vnt_private *priv +) +{ + bool bResult = true; + + switch (priv->byRFType) { + case RF_AIROHA: + case RF_AL2230S: + priv->byMaxPwrLevel = AL2230_PWR_IDX_LEN; + bResult = RFbAL2230Init(priv); + break; + case RF_AIROHA7230: + priv->byMaxPwrLevel = AL7230_PWR_IDX_LEN; + bResult = s_bAL7230Init(priv); + break; + case RF_NOTHING: + bResult = true; + break; + default: + bResult = false; + break; + } + return bResult; +} + +/* + * Description: Select channel + * + * Parameters: + * In: + * byRFType + * byChannel - Channel number + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, + u16 byChannel) +{ + bool bResult = true; + + switch (byRFType) { + case RF_AIROHA: + case RF_AL2230S: + bResult = RFbAL2230SelectChannel(priv, byChannel); + break; + //{{ RobertYu: 20050104 + case RF_AIROHA7230: + bResult = s_bAL7230SelectChannel(priv, byChannel); + break; + //}} RobertYu + case RF_NOTHING: + bResult = true; + break; + default: + bResult = false; + break; + } + return bResult; +} + +/* + * Description: Write WakeProgSyn + * + * Parameters: + * In: + * dwIoBase - I/O base address + * uChannel - channel number + * bySleepCnt - SleepProgSyn count + * + * Return Value: None. + * + */ +bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType, + u16 uChannel) +{ + void __iomem *dwIoBase = priv->PortOffset; + int ii; + unsigned char byInitCount = 0; + unsigned char bySleepCount = 0; + + VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0); + switch (byRFType) { + case RF_AIROHA: + case RF_AL2230S: + + if (uChannel > CB_MAX_CHANNEL_24G) + return false; + + /* Init Reg + Channel Reg (2) */ + byInitCount = CB_AL2230_INIT_SEQ + 2; + bySleepCount = 0; + if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) + return false; + + for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]); + + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]); + ii++; + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]); + break; + + /* Need to check, PLLON need to be low for channel setting */ + case RF_AIROHA7230: + /* Init Reg + Channel Reg (3) */ + byInitCount = CB_AL7230_INIT_SEQ + 3; + bySleepCount = 0; + if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) + return false; + + if (uChannel <= CB_MAX_CHANNEL_24G) { + for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]); + } else { + for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]); + } + + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]); + ii++; + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]); + ii++; + MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]); + break; + + case RF_NOTHING: + return true; + + default: + return false; + } + + MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount)); + + return true; +} + +/* + * Description: Set Tx power + * + * Parameters: + * In: + * dwIoBase - I/O base address + * dwRFPowerTable - RF Tx Power Setting + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ +bool RFbSetPower( + struct vnt_private *priv, + unsigned int uRATE, + u16 uCH +) +{ + bool bResult = true; + unsigned char byPwr = 0; + unsigned char byDec = 0; + + if (priv->dwDiagRefCount != 0) + return true; + + if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) + return false; + + switch (uRATE) { + case RATE_1M: + case RATE_2M: + case RATE_5M: + case RATE_11M: + if (uCH > CB_MAX_CHANNEL_24G) + return false; + + byPwr = priv->abyCCKPwrTbl[uCH]; + break; + case RATE_6M: + case RATE_9M: + case RATE_12M: + case RATE_18M: + byPwr = priv->abyOFDMPwrTbl[uCH]; + if (priv->byRFType == RF_UW2452) + byDec = byPwr + 14; + else + byDec = byPwr + 10; + + if (byDec >= priv->byMaxPwrLevel) + byDec = priv->byMaxPwrLevel-1; + + byPwr = byDec; + break; + case RATE_24M: + case RATE_36M: + case RATE_48M: + case RATE_54M: + byPwr = priv->abyOFDMPwrTbl[uCH]; + break; + } + + if (priv->byCurPwr == byPwr) + return true; + + bResult = RFbRawSetPower(priv, byPwr, uRATE); + if (bResult) + priv->byCurPwr = byPwr; + + return bResult; +} + +/* + * Description: Set Tx power + * + * Parameters: + * In: + * dwIoBase - I/O base address + * dwRFPowerTable - RF Tx Power Setting + * Out: + * none + * + * Return Value: true if succeeded; false if failed. + * + */ + +bool RFbRawSetPower( + struct vnt_private *priv, + unsigned char byPwr, + unsigned int uRATE +) +{ + bool bResult = true; + unsigned long dwMax7230Pwr = 0; + + if (byPwr >= priv->byMaxPwrLevel) + return false; + + switch (priv->byRFType) { + case RF_AIROHA: + bResult &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]); + if (uRATE <= RATE_11M) + bResult &= IFRFbWriteEmbedded(priv, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + else + bResult &= IFRFbWriteEmbedded(priv, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + + break; + + case RF_AL2230S: + bResult &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]); + if (uRATE <= RATE_11M) { + bResult &= IFRFbWriteEmbedded(priv, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + bResult &= IFRFbWriteEmbedded(priv, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + } else { + bResult &= IFRFbWriteEmbedded(priv, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + bResult &= IFRFbWriteEmbedded(priv, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + } + + break; + + case RF_AIROHA7230: + /* 0x080F1B00 for 3 wire control TxGain(D10) + * and 0x31 as TX Gain value */ + dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) | + (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW; + + bResult &= IFRFbWriteEmbedded(priv, dwMax7230Pwr); + break; + + default: + break; + } + return bResult; +} + +/*+ + * + * Routine Description: + * Translate RSSI to dBm + * + * Parameters: + * In: + * priv - The adapter to be translated + * byCurrRSSI - RSSI to be translated + * Out: + * pdwdbm - Translated dbm number + * + * Return Value: none + * + -*/ +void +RFvRSSITodBm( + struct vnt_private *priv, + unsigned char byCurrRSSI, + long *pldBm + ) +{ + unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03); + long b = (byCurrRSSI & 0x3F); + long a = 0; + unsigned char abyAIROHARF[4] = {0, 18, 0, 40}; + + switch (priv->byRFType) { + case RF_AIROHA: + case RF_AL2230S: + case RF_AIROHA7230: + a = abyAIROHARF[byIdx]; + break; + default: + break; + } + + *pldBm = -1 * (a + b * 2); +} + +/* Post processing for the 11b/g and 11a. + * for save time on changing Reg2,3,5,7,10,12,15 */ +bool RFbAL7230SelectChannelPostProcess(struct vnt_private *priv, + u16 byOldChannel, + u16 byNewChannel) +{ + bool bResult; + + bResult = true; + + /* if change between 11 b/g and 11a need to update the following + * register + * Channel Index 1~14 */ + if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) { + /* Change from 2.4G to 5G [Reg] */ + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[2]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[3]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[5]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[7]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[10]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[12]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[15]); + } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) { + /* Change from 5G to 2.4G [Reg] */ + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[2]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[3]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[5]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[7]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[10]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[12]); + bResult &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[15]); + } + + return bResult; +} diff --git a/kernel/drivers/staging/vt6655/rf.h b/kernel/drivers/staging/vt6655/rf.h new file mode 100644 index 000000000..2ea21e2b0 --- /dev/null +++ b/kernel/drivers/staging/vt6655/rf.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: rf.h + * + * Purpose: + * + * Author: Jerry Chen + * + * Date: Feb. 19, 2004 + * + */ + +#ifndef __RF_H__ +#define __RF_H__ + +#include "device.h" + +/*--------------------- Export Definitions -------------------------*/ +// +// Baseband RF pair definition in eeprom (Bits 6..0) +// +#define RF_RFMD2959 0x01 +#define RF_MAXIMAG 0x02 +#define RF_AIROHA 0x03 + +#define RF_UW2451 0x05 +#define RF_MAXIMG 0x06 +#define RF_MAXIM2829 0x07 // RobertYu: 20041118 +#define RF_UW2452 0x08 // RobertYu: 20041210 +#define RF_AIROHA7230 0x0a // RobertYu: 20050104 +#define RF_UW2453 0x0b + +#define RF_VT3226 0x09 +#define RF_AL2230S 0x0e + +#define RF_NOTHING 0x7E +#define RF_EMU 0x80 +#define RF_MASK 0x7F + +#define ZONE_FCC 0 +#define ZONE_MKK1 1 +#define ZONE_ETSI 2 +#define ZONE_IC 3 +#define ZONE_SPAIN 4 +#define ZONE_FRANCE 5 +#define ZONE_MKK 6 +#define ZONE_ISRAEL 7 + +//[20050104] CB_MAXIM2829_CHANNEL_5G_HIGH, CB_UW2452_CHANNEL_5G_HIGH: 40==>41 +#define CB_MAXIM2829_CHANNEL_5G_HIGH 41 //Index41: channel = 100, Tf = 5500MHz, set the (A3:A0=0101) D6=1 +#define CB_UW2452_CHANNEL_5G_HIGH 41 //[20041210] Index41: channel = 100, Tf = 5500MHz, change VCO2->VCO3 + +/*--------------------- Export Classes ----------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +bool IFRFbWriteEmbedded(struct vnt_private *, unsigned long dwData); +bool RFbSelectChannel(struct vnt_private *, unsigned char byRFType, u16); +bool RFbInit( + struct vnt_private * +); +bool RFvWriteWakeProgSyn(struct vnt_private *, unsigned char byRFType, u16); +bool RFbSetPower(struct vnt_private *, unsigned int uRATE, u16); +bool RFbRawSetPower( + struct vnt_private *, + unsigned char byPwr, + unsigned int uRATE +); + +void +RFvRSSITodBm( + struct vnt_private *, + unsigned char byCurrRSSI, + long *pldBm +); + +//{{ RobertYu: 20050104 +bool RFbAL7230SelectChannelPostProcess(struct vnt_private *, u16, u16); +//}} RobertYu + +#endif // __RF_H__ diff --git a/kernel/drivers/staging/vt6655/rxtx.c b/kernel/drivers/staging/vt6655/rxtx.c new file mode 100644 index 000000000..74687761b --- /dev/null +++ b/kernel/drivers/staging/vt6655/rxtx.c @@ -0,0 +1,1522 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: rxtx.c + * + * Purpose: handle WMAC/802.3/802.11 rx & tx functions + * + * Author: Lyndon Chen + * + * Date: May 20, 2003 + * + * Functions: + * s_vGenerateTxParameter - Generate tx dma required parameter. + * vGenerateMACHeader - Translate 802.3 to 802.11 header + * cbGetFragCount - Calculate fragment number count + * csBeacon_xmit - beacon tx function + * csMgmt_xmit - management tx function + * s_cbFillTxBufHead - fulfill tx dma buffer header + * s_uGetDataDuration - get tx data required duration + * s_uFillDataHead- fulfill tx data duration header + * s_uGetRTSCTSDuration- get rtx/cts required duration + * s_uGetRTSCTSRsvTime- get rts/cts reserved time + * s_uGetTxRsvTime- get frame reserved time + * s_vFillCTSHead- fulfill CTS ctl header + * s_vFillFragParameter- Set fragment ctl parameter. + * s_vFillRTSHead- fulfill RTS ctl header + * s_vFillTxKey- fulfill tx encrypt key + * s_vSWencryption- Software encrypt header + * vDMA0_tx_80211- tx 802.11 frame via dma0 + * vGenerateFIFOHeader- Generate tx FIFO ctl header + * + * Revision History: + * + */ + +#include "device.h" +#include "rxtx.h" +#include "card.h" +#include "mac.h" +#include "baseband.h" +#include "rf.h" + +/*--------------------- Static Definitions -------------------------*/ + +/*--------------------- Static Classes ----------------------------*/ + +/*--------------------- Static Variables --------------------------*/ + +/*--------------------- Static Functions --------------------------*/ + +/*--------------------- Static Definitions -------------------------*/ +#define CRITICAL_PACKET_LEN 256 /* if packet size < 256 -> in-direct send + packet size >= 256 -> direct send */ + +static const unsigned short wTimeStampOff[2][MAX_RATE] = { + {384, 288, 226, 209, 54, 43, 37, 31, 28, 25, 24, 23}, /* Long Preamble */ + {384, 192, 130, 113, 54, 43, 37, 31, 28, 25, 24, 23}, /* Short Preamble */ +}; + +static const unsigned short wFB_Opt0[2][5] = { + {RATE_12M, RATE_18M, RATE_24M, RATE_36M, RATE_48M}, /* fallback_rate0 */ + {RATE_12M, RATE_12M, RATE_18M, RATE_24M, RATE_36M}, /* fallback_rate1 */ +}; +static const unsigned short wFB_Opt1[2][5] = { + {RATE_12M, RATE_18M, RATE_24M, RATE_24M, RATE_36M}, /* fallback_rate0 */ + {RATE_6M , RATE_6M, RATE_12M, RATE_12M, RATE_18M}, /* fallback_rate1 */ +}; + +#define RTSDUR_BB 0 +#define RTSDUR_BA 1 +#define RTSDUR_AA 2 +#define CTSDUR_BA 3 +#define RTSDUR_BA_F0 4 +#define RTSDUR_AA_F0 5 +#define RTSDUR_BA_F1 6 +#define RTSDUR_AA_F1 7 +#define CTSDUR_BA_F0 8 +#define CTSDUR_BA_F1 9 +#define DATADUR_B 10 +#define DATADUR_A 11 +#define DATADUR_A_F0 12 +#define DATADUR_A_F1 13 + +/*--------------------- Static Functions --------------------------*/ +static +void +s_vFillRTSHead( + struct vnt_private *pDevice, + unsigned char byPktType, + void *pvRTS, + unsigned int cbFrameLength, + bool bNeedAck, + bool bDisCRC, + struct ieee80211_hdr *hdr, + unsigned short wCurrentRate, + unsigned char byFBOption +); + +static +void +s_vGenerateTxParameter( + struct vnt_private *pDevice, + unsigned char byPktType, + struct vnt_tx_fifo_head *, + void *pvRrvTime, + void *pvRTS, + void *pvCTS, + unsigned int cbFrameSize, + bool bNeedACK, + unsigned int uDMAIdx, + void *psEthHeader, + unsigned short wCurrentRate +); + +static unsigned int +s_cbFillTxBufHead(struct vnt_private *pDevice, unsigned char byPktType, + unsigned char *pbyTxBufferAddr, + unsigned int uDMAIdx, PSTxDesc pHeadTD, + unsigned int uNodeIndex); + +static +__le16 +s_uFillDataHead( + struct vnt_private *pDevice, + unsigned char byPktType, + void *pTxDataHead, + unsigned int cbFrameLength, + unsigned int uDMAIdx, + bool bNeedAck, + unsigned int uFragIdx, + unsigned int cbLastFragmentSize, + unsigned int uMACfragNum, + unsigned char byFBOption, + unsigned short wCurrentRate, + bool is_pspoll +); + +/*--------------------- Export Variables --------------------------*/ + +static __le16 vnt_time_stamp_off(struct vnt_private *priv, u16 rate) +{ + return cpu_to_le16(wTimeStampOff[priv->byPreambleType % 2] + [rate % MAX_RATE]); +} + +/*byPktType : PK_TYPE_11A 0 + PK_TYPE_11B 1 + PK_TYPE_11GB 2 + PK_TYPE_11GA 3 +*/ +static +unsigned int +s_uGetTxRsvTime( + struct vnt_private *pDevice, + unsigned char byPktType, + unsigned int cbFrameLength, + unsigned short wRate, + bool bNeedAck +) +{ + unsigned int uDataTime, uAckTime; + + uDataTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, cbFrameLength, wRate); + if (byPktType == PK_TYPE_11B) /* llb,CCK mode */ + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, (unsigned short)pDevice->byTopCCKBasicRate); + else /* 11g 2.4G OFDM mode & 11a 5G OFDM mode */ + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, (unsigned short)pDevice->byTopOFDMBasicRate); + + if (bNeedAck) + return uDataTime + pDevice->uSIFS + uAckTime; + else + return uDataTime; +} + +static __le16 vnt_rxtx_rsvtime_le16(struct vnt_private *priv, u8 pkt_type, + u32 frame_length, u16 rate, bool need_ack) +{ + return cpu_to_le16((u16)s_uGetTxRsvTime(priv, pkt_type, + frame_length, rate, need_ack)); +} + +/* byFreqType: 0=>5GHZ 1=>2.4GHZ */ +static +__le16 +s_uGetRTSCTSRsvTime( + struct vnt_private *pDevice, + unsigned char byRTSRsvType, + unsigned char byPktType, + unsigned int cbFrameLength, + unsigned short wCurrentRate +) +{ + unsigned int uRrvTime, uRTSTime, uCTSTime, uAckTime, uDataTime; + + uRrvTime = uRTSTime = uCTSTime = uAckTime = uDataTime = 0; + + uDataTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, cbFrameLength, wCurrentRate); + if (byRTSRsvType == 0) { /* RTSTxRrvTime_bb */ + uRTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 20, pDevice->byTopCCKBasicRate); + uCTSTime = uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + } else if (byRTSRsvType == 1) { /* RTSTxRrvTime_ba, only in 2.4GHZ */ + uRTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 20, pDevice->byTopCCKBasicRate); + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + } else if (byRTSRsvType == 2) { /* RTSTxRrvTime_aa */ + uRTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 20, pDevice->byTopOFDMBasicRate); + uCTSTime = uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + } else if (byRTSRsvType == 3) { /* CTSTxRrvTime_ba, only in 2.4GHZ */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uRrvTime = uCTSTime + uAckTime + uDataTime + 2*pDevice->uSIFS; + return cpu_to_le16((u16)uRrvTime); + } + + /* RTSRrvTime */ + uRrvTime = uRTSTime + uCTSTime + uAckTime + uDataTime + 3*pDevice->uSIFS; + return cpu_to_le16((u16)uRrvTime); +} + +/* byFreqType 0: 5GHz, 1:2.4Ghz */ +static +unsigned int +s_uGetDataDuration( + struct vnt_private *pDevice, + unsigned char byDurType, + unsigned int cbFrameLength, + unsigned char byPktType, + unsigned short wRate, + bool bNeedAck, + unsigned int uFragIdx, + unsigned int cbLastFragmentSize, + unsigned int uMACfragNum, + unsigned char byFBOption +) +{ + bool bLastFrag = false; + unsigned int uAckTime = 0, uNextPktTime = 0; + + if (uFragIdx == (uMACfragNum-1)) + bLastFrag = true; + + switch (byDurType) { + case DATADUR_B: /* DATADUR_B */ + if (((uMACfragNum == 1)) || bLastFrag) {/* Non Frag or Last Frag */ + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + return pDevice->uSIFS + uAckTime; + } else { + return 0; + } + } else {/* First Frag or Mid Frag */ + if (uFragIdx == (uMACfragNum-2)) + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wRate, bNeedAck); + else + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); + + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + return pDevice->uSIFS + uAckTime + uNextPktTime; + } else { + return pDevice->uSIFS + uNextPktTime; + } + } + break; + + case DATADUR_A: /* DATADUR_A */ + if (((uMACfragNum == 1)) || bLastFrag) {/* Non Frag or Last Frag */ + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + return pDevice->uSIFS + uAckTime; + } else { + return 0; + } + } else {/* First Frag or Mid Frag */ + if (uFragIdx == (uMACfragNum-2)) + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wRate, bNeedAck); + else + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); + + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + return pDevice->uSIFS + uAckTime + uNextPktTime; + } else { + return pDevice->uSIFS + uNextPktTime; + } + } + break; + + case DATADUR_A_F0: /* DATADUR_A_F0 */ + if (((uMACfragNum == 1)) || bLastFrag) {/* Non Frag or Last Frag */ + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + return pDevice->uSIFS + uAckTime; + } else { + return 0; + } + } else { /* First Frag or Mid Frag */ + if (byFBOption == AUTO_FB_0) { + if (wRate < RATE_18M) + wRate = RATE_18M; + else if (wRate > RATE_54M) + wRate = RATE_54M; + + if (uFragIdx == (uMACfragNum-2)) + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); + else + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); + + } else { /* (byFBOption == AUTO_FB_1) */ + if (wRate < RATE_18M) + wRate = RATE_18M; + else if (wRate > RATE_54M) + wRate = RATE_54M; + + if (uFragIdx == (uMACfragNum-2)) + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); + else + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); + + } + + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + return pDevice->uSIFS + uAckTime + uNextPktTime; + } else { + return pDevice->uSIFS + uNextPktTime; + } + } + break; + + case DATADUR_A_F1: /* DATADUR_A_F1 */ + if (((uMACfragNum == 1)) || bLastFrag) { /* Non Frag or Last Frag */ + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + return pDevice->uSIFS + uAckTime; + } else { + return 0; + } + } else { /* First Frag or Mid Frag */ + if (byFBOption == AUTO_FB_0) { + if (wRate < RATE_18M) + wRate = RATE_18M; + else if (wRate > RATE_54M) + wRate = RATE_54M; + + if (uFragIdx == (uMACfragNum-2)) + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); + else + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); + + } else { /* (byFBOption == AUTO_FB_1) */ + if (wRate < RATE_18M) + wRate = RATE_18M; + else if (wRate > RATE_54M) + wRate = RATE_54M; + + if (uFragIdx == (uMACfragNum-2)) + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbLastFragmentSize, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); + else + uNextPktTime = s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); + } + if (bNeedAck) { + uAckTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + return pDevice->uSIFS + uAckTime + uNextPktTime; + } else { + return pDevice->uSIFS + uNextPktTime; + } + } + break; + + default: + break; + } + + ASSERT(false); + return 0; +} + +/* byFreqType: 0=>5GHZ 1=>2.4GHZ */ +static +__le16 +s_uGetRTSCTSDuration( + struct vnt_private *pDevice, + unsigned char byDurType, + unsigned int cbFrameLength, + unsigned char byPktType, + unsigned short wRate, + bool bNeedAck, + unsigned char byFBOption +) +{ + unsigned int uCTSTime = 0, uDurTime = 0; + + switch (byDurType) { + case RTSDUR_BB: /* RTSDuration_bb */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); + break; + + case RTSDUR_BA: /* RTSDuration_ba */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); + break; + + case RTSDUR_AA: /* RTSDuration_aa */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); + break; + + case CTSDUR_BA: /* CTSDuration_ba */ + uDurTime = pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wRate, bNeedAck); + break; + + case RTSDUR_BA_F0: /* RTSDuration_ba_f0 */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); + else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2 * pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); + + break; + + case RTSDUR_AA_F0: /* RTSDuration_aa_f0 */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); + else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); + + break; + + case RTSDUR_BA_F1: /* RTSDuration_ba_f1 */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopCCKBasicRate); + if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); + else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); + + break; + + case RTSDUR_AA_F1: /* RTSDuration_aa_f1 */ + uCTSTime = BBuGetFrameTime(pDevice->byPreambleType, byPktType, 14, pDevice->byTopOFDMBasicRate); + if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); + else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = uCTSTime + 2*pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); + + break; + + case CTSDUR_BA_F0: /* CTSDuration_ba_f0 */ + if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE0][wRate-RATE_18M], bNeedAck); + else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE0][wRate-RATE_18M], bNeedAck); + + break; + + case CTSDUR_BA_F1: /* CTSDuration_ba_f1 */ + if ((byFBOption == AUTO_FB_0) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt0[FB_RATE1][wRate-RATE_18M], bNeedAck); + else if ((byFBOption == AUTO_FB_1) && (wRate >= RATE_18M) && (wRate <= RATE_54M)) + uDurTime = pDevice->uSIFS + s_uGetTxRsvTime(pDevice, byPktType, cbFrameLength, wFB_Opt1[FB_RATE1][wRate-RATE_18M], bNeedAck); + + break; + + default: + break; + } + + return cpu_to_le16((u16)uDurTime); +} + +static +__le16 +s_uFillDataHead( + struct vnt_private *pDevice, + unsigned char byPktType, + void *pTxDataHead, + unsigned int cbFrameLength, + unsigned int uDMAIdx, + bool bNeedAck, + unsigned int uFragIdx, + unsigned int cbLastFragmentSize, + unsigned int uMACfragNum, + unsigned char byFBOption, + unsigned short wCurrentRate, + bool is_pspoll +) +{ + + if (pTxDataHead == NULL) + return 0; + + + if (byPktType == PK_TYPE_11GB || byPktType == PK_TYPE_11GA) { + if (byFBOption == AUTO_FB_NONE) { + struct vnt_tx_datahead_g *buf = pTxDataHead; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, cbFrameLength, wCurrentRate, + byPktType, &buf->a); + + vnt_get_phy_field(pDevice, cbFrameLength, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->b); + + if (is_pspoll) { + __le16 dur = cpu_to_le16(pDevice->current_aid | BIT(14) | BIT(15)); + + buf->duration_a = dur; + buf->duration_b = dur; + } else { + /* Get Duration and TimeStamp */ + buf->duration_a = + cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A, cbFrameLength, + byPktType, wCurrentRate, bNeedAck, uFragIdx, + cbLastFragmentSize, uMACfragNum, + byFBOption)); + buf->duration_b = + cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_B, cbFrameLength, + PK_TYPE_11B, pDevice->byTopCCKBasicRate, + bNeedAck, uFragIdx, cbLastFragmentSize, + uMACfragNum, byFBOption)); + } + + buf->time_stamp_off_a = vnt_time_stamp_off(pDevice, wCurrentRate); + buf->time_stamp_off_b = vnt_time_stamp_off(pDevice, pDevice->byTopCCKBasicRate); + + return buf->duration_a; + } else { + /* Auto Fallback */ + struct vnt_tx_datahead_g_fb *buf = pTxDataHead; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, cbFrameLength, wCurrentRate, + byPktType, &buf->a); + + vnt_get_phy_field(pDevice, cbFrameLength, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->b); + /* Get Duration and TimeStamp */ + buf->duration_a = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + buf->duration_b = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_B, cbFrameLength, PK_TYPE_11B, + pDevice->byTopCCKBasicRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + buf->duration_a_f0 = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A_F0, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + buf->duration_a_f1 = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A_F1, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + + buf->time_stamp_off_a = vnt_time_stamp_off(pDevice, wCurrentRate); + buf->time_stamp_off_b = vnt_time_stamp_off(pDevice, pDevice->byTopCCKBasicRate); + + return buf->duration_a; + } /* if (byFBOption == AUTO_FB_NONE) */ + } else if (byPktType == PK_TYPE_11A) { + if ((byFBOption != AUTO_FB_NONE)) { + /* Auto Fallback */ + struct vnt_tx_datahead_a_fb *buf = pTxDataHead; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, cbFrameLength, wCurrentRate, + byPktType, &buf->a); + + /* Get Duration and TimeStampOff */ + buf->duration = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + buf->duration_f0 = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A_F0, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + buf->duration_f1 = cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A_F1, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, cbLastFragmentSize, uMACfragNum, byFBOption)); + buf->time_stamp_off = vnt_time_stamp_off(pDevice, wCurrentRate); + return buf->duration; + } else { + struct vnt_tx_datahead_ab *buf = pTxDataHead; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, cbFrameLength, wCurrentRate, + byPktType, &buf->ab); + + if (is_pspoll) { + __le16 dur = cpu_to_le16(pDevice->current_aid | BIT(14) | BIT(15)); + + buf->duration = dur; + } else { + /* Get Duration and TimeStampOff */ + buf->duration = + cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_A, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, + cbLastFragmentSize, uMACfragNum, + byFBOption)); + } + + buf->time_stamp_off = vnt_time_stamp_off(pDevice, wCurrentRate); + return buf->duration; + } + } else { + struct vnt_tx_datahead_ab *buf = pTxDataHead; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, cbFrameLength, wCurrentRate, + byPktType, &buf->ab); + + if (is_pspoll) { + __le16 dur = cpu_to_le16(pDevice->current_aid | BIT(14) | BIT(15)); + + buf->duration = dur; + } else { + /* Get Duration and TimeStampOff */ + buf->duration = + cpu_to_le16((u16)s_uGetDataDuration(pDevice, DATADUR_B, cbFrameLength, byPktType, + wCurrentRate, bNeedAck, uFragIdx, + cbLastFragmentSize, uMACfragNum, + byFBOption)); + } + + buf->time_stamp_off = vnt_time_stamp_off(pDevice, wCurrentRate); + return buf->duration; + } + return 0; +} + + +static +void +s_vFillRTSHead( + struct vnt_private *pDevice, + unsigned char byPktType, + void *pvRTS, + unsigned int cbFrameLength, + bool bNeedAck, + bool bDisCRC, + struct ieee80211_hdr *hdr, + unsigned short wCurrentRate, + unsigned char byFBOption +) +{ + unsigned int uRTSFrameLen = 20; + + if (pvRTS == NULL) + return; + + if (bDisCRC) { + /* When CRCDIS bit is on, H/W forgot to generate FCS for RTS frame, + in this case we need to decrease its length by 4. */ + uRTSFrameLen -= 4; + } + + /* Note: So far RTSHead dosen't appear in ATIM & Beacom DMA, so we don't need to take them into account. + Otherwise, we need to modify codes for them. */ + if (byPktType == PK_TYPE_11GB || byPktType == PK_TYPE_11GA) { + if (byFBOption == AUTO_FB_NONE) { + struct vnt_rts_g *buf = pvRTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->b); + + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopOFDMBasicRate, + byPktType, &buf->a); + /* Get Duration */ + buf->duration_bb = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BB, + cbFrameLength, PK_TYPE_11B, + pDevice->byTopCCKBasicRate, + bNeedAck, byFBOption); + buf->duration_aa = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->duration_ba = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + + buf->data.duration = buf->duration_aa; + /* Get RTS Frame body */ + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | + IEEE80211_STYPE_RTS); + + ether_addr_copy(buf->data.ra, hdr->addr1); + ether_addr_copy(buf->data.ta, hdr->addr2); + } else { + struct vnt_rts_g_fb *buf = pvRTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->b); + + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopOFDMBasicRate, + byPktType, &buf->a); + /* Get Duration */ + buf->duration_bb = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BB, + cbFrameLength, PK_TYPE_11B, + pDevice->byTopCCKBasicRate, + bNeedAck, byFBOption); + buf->duration_aa = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->duration_ba = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->rts_duration_ba_f0 = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BA_F0, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->rts_duration_aa_f0 = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA_F0, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->rts_duration_ba_f1 = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BA_F1, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->rts_duration_aa_f1 = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA_F1, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->data.duration = buf->duration_aa; + /* Get RTS Frame body */ + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | + IEEE80211_STYPE_RTS); + + ether_addr_copy(buf->data.ra, hdr->addr1); + ether_addr_copy(buf->data.ta, hdr->addr2); + } /* if (byFBOption == AUTO_FB_NONE) */ + } else if (byPktType == PK_TYPE_11A) { + if (byFBOption == AUTO_FB_NONE) { + struct vnt_rts_ab *buf = pvRTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopOFDMBasicRate, + byPktType, &buf->ab); + /* Get Duration */ + buf->duration = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->data.duration = buf->duration; + /* Get RTS Frame body */ + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | + IEEE80211_STYPE_RTS); + + ether_addr_copy(buf->data.ra, hdr->addr1); + ether_addr_copy(buf->data.ta, hdr->addr2); + } else { + struct vnt_rts_a_fb *buf = pvRTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopOFDMBasicRate, + byPktType, &buf->a); + /* Get Duration */ + buf->duration = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->rts_duration_f0 = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA_F0, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->rts_duration_f1 = + s_uGetRTSCTSDuration(pDevice, RTSDUR_AA_F1, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + buf->data.duration = buf->duration; + /* Get RTS Frame body */ + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | + IEEE80211_STYPE_RTS); + + ether_addr_copy(buf->data.ra, hdr->addr1); + ether_addr_copy(buf->data.ta, hdr->addr2); + } + } else if (byPktType == PK_TYPE_11B) { + struct vnt_rts_ab *buf = pvRTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uRTSFrameLen, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->ab); + /* Get Duration */ + buf->duration = + s_uGetRTSCTSDuration(pDevice, RTSDUR_BB, cbFrameLength, + byPktType, wCurrentRate, bNeedAck, + byFBOption); + + buf->data.duration = buf->duration; + /* Get RTS Frame body */ + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS); + + ether_addr_copy(buf->data.ra, hdr->addr1); + ether_addr_copy(buf->data.ta, hdr->addr2); + } +} + +static +void +s_vFillCTSHead( + struct vnt_private *pDevice, + unsigned int uDMAIdx, + unsigned char byPktType, + void *pvCTS, + unsigned int cbFrameLength, + bool bNeedAck, + bool bDisCRC, + unsigned short wCurrentRate, + unsigned char byFBOption +) +{ + unsigned int uCTSFrameLen = 14; + + if (pvCTS == NULL) + return; + + if (bDisCRC) { + /* When CRCDIS bit is on, H/W forgot to generate FCS for CTS frame, + in this case we need to decrease its length by 4. */ + uCTSFrameLen -= 4; + } + + if (byPktType == PK_TYPE_11GB || byPktType == PK_TYPE_11GA) { + if (byFBOption != AUTO_FB_NONE && uDMAIdx != TYPE_ATIMDMA && uDMAIdx != TYPE_BEACONDMA) { + /* Auto Fall back */ + struct vnt_cts_fb *buf = pvCTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uCTSFrameLen, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->b); + + buf->duration_ba = + s_uGetRTSCTSDuration(pDevice, CTSDUR_BA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + + /* Get CTSDuration_ba_f0 */ + buf->cts_duration_ba_f0 = + s_uGetRTSCTSDuration(pDevice, CTSDUR_BA_F0, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + + /* Get CTSDuration_ba_f1 */ + buf->cts_duration_ba_f1 = + s_uGetRTSCTSDuration(pDevice, CTSDUR_BA_F1, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + + /* Get CTS Frame body */ + buf->data.duration = buf->duration_ba; + + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | + IEEE80211_STYPE_CTS); + + buf->reserved2 = 0x0; + + ether_addr_copy(buf->data.ra, + pDevice->abyCurrentNetAddr); + } else { /* if (byFBOption != AUTO_FB_NONE && uDMAIdx != TYPE_ATIMDMA && uDMAIdx != TYPE_BEACONDMA) */ + struct vnt_cts *buf = pvCTS; + /* Get SignalField, ServiceField & Length */ + vnt_get_phy_field(pDevice, uCTSFrameLen, + pDevice->byTopCCKBasicRate, + PK_TYPE_11B, &buf->b); + + /* Get CTSDuration_ba */ + buf->duration_ba = + s_uGetRTSCTSDuration(pDevice, CTSDUR_BA, + cbFrameLength, byPktType, + wCurrentRate, bNeedAck, + byFBOption); + + /* Get CTS Frame body */ + buf->data.duration = buf->duration_ba; + + buf->data.frame_control = + cpu_to_le16(IEEE80211_FTYPE_CTL | + IEEE80211_STYPE_CTS); + + buf->reserved2 = 0x0; + ether_addr_copy(buf->data.ra, + pDevice->abyCurrentNetAddr); + } + } +} + +/*+ + * + * Description: + * Generate FIFO control for MAC & Baseband controller + * + * Parameters: + * In: + * pDevice - Pointer to adapter + * pTxDataHead - Transmit Data Buffer + * pTxBufHead - pTxBufHead + * pvRrvTime - pvRrvTime + * pvRTS - RTS Buffer + * pCTS - CTS Buffer + * cbFrameSize - Transmit Data Length (Hdr+Payload+FCS) + * bNeedACK - If need ACK + * uDescIdx - Desc Index + * Out: + * none + * + * Return Value: none + * + - + * unsigned int cbFrameSize, Hdr+Payload+FCS */ +static +void +s_vGenerateTxParameter( + struct vnt_private *pDevice, + unsigned char byPktType, + struct vnt_tx_fifo_head *tx_buffer_head, + void *pvRrvTime, + void *pvRTS, + void *pvCTS, + unsigned int cbFrameSize, + bool bNeedACK, + unsigned int uDMAIdx, + void *psEthHeader, + unsigned short wCurrentRate +) +{ + u16 fifo_ctl = le16_to_cpu(tx_buffer_head->fifo_ctl); + bool bDisCRC = false; + unsigned char byFBOption = AUTO_FB_NONE; + + tx_buffer_head->current_rate = cpu_to_le16(wCurrentRate); + + if (fifo_ctl & FIFOCTL_CRCDIS) + bDisCRC = true; + + if (fifo_ctl & FIFOCTL_AUTO_FB_0) + byFBOption = AUTO_FB_0; + else if (fifo_ctl & FIFOCTL_AUTO_FB_1) + byFBOption = AUTO_FB_1; + + if (!pvRrvTime) + return; + + if (byPktType == PK_TYPE_11GB || byPktType == PK_TYPE_11GA) { + if (pvRTS != NULL) { /* RTS_need + Fill RsvTime */ + struct vnt_rrv_time_rts *buf = pvRrvTime; + + buf->rts_rrv_time_aa = s_uGetRTSCTSRsvTime(pDevice, 2, byPktType, cbFrameSize, wCurrentRate); + buf->rts_rrv_time_ba = s_uGetRTSCTSRsvTime(pDevice, 1, byPktType, cbFrameSize, wCurrentRate); + buf->rts_rrv_time_bb = s_uGetRTSCTSRsvTime(pDevice, 0, byPktType, cbFrameSize, wCurrentRate); + buf->rrv_time_a = vnt_rxtx_rsvtime_le16(pDevice, byPktType, cbFrameSize, wCurrentRate, bNeedACK); + buf->rrv_time_b = vnt_rxtx_rsvtime_le16(pDevice, PK_TYPE_11B, cbFrameSize, pDevice->byTopCCKBasicRate, bNeedACK); + + s_vFillRTSHead(pDevice, byPktType, pvRTS, cbFrameSize, bNeedACK, bDisCRC, psEthHeader, wCurrentRate, byFBOption); + } else {/* RTS_needless, PCF mode */ + struct vnt_rrv_time_cts *buf = pvRrvTime; + + buf->rrv_time_a = vnt_rxtx_rsvtime_le16(pDevice, byPktType, cbFrameSize, wCurrentRate, bNeedACK); + buf->rrv_time_b = vnt_rxtx_rsvtime_le16(pDevice, PK_TYPE_11B, cbFrameSize, pDevice->byTopCCKBasicRate, bNeedACK); + buf->cts_rrv_time_ba = s_uGetRTSCTSRsvTime(pDevice, 3, byPktType, cbFrameSize, wCurrentRate); + + /* Fill CTS */ + s_vFillCTSHead(pDevice, uDMAIdx, byPktType, pvCTS, cbFrameSize, bNeedACK, bDisCRC, wCurrentRate, byFBOption); + } + } else if (byPktType == PK_TYPE_11A) { + if (pvRTS != NULL) {/* RTS_need, non PCF mode */ + struct vnt_rrv_time_ab *buf = pvRrvTime; + + buf->rts_rrv_time = s_uGetRTSCTSRsvTime(pDevice, 2, byPktType, cbFrameSize, wCurrentRate); + buf->rrv_time = vnt_rxtx_rsvtime_le16(pDevice, byPktType, cbFrameSize, wCurrentRate, bNeedACK); + + /* Fill RTS */ + s_vFillRTSHead(pDevice, byPktType, pvRTS, cbFrameSize, bNeedACK, bDisCRC, psEthHeader, wCurrentRate, byFBOption); + } else if (pvRTS == NULL) {/* RTS_needless, non PCF mode */ + struct vnt_rrv_time_ab *buf = pvRrvTime; + + buf->rrv_time = vnt_rxtx_rsvtime_le16(pDevice, PK_TYPE_11A, cbFrameSize, wCurrentRate, bNeedACK); + } + } else if (byPktType == PK_TYPE_11B) { + if ((pvRTS != NULL)) {/* RTS_need, non PCF mode */ + struct vnt_rrv_time_ab *buf = pvRrvTime; + + buf->rts_rrv_time = s_uGetRTSCTSRsvTime(pDevice, 0, byPktType, cbFrameSize, wCurrentRate); + buf->rrv_time = vnt_rxtx_rsvtime_le16(pDevice, PK_TYPE_11B, cbFrameSize, wCurrentRate, bNeedACK); + + /* Fill RTS */ + s_vFillRTSHead(pDevice, byPktType, pvRTS, cbFrameSize, bNeedACK, bDisCRC, psEthHeader, wCurrentRate, byFBOption); + } else { /* RTS_needless, non PCF mode */ + struct vnt_rrv_time_ab *buf = pvRrvTime; + + buf->rrv_time = vnt_rxtx_rsvtime_le16(pDevice, PK_TYPE_11B, cbFrameSize, wCurrentRate, bNeedACK); + } + } +} + +static unsigned int +s_cbFillTxBufHead(struct vnt_private *pDevice, unsigned char byPktType, + unsigned char *pbyTxBufferAddr, + unsigned int uDMAIdx, PSTxDesc pHeadTD, + unsigned int is_pspoll) +{ + PDEVICE_TD_INFO td_info = pHeadTD->pTDInfo; + struct sk_buff *skb = td_info->skb; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + struct vnt_tx_fifo_head *tx_buffer_head = + (struct vnt_tx_fifo_head *)td_info->buf; + u16 fifo_ctl = le16_to_cpu(tx_buffer_head->fifo_ctl); + unsigned int cbFrameSize; + __le16 uDuration; + unsigned char *pbyBuffer; + unsigned int uLength = 0; + unsigned int cbMICHDR = 0; + unsigned int uMACfragNum = 1; + unsigned int uPadding = 0; + unsigned int cbReqCount = 0; + bool bNeedACK = (bool)(fifo_ctl & FIFOCTL_NEEDACK); + bool bRTS = (bool)(fifo_ctl & FIFOCTL_RTS); + PSTxDesc ptdCurr; + unsigned int cbHeaderLength = 0; + void *pvRrvTime; + struct vnt_mic_hdr *pMICHDR; + void *pvRTS; + void *pvCTS; + void *pvTxDataHd; + unsigned short wTxBufSize; /* FFinfo size */ + unsigned char byFBOption = AUTO_FB_NONE; + + pvRrvTime = pMICHDR = pvRTS = pvCTS = pvTxDataHd = NULL; + + cbFrameSize = skb->len + 4; + + if (info->control.hw_key) { + switch (info->control.hw_key->cipher) { + case WLAN_CIPHER_SUITE_CCMP: + cbMICHDR = sizeof(struct vnt_mic_hdr); + default: + break; + } + + cbFrameSize += info->control.hw_key->icv_len; + + if (pDevice->byLocalID > REV_ID_VT3253_A1) { + /* MAC Header should be padding 0 to DW alignment. */ + uPadding = 4 - (ieee80211_get_hdrlen_from_skb(skb) % 4); + uPadding %= 4; + } + } + + /* + * Use for AUTO FALL BACK + */ + if (fifo_ctl & FIFOCTL_AUTO_FB_0) + byFBOption = AUTO_FB_0; + else if (fifo_ctl & FIFOCTL_AUTO_FB_1) + byFBOption = AUTO_FB_1; + + + /* Set RrvTime/RTS/CTS Buffer */ + wTxBufSize = sizeof(STxBufHead); + if (byPktType == PK_TYPE_11GB || byPktType == PK_TYPE_11GA) {/* 802.11g packet */ + + if (byFBOption == AUTO_FB_NONE) { + if (bRTS == true) {/* RTS_need */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_rts)); + pvRTS = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_rts) + cbMICHDR); + pvCTS = NULL; + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_rts) + + cbMICHDR + sizeof(struct vnt_rts_g)); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_rts) + + cbMICHDR + sizeof(struct vnt_rts_g) + + sizeof(struct vnt_tx_datahead_g); + } else { /* RTS_needless */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_cts)); + pvRTS = NULL; + pvCTS = (void *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_cts) + cbMICHDR); + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + + sizeof(struct vnt_rrv_time_cts) + cbMICHDR + sizeof(struct vnt_cts)); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_cts) + + cbMICHDR + sizeof(struct vnt_cts) + sizeof(struct vnt_tx_datahead_g); + } + } else { + /* Auto Fall Back */ + if (bRTS == true) {/* RTS_need */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_rts)); + pvRTS = (void *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_rts) + cbMICHDR); + pvCTS = NULL; + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_rts) + + cbMICHDR + sizeof(struct vnt_rts_g_fb)); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_rts) + + cbMICHDR + sizeof(struct vnt_rts_g_fb) + sizeof(struct vnt_tx_datahead_g_fb); + } else { /* RTS_needless */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_cts)); + pvRTS = NULL; + pvCTS = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_cts) + cbMICHDR); + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_cts) + + cbMICHDR + sizeof(struct vnt_cts_fb)); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_cts) + + cbMICHDR + sizeof(struct vnt_cts_fb) + sizeof(struct vnt_tx_datahead_g_fb); + } + } /* Auto Fall Back */ + } else {/* 802.11a/b packet */ + + if (byFBOption == AUTO_FB_NONE) { + if (bRTS == true) { + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab)); + pvRTS = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab) + cbMICHDR); + pvCTS = NULL; + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + + sizeof(struct vnt_rrv_time_ab) + cbMICHDR + sizeof(struct vnt_rts_ab)); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_ab) + + cbMICHDR + sizeof(struct vnt_rts_ab) + sizeof(struct vnt_tx_datahead_ab); + } else { /* RTS_needless, need MICHDR */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab)); + pvRTS = NULL; + pvCTS = NULL; + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab) + cbMICHDR); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_ab) + + cbMICHDR + sizeof(struct vnt_tx_datahead_ab); + } + } else { + /* Auto Fall Back */ + if (bRTS == true) { /* RTS_need */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *) (pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab)); + pvRTS = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab) + cbMICHDR); + pvCTS = NULL; + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + + sizeof(struct vnt_rrv_time_ab) + cbMICHDR + sizeof(struct vnt_rts_a_fb)); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_ab) + + cbMICHDR + sizeof(struct vnt_rts_a_fb) + sizeof(struct vnt_tx_datahead_a_fb); + } else { /* RTS_needless */ + pvRrvTime = (void *)(pbyTxBufferAddr + wTxBufSize); + pMICHDR = (struct vnt_mic_hdr *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab)); + pvRTS = NULL; + pvCTS = NULL; + pvTxDataHd = (void *)(pbyTxBufferAddr + wTxBufSize + sizeof(struct vnt_rrv_time_ab) + cbMICHDR); + cbHeaderLength = wTxBufSize + sizeof(struct vnt_rrv_time_ab) + + cbMICHDR + sizeof(struct vnt_tx_datahead_a_fb); + } + } /* Auto Fall Back */ + } + + td_info->mic_hdr = pMICHDR; + + memset((void *)(pbyTxBufferAddr + wTxBufSize), 0, (cbHeaderLength - wTxBufSize)); + + /* Fill FIFO,RrvTime,RTS,and CTS */ + s_vGenerateTxParameter(pDevice, byPktType, tx_buffer_head, pvRrvTime, pvRTS, pvCTS, + cbFrameSize, bNeedACK, uDMAIdx, hdr, pDevice->wCurrentRate); + /* Fill DataHead */ + uDuration = s_uFillDataHead(pDevice, byPktType, pvTxDataHd, cbFrameSize, uDMAIdx, bNeedACK, + 0, 0, uMACfragNum, byFBOption, pDevice->wCurrentRate, is_pspoll); + + hdr->duration_id = uDuration; + + cbReqCount = cbHeaderLength + uPadding + skb->len; + pbyBuffer = (unsigned char *)pHeadTD->pTDInfo->buf; + uLength = cbHeaderLength + uPadding; + + /* Copy the Packet into a tx Buffer */ + memcpy((pbyBuffer + uLength), skb->data, skb->len); + + ptdCurr = (PSTxDesc)pHeadTD; + + ptdCurr->pTDInfo->dwReqCount = cbReqCount; + ptdCurr->pTDInfo->dwHeaderLength = cbHeaderLength; + ptdCurr->pTDInfo->skb_dma = ptdCurr->pTDInfo->buf_dma; + + return cbHeaderLength; +} + +static void vnt_fill_txkey(struct ieee80211_hdr *hdr, u8 *key_buffer, + struct ieee80211_key_conf *tx_key, + struct sk_buff *skb, u16 payload_len, + struct vnt_mic_hdr *mic_hdr) +{ + struct ieee80211_key_seq seq; + u8 *iv = ((u8 *)hdr + ieee80211_get_hdrlen_from_skb(skb)); + + /* strip header and icv len from payload */ + payload_len -= ieee80211_get_hdrlen_from_skb(skb); + payload_len -= tx_key->icv_len; + + switch (tx_key->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + memcpy(key_buffer, iv, 3); + memcpy(key_buffer + 3, tx_key->key, tx_key->keylen); + + if (tx_key->keylen == WLAN_KEY_LEN_WEP40) { + memcpy(key_buffer + 8, iv, 3); + memcpy(key_buffer + 11, + tx_key->key, WLAN_KEY_LEN_WEP40); + } + + break; + case WLAN_CIPHER_SUITE_TKIP: + ieee80211_get_tkip_p2k(tx_key, skb, key_buffer); + + break; + case WLAN_CIPHER_SUITE_CCMP: + + if (!mic_hdr) + return; + + mic_hdr->id = 0x59; + mic_hdr->payload_len = cpu_to_be16(payload_len); + ether_addr_copy(mic_hdr->mic_addr2, hdr->addr2); + + ieee80211_get_key_tx_seq(tx_key, &seq); + + memcpy(mic_hdr->ccmp_pn, seq.ccmp.pn, IEEE80211_CCMP_PN_LEN); + + if (ieee80211_has_a4(hdr->frame_control)) + mic_hdr->hlen = cpu_to_be16(28); + else + mic_hdr->hlen = cpu_to_be16(22); + + ether_addr_copy(mic_hdr->addr1, hdr->addr1); + ether_addr_copy(mic_hdr->addr2, hdr->addr2); + ether_addr_copy(mic_hdr->addr3, hdr->addr3); + + mic_hdr->frame_control = cpu_to_le16( + le16_to_cpu(hdr->frame_control) & 0xc78f); + mic_hdr->seq_ctrl = cpu_to_le16( + le16_to_cpu(hdr->seq_ctrl) & 0xf); + + if (ieee80211_has_a4(hdr->frame_control)) + ether_addr_copy(mic_hdr->addr4, hdr->addr4); + + memcpy(key_buffer, tx_key->key, WLAN_KEY_LEN_CCMP); + + break; + default: + break; + } +} + +int vnt_generate_fifo_header(struct vnt_private *priv, u32 dma_idx, + PSTxDesc head_td, struct sk_buff *skb) +{ + PDEVICE_TD_INFO td_info = head_td->pTDInfo; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct ieee80211_tx_rate *tx_rate = &info->control.rates[0]; + struct ieee80211_rate *rate; + struct ieee80211_key_conf *tx_key; + struct ieee80211_hdr *hdr; + struct vnt_tx_fifo_head *tx_buffer_head = + (struct vnt_tx_fifo_head *)td_info->buf; + u16 tx_body_size = skb->len, current_rate; + u8 pkt_type; + bool is_pspoll = false; + + memset(tx_buffer_head, 0, sizeof(*tx_buffer_head)); + + hdr = (struct ieee80211_hdr *)(skb->data); + + rate = ieee80211_get_tx_rate(priv->hw, info); + + current_rate = rate->hw_value; + if (priv->wCurrentRate != current_rate && + !(priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { + priv->wCurrentRate = current_rate; + + RFbSetPower(priv, priv->wCurrentRate, + priv->hw->conf.chandef.chan->hw_value); + } + + if (current_rate > RATE_11M) { + if (info->band == IEEE80211_BAND_5GHZ) { + pkt_type = PK_TYPE_11A; + } else { + if (tx_rate->flags & IEEE80211_TX_RC_USE_CTS_PROTECT) + pkt_type = PK_TYPE_11GB; + else + pkt_type = PK_TYPE_11GA; + } + } else { + pkt_type = PK_TYPE_11B; + } + + /*Set fifo controls */ + if (pkt_type == PK_TYPE_11A) + tx_buffer_head->fifo_ctl = 0; + else if (pkt_type == PK_TYPE_11B) + tx_buffer_head->fifo_ctl = cpu_to_le16(FIFOCTL_11B); + else if (pkt_type == PK_TYPE_11GB) + tx_buffer_head->fifo_ctl = cpu_to_le16(FIFOCTL_11GB); + else if (pkt_type == PK_TYPE_11GA) + tx_buffer_head->fifo_ctl = cpu_to_le16(FIFOCTL_11GA); + + /* generate interrupt */ + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_GENINT); + + if (!ieee80211_is_data(hdr->frame_control)) { + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_TMOEN); + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_ISDMA0); + tx_buffer_head->time_stamp = + cpu_to_le16(DEFAULT_MGN_LIFETIME_RES_64us); + } else { + tx_buffer_head->time_stamp = + cpu_to_le16(DEFAULT_MSDU_LIFETIME_RES_64us); + } + + if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_NEEDACK); + + if (ieee80211_has_retry(hdr->frame_control)) + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_LRETRY); + + if (tx_rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) + priv->byPreambleType = PREAMBLE_SHORT; + else + priv->byPreambleType = PREAMBLE_LONG; + + if (tx_rate->flags & IEEE80211_TX_RC_USE_RTS_CTS) + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_RTS); + + if (ieee80211_has_a4(hdr->frame_control)) { + tx_buffer_head->fifo_ctl |= cpu_to_le16(FIFOCTL_LHEAD); + priv->bLongHeader = true; + } + + if (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER) + is_pspoll = true; + + tx_buffer_head->frag_ctl = + cpu_to_le16(ieee80211_get_hdrlen_from_skb(skb) << 10); + + if (info->control.hw_key) { + tx_key = info->control.hw_key; + + switch (info->control.hw_key->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_LEGACY); + break; + case WLAN_CIPHER_SUITE_TKIP: + tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_TKIP); + break; + case WLAN_CIPHER_SUITE_CCMP: + tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_AES); + default: + break; + } + } + + tx_buffer_head->current_rate = cpu_to_le16(current_rate); + + /* legacy rates TODO use ieee80211_tx_rate */ + if (current_rate >= RATE_18M && ieee80211_is_data(hdr->frame_control)) { + if (priv->byAutoFBCtrl == AUTO_FB_0) + tx_buffer_head->fifo_ctl |= + cpu_to_le16(FIFOCTL_AUTO_FB_0); + else if (priv->byAutoFBCtrl == AUTO_FB_1) + tx_buffer_head->fifo_ctl |= + cpu_to_le16(FIFOCTL_AUTO_FB_1); + + } + + tx_buffer_head->frag_ctl |= cpu_to_le16(FRAGCTL_NONFRAG); + + s_cbFillTxBufHead(priv, pkt_type, (u8 *)tx_buffer_head, + dma_idx, head_td, is_pspoll); + + if (info->control.hw_key) { + tx_key = info->control.hw_key; + if (tx_key->keylen > 0) + vnt_fill_txkey(hdr, tx_buffer_head->tx_key, + tx_key, skb, tx_body_size, td_info->mic_hdr); + } + + return 0; +} + +static int vnt_beacon_xmit(struct vnt_private *priv, + struct sk_buff *skb) +{ + struct vnt_tx_short_buf_head *short_head = + (struct vnt_tx_short_buf_head *)priv->tx_beacon_bufs; + struct ieee80211_mgmt *mgmt_hdr = (struct ieee80211_mgmt *) + (priv->tx_beacon_bufs + sizeof(*short_head)); + struct ieee80211_tx_info *info; + u32 frame_size = skb->len + 4; + u16 current_rate; + + memset(priv->tx_beacon_bufs, 0, sizeof(*short_head)); + + if (priv->byBBType == BB_TYPE_11A) { + current_rate = RATE_6M; + + /* Get SignalField,ServiceField,Length */ + vnt_get_phy_field(priv, frame_size, current_rate, + PK_TYPE_11A, &short_head->ab); + + /* Get Duration and TimeStampOff */ + short_head->duration = + cpu_to_le16((u16)s_uGetDataDuration(priv, DATADUR_B, + frame_size, PK_TYPE_11A, current_rate, + false, 0, 0, 1, AUTO_FB_NONE)); + + short_head->time_stamp_off = + vnt_time_stamp_off(priv, current_rate); + } else { + current_rate = RATE_1M; + short_head->fifo_ctl |= cpu_to_le16(FIFOCTL_11B); + + /* Get SignalField,ServiceField,Length */ + vnt_get_phy_field(priv, frame_size, current_rate, + PK_TYPE_11B, &short_head->ab); + + /* Get Duration and TimeStampOff */ + short_head->duration = + cpu_to_le16((u16)s_uGetDataDuration(priv, DATADUR_B, + frame_size, PK_TYPE_11B, current_rate, + false, 0, 0, 1, AUTO_FB_NONE)); + + short_head->time_stamp_off = + vnt_time_stamp_off(priv, current_rate); + } + + short_head->fifo_ctl |= cpu_to_le16(FIFOCTL_GENINT); + + /* Copy Beacon */ + memcpy(mgmt_hdr, skb->data, skb->len); + + /* time stamp always 0 */ + mgmt_hdr->u.beacon.timestamp = 0; + + info = IEEE80211_SKB_CB(skb); + if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)mgmt_hdr; + + hdr->duration_id = 0; + hdr->seq_ctrl = cpu_to_le16(priv->wSeqCounter << 4); + } + + priv->wSeqCounter++; + if (priv->wSeqCounter > 0x0fff) + priv->wSeqCounter = 0; + + priv->wBCNBufLen = sizeof(*short_head) + skb->len; + + MACvSetCurrBCNTxDescAddr(priv->PortOffset, priv->tx_beacon_dma); + + MACvSetCurrBCNLength(priv->PortOffset, priv->wBCNBufLen); + /* Set auto Transmit on */ + MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR, TCR_AUTOBCNTX); + /* Poll Transmit the adapter */ + MACvTransmitBCN(priv->PortOffset); + + return 0; +} + +int vnt_beacon_make(struct vnt_private *priv, struct ieee80211_vif *vif) +{ + struct sk_buff *beacon; + + beacon = ieee80211_beacon_get(priv->hw, vif); + if (!beacon) + return -ENOMEM; + + if (vnt_beacon_xmit(priv, beacon)) { + ieee80211_free_txskb(priv->hw, beacon); + return -ENODEV; + } + + return 0; +} + +int vnt_beacon_enable(struct vnt_private *priv, struct ieee80211_vif *vif, + struct ieee80211_bss_conf *conf) +{ + VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST); + + VNSvOutPortB(priv->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN); + + CARDvSetFirstNextTBTT(priv, conf->beacon_int); + + CARDbSetBeaconPeriod(priv, conf->beacon_int); + + return vnt_beacon_make(priv, vif); +} diff --git a/kernel/drivers/staging/vt6655/rxtx.h b/kernel/drivers/staging/vt6655/rxtx.h new file mode 100644 index 000000000..b9bd1639b --- /dev/null +++ b/kernel/drivers/staging/vt6655/rxtx.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: rxtx.h + * + * Purpose: + * + * Author: Jerry Chen + * + * Date: Jun. 27, 2002 + * + */ + +#ifndef __RXTX_H__ +#define __RXTX_H__ + +#include "device.h" + +#define DEFAULT_MSDU_LIFETIME_RES_64us 8000 /* 64us */ +#define DEFAULT_MGN_LIFETIME_RES_64us 125 /* 64us */ + + +/*--------------------- Export Definitions -------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +/* MIC HDR data header */ +struct vnt_mic_hdr { + u8 id; + u8 tx_priority; + u8 mic_addr2[ETH_ALEN]; + u8 ccmp_pn[IEEE80211_CCMP_PN_LEN]; + __be16 payload_len; + __be16 hlen; + __le16 frame_control; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctrl; + u8 addr4[ETH_ALEN]; + u16 packing; /* packing to 48 bytes */ +} __packed; + +/* RsvTime buffer header */ +struct vnt_rrv_time_rts { + __le16 rts_rrv_time_ba; + __le16 rts_rrv_time_aa; + __le16 rts_rrv_time_bb; + u16 reserved; + __le16 rrv_time_b; + __le16 rrv_time_a; +} __packed; + +struct vnt_rrv_time_cts { + __le16 cts_rrv_time_ba; + u16 reserved; + __le16 rrv_time_b; + __le16 rrv_time_a; +} __packed; + +struct vnt_rrv_time_ab { + __le16 rts_rrv_time; + __le16 rrv_time; +} __packed; + +/* TX data header */ +struct vnt_tx_datahead_g { + struct vnt_phy_field b; + struct vnt_phy_field a; + __le16 duration_b; + __le16 duration_a; + __le16 time_stamp_off_b; + __le16 time_stamp_off_a; +} __packed; + +struct vnt_tx_datahead_g_fb { + struct vnt_phy_field b; + struct vnt_phy_field a; + __le16 duration_b; + __le16 duration_a; + __le16 duration_a_f0; + __le16 duration_a_f1; + __le16 time_stamp_off_b; + __le16 time_stamp_off_a; +} __packed; + +struct vnt_tx_datahead_ab { + struct vnt_phy_field ab; + __le16 duration; + __le16 time_stamp_off; +} __packed; + +struct vnt_tx_datahead_a_fb { + struct vnt_phy_field a; + __le16 duration; + __le16 time_stamp_off; + __le16 duration_f0; + __le16 duration_f1; +} __packed; + +/* RTS buffer header */ +struct vnt_rts_g { + struct vnt_phy_field b; + struct vnt_phy_field a; + __le16 duration_ba; + __le16 duration_aa; + __le16 duration_bb; + u16 reserved; + struct ieee80211_rts data; +} __packed; + +struct vnt_rts_g_fb { + struct vnt_phy_field b; + struct vnt_phy_field a; + __le16 duration_ba; + __le16 duration_aa; + __le16 duration_bb; + u16 wReserved; + __le16 rts_duration_ba_f0; + __le16 rts_duration_aa_f0; + __le16 rts_duration_ba_f1; + __le16 rts_duration_aa_f1; + struct ieee80211_rts data; +} __packed; + +struct vnt_rts_ab { + struct vnt_phy_field ab; + __le16 duration; + u16 reserved; + struct ieee80211_rts data; +} __packed; + +struct vnt_rts_a_fb { + struct vnt_phy_field a; + __le16 duration; + u16 reserved; + __le16 rts_duration_f0; + __le16 rts_duration_f1; + struct ieee80211_rts data; +} __packed; + +/* CTS buffer header */ +struct vnt_cts { + struct vnt_phy_field b; + __le16 duration_ba; + u16 reserved; + struct ieee80211_cts data; + u16 reserved2; +} __packed; + +struct vnt_cts_fb { + struct vnt_phy_field b; + __le16 duration_ba; + u16 reserved; + __le16 cts_duration_ba_f0; + __le16 cts_duration_ba_f1; + struct ieee80211_cts data; + u16 reserved2; +} __packed; + +struct vnt_tx_fifo_head { + u8 tx_key[WLAN_KEY_LEN_CCMP]; + __le16 fifo_ctl; + __le16 time_stamp; + __le16 frag_ctl; + __le16 current_rate; +} __packed; + +struct vnt_tx_short_buf_head { + __le16 fifo_ctl; + u16 time_stamp; + struct vnt_phy_field ab; + __le16 duration; + __le16 time_stamp_off; +} __packed; + +int vnt_generate_fifo_header(struct vnt_private *, u32, + PSTxDesc head_td, struct sk_buff *); +int vnt_beacon_make(struct vnt_private *, struct ieee80211_vif *); +int vnt_beacon_enable(struct vnt_private *, struct ieee80211_vif *, + struct ieee80211_bss_conf *); + +#endif // __RXTX_H__ diff --git a/kernel/drivers/staging/vt6655/srom.c b/kernel/drivers/staging/vt6655/srom.c new file mode 100644 index 000000000..9ec49e653 --- /dev/null +++ b/kernel/drivers/staging/vt6655/srom.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: srom.c + * + * Purpose:Implement functions to access eeprom + * + * Author: Jerry Chen + * + * Date: Jan 29, 2003 + * + * Functions: + * SROMbyReadEmbedded - Embedded read eeprom via MAC + * SROMbWriteEmbedded - Embedded write eeprom via MAC + * SROMvRegBitsOn - Set Bits On in eeprom + * SROMvRegBitsOff - Clear Bits Off in eeprom + * SROMbIsRegBitsOn - Test if Bits On in eeprom + * SROMbIsRegBitsOff - Test if Bits Off in eeprom + * SROMvReadAllContents - Read all contents in eeprom + * SROMvWriteAllContents - Write all contents in eeprom + * SROMvReadEtherAddress - Read Ethernet Address in eeprom + * SROMvWriteEtherAddress - Write Ethernet Address in eeprom + * SROMvReadSubSysVenId - Read Sub_VID and Sub_SysId in eeprom + * SROMbAutoLoad - Auto Load eeprom to MAC register + * + * Revision History: + * + */ + +#include "upc.h" +#include "tmacro.h" +#include "mac.h" +#include "srom.h" + +/*--------------------- Static Definitions -------------------------*/ + +/*--------------------- Static Classes ----------------------------*/ + +/*--------------------- Static Variables --------------------------*/ + +/*--------------------- Static Functions --------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +/* + * Description: Read a byte from EEPROM, by MAC I2C + * + * Parameters: + * In: + * dwIoBase - I/O base address + * byContntOffset - address of EEPROM + * Out: + * none + * + * Return Value: data read + * + */ +unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, unsigned char byContntOffset) +{ + unsigned short wDelay, wNoACK; + unsigned char byWait; + unsigned char byData; + unsigned char byOrg; + + byData = 0xFF; + VNSvInPortB(dwIoBase + MAC_REG_I2MCFG, &byOrg); + /* turn off hardware retry for getting NACK */ + VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY))); + for (wNoACK = 0; wNoACK < W_MAX_I2CRETRY; wNoACK++) { + VNSvOutPortB(dwIoBase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID); + VNSvOutPortB(dwIoBase + MAC_REG_I2MTGAD, byContntOffset); + + /* issue read command */ + VNSvOutPortB(dwIoBase + MAC_REG_I2MCSR, I2MCSR_EEMR); + /* wait DONE be set */ + for (wDelay = 0; wDelay < W_MAX_TIMEOUT; wDelay++) { + VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &byWait); + if (byWait & (I2MCSR_DONE | I2MCSR_NACK)) + break; + PCAvDelayByIO(CB_DELAY_LOOP_WAIT); + } + if ((wDelay < W_MAX_TIMEOUT) && + (!(byWait & I2MCSR_NACK))) { + break; + } + } + VNSvInPortB(dwIoBase + MAC_REG_I2MDIPT, &byData); + VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg); + return byData; +} + +/* + * Description: Read all contents of eeprom to buffer + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * pbyEepromRegs - EEPROM content Buffer + * + * Return Value: none + * + */ +void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs) +{ + int ii; + + /* ii = Rom Address */ + for (ii = 0; ii < EEP_MAX_CONTEXT_SIZE; ii++) { + *pbyEepromRegs = SROMbyReadEmbedded(dwIoBase, (unsigned char)ii); + pbyEepromRegs++; + } +} + +/* + * Description: Read Ethernet Address from eeprom to buffer + * + * Parameters: + * In: + * dwIoBase - I/O base address + * Out: + * pbyEtherAddress - Ethernet Address buffer + * + * Return Value: none + * + */ +void SROMvReadEtherAddress(void __iomem *dwIoBase, unsigned char *pbyEtherAddress) +{ + unsigned char ii; + + /* ii = Rom Address */ + for (ii = 0; ii < ETH_ALEN; ii++) { + *pbyEtherAddress = SROMbyReadEmbedded(dwIoBase, ii); + pbyEtherAddress++; + } +} diff --git a/kernel/drivers/staging/vt6655/srom.h b/kernel/drivers/staging/vt6655/srom.h new file mode 100644 index 000000000..531bf0069 --- /dev/null +++ b/kernel/drivers/staging/vt6655/srom.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * + * File: srom.h + * + * Purpose: Implement functions to access eeprom + * + * Author: Jerry Chen + * + * Date: Jan 29, 2003 + */ + +#ifndef __SROM_H__ +#define __SROM_H__ + +/*--------------------- Export Definitions -------------------------*/ + +#define EEP_MAX_CONTEXT_SIZE 256 + +#define CB_EEPROM_READBYTE_WAIT 900 /* us */ + +#define W_MAX_I2CRETRY 0x0fff + +/* Contents in the EEPROM */ +#define EEP_OFS_PAR 0x00 /* physical address */ +#define EEP_OFS_ANTENNA 0x16 +#define EEP_OFS_RADIOCTL 0x17 +#define EEP_OFS_RFTYPE 0x1B /* for select RF */ +#define EEP_OFS_MINCHANNEL 0x1C /* Min Channel # */ +#define EEP_OFS_MAXCHANNEL 0x1D /* Max Channel # */ +#define EEP_OFS_SIGNATURE 0x1E +#define EEP_OFS_ZONETYPE 0x1F +#define EEP_OFS_RFTABLE 0x20 /* RF POWER TABLE */ +#define EEP_OFS_PWR_CCK 0x20 +#define EEP_OFS_SETPT_CCK 0x21 +#define EEP_OFS_PWR_OFDMG 0x23 +#define EEP_OFS_SETPT_OFDMG 0x24 +#define EEP_OFS_PWR_FORMULA_OST 0x26 +#define EEP_OFS_MAJOR_VER 0x2E +#define EEP_OFS_MINOR_VER 0x2F +#define EEP_OFS_CCK_PWR_TBL 0x30 +#define EEP_OFS_CCK_PWR_dBm 0x3F +#define EEP_OFS_OFDM_PWR_TBL 0x40 +#define EEP_OFS_OFDM_PWR_dBm 0x4F +/*{{ RobertYu: 20041124 */ +#define EEP_OFS_SETPT_OFDMA 0x4E +#define EEP_OFS_OFDMA_PWR_TBL 0x50 +/*}}*/ +#define EEP_OFS_OFDMA_PWR_dBm 0xD2 + +/*----------need to remove --------------------*/ +#define EEP_OFS_BBTAB_LEN 0x70 /* BB Table Length */ +#define EEP_OFS_BBTAB_ADR 0x71 /* BB Table Offset */ +#define EEP_OFS_CHECKSUM 0xFF /* reserved area for baseband 28h~78h */ + +#define EEP_I2C_DEV_ID 0x50 /* EEPROM device address on I2C bus */ + +/* Bits in EEP_OFS_ANTENNA */ +#define EEP_ANTENNA_MAIN 0x01 +#define EEP_ANTENNA_AUX 0x02 +#define EEP_ANTINV 0x04 + +/* Bits in EEP_OFS_RADIOCTL */ +#define EEP_RADIOCTL_ENABLE 0x80 +#define EEP_RADIOCTL_INV 0x01 + +/*--------------------- Export Types ------------------------------*/ + +/*--------------------- Export Macros ------------------------------*/ + +/*--------------------- Export Classes ----------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, + unsigned char byContntOffset); + +void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs); + +void SROMvReadEtherAddress(void __iomem *dwIoBase, + unsigned char *pbyEtherAddress); + +#endif /* __EEPROM_H__*/ diff --git a/kernel/drivers/staging/vt6655/test b/kernel/drivers/staging/vt6655/test new file mode 100644 index 000000000..039f7d71c --- /dev/null +++ b/kernel/drivers/staging/vt6655/test @@ -0,0 +1,9 @@ +KSP := /lib/modules/$(shell uname -r)/build \ + /usr/src/linux-$(shell uname -r) \ + /usr/src/linux-$(shell uname -r | sed 's/-.*//') \ +# /usr/src/kernel-headers-$(shell uname -r) \ +# /usr/src/kernel-source-$(shell uname -r) \ +# /usr/src/linux-$(shell uname -r | sed 's/\([0-9]*\.[0-9]*\)\..*/\1/') \ +# /usr/src/linux /home/plice +test_dir = $(shell [ -e $(dir)/include/linux ] && echo $(dir)) +KSP := $(foreach dir, $(KSP), $(test_dir))
\ No newline at end of file diff --git a/kernel/drivers/staging/vt6655/tmacro.h b/kernel/drivers/staging/vt6655/tmacro.h new file mode 100644 index 000000000..597efefc0 --- /dev/null +++ b/kernel/drivers/staging/vt6655/tmacro.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: tmacro.h + * + * Purpose: define basic common types and macros + * + * Author: Tevin Chen + * + * Date: May 21, 1996 + * + */ + +#ifndef __TMACRO_H__ +#define __TMACRO_H__ + +/****** Common helper macros ***********************************************/ + +#if !defined(LOBYTE) +#define LOBYTE(w) ((unsigned char)(w)) +#endif +#if !defined(HIBYTE) +#define HIBYTE(w) ((unsigned char)(((unsigned short)(w) >> 8) & 0xFF)) +#endif + +#if !defined(LOWORD) +#define LOWORD(d) ((unsigned short)(d)) +#endif +#if !defined(HIWORD) +#define HIWORD(d) ((unsigned short)((((unsigned long)(d)) >> 16) & 0xFFFF)) +#endif + +#define LODWORD(q) ((q).u.dwLowDword) +#define HIDWORD(q) ((q).u.dwHighDword) + +#if !defined(MAKEWORD) +#define MAKEWORD(lb, hb) ((unsigned short)(((unsigned char)(lb)) | (((unsigned short)((unsigned char)(hb))) << 8))) +#endif +#if !defined(MAKEDWORD) +#define MAKEDWORD(lw, hw) ((unsigned long)(((unsigned short)(lw)) | (((unsigned long)((unsigned short)(hw))) << 16))) +#endif + +#endif /* __TMACRO_H__ */ diff --git a/kernel/drivers/staging/vt6655/upc.h b/kernel/drivers/staging/vt6655/upc.h new file mode 100644 index 000000000..cc63dc8d4 --- /dev/null +++ b/kernel/drivers/staging/vt6655/upc.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * File: upc.h + * + * Purpose: Macros to access device + * + * Author: Tevin Chen + * + * Date: Mar 17, 1997 + * + */ + +#ifndef __UPC_H__ +#define __UPC_H__ + +#include "device.h" + +/*--------------------- Export Definitions -------------------------*/ + + +/* For memory mapped IO */ + + +#define VNSvInPortB(dwIOAddress, pbyData) \ +do { \ + *(pbyData) = ioread8(dwIOAddress); \ +} while (0) + +#define VNSvInPortW(dwIOAddress, pwData) \ +do { \ + *(pwData) = ioread16(dwIOAddress); \ +} while (0) + +#define VNSvInPortD(dwIOAddress, pdwData) \ +do { \ + *(pdwData) = ioread32(dwIOAddress); \ +} while (0) + +#define VNSvOutPortB(dwIOAddress, byData) \ +do { \ + iowrite8((u8)byData, dwIOAddress); \ +} while (0) + +#define VNSvOutPortW(dwIOAddress, wData) \ +do { \ + iowrite16((u16)wData, dwIOAddress); \ +} while (0) + +#define VNSvOutPortD(dwIOAddress, dwData) \ +do { \ + iowrite32((u32)dwData, dwIOAddress); \ +} while (0) + +#define PCAvDelayByIO(uDelayUnit) \ +do { \ + unsigned char byData; \ + unsigned long ii; \ + \ + if (uDelayUnit <= 50) { \ + udelay(uDelayUnit); \ + } else { \ + for (ii = 0; ii < (uDelayUnit); ii++) \ + byData = inb(0x61); \ + } \ +} while (0) + +/*--------------------- Export Classes ----------------------------*/ + +/*--------------------- Export Variables --------------------------*/ + +/*--------------------- Export Functions --------------------------*/ + +#endif /* __UPC_H__ */ |