diff options
| author |   José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-11 10:41:07 +0300 |
|---|---|---|
| committer | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-13 08:17:18 +0300 |
| commit | e09b41010ba33a20a87472ee821fa407a5b8da36 (patch) | |
| tree | d10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c | |
| parent | f93b97fd65072de626c074dbe099a1fff05ce060 (diff) | |
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page.
During the rebasing, the following patch collided:
Force tick interrupt and get rid of softirq magic(I70131fb85).
Collisions have been removed because its logic was found on the
source already.
Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769
Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c')
| -rw-r--r-- | kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 1304 |
1 files changed, 724 insertions, 580 deletions
diff --git a/kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index fdd2c8729..87a4f4414 100644 --- a/kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/kernel/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -9,20 +9,34 @@ */ #include <linux/kernel.h> -#include <linux/platform_data/gpio-rcar.h> #include "core.h" #include "sh_pfc.h" +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ + PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ - PORT_GP_32(7, fn, sfx) + PORT_GP_26(7, fn, sfx) enum { PINMUX_RESERVED = 0, @@ -809,459 +823,459 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP0_14, D14), PINMUX_IPSR_DATA(IP0_15, D15), PINMUX_IPSR_DATA(IP0_18_16, A0), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), - PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2), + PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2), PINMUX_IPSR_DATA(IP0_18_16, PWM2_B), PINMUX_IPSR_DATA(IP0_20_19, A1), - PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_22_21, A2), - PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_24_23, A3), - PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_26_25, A4), - PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_28_27, A5), - PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), PINMUX_IPSR_DATA(IP0_30_29, A6), - PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), /* IPSR1 */ PINMUX_IPSR_DATA(IP1_1_0, A7), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), PINMUX_IPSR_DATA(IP1_3_2, A8), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0), + PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0), PINMUX_IPSR_DATA(IP1_5_4, A9), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0), + PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0), PINMUX_IPSR_DATA(IP1_7_6, A10), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_10_8, A11), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), + PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3), + PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_13_11, A12), - PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3), - PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3), + PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_16_14, A13), - PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_19_17, A14), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2), - PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), + PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), PINMUX_IPSR_DATA(IP1_22_20, A15), - PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), PINMUX_IPSR_DATA(IP1_25_23, A16), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2), - PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP1_28_26, A17), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2), + PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2), PINMUX_IPSR_DATA(IP1_31_29, A18), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), /* IPSR2 */ PINMUX_IPSR_DATA(IP2_2_0, A19), PINMUX_IPSR_DATA(IP2_2_0, DACK1), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), - PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP2_2_0, A20), - PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0), PINMUX_IPSR_DATA(IP2_6_5, A21), - PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0), PINMUX_IPSR_DATA(IP2_9_7, A22), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), PINMUX_IPSR_DATA(IP2_12_10, A23), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), + PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), PINMUX_IPSR_DATA(IP2_15_13, A24), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP2_18_16, A25), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0), + PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP2_20_19, CS0_N), - PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0), PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26), - PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0), PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N), - PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N), - PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0), PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1), /* IPSR3 */ PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N), - PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0), - PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2), PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N), PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP3_5_3, PWM1), PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1), PINMUX_IPSR_DATA(IP3_8_6, BS_N), PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), + PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), + PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), PINMUX_IPSR_DATA(IP3_8_6, PWM2), PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2), PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), - PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1), PINMUX_IPSR_DATA(IP3_13_12, WE0_N), - PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP3_15_14, WE1_N), - PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1), - PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0), - PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), PINMUX_IPSR_DATA(IP3_19_18, DREQ0), PINMUX_IPSR_DATA(IP3_19_18, PWM3), PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3), PINMUX_IPSR_DATA(IP3_21_20, DACK0), PINMUX_IPSR_DATA(IP3_21_20, DRACK0), - PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), + PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), + PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2), + PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2), + PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2), + PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), /* IPSR4 */ - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1), - PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), + PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1), + PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1), + PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1), + PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1), + PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1), + PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1), + PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), + PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1), + PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1), + PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2), - PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4), - PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2), - PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), PINMUX_IPSR_DATA(IP4_19, SSI_SCK34), PINMUX_IPSR_DATA(IP4_20, SSI_WS34), PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3), PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4), - PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4), - PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4), - PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B), /* IPSR5 */ PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B), PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B), PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), + PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B), PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), + PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B), PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B), - PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), - PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), - PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), - PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3), - PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3), + PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3), + PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), /* IPSR6 */ - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), - PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), + PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), + PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), - PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_DATA(IP6_9_8, IRQ0), - PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), PINMUX_IPSR_DATA(IP6_11_10, IRQ1), - PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), + PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), PINMUX_IPSR_DATA(IP6_13_12, IRQ2), - PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), + PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_DATA(IP6_15_14, IRQ3), - PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), - PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2), + PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_DATA(IP6_18_16, IRQ4), - PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), - PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2), + PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_DATA(IP6_20_19, IRQ5), - PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), - PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4), + PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_23_21, IRQ6), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), - PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), + PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4), + PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), PINMUX_IPSR_DATA(IP6_26_24, IRQ7), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP6_29_27, IRQ8), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), + PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), /* IPSR7 */ PINMUX_IPSR_DATA(IP7_2_0, IRQ9), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), + PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), + PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), + PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0), PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1), PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), + PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2), PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2), - PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3), PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3), - PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4), PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4), - PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), + PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5), PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5), - PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6), PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6), - PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7), PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7), - PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0), PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1), PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2), PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), /* IPSR8 */ PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3), PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4), PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5), PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6), PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7), PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), + PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0), PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1), PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), + PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2), PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18), - PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B), - PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3), PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19), - PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4), PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), - PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), + PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5), PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0), /* IPSR9 */ PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6), PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2), + PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7), PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), + PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2), + PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS), PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0), PINMUX_IPSR_DATA(IP9_7, QCLK), PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE), - PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1), PINMUX_IPSR_DATA(IP9_10_8, PWM4), PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC), PINMUX_IPSR_DATA(IP9_11, QSTH_QHS), @@ -1269,280 +1283,280 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP9_12, QSTB_QHE), PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE), - PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1), PINMUX_IPSR_DATA(IP9_16, DU1_DISP), PINMUX_IPSR_DATA(IP9_16, QPOLA), PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE), PINMUX_IPSR_DATA(IP9_18_17, QPOLB), PINMUX_IPSR_DATA(IP9_18_17, PWM4_B), PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3), - PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP9_31_29, VI0_G0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0), + PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0), + PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N), /* IPSR10 */ PINMUX_IPSR_DATA(IP10_2_0, VI0_G1), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0), + PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0), + PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N), PINMUX_IPSR_DATA(IP10_5_3, VI0_G2), PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1), + PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N), PINMUX_IPSR_DATA(IP10_8_6, VI0_G3), PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1), + PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N), PINMUX_IPSR_DATA(IP10_11_9, VI0_G4), PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), + PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), + PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), PINMUX_IPSR_DATA(IP10_14_12, VI0_G5), PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), + PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), PINMUX_IPSR_DATA(IP10_16_15, VI0_G6), PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK), - PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), PINMUX_IPSR_DATA(IP10_18_17, VI0_G7), PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), PINMUX_IPSR_DATA(IP10_21_19, VI0_R0), PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N), PINMUX_IPSR_DATA(IP10_24_22, VI0_R1), PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N), PINMUX_IPSR_DATA(IP10_26_25, VI0_R2), PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_28_27, VI0_R3), PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4), - PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), PINMUX_IPSR_DATA(IP10_31_29, VI0_R4), PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3), + PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3), /* IPSR11 */ PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3), PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1), PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), - PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), - PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), - PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), - PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), - PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), - PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), - PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), - PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), - PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), - PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), - PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0), PINMUX_IPSR_DATA(IP11_27, AVB_MDC), PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2), PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), - PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2), /* IPSR12 */ PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), - PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), - PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0), PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), - PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), - PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0), PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), - PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), - PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), - PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), - PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), - PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), - PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), - PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), - PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), - PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), - PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), - PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), /* IPSR13 */ - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), + PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), - PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), + PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), PINMUX_IPSR_DATA(IP13_10, SD0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_11, SD0_CMD), - PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), + PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1), PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), - PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1), + PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), + PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2), PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), - PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), + PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1), + PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), + PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2), PINMUX_IPSR_DATA(IP13_22, SD1_CMD), - PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), PINMUX_IPSR_DATA(IP13_30_28, PWM0), PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), - PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2), /* IPSR14 */ PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), - PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2), PINMUX_IPSR_DATA(IP14_2, SD2_CLK), PINMUX_IPSR_DATA(IP14_2, MMC_CLK), PINMUX_IPSR_DATA(IP14_3, SD2_CMD), @@ -1557,123 +1571,123 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP14_7, MMC_D3), PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), - PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), - PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2), + PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), - PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), - PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), - PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2), + PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), - PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), - PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), + PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2), PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), + PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), + PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), + PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), + PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2), PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), /* IPSR15 */ - PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), - PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), - PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), + PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), + PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), + PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), - PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), PINMUX_IPSR_DATA(IP15_11_9, PWM5), PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), - PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), + PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), PINMUX_IPSR_DATA(IP15_14_12, PWM6), PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), - PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), - PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), + PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), + PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0), + PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0), PINMUX_IPSR_DATA(IP15_23_21, TCLK2), - PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), - PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), - PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), + PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), /* IPSR16 */ - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), - PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), + PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), + PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK), - PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), - PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), - PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), - PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), }; static const struct sh_pfc_pin pinmux_pins[] = { @@ -2928,6 +2942,79 @@ static const unsigned int msiof2_tx_e_pins[] = { static const unsigned int msiof2_tx_e_mux[] = { MSIOF2_TXD_E_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(6, 14), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(5, 30), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(1, 17), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + RCAR_GP_PIN(6, 15), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(1, 18), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + RCAR_GP_PIN(0, 16), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(1, 24), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(3, 26), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + RCAR_GP_PIN(3, 31), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(7, 21), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + RCAR_GP_PIN(7, 20), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(7, 22), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3898,24 +3985,6 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; - -union vin_data { - unsigned int data24[24]; - unsigned int data20[20]; - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -#define VIN_DATA_PIN_GROUP(n, s) \ - { \ - .name = #n#s, \ - .pins = n##_pins.data##s, \ - .mux = n##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ - } - /* - VIN0 ------------------------------------------------------------------- */ static const union vin_data vin0_data_pins = { .data24 = { @@ -4348,6 +4417,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_sync_e), SH_PFC_PIN_GROUP(msiof2_rx_e), SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -4745,6 +4826,39 @@ static const char * const msiof2_groups[] = { "msiof2_tx_e", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -4989,6 +5103,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -6000,7 +6121,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, 2, 2, 1, 2, 2, 2) { - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SCIF1 [2] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, @@ -6027,11 +6148,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_VI1 [2] */ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_TMU [1] */ FN_SEL_TMU1_0, FN_SEL_TMU1_1, @@ -6049,7 +6170,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 0, 0, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SCIF [1] */ FN_SEL_SCIF_0, FN_SEL_SCIF_1, @@ -6059,13 +6180,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* SEL_CAN1 [2] */ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SCIFA2 [1] */ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, /* SEL_SCIF4 [2] */ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_ADG [1] */ FN_SEL_ADG_0, FN_SEL_ADG_1, @@ -6075,7 +6196,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* SEL_SCIFA5 [2] */ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_GPS [2] */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, @@ -6085,7 +6206,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, /* SEL_SIM [1] */ FN_SEL_SIM_0, FN_SEL_SIM_1, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SSI8 [1] */ FN_SEL_SSI8_0, FN_SEL_SSI8_1, } @@ -6115,7 +6236,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_MMC_0, FN_SEL_MMC_1, /* SEL_SCIF5 [1] */ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_IIC2 [2] */ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, @@ -6125,11 +6246,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* SEL_IIC0 [2] */ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, @@ -6143,7 +6264,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, /* SEL_DIS [2] */ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_RAD [1] */ FN_SEL_RAD_0, FN_SEL_RAD_1, @@ -6155,15 +6276,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, /* SEL_SOF2 [3] */ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, FN_SEL_SOF2_4, 0, 0, 0, - /* RESEVED [1] */ + /* RESERVED [1] */ 0, 0, /* SEL_SSI1 [1] */ FN_SEL_SSI1_0, FN_SEL_SSI1_1, @@ -6171,16 +6292,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SSI0_0, FN_SEL_SSI0_1, /* SEL_SSP [2] */ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, - /* RESEVED [2] */ + /* RESERVED [2] */ 0, 0, 0, 0, } }, { }, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", .unlock_reg = 0xe6060000, /* PMMR */ @@ -6196,6 +6318,28 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7793 +const struct sh_pfc_soc_info r8a7793_pinmux_info = { + .name = "r8a77930_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif |