diff options
author | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-11 10:41:07 +0300 |
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committer | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-13 08:17:18 +0300 |
commit | e09b41010ba33a20a87472ee821fa407a5b8da36 (patch) | |
tree | d10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/drivers/clk/tegra/cvb.h | |
parent | f93b97fd65072de626c074dbe099a1fff05ce060 (diff) |
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page.
During the rebasing, the following patch collided:
Force tick interrupt and get rid of softirq magic(I70131fb85).
Collisions have been removed because its logic was found on the
source already.
Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769
Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/drivers/clk/tegra/cvb.h')
-rw-r--r-- | kernel/drivers/clk/tegra/cvb.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/kernel/drivers/clk/tegra/cvb.h b/kernel/drivers/clk/tegra/cvb.h new file mode 100644 index 000000000..f62cdc4f4 --- /dev/null +++ b/kernel/drivers/clk/tegra/cvb.h @@ -0,0 +1,67 @@ +/* + * Utility functions for parsing Tegra CVB voltage tables + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __DRIVERS_CLK_TEGRA_CVB_H +#define __DRIVERS_CLK_TEGRA_CVB_H + +#include <linux/types.h> + +struct device; + +#define MAX_DVFS_FREQS 40 + +struct rail_alignment { + int offset_uv; + int step_uv; +}; + +struct cvb_coefficients { + int c0; + int c1; + int c2; +}; + +struct cvb_table_freq_entry { + unsigned long freq; + struct cvb_coefficients coefficients; +}; + +struct cvb_cpu_dfll_data { + u32 tune0_low; + u32 tune0_high; + u32 tune1; +}; + +struct cvb_table { + int speedo_id; + int process_id; + + int min_millivolts; + int max_millivolts; + struct rail_alignment alignment; + + int speedo_scale; + int voltage_scale; + struct cvb_table_freq_entry cvb_table[MAX_DVFS_FREQS]; + struct cvb_cpu_dfll_data cpu_dfll_data; +}; + +const struct cvb_table *tegra_cvb_build_opp_table( + const struct cvb_table *cvb_tables, + size_t sz, int process_id, + int speedo_id, int speedo_value, + unsigned long max_rate, + struct device *opp_dev); + +#endif |