diff options
author | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-11 10:41:07 +0300 |
---|---|---|
committer | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-13 08:17:18 +0300 |
commit | e09b41010ba33a20a87472ee821fa407a5b8da36 (patch) | |
tree | d10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/drivers/clk/shmobile/clk-div6.c | |
parent | f93b97fd65072de626c074dbe099a1fff05ce060 (diff) |
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page.
During the rebasing, the following patch collided:
Force tick interrupt and get rid of softirq magic(I70131fb85).
Collisions have been removed because its logic was found on the
source already.
Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769
Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/drivers/clk/shmobile/clk-div6.c')
-rw-r--r-- | kernel/drivers/clk/shmobile/clk-div6.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/drivers/clk/shmobile/clk-div6.c b/kernel/drivers/clk/shmobile/clk-div6.c index 036a692c7..b4c8d6746 100644 --- a/kernel/drivers/clk/shmobile/clk-div6.c +++ b/kernel/drivers/clk/shmobile/clk-div6.c @@ -11,12 +11,12 @@ */ #include <linux/clk-provider.h> -#include <linux/clkdev.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/slab.h> #define CPG_DIV6_CKSTP BIT(8) #define CPG_DIV6_DIV(d) ((d) & 0x3f) @@ -133,13 +133,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) hw_index = (clk_readl(clock->reg) >> clock->src_shift) & (BIT(clock->src_width) - 1); - for (i = 0; i < __clk_get_num_parents(hw->clk); i++) { + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (clock->parents[i] == hw_index) return i; } pr_err("%s: %s DIV6 clock set to invalid parent %u\n", - __func__, __clk_get_name(hw->clk), hw_index); + __func__, clk_hw_get_name(hw), hw_index); return 0; } @@ -149,7 +149,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) u8 hw_index; u32 mask; - if (index >= __clk_get_num_parents(hw->clk)) + if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); |