diff options
author | Don Dugger <donald.d.dugger@intel.com> | 2015-10-29 22:15:25 +0000 |
---|---|---|
committer | Gerrit Code Review <gerrit@172.30.200.206> | 2015-10-29 22:15:25 +0000 |
commit | afc76d554ed517e38d46b6b182a7016406a1323f (patch) | |
tree | 06133cb33a43488837ea67667458e1582f2f40ce /kernel/drivers/clk/pxa | |
parent | 41f827bfbb10e03c4d228fbcc801dd51fb9983b0 (diff) | |
parent | ec0a2ed6d8a5e555edef907895c041e285fdb495 (diff) |
Merge "These changes are a raw update to a vanilla kernel 4.1.10, with the recently announced rt patch patch-4.1.10-rt10.patch. No further changes needed."
Diffstat (limited to 'kernel/drivers/clk/pxa')
-rw-r--r-- | kernel/drivers/clk/pxa/clk-pxa25x.c | 2 | ||||
-rw-r--r-- | kernel/drivers/clk/pxa/clk-pxa27x.c | 2 | ||||
-rw-r--r-- | kernel/drivers/clk/pxa/clk-pxa3xx.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/kernel/drivers/clk/pxa/clk-pxa25x.c b/kernel/drivers/clk/pxa/clk-pxa25x.c index 6cd88d963..542e45ef5 100644 --- a/kernel/drivers/clk/pxa/clk-pxa25x.c +++ b/kernel/drivers/clk/pxa/clk-pxa25x.c @@ -79,7 +79,7 @@ unsigned int pxa25x_get_clk_frequency_khz(int info) clks[3] / 1000000, (clks[3] % 1000000) / 10000); } - return (unsigned int)clks[0]; + return (unsigned int)clks[0] / KHz; } static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw, diff --git a/kernel/drivers/clk/pxa/clk-pxa27x.c b/kernel/drivers/clk/pxa/clk-pxa27x.c index 5f9b54b02..267511df1 100644 --- a/kernel/drivers/clk/pxa/clk-pxa27x.c +++ b/kernel/drivers/clk/pxa/clk-pxa27x.c @@ -80,7 +80,7 @@ unsigned int pxa27x_get_clk_frequency_khz(int info) pr_info("System bus clock: %ld.%02ldMHz\n", clks[4] / 1000000, (clks[4] % 1000000) / 10000); } - return (unsigned int)clks[0]; + return (unsigned int)clks[0] / KHz; } bool pxa27x_is_ppll_disabled(void) diff --git a/kernel/drivers/clk/pxa/clk-pxa3xx.c b/kernel/drivers/clk/pxa/clk-pxa3xx.c index ac03ba49e..4af4eed5f 100644 --- a/kernel/drivers/clk/pxa/clk-pxa3xx.c +++ b/kernel/drivers/clk/pxa/clk-pxa3xx.c @@ -78,7 +78,7 @@ unsigned int pxa3xx_get_clk_frequency_khz(int info) pr_info("System bus clock: %ld.%02ldMHz\n", clks[4] / 1000000, (clks[4] % 1000000) / 10000); } - return (unsigned int)clks[0]; + return (unsigned int)clks[0] / KHz; } static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw, |