diff options
author | 2015-08-04 12:17:53 -0700 | |
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committer | 2015-08-04 15:44:42 -0700 | |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/x86/pci/mmconfig_32.c | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/x86/pci/mmconfig_32.c')
-rw-r--r-- | kernel/arch/x86/pci/mmconfig_32.c | 157 |
1 files changed, 157 insertions, 0 deletions
diff --git a/kernel/arch/x86/pci/mmconfig_32.c b/kernel/arch/x86/pci/mmconfig_32.c new file mode 100644 index 000000000..43984bc16 --- /dev/null +++ b/kernel/arch/x86/pci/mmconfig_32.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx> + * Copyright (C) 2004 Intel Corp. + * + * This code is released under the GNU General Public License version 2. + */ + +/* + * mmconfig.c - Low-level direct PCI config space access via MMCONFIG + */ + +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/rcupdate.h> +#include <asm/e820.h> +#include <asm/pci_x86.h> + +/* Assume systems with more busses have correct MCFG */ +#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG)) + +/* The base address of the last MMCONFIG device accessed */ +static u32 mmcfg_last_accessed_device; +static int mmcfg_last_accessed_cpu; + +/* + * Functions for accessing PCI configuration space with MMCONFIG accesses + */ +static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn) +{ + struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); + + if (cfg) + return cfg->address; + return 0; +} + +/* + * This is always called under pci_config_lock + */ +static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) +{ + u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); + int cpu = smp_processor_id(); + if (dev_base != mmcfg_last_accessed_device || + cpu != mmcfg_last_accessed_cpu) { + mmcfg_last_accessed_device = dev_base; + mmcfg_last_accessed_cpu = cpu; + set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); + } +} + +static int pci_mmcfg_read(unsigned int seg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *value) +{ + unsigned long flags; + u32 base; + + if ((bus > 255) || (devfn > 255) || (reg > 4095)) { +err: *value = -1; + return -EINVAL; + } + + rcu_read_lock(); + base = get_base_addr(seg, bus, devfn); + if (!base) { + rcu_read_unlock(); + goto err; + } + + raw_spin_lock_irqsave(&pci_config_lock, flags); + + pci_exp_set_dev_base(base, bus, devfn); + + switch (len) { + case 1: + *value = mmio_config_readb(mmcfg_virt_addr + reg); + break; + case 2: + *value = mmio_config_readw(mmcfg_virt_addr + reg); + break; + case 4: + *value = mmio_config_readl(mmcfg_virt_addr + reg); + break; + } + raw_spin_unlock_irqrestore(&pci_config_lock, flags); + rcu_read_unlock(); + + return 0; +} + +static int pci_mmcfg_write(unsigned int seg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 value) +{ + unsigned long flags; + u32 base; + + if ((bus > 255) || (devfn > 255) || (reg > 4095)) + return -EINVAL; + + rcu_read_lock(); + base = get_base_addr(seg, bus, devfn); + if (!base) { + rcu_read_unlock(); + return -EINVAL; + } + + raw_spin_lock_irqsave(&pci_config_lock, flags); + + pci_exp_set_dev_base(base, bus, devfn); + + switch (len) { + case 1: + mmio_config_writeb(mmcfg_virt_addr + reg, value); + break; + case 2: + mmio_config_writew(mmcfg_virt_addr + reg, value); + break; + case 4: + mmio_config_writel(mmcfg_virt_addr + reg, value); + break; + } + raw_spin_unlock_irqrestore(&pci_config_lock, flags); + rcu_read_unlock(); + + return 0; +} + +const struct pci_raw_ops pci_mmcfg = { + .read = pci_mmcfg_read, + .write = pci_mmcfg_write, +}; + +int __init pci_mmcfg_arch_init(void) +{ + printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n"); + raw_pci_ext_ops = &pci_mmcfg; + return 1; +} + +void __init pci_mmcfg_arch_free(void) +{ +} + +int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg) +{ + return 0; +} + +void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg) +{ + unsigned long flags; + + /* Invalidate the cached mmcfg map entry. */ + raw_spin_lock_irqsave(&pci_config_lock, flags); + mmcfg_last_accessed_device = 0; + raw_spin_unlock_irqrestore(&pci_config_lock, flags); +} |