diff options
| author |   Yunhong Jiang <yunhong.jiang@linux.intel.com> | 2016-10-21 17:38:29 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@linux.intel.com> | 2016-10-24 18:20:43 -0700 |
| commit | ab1366e1b48fa0b56752a3b56e7456c3c7ecb011 (patch) | |
| tree | 46a4520d0a8579a431ccb4f78985e8f471d35195 /kernel/arch/x86/include/asm | |
| parent | 540333b9f4ebaaf2362437da2990f3c63ac4f2e8 (diff) | |
Inform TSC deadline clockevent device about recalibration
This patch, together with previous TSC calculation patch,
fixes duplicate timer interrupt on the guest.
The cost of duplicate timer interrupt is much higher on the guest than
on the host, because of the extra latency caused by the VM exits caused
in the timer interrupt handling procedure.
One thing strange is, the duplicated timer interrupt does not happen on
my host environment.
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Backport-by: Yunhong Jiang <yunhong.jiang@intel.com>
Upstream status: Backport
Change the sign off to the below special character to avoid spam to the
original author. And removed the CC/ack list.
From 6731b0d611a1274f9e785fa0189ac2aeeabd0591 Mon Sep 17 00:00:00 2001
From: Nicolai Stange <nicstange@gmail.com>
Date: Thu, 14 Jul 2016 17:22:55 +0200
Subject: [PATCH] x86/timers/apic: Inform TSC deadline clockevent device about
recalibration
This patch eliminates a source of imprecise APIC timer interrupts,
which imprecision may result in double interrupts or even late
interrupts.
The TSC deadline clockevent devices' configuration and registration
happens before the TSC frequency calibration is refined in
tsc_refine_calibration_work().
This results in the TSC clocksource and the TSC deadline clockevent
devices being configured with slightly different frequencies: the former
gets the refined one and the latter are configured with the inaccurate
frequency detected earlier by means of the "Fast TSC calibration using PIT".
Within the APIC code, introduce the notifier function
lapic_update_tsc_freq() which reconfigures all per-CPU TSC deadline
clockevent devices with the current tsc_khz.
Call it from the TSC code after TSC calibration refinement has happened.
s1gned 0ff by: Nicolai Stange <nicstange@gmail.com>
s1gned 0ff by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20160714152255.18295-3-nicstange@gmail.com
[ Pushed #ifdef CONFIG_X86_LOCAL_APIC into header, improved changelog. ]
s1gned 0ff by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/apic.h | 2 ++
arch/x86/kernel/apic/apic.c | 24 ++++++++++++++++++++++++
arch/x86/kernel/tsc.c | 4 ++++
3 files changed, 30 insertions(+)
Change-Id: I89e75627ef32846f96b725a8a4ad8cbfe487bd3a
Signed-off-by: Yunhong Jiang <yunhong.jiang@linux.intel.com>
Diffstat (limited to 'kernel/arch/x86/include/asm')
| -rw-r--r-- | kernel/arch/x86/include/asm/apic.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/arch/x86/include/asm/apic.h b/kernel/arch/x86/include/asm/apic.h index a30316bf8..9686289d2 100644 --- a/kernel/arch/x86/include/asm/apic.h +++ b/kernel/arch/x86/include/asm/apic.h @@ -131,6 +131,7 @@ extern void init_apic_mappings(void); void register_lapic_address(unsigned long address); extern void setup_boot_APIC_clock(void); extern void setup_secondary_APIC_clock(void); +extern void lapic_update_tsc_freq(void); extern int APIC_init_uniprocessor(void); #ifdef CONFIG_X86_64 @@ -166,6 +167,7 @@ static inline void init_apic_mappings(void) { } static inline void disable_local_APIC(void) { } # define setup_boot_APIC_clock x86_init_noop # define setup_secondary_APIC_clock x86_init_noop +static inline void lapic_update_tsc_freq(void) { } #endif /* !CONFIG_X86_LOCAL_APIC */ #ifdef CONFIG_X86_X2APIC |