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author | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
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committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/unicore32/include/mach/regs-ost.h | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/unicore32/include/mach/regs-ost.h')
-rw-r--r-- | kernel/arch/unicore32/include/mach/regs-ost.h | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/kernel/arch/unicore32/include/mach/regs-ost.h b/kernel/arch/unicore32/include/mach/regs-ost.h new file mode 100644 index 000000000..4a85fb463 --- /dev/null +++ b/kernel/arch/unicore32/include/mach/regs-ost.h @@ -0,0 +1,90 @@ +/* + * PKUnity Operating System Timer (OST) Registers + */ +/* + * Match Reg 0 OST_OSMR0 + */ +#define OST_OSMR0 (PKUNITY_OST_BASE + 0x0000) +/* + * Match Reg 1 OST_OSMR1 + */ +#define OST_OSMR1 (PKUNITY_OST_BASE + 0x0004) +/* + * Match Reg 2 OST_OSMR2 + */ +#define OST_OSMR2 (PKUNITY_OST_BASE + 0x0008) +/* + * Match Reg 3 OST_OSMR3 + */ +#define OST_OSMR3 (PKUNITY_OST_BASE + 0x000C) +/* + * Counter Reg OST_OSCR + */ +#define OST_OSCR (PKUNITY_OST_BASE + 0x0010) +/* + * Status Reg OST_OSSR + */ +#define OST_OSSR (PKUNITY_OST_BASE + 0x0014) +/* + * Watchdog Enable Reg OST_OWER + */ +#define OST_OWER (PKUNITY_OST_BASE + 0x0018) +/* + * Interrupt Enable Reg OST_OIER + */ +#define OST_OIER (PKUNITY_OST_BASE + 0x001C) + +/* + * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80 + * PWCR: Pulse Width Control Reg + * DCCR: Duty Cycle Control Reg + * PCR: Period Control Reg + */ +#define OST_PWM_PWCR (0x00) +#define OST_PWM_DCCR (0x04) +#define OST_PWM_PCR (0x08) + +/* + * Match detected 0 OST_OSSR_M0 + */ +#define OST_OSSR_M0 FIELD(1, 1, 0) +/* + * Match detected 1 OST_OSSR_M1 + */ +#define OST_OSSR_M1 FIELD(1, 1, 1) +/* + * Match detected 2 OST_OSSR_M2 + */ +#define OST_OSSR_M2 FIELD(1, 1, 2) +/* + * Match detected 3 OST_OSSR_M3 + */ +#define OST_OSSR_M3 FIELD(1, 1, 3) + +/* + * Interrupt enable 0 OST_OIER_E0 + */ +#define OST_OIER_E0 FIELD(1, 1, 0) +/* + * Interrupt enable 1 OST_OIER_E1 + */ +#define OST_OIER_E1 FIELD(1, 1, 1) +/* + * Interrupt enable 2 OST_OIER_E2 + */ +#define OST_OIER_E2 FIELD(1, 1, 2) +/* + * Interrupt enable 3 OST_OIER_E3 + */ +#define OST_OIER_E3 FIELD(1, 1, 3) + +/* + * Watchdog Match Enable OST_OWER_WME + */ +#define OST_OWER_WME FIELD(1, 1, 0) + +/* + * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE + */ +#define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10) + |