diff options
| author |   Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
| commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
| tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/unicore32/include/mach/regs-nand.h | |
| parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) | |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/unicore32/include/mach/regs-nand.h')
| -rw-r--r-- | kernel/arch/unicore32/include/mach/regs-nand.h | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/kernel/arch/unicore32/include/mach/regs-nand.h b/kernel/arch/unicore32/include/mach/regs-nand.h new file mode 100644 index 000000000..a7c5563bb --- /dev/null +++ b/kernel/arch/unicore32/include/mach/regs-nand.h @@ -0,0 +1,79 @@ +/* + * PKUnity NAND Controller Registers + */ +/* + * ID Reg. 0 NAND_IDR0 + */ +#define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000) +/* + * ID Reg. 1 NAND_IDR1 + */ +#define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004) +/* + * ID Reg. 2 NAND_IDR2 + */ +#define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008) +/* + * ID Reg. 3 NAND_IDR3 + */ +#define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C) +/* + * Page Address Reg 0 NAND_PAR0 + */ +#define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010) +/* + * Page Address Reg 1 NAND_PAR1 + */ +#define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014) +/* + * Page Address Reg 2 NAND_PAR2 + */ +#define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018) +/* + * ECC Enable Reg NAND_ECCEN + */ +#define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C) +/* + * Buffer Reg NAND_BUF + */ +#define NAND_BUF (PKUNITY_NAND_BASE + 0x0020) +/* + * ECC Status Reg NAND_ECCSR + */ +#define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024) +/* + * Command Reg NAND_CMD + */ +#define NAND_CMD (PKUNITY_NAND_BASE + 0x0028) +/* + * DMA Configure Reg NAND_DMACR + */ +#define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C) +/* + * Interrupt Reg NAND_IR + */ +#define NAND_IR (PKUNITY_NAND_BASE + 0x0030) +/* + * Interrupt Mask Reg NAND_IMR + */ +#define NAND_IMR (PKUNITY_NAND_BASE + 0x0034) +/* + * Chip Enable Reg NAND_CHIPEN + */ +#define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038) +/* + * Address Reg NAND_ADDR + */ +#define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C) + +/* + * Command bits NAND_CMD_CMD_MASK + */ +#define NAND_CMD_CMD_MASK FMASK(4, 4) +#define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4) +#define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4) +#define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4) +#define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4) +#define NAND_CMD_CMD_READID FIELD(0x9, 4, 4) +#define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4) + |