diff options
| author |   Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
| commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
| tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/unicore32/include/asm/fpu-ucf64.h | |
| parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) | |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/unicore32/include/asm/fpu-ucf64.h')
| -rw-r--r-- | kernel/arch/unicore32/include/asm/fpu-ucf64.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/kernel/arch/unicore32/include/asm/fpu-ucf64.h b/kernel/arch/unicore32/include/asm/fpu-ucf64.h new file mode 100644 index 000000000..16c145788 --- /dev/null +++ b/kernel/arch/unicore32/include/asm/fpu-ucf64.h @@ -0,0 +1,53 @@ +/* + * linux/arch/unicore32/include/asm/fpu-ucf64.h + * + * Code specific to PKUnity SoC and UniCore ISA + * + * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> + * Copyright (C) 2001-2010 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#define FPSCR s31 + +/* FPSCR bits */ +#define FPSCR_DEFAULT_NAN (1<<25) + +#define FPSCR_CMPINSTR_BIT (1<<31) + +#define FPSCR_CON (1<<29) +#define FPSCR_TRAP (1<<27) + +/* RND mode */ +#define FPSCR_ROUND_NEAREST (0<<0) +#define FPSCR_ROUND_PLUSINF (2<<0) +#define FPSCR_ROUND_MINUSINF (3<<0) +#define FPSCR_ROUND_TOZERO (1<<0) +#define FPSCR_RMODE_BIT (0) +#define FPSCR_RMODE_MASK (7 << FPSCR_RMODE_BIT) + +/* trap enable */ +#define FPSCR_IOE (1<<16) +#define FPSCR_OFE (1<<14) +#define FPSCR_UFE (1<<13) +#define FPSCR_IXE (1<<12) +#define FPSCR_HIE (1<<11) +#define FPSCR_NDE (1<<10) /* non denomal */ + +/* flags */ +#define FPSCR_IDC (1<<24) +#define FPSCR_HIC (1<<23) +#define FPSCR_IXC (1<<22) +#define FPSCR_OFC (1<<21) +#define FPSCR_UFC (1<<20) +#define FPSCR_IOC (1<<19) + +/* stick bits */ +#define FPSCR_IOS (1<<9) +#define FPSCR_OFS (1<<7) +#define FPSCR_UFS (1<<6) +#define FPSCR_IXS (1<<5) +#define FPSCR_HIS (1<<4) +#define FPSCR_NDS (1<<3) /*non denomal */ |