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| author |   Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
| commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
| tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/sh/include/cpu-sh3/cpu/mmu_context.h | |
| parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) | |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/sh/include/cpu-sh3/cpu/mmu_context.h')
| -rw-r--r-- | kernel/arch/sh/include/cpu-sh3/cpu/mmu_context.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/kernel/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/kernel/arch/sh/include/cpu-sh3/cpu/mmu_context.h new file mode 100644 index 000000000..0c7c735ea --- /dev/null +++ b/kernel/arch/sh/include/cpu-sh3/cpu/mmu_context.h @@ -0,0 +1,45 @@ +/* + * include/asm-sh/cpu-sh3/mmu_context.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H +#define __ASM_CPU_SH3_MMU_CONTEXT_H + +#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */ +#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */ +#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */ +#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ + +#define MMUCR 0xFFFFFFE0 /* MMU Control Register */ +#define MMUCR_TI (1 << 2) /* TLB flush bit */ + +#define MMU_TLB_ADDRESS_ARRAY 0xF2000000 +#define MMU_PAGE_ASSOC_BIT 0x80 + +#define MMU_NTLB_ENTRIES 128 /* for 7708 */ +#define MMU_NTLB_WAYS 4 +#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ + +#define TRA 0xffffffd0 +#define EXPEVT 0xffffffd4 + +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7706) || \ + defined(CONFIG_CPU_SUBTYPE_SH7707) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7712) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) +#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ +#else +#define INTEVT 0xffffffd8 +#endif + +#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ + |