Add the rt linux 4.1.3-rt3 as base

Import the rt linux 4.1.3-rt3 as OPNFV kvm base.

It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:

commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Sat Jul 25 12:13:34 2015 +0200

    Prepare v4.1.3-rt3

    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.

Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>

3 files changed, 130 insertions, 0 deletions

diff --git a/kernel/arch/sh/include/cpu-sh2/cpu/cache.h b/kernel/arch/sh/include/cpu-sh2/cpu/cache.h
new file mode 100644
index 000000000..aa1b2b908
--- /dev/null
+++ b/kernel/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -0,0 +1,43 @@
+/*
+ * include/asm-sh/cpu-sh2/cache.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_CACHE_H
+#define __ASM_CPU_SH2_CACHE_H
+
+#define L1_CACHE_SHIFT	4
+
+#define SH_CACHE_VALID		1
+#define SH_CACHE_UPDATED	2
+#define SH_CACHE_COMBINED	4
+#define SH_CACHE_ASSOC		8
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define SH_CCR		0xffffffec
+
+#define CCR_CACHE_CE	0x01	/* Cache enable */
+#define CCR_CACHE_WT	0x02    /* CCR[bit1=1,bit2=1] */
+				/* 0x00000000-0x7fffffff: Write-through  */
+				/* 0x80000000-0x9fffffff: Write-back     */
+                                /* 0xc0000000-0xdfffffff: Write-through  */
+#define CCR_CACHE_CB	0x04    /* CCR[bit1=0,bit2=0] */
+				/* 0x00000000-0x7fffffff: Write-back     */
+				/* 0x80000000-0x9fffffff: Write-through  */
+                                /* 0xc0000000-0xdfffffff: Write-back     */
+#define CCR_CACHE_CF	0x08	/* Cache invalidate */
+
+#define CACHE_OC_ADDRESS_ARRAY	0xf0000000
+#define CACHE_OC_DATA_ARRAY	0xf1000000
+
+#define CCR_CACHE_ENABLE	CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
+#define CACHE_PHYSADDR_MASK	0x1ffffc00
+
+#endif
+
+#endif /* __ASM_CPU_SH2_CACHE_H */
diff --git a/kernel/arch/sh/include/cpu-sh2/cpu/freq.h b/kernel/arch/sh/include/cpu-sh2/cpu/freq.h
new file mode 100644
index 000000000..31de475da
--- /dev/null
+++ b/kernel/arch/sh/include/cpu-sh2/cpu/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_FREQ_H
+#define __ASM_CPU_SH2_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7619)
+#define FREQCR	0xf815ff80
+#endif
+
+#endif /* __ASM_CPU_SH2_FREQ_H */
+
diff --git a/kernel/arch/sh/include/cpu-sh2/cpu/watchdog.h b/kernel/arch/sh/include/cpu-sh2/cpu/watchdog.h
new file mode 100644
index 000000000..1eab8aa63
--- /dev/null
+++ b/kernel/arch/sh/include/cpu-sh2/cpu/watchdog.h
@@ -0,0 +1,69 @@
+/*
+ * include/asm-sh/cpu-sh2/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2_WATCHDOG_H
+#define __ASM_CPU_SH2_WATCHDOG_H
+
+/*
+ * More SH-2 brilliance .. its not good enough that we can't read
+ * and write the same sizes to WTCNT, now we have to read and write
+ * with different sizes at different addresses for WTCNT _and_ RSTCSR.
+ *
+ * At least on the bright side no one has managed to screw over WTCSR
+ * in this fashion .. yet.
+ */
+/* Register definitions */
+#define WTCNT		0xfffffe80
+#define WTCSR		0xfffffe80
+#define RSTCSR		0xfffffe82
+
+#define WTCNT_R		(WTCNT + 1)
+#define RSTCSR_R	(RSTCSR + 1)
+
+/* Bit definitions */
+#define WTCSR_IOVF	0x80
+#define WTCSR_WT	0x40
+#define WTCSR_TME	0x20
+#define WTCSR_RSTS	0x00
+
+#define RSTCSR_RSTS	0x20
+
+/**
+ * 	sh_wdt_read_rstcsr - Read from Reset Control/Status Register
+ *
+ *	Reads back the RSTCSR value.
+ */
+static inline __u8 sh_wdt_read_rstcsr(void)
+{
+	/*
+	 * Same read/write brain-damage as for WTCNT here..
+	 */
+	return __raw_readb(RSTCSR_R);
+}
+
+/**
+ * 	sh_wdt_write_csr - Write to Reset Control/Status Register
+ *
+ * 	@val: Value to write
+ *
+ * 	Writes the given value @val to the lower byte of the control/status
+ * 	register. The upper byte is set manually on each write.
+ */
+static inline void sh_wdt_write_rstcsr(__u8 val)
+{
+	/*
+	 * Note: Due to the brain-damaged nature of this register,
+	 * we can't presently touch the WOVF bit, since the upper byte
+	 * has to be swapped for this. So just leave it alone..
+	 */
+	__raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
+}
+
+#endif /* __ASM_CPU_SH2_WATCHDOG_H */
+