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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/parisc/include/asm/perf.h
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/parisc/include/asm/perf.h')
-rw-r--r--kernel/arch/parisc/include/asm/perf.h74
1 files changed, 74 insertions, 0 deletions
diff --git a/kernel/arch/parisc/include/asm/perf.h b/kernel/arch/parisc/include/asm/perf.h
new file mode 100644
index 000000000..a18e11972
--- /dev/null
+++ b/kernel/arch/parisc/include/asm/perf.h
@@ -0,0 +1,74 @@
+#ifndef _ASM_PERF_H_
+#define _ASM_PERF_H_
+
+/* ioctls */
+#define PA_PERF_ON _IO('p', 1)
+#define PA_PERF_OFF _IOR('p', 2, unsigned int)
+#define PA_PERF_VERSION _IOR('p', 3, int)
+
+#define PA_PERF_DEV "perf"
+#define PA_PERF_MINOR 146
+
+/* Interface types */
+#define UNKNOWN_INTF 255
+#define ONYX_INTF 0
+#define CUDA_INTF 1
+
+/* Common Onyx and Cuda images */
+#define CPI 0
+#define BUSUTIL 1
+#define TLBMISS 2
+#define TLBHANDMISS 3
+#define PTKN 4
+#define PNTKN 5
+#define IMISS 6
+#define DMISS 7
+#define DMISS_ACCESS 8
+#define BIG_CPI 9
+#define BIG_LS 10
+#define BR_ABORT 11
+#define ISNT 12
+#define QUADRANT 13
+#define RW_PDFET 14
+#define RW_WDFET 15
+#define SHLIB_CPI 16
+
+/* Cuda only Images */
+#define FLOPS 17
+#define CACHEMISS 18
+#define BRANCHES 19
+#define CRSTACK 20
+#define I_CACHE_SPEC 21
+#define MAX_CUDA_IMAGES 22
+
+/* Onyx only Images */
+#define ADDR_INV_ABORT_ALU 17
+#define BRAD_STALL 18
+#define CNTL_IN_PIPEL 19
+#define DSNT_XFH 20
+#define FET_SIG1 21
+#define FET_SIG2 22
+#define G7_1 23
+#define G7_2 24
+#define G7_3 25
+#define G7_4 26
+#define MPB_LABORT 27
+#define PANIC 28
+#define RARE_INST 29
+#define RW_DFET 30
+#define RW_IFET 31
+#define RW_SDFET 32
+#define SPEC_IFET 33
+#define ST_COND0 34
+#define ST_COND1 35
+#define ST_COND2 36
+#define ST_COND3 37
+#define ST_COND4 38
+#define ST_UNPRED0 39
+#define ST_UNPRED1 40
+#define UNPRED 41
+#define GO_STORE 42
+#define SHLIB_CALL 43
+#define MAX_ONYX_IMAGES 44
+
+#endif