Add the rt linux 4.1.3-rt3 as base

Import the rt linux 4.1.3-rt3 as OPNFV kvm base.

It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:

commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Sat Jul 25 12:13:34 2015 +0200

    Prepare v4.1.3-rt3

    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.

Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>

1 files changed, 60 insertions, 0 deletions

diff --git a/kernel/arch/mn10300/include/asm/reset-regs.h b/kernel/arch/mn10300/include/asm/reset-regs.h
new file mode 100644
index 000000000..8ca2a42d3
--- /dev/null
+++ b/kernel/arch/mn10300/include/asm/reset-regs.h
@@ -0,0 +1,60 @@
+/* MN10300 Reset controller and watchdog timer definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_RESET_REGS_H
+#define _ASM_RESET_REGS_H
+
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+
+#ifdef __KERNEL__
+
+/*
+ * watchdog timer registers
+ */
+#define WDBC			__SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */
+
+#define WDCTR			__SYSREG(0xc0001002, u8)  /* watchdog timer control reg */
+#define WDCTR_WDCK		0x07	/* clock source selection */
+#define WDCTR_WDCK_256th	0x00	/* - OSCI/256 */
+#define WDCTR_WDCK_1024th	0x01	/* - OSCI/1024 */
+#define WDCTR_WDCK_2048th	0x02	/* - OSCI/2048 */
+#define WDCTR_WDCK_16384th	0x03	/* - OSCI/16384 */
+#define WDCTR_WDCK_65536th	0x04	/* - OSCI/65536 */
+#define WDCTR_WDRST		0x40	/* binary counter reset */
+#define WDCTR_WDCNE		0x80	/* watchdog timer enable */
+
+#define RSTCTR			__SYSREG(0xc0001004, u8) /* reset control reg */
+#define RSTCTR_CHIPRST		0x01	/* chip reset */
+#define RSTCTR_DBFRST		0x02	/* double fault reset flag */
+#define RSTCTR_WDTRST		0x04	/* watchdog timer reset flag */
+#define RSTCTR_WDREN		0x08	/* watchdog timer reset enable */
+
+#ifndef __ASSEMBLY__
+
+static inline void mn10300_proc_hard_reset(void)
+{
+	RSTCTR &= ~RSTCTR_CHIPRST;
+	RSTCTR |= RSTCTR_CHIPRST;
+}
+
+extern unsigned int watchdog_alert_counter[];
+
+extern void watchdog_go(void);
+extern asmlinkage void watchdog_handler(void);
+extern asmlinkage
+void watchdog_interrupt(struct pt_regs *, enum exception_code);
+
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_RESET_REGS_H */