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authorJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-04-11 10:41:07 +0300
committerJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-04-13 08:17:18 +0300
commite09b41010ba33a20a87472ee821fa407a5b8da36 (patch)
treed10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/arch/mips/sibyte/Kconfig
parentf93b97fd65072de626c074dbe099a1fff05ce060 (diff)
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page. During the rebasing, the following patch collided: Force tick interrupt and get rid of softirq magic(I70131fb85). Collisions have been removed because its logic was found on the source already. Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769 Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/arch/mips/sibyte/Kconfig')
-rw-r--r--kernel/arch/mips/sibyte/Kconfig21
1 files changed, 8 insertions, 13 deletions
diff --git a/kernel/arch/mips/sibyte/Kconfig b/kernel/arch/mips/sibyte/Kconfig
index 5fbd3605d..cb9a095f5 100644
--- a/kernel/arch/mips/sibyte/Kconfig
+++ b/kernel/arch/mips/sibyte/Kconfig
@@ -3,7 +3,7 @@ config SIBYTE_SB1250
select CEVT_SB1250
select CSRC_SB1250
select HW_HAS_PCI
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_ENABLE_LDT_IF_PCI
select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC
@@ -13,7 +13,7 @@ config SIBYTE_BCM1120
bool
select CEVT_SB1250
select CSRC_SB1250
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_BCM112X
select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC
@@ -23,7 +23,7 @@ config SIBYTE_BCM1125
select CEVT_SB1250
select CSRC_SB1250
select HW_HAS_PCI
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_BCM112X
select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC
@@ -33,7 +33,7 @@ config SIBYTE_BCM1125H
select CEVT_SB1250
select CSRC_SB1250
select HW_HAS_PCI
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_BCM112X
select SIBYTE_ENABLE_LDT_IF_PCI
select SIBYTE_HAS_ZBUS_PROFILING
@@ -43,7 +43,7 @@ config SIBYTE_BCM112X
bool
select CEVT_SB1250
select CSRC_SB1250
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_SB1xxx_SOC
select SIBYTE_HAS_ZBUS_PROFILING
@@ -52,7 +52,7 @@ config SIBYTE_BCM1x80
select CEVT_BCM1480
select CSRC_BCM1480
select HW_HAS_PCI
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC
select SYS_SUPPORTS_SMP
@@ -62,7 +62,7 @@ config SIBYTE_BCM1x55
select CEVT_BCM1480
select CSRC_BCM1480
select HW_HAS_PCI
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SIBYTE_SB1xxx_SOC
select SIBYTE_HAS_ZBUS_PROFILING
select SYS_SUPPORTS_SMP
@@ -70,7 +70,7 @@ config SIBYTE_BCM1x55
config SIBYTE_SB1xxx_SOC
bool
select DMA_COHERENT
- select IRQ_CPU
+ select IRQ_MIPS_CPU
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
@@ -81,11 +81,6 @@ choice
prompt "SiByte SOC Stepping"
depends on SIBYTE_SB1xxx_SOC
-config CPU_SB1_PASS_1
- bool "1250 Pass1"
- depends on SIBYTE_SB1250
- select CPU_HAS_PREFETCH
-
config CPU_SB1_PASS_2_1250
bool "1250 An"
depends on SIBYTE_SB1250