diff options
author | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-11 10:41:07 +0300 |
---|---|---|
committer | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-04-13 08:17:18 +0300 |
commit | e09b41010ba33a20a87472ee821fa407a5b8da36 (patch) | |
tree | d10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/arch/mips/pistachio | |
parent | f93b97fd65072de626c074dbe099a1fff05ce060 (diff) |
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page.
During the rebasing, the following patch collided:
Force tick interrupt and get rid of softirq magic(I70131fb85).
Collisions have been removed because its logic was found on the
source already.
Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769
Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/arch/mips/pistachio')
-rw-r--r-- | kernel/arch/mips/pistachio/Kconfig | 13 | ||||
-rw-r--r-- | kernel/arch/mips/pistachio/init.c | 9 | ||||
-rw-r--r-- | kernel/arch/mips/pistachio/time.c | 7 |
3 files changed, 26 insertions, 3 deletions
diff --git a/kernel/arch/mips/pistachio/Kconfig b/kernel/arch/mips/pistachio/Kconfig new file mode 100644 index 000000000..97731ea94 --- /dev/null +++ b/kernel/arch/mips/pistachio/Kconfig @@ -0,0 +1,13 @@ +config PISTACHIO_GPTIMER_CLKSRC + bool "Enable General Purpose Timer based clocksource" + depends on MACH_PISTACHIO + select CLKSRC_PISTACHIO + select MIPS_EXTERNAL_TIMER + help + This option enables a clocksource driver based on a Pistachio + SoC General Purpose external timer. + + If you want to enable the CPUFreq, you need to enable + this option. + + If you don't want to enable CPUFreq, you can leave this disabled. diff --git a/kernel/arch/mips/pistachio/init.c b/kernel/arch/mips/pistachio/init.c index d2dc83652..96ba2cc9a 100644 --- a/kernel/arch/mips/pistachio/init.c +++ b/kernel/arch/mips/pistachio/init.c @@ -58,18 +58,23 @@ void __init plat_mem_setup(void) panic("Device-tree not present"); __dt_setup_arch((void *)fw_arg1); - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); plat_setup_iocoherency(); } -#define DEFAULT_CPC_BASE_ADDR 0x1bde0000 +#define DEFAULT_CPC_BASE_ADDR 0x1bde0000 +#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000 phys_addr_t mips_cpc_default_phys_base(void) { return DEFAULT_CPC_BASE_ADDR; } +phys_addr_t mips_cdmm_phys_base(void) +{ + return DEFAULT_CDMM_BASE_ADDR; +} + static void __init mips_nmi_setup(void) { void *base; diff --git a/kernel/arch/mips/pistachio/time.c b/kernel/arch/mips/pistachio/time.c index ab73f6f40..1022201b2 100644 --- a/kernel/arch/mips/pistachio/time.c +++ b/kernel/arch/mips/pistachio/time.c @@ -28,13 +28,18 @@ int get_c0_perfcount_int(void) } EXPORT_SYMBOL_GPL(get_c0_perfcount_int); +int get_c0_fdc_int(void) +{ + return gic_get_c0_fdc_int(); +} + void __init plat_time_init(void) { struct device_node *np; struct clk *clk; of_clk_init(NULL); - clocksource_of_init(); + clocksource_probe(); np = of_get_cpu_node(0, NULL); if (!np) { |