summaryrefslogtreecommitdiffstats
path: root/kernel/arch/mips/include/asm/prefetch.h
diff options
context:
space:
mode:
authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/mips/include/asm/prefetch.h
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/mips/include/asm/prefetch.h')
-rw-r--r--kernel/arch/mips/include/asm/prefetch.h87
1 files changed, 87 insertions, 0 deletions
diff --git a/kernel/arch/mips/include/asm/prefetch.h b/kernel/arch/mips/include/asm/prefetch.h
new file mode 100644
index 000000000..a56594f36
--- /dev/null
+++ b/kernel/arch/mips/include/asm/prefetch.h
@@ -0,0 +1,87 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_PREFETCH_H
+#define __ASM_PREFETCH_H
+
+
+/*
+ * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
+ * rather than wasting time we pretend these processors don't support
+ * prefetching at all.
+ *
+ * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
+ * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
+ *
+ * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
+ *
+ * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
+ * Pref_PrepareForStore also.
+ *
+ * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
+ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
+ * current versions due to erratum G105.
+ *
+ * VR5500 (including VR5701 and VR7701) only implement load prefetch.
+ *
+ * Finally MIPS32 and MIPS64 implement all of the following hints.
+ */
+
+#define Pref_Load 0
+#define Pref_Store 1
+ /* 2 and 3 are reserved */
+#define Pref_LoadStreamed 4
+#define Pref_StoreStreamed 5
+#define Pref_LoadRetained 6
+#define Pref_StoreRetained 7
+ /* 8 ... 24 are reserved */
+#define Pref_WriteBackInvalidate 25
+#define Pref_PrepareForStore 30
+
+#ifdef __ASSEMBLY__
+
+ .macro __pref hint addr
+#ifdef CONFIG_CPU_HAS_PREFETCH
+ pref \hint, \addr
+#endif
+ .endm
+
+ .macro pref_load addr
+ __pref Pref_Load, \addr
+ .endm
+
+ .macro pref_store addr
+ __pref Pref_Store, \addr
+ .endm
+
+ .macro pref_load_streamed addr
+ __pref Pref_LoadStreamed, \addr
+ .endm
+
+ .macro pref_store_streamed addr
+ __pref Pref_StoreStreamed, \addr
+ .endm
+
+ .macro pref_load_retained addr
+ __pref Pref_LoadRetained, \addr
+ .endm
+
+ .macro pref_store_retained addr
+ __pref Pref_StoreRetained, \addr
+ .endm
+
+ .macro pref_wback_inv addr
+ __pref Pref_WriteBackInvalidate, \addr
+ .endm
+
+ .macro pref_prepare_for_store addr
+ __pref Pref_PrepareForStore, \addr
+ .endm
+
+#endif
+
+#endif /* __ASM_PREFETCH_H */