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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/mips/cobalt/irq.c
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/mips/cobalt/irq.c')
-rw-r--r--kernel/arch/mips/cobalt/irq.c62
1 files changed, 62 insertions, 0 deletions
diff --git a/kernel/arch/mips/cobalt/irq.c b/kernel/arch/mips/cobalt/irq.c
new file mode 100644
index 000000000..965c777d3
--- /dev/null
+++ b/kernel/arch/mips/cobalt/irq.c
@@ -0,0 +1,62 @@
+/*
+ * IRQ vector handles
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+
+#include <asm/i8259.h>
+#include <asm/irq_cpu.h>
+#include <asm/irq_gt641xx.h>
+#include <asm/gt64120.h>
+
+#include <irq.h>
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
+ int irq;
+
+ if (pending & CAUSEF_IP2)
+ gt641xx_irq_dispatch();
+ else if (pending & CAUSEF_IP6) {
+ irq = i8259_irq();
+ if (irq < 0)
+ spurious_interrupt();
+ else
+ do_IRQ(irq);
+ } else if (pending & CAUSEF_IP3)
+ do_IRQ(MIPS_CPU_IRQ_BASE + 3);
+ else if (pending & CAUSEF_IP4)
+ do_IRQ(MIPS_CPU_IRQ_BASE + 4);
+ else if (pending & CAUSEF_IP5)
+ do_IRQ(MIPS_CPU_IRQ_BASE + 5);
+ else if (pending & CAUSEF_IP7)
+ do_IRQ(MIPS_CPU_IRQ_BASE + 7);
+ else
+ spurious_interrupt();
+}
+
+static struct irqaction cascade = {
+ .handler = no_action,
+ .name = "cascade",
+ .flags = IRQF_NO_THREAD,
+};
+
+void __init arch_init_irq(void)
+{
+ mips_cpu_irq_init();
+ gt641xx_irq_init();
+ init_i8259_irqs();
+
+ setup_irq(GT641XX_CASCADE_IRQ, &cascade);
+ setup_irq(I8259_CASCADE_IRQ, &cascade);
+}