diff options
author | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
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committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/metag/include/asm/metag_isa.h | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/metag/include/asm/metag_isa.h')
-rw-r--r-- | kernel/arch/metag/include/asm/metag_isa.h | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/kernel/arch/metag/include/asm/metag_isa.h b/kernel/arch/metag/include/asm/metag_isa.h new file mode 100644 index 000000000..c8aa2ae38 --- /dev/null +++ b/kernel/arch/metag/include/asm/metag_isa.h @@ -0,0 +1,81 @@ +/* + * asm/metag_isa.h + * + * Copyright (C) 2000-2007, 2012 Imagination Technologies. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + * + * Various defines for Meta instruction set. + */ + +#ifndef _ASM_METAG_ISA_H_ +#define _ASM_METAG_ISA_H_ + + +/* L1 cache layout */ + +/* Data cache line size as bytes and shift */ +#define DCACHE_LINE_BYTES 64 +#define DCACHE_LINE_S 6 + +/* Number of ways in the data cache */ +#define DCACHE_WAYS 4 + +/* Instruction cache line size as bytes and shift */ +#define ICACHE_LINE_BYTES 64 +#define ICACHE_LINE_S 6 + +/* Number of ways in the instruction cache */ +#define ICACHE_WAYS 4 + + +/* + * CACHEWD/CACHEWL instructions use the bottom 8 bits of the data presented to + * control the operation actually achieved. + */ +/* Use of these two bits should be discouraged since the bits dont have + * consistent meanings + */ +#define CACHEW_ICACHE_BIT 0x01 +#define CACHEW_TLBFLUSH_BIT 0x02 + +#define CACHEW_FLUSH_L1D_L2 0x0 +#define CACHEW_INVALIDATE_L1I 0x1 +#define CACHEW_INVALIDATE_L1DTLB 0x2 +#define CACHEW_INVALIDATE_L1ITLB 0x3 +#define CACHEW_WRITEBACK_L1D_L2 0x4 +#define CACHEW_INVALIDATE_L1D 0x8 +#define CACHEW_INVALIDATE_L1D_L2 0xC + +/* + * CACHERD/CACHERL instructions use bits 3:5 of the address presented to + * control the operation achieved and hence the specific result. + */ +#define CACHER_ADDR_BITS 0xFFFFFFC0 +#define CACHER_OPER_BITS 0x00000030 +#define CACHER_OPER_S 4 +#define CACHER_OPER_LINPHY 0 +#define CACHER_ICACHE_BIT 0x00000008 +#define CACHER_ICACHE_S 3 + +/* + * CACHERD/CACHERL LINPHY Oper result is one/two 32-bit words + * + * If CRLINPHY0_VAL_BIT (Bit 0) set then, + * Lower 32-bits corresponds to MMCU_ENTRY_* above. + * Upper 32-bits corresponds to CRLINPHY1_* values below (if requested). + * else + * Lower 32-bits corresponds to CRLINPHY0_* values below. + * Upper 32-bits undefined. + */ +#define CRLINPHY0_VAL_BIT 0x00000001 +#define CRLINPHY0_FIRST_BIT 0x00000004 /* Set if VAL=0 due to first level */ + +#define CRLINPHY1_READ_BIT 0x00000001 /* Set if reads permitted */ +#define CRLINPHY1_SINGLE_BIT 0x00000004 /* Set if TLB does not cache entry */ +#define CRLINPHY1_PAGEMSK_BITS 0x0000FFF0 /* Set to ((2^n-1)>>12) value */ +#define CRLINPHY1_PAGEMSK_S 4 + +#endif /* _ASM_METAG_ISA_H_ */ |