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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/m68k/fpsp040/sto_res.S
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/m68k/fpsp040/sto_res.S')
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diff --git a/kernel/arch/m68k/fpsp040/sto_res.S b/kernel/arch/m68k/fpsp040/sto_res.S
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+|
+| sto_res.sa 3.1 12/10/90
+|
+| Takes the result and puts it in where the user expects it.
+| Library functions return result in fp0. If fp0 is not the
+| users destination register then fp0 is moved to the
+| correct floating-point destination register. fp0 and fp1
+| are then restored to the original contents.
+|
+| Input: result in fp0,fp1
+|
+| d2 & a0 should be kept unmodified
+|
+| Output: moves the result to the true destination reg or mem
+|
+| Modifies: destination floating point register
+|
+
+| Copyright (C) Motorola, Inc. 1990
+| All Rights Reserved
+|
+| For details on the license for this file, please see the
+| file, README, in this same directory.
+
+STO_RES: |idnt 2,1 | Motorola 040 Floating Point Software Package
+
+
+ |section 8
+
+#include "fpsp.h"
+
+ .global sto_cos
+sto_cos:
+ bfextu CMDREG1B(%a6){#13:#3},%d0 |extract cos destination
+ cmpib #3,%d0 |check for fp0/fp1 cases
+ bles c_fp0123
+ fmovemx %fp1-%fp1,-(%a7)
+ moveql #7,%d1
+ subl %d0,%d1 |d1 = 7- (dest. reg. no.)
+ clrl %d0
+ bsetl %d1,%d0 |d0 is dynamic register mask
+ fmovemx (%a7)+,%d0
+ rts
+c_fp0123:
+ cmpib #0,%d0
+ beqs c_is_fp0
+ cmpib #1,%d0
+ beqs c_is_fp1
+ cmpib #2,%d0
+ beqs c_is_fp2
+c_is_fp3:
+ fmovemx %fp1-%fp1,USER_FP3(%a6)
+ rts
+c_is_fp2:
+ fmovemx %fp1-%fp1,USER_FP2(%a6)
+ rts
+c_is_fp1:
+ fmovemx %fp1-%fp1,USER_FP1(%a6)
+ rts
+c_is_fp0:
+ fmovemx %fp1-%fp1,USER_FP0(%a6)
+ rts
+
+
+ .global sto_res
+sto_res:
+ bfextu CMDREG1B(%a6){#6:#3},%d0 |extract destination register
+ cmpib #3,%d0 |check for fp0/fp1 cases
+ bles fp0123
+ fmovemx %fp0-%fp0,-(%a7)
+ moveql #7,%d1
+ subl %d0,%d1 |d1 = 7- (dest. reg. no.)
+ clrl %d0
+ bsetl %d1,%d0 |d0 is dynamic register mask
+ fmovemx (%a7)+,%d0
+ rts
+fp0123:
+ cmpib #0,%d0
+ beqs is_fp0
+ cmpib #1,%d0
+ beqs is_fp1
+ cmpib #2,%d0
+ beqs is_fp2
+is_fp3:
+ fmovemx %fp0-%fp0,USER_FP3(%a6)
+ rts
+is_fp2:
+ fmovemx %fp0-%fp0,USER_FP2(%a6)
+ rts
+is_fp1:
+ fmovemx %fp0-%fp0,USER_FP1(%a6)
+ rts
+is_fp0:
+ fmovemx %fp0-%fp0,USER_FP0(%a6)
+ rts
+
+ |end