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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/m32r/platforms/usrv
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/m32r/platforms/usrv')
-rw-r--r--kernel/arch/m32r/platforms/usrv/Makefile1
-rw-r--r--kernel/arch/m32r/platforms/usrv/io.c225
-rw-r--r--kernel/arch/m32r/platforms/usrv/setup.c212
3 files changed, 438 insertions, 0 deletions
diff --git a/kernel/arch/m32r/platforms/usrv/Makefile b/kernel/arch/m32r/platforms/usrv/Makefile
new file mode 100644
index 000000000..0de59084f
--- /dev/null
+++ b/kernel/arch/m32r/platforms/usrv/Makefile
@@ -0,0 +1 @@
+obj-y := setup.o io.o
diff --git a/kernel/arch/m32r/platforms/usrv/io.c b/kernel/arch/m32r/platforms/usrv/io.c
new file mode 100644
index 000000000..f5e50d37b
--- /dev/null
+++ b/kernel/arch/m32r/platforms/usrv/io.c
@@ -0,0 +1,225 @@
+/*
+ * linux/arch/m32r/platforms/usrv/io.c
+ *
+ * Typical I/O routines for uServer board.
+ *
+ * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto, Takeo Takahashi
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ */
+
+#include <asm/m32r.h>
+#include <asm/page.h>
+#include <asm/io.h>
+
+#include <linux/types.h>
+#include "../../../../drivers/pcmcia/m32r_cfc.h"
+
+extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
+extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
+#define CFC_IOSTART CFC_IOPORT_BASE
+#define CFC_IOEND (CFC_IOSTART + (M32R_PCC_MAPSIZE * M32R_MAX_PCC) - 1)
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+#define UART0_REGSTART 0x04c20000
+#define UART1_REGSTART 0x04c20100
+#define UART_IOMAP_SIZE 8
+#define UART0_IOSTART 0x3f8
+#define UART0_IOEND (UART0_IOSTART + UART_IOMAP_SIZE - 1)
+#define UART1_IOSTART 0x2f8
+#define UART1_IOEND (UART1_IOSTART + UART_IOMAP_SIZE - 1)
+#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
+
+#define PORT2ADDR(port) _port2addr(port)
+
+static inline void *_port2addr(unsigned long port)
+{
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ if (port >= UART0_IOSTART && port <= UART0_IOEND)
+ port = ((port - UART0_IOSTART) << 1) + UART0_REGSTART;
+ else if (port >= UART1_IOSTART && port <= UART1_IOEND)
+ port = ((port - UART1_IOSTART) << 1) + UART1_REGSTART;
+#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
+ return (void *)(port | (NONCACHE_OFFSET));
+}
+
+static inline void delay(void)
+{
+ __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
+}
+
+unsigned char _inb(unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ unsigned char b;
+ pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
+ return b;
+ } else
+ return *(volatile unsigned char *)PORT2ADDR(port);
+}
+
+unsigned short _inw(unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ unsigned short w;
+ pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
+ return w;
+ } else
+ return *(volatile unsigned short *)PORT2ADDR(port);
+}
+
+unsigned long _inl(unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND) {
+ unsigned long l;
+ pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
+ return l;
+ } else
+ return *(volatile unsigned long *)PORT2ADDR(port);
+}
+
+unsigned char _inb_p(unsigned long port)
+{
+ unsigned char v = _inb(port);
+ delay();
+ return v;
+}
+
+unsigned short _inw_p(unsigned long port)
+{
+ unsigned short v = _inw(port);
+ delay();
+ return v;
+}
+
+unsigned long _inl_p(unsigned long port)
+{
+ unsigned long v = _inl(port);
+ delay();
+ return v;
+}
+
+void _outb(unsigned char b, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
+ else
+ *(volatile unsigned char *)PORT2ADDR(port) = b;
+}
+
+void _outw(unsigned short w, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
+ else
+ *(volatile unsigned short *)PORT2ADDR(port) = w;
+}
+
+void _outl(unsigned long l, unsigned long port)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
+ else
+ *(volatile unsigned long *)PORT2ADDR(port) = l;
+}
+
+void _outb_p(unsigned char b, unsigned long port)
+{
+ _outb(b, port);
+ delay();
+}
+
+void _outw_p(unsigned short w, unsigned long port)
+{
+ _outw(w, port);
+ delay();
+}
+
+void _outl_p(unsigned long l, unsigned long port)
+{
+ _outl(l, port);
+ delay();
+}
+
+void _insb(unsigned int port, void * addr, unsigned long count)
+{
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_ioread_byte(0, port, addr, sizeof(unsigned char), count, 1);
+ else {
+ unsigned char *buf = addr;
+ unsigned char *portp = PORT2ADDR(port);
+ while (count--)
+ *buf++ = *(volatile unsigned char *)portp;
+ }
+}
+
+void _insw(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_ioread_word(0, port, addr, sizeof(unsigned short), count,
+ 1);
+ else {
+ portp = PORT2ADDR(port);
+ while (count--)
+ *buf++ = *(volatile unsigned short *)portp;
+ }
+}
+
+void _insl(unsigned int port, void * addr, unsigned long count)
+{
+ unsigned long *buf = addr;
+ unsigned long *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--)
+ *buf++ = *(volatile unsigned long *)portp;
+}
+
+void _outsb(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned char *buf = addr;
+ unsigned char *portp;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
+ count, 1);
+ else {
+ portp = PORT2ADDR(port);
+ while (count--)
+ *(volatile unsigned char *)portp = *buf++;
+ }
+}
+
+void _outsw(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned short *buf = addr;
+ unsigned short *portp;
+
+ if (port >= CFC_IOSTART && port <= CFC_IOEND)
+ pcc_iowrite_word(0, port, (void *)addr, sizeof(unsigned short),
+ count, 1);
+ else {
+ portp = PORT2ADDR(port);
+ while (count--)
+ *(volatile unsigned short *)portp = *buf++;
+ }
+}
+
+void _outsl(unsigned int port, const void * addr, unsigned long count)
+{
+ const unsigned long *buf = addr;
+ unsigned char *portp;
+
+ portp = PORT2ADDR(port);
+ while (count--)
+ *(volatile unsigned long *)portp = *buf++;
+}
diff --git a/kernel/arch/m32r/platforms/usrv/setup.c b/kernel/arch/m32r/platforms/usrv/setup.c
new file mode 100644
index 000000000..dcde0ec77
--- /dev/null
+++ b/kernel/arch/m32r/platforms/usrv/setup.c
@@ -0,0 +1,212 @@
+/*
+ * linux/arch/m32r/platforms/usrv/setup.c
+ *
+ * Setup routines for MITSUBISHI uServer
+ *
+ * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
+ * Hitoshi Yamamoto
+ */
+
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/m32r.h>
+#include <asm/io.h>
+
+#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
+
+icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
+
+static void disable_mappi_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
+ outl(data, port);
+}
+
+static void enable_mappi_irq(unsigned int irq)
+{
+ unsigned long port, data;
+
+ port = irq2port(irq);
+ data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
+ outl(data, port);
+}
+
+static void mask_mappi(struct irq_data *data)
+{
+ disable_mappi_irq(data->irq);
+}
+
+static void unmask_mappi(struct irq_data *data)
+{
+ enable_mappi_irq(data->irq);
+}
+
+static void shutdown_mappi(struct irq_data *data)
+{
+ unsigned long port;
+
+ port = irq2port(data->irq);
+ outl(M32R_ICUCR_ILEVEL7, port);
+}
+
+static struct irq_chip mappi_irq_type =
+{
+ .name = "M32700-IRQ",
+ .irq_shutdown = shutdown_mappi,
+ .irq_mask = mask_mappi,
+ .irq_unmask = unmask_mappi,
+};
+
+/*
+ * Interrupt Control Unit of PLD on M32700UT (Level 2)
+ */
+#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
+#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
+ (((x) - 1) * sizeof(unsigned short)))
+
+typedef struct {
+ unsigned short icucr; /* ICU Control Register */
+} pld_icu_data_t;
+
+static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
+
+static void disable_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
+ outw(data, port);
+}
+
+static void enable_m32700ut_pld_irq(unsigned int irq)
+{
+ unsigned long port, data;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(irq);
+ port = pldirq2port(pldirq);
+ data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
+ outw(data, port);
+}
+
+static void mask_m32700ut_pld(struct irq_data *data)
+{
+ disable_m32700ut_pld_irq(data->irq);
+}
+
+static void unmask_m32700ut_pld(struct irq_data *data)
+{
+ enable_m32700ut_pld_irq(data->irq);
+ enable_mappi_irq(M32R_IRQ_INT1);
+}
+
+static void shutdown_m32700ut_pld(struct irq_data *data)
+{
+ unsigned long port;
+ unsigned int pldirq;
+
+ pldirq = irq2pldirq(data->irq);
+ port = pldirq2port(pldirq);
+ outw(PLD_ICUCR_ILEVEL7, port);
+}
+
+static struct irq_chip m32700ut_pld_irq_type =
+{
+ .name = "USRV-PLD-IRQ",
+ .irq_shutdown = shutdown_m32700ut_pld,
+ .irq_mask = mask_m32700ut_pld,
+ .irq_unmask = unmask_m32700ut_pld,
+};
+
+void __init init_IRQ(void)
+{
+ static int once = 0;
+ int i;
+
+ if (once)
+ return;
+ else
+ once++;
+
+ /* MFT2 : system timer */
+ irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
+ handle_level_irq);
+ icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
+ disable_mappi_irq(M32R_IRQ_MFT2);
+
+#if defined(CONFIG_SERIAL_M32R_SIO)
+ /* SIO0_R : uart receive data */
+ irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
+ handle_level_irq);
+ icu_data[M32R_IRQ_SIO0_R].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO0_R);
+
+ /* SIO0_S : uart send data */
+ irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
+ handle_level_irq);
+ icu_data[M32R_IRQ_SIO0_S].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO0_S);
+
+ /* SIO1_R : uart receive data */
+ irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
+ handle_level_irq);
+ icu_data[M32R_IRQ_SIO1_R].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO1_R);
+
+ /* SIO1_S : uart send data */
+ irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
+ handle_level_irq);
+ icu_data[M32R_IRQ_SIO1_S].icucr = 0;
+ disable_mappi_irq(M32R_IRQ_SIO1_S);
+#endif /* CONFIG_SERIAL_M32R_SIO */
+
+ /* INT#67-#71: CFC#0 IREQ on PLD */
+ for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
+ irq_set_chip_and_handler(PLD_IRQ_CF0 + i,
+ &m32700ut_pld_irq_type,
+ handle_level_irq);
+ pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
+ = PLD_ICUCR_ISMOD01; /* 'L' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
+ }
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ /* INT#76: 16552D#0 IREQ on PLD */
+ irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
+ handle_level_irq);
+ pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
+ = PLD_ICUCR_ISMOD03; /* 'H' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_UART0);
+
+ /* INT#77: 16552D#1 IREQ on PLD */
+ irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
+ handle_level_irq);
+ pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
+ = PLD_ICUCR_ISMOD03; /* 'H' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_UART1);
+#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
+
+#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
+ /* INT#80: AK4524 IREQ on PLD */
+ irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
+ handle_level_irq);
+ pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
+ = PLD_ICUCR_ISMOD01; /* 'L' level sense */
+ disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
+#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
+
+ /*
+ * INT1# is used for UART, MMC, CF Controller in FPGA.
+ * We enable it here.
+ */
+ icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
+ enable_mappi_irq(M32R_IRQ_INT1);
+}