diff options
| author |   Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
| commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
| tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/avr32/lib/io-writesb.S | |
| parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) | |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/avr32/lib/io-writesb.S')
| -rw-r--r-- | kernel/arch/avr32/lib/io-writesb.S | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/kernel/arch/avr32/lib/io-writesb.S b/kernel/arch/avr32/lib/io-writesb.S new file mode 100644 index 000000000..b4ebaaccc --- /dev/null +++ b/kernel/arch/avr32/lib/io-writesb.S @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + .text +.Lnot_word_aligned: +1: ld.ub r8, r11++ + sub r10, 1 + st.b r12[0], r8 + reteq r12 + tst r11, r9 + brne 1b + + /* fall through */ + + .global __raw_writesb + .type __raw_writesb,@function +__raw_writesb: + cp.w r10, 0 + mov r9, 3 + reteq r12 + + tst r11, r9 + brne .Lnot_word_aligned + + sub r10, 4 + brlt 2f + +1: ld.w r8, r11++ + bfextu r9, r8, 24, 8 + st.b r12[0], r9 + bfextu r9, r8, 16, 8 + st.b r12[0], r9 + bfextu r9, r8, 8, 8 + st.b r12[0], r9 + st.b r12[0], r8 + sub r10, 4 + brge 1b + +2: sub r10, -4 + reteq r12 + +3: ld.ub r8, r11++ + sub r10, 1 + st.b r12[0], r8 + brne 3b + + retal r12 |