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authorJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-04-11 10:41:07 +0300
committerJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-04-13 08:17:18 +0300
commite09b41010ba33a20a87472ee821fa407a5b8da36 (patch)
treed10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/arch/arm/mach-socfpga/socfpga.c
parentf93b97fd65072de626c074dbe099a1fff05ce060 (diff)
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page. During the rebasing, the following patch collided: Force tick interrupt and get rid of softirq magic(I70131fb85). Collisions have been removed because its logic was found on the source already. Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769 Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/arch/arm/mach-socfpga/socfpga.c')
-rw-r--r--kernel/arch/arm/mach-socfpga/socfpga.c67
1 files changed, 31 insertions, 36 deletions
diff --git a/kernel/arch/arm/mach-socfpga/socfpga.c b/kernel/arch/arm/mach-socfpga/socfpga.c
index f5e597c20..a1c0efaa8 100644
--- a/kernel/arch/arm/mach-socfpga/socfpga.c
+++ b/kernel/arch/arm/mach-socfpga/socfpga.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation
+ * Copyright (C) 2012-2015 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,43 +27,11 @@
#include "core.h"
-void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
void __iomem *sys_manager_base_addr;
void __iomem *rst_manager_base_addr;
+void __iomem *sdr_ctl_base_addr;
unsigned long socfpga_cpu1start_addr;
-static struct map_desc scu_io_desc __initdata = {
- .virtual = SOCFPGA_SCU_VIRT_BASE,
- .pfn = 0, /* run-time */
- .length = SZ_8K,
- .type = MT_DEVICE,
-};
-
-static struct map_desc uart_io_desc __initdata = {
- .virtual = 0xfec02000,
- .pfn = __phys_to_pfn(0xffc02000),
- .length = SZ_8K,
- .type = MT_DEVICE,
-};
-
-static void __init socfpga_scu_map_io(void)
-{
- unsigned long base;
-
- /* Get SCU base */
- asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
-
- scu_io_desc.pfn = __phys_to_pfn(base);
- iotable_init(&scu_io_desc, 1);
-}
-
-static void __init socfpga_map_io(void)
-{
- socfpga_scu_map_io();
- iotable_init(&uart_io_desc, 1);
- early_printk("Early printk initialized\n");
-}
-
void __init socfpga_sysmgr_init(void)
{
struct device_node *np;
@@ -82,6 +50,9 @@ void __init socfpga_sysmgr_init(void)
np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
rst_manager_base_addr = of_iomap(np, 0);
+
+ np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
+ sdr_ctl_base_addr = of_iomap(np, 0);
}
static void __init socfpga_init_irq(void)
@@ -103,6 +74,19 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
}
+static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
+{
+ u32 temp;
+
+ temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
+
+ if (mode == REBOOT_HARD)
+ temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
+ else
+ temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+ writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
+}
+
static const char *altera_dt_match[] = {
"altr,socfpga",
NULL
@@ -111,9 +95,20 @@ static const char *altera_dt_match[] = {
DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
- .smp = smp_ops(socfpga_smp_ops),
- .map_io = socfpga_map_io,
.init_irq = socfpga_init_irq,
.restart = socfpga_cyclone5_restart,
.dt_compat = altera_dt_match,
MACHINE_END
+
+static const char *altera_a10_dt_match[] = {
+ "altr,socfpga-arria10",
+ NULL
+};
+
+DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+ .init_irq = socfpga_init_irq,
+ .restart = socfpga_arria10_restart,
+ .dt_compat = altera_a10_dt_match,
+MACHINE_END