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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/mach-rpc/irq.c
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/mach-rpc/irq.c')
-rw-r--r--kernel/arch/arm/mach-rpc/irq.c168
1 files changed, 168 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-rpc/irq.c b/kernel/arch/arm/mach-rpc/irq.c
new file mode 100644
index 000000000..3e4fa849c
--- /dev/null
+++ b/kernel/arch/arm/mach-rpc/irq.c
@@ -0,0 +1,168 @@
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+
+#include <asm/mach/irq.h>
+#include <asm/hardware/iomd.h>
+#include <asm/irq.h>
+#include <asm/fiq.h>
+
+static void iomd_ack_irq_a(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << d->irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKA);
+ iomd_writeb(mask, IOMD_IRQCLRA);
+}
+
+static void iomd_mask_irq_a(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << d->irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKA);
+}
+
+static void iomd_unmask_irq_a(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << d->irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val | mask, IOMD_IRQMASKA);
+}
+
+static struct irq_chip iomd_a_chip = {
+ .irq_ack = iomd_ack_irq_a,
+ .irq_mask = iomd_mask_irq_a,
+ .irq_unmask = iomd_unmask_irq_a,
+};
+
+static void iomd_mask_irq_b(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << (d->irq & 7);
+ val = iomd_readb(IOMD_IRQMASKB);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKB);
+}
+
+static void iomd_unmask_irq_b(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << (d->irq & 7);
+ val = iomd_readb(IOMD_IRQMASKB);
+ iomd_writeb(val | mask, IOMD_IRQMASKB);
+}
+
+static struct irq_chip iomd_b_chip = {
+ .irq_ack = iomd_mask_irq_b,
+ .irq_mask = iomd_mask_irq_b,
+ .irq_unmask = iomd_unmask_irq_b,
+};
+
+static void iomd_mask_irq_dma(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << (d->irq & 7);
+ val = iomd_readb(IOMD_DMAMASK);
+ iomd_writeb(val & ~mask, IOMD_DMAMASK);
+}
+
+static void iomd_unmask_irq_dma(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << (d->irq & 7);
+ val = iomd_readb(IOMD_DMAMASK);
+ iomd_writeb(val | mask, IOMD_DMAMASK);
+}
+
+static struct irq_chip iomd_dma_chip = {
+ .irq_ack = iomd_mask_irq_dma,
+ .irq_mask = iomd_mask_irq_dma,
+ .irq_unmask = iomd_unmask_irq_dma,
+};
+
+static void iomd_mask_irq_fiq(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << (d->irq & 7);
+ val = iomd_readb(IOMD_FIQMASK);
+ iomd_writeb(val & ~mask, IOMD_FIQMASK);
+}
+
+static void iomd_unmask_irq_fiq(struct irq_data *d)
+{
+ unsigned int val, mask;
+
+ mask = 1 << (d->irq & 7);
+ val = iomd_readb(IOMD_FIQMASK);
+ iomd_writeb(val | mask, IOMD_FIQMASK);
+}
+
+static struct irq_chip iomd_fiq_chip = {
+ .irq_ack = iomd_mask_irq_fiq,
+ .irq_mask = iomd_mask_irq_fiq,
+ .irq_unmask = iomd_unmask_irq_fiq,
+};
+
+extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
+
+void __init rpc_init_irq(void)
+{
+ unsigned int irq, flags;
+
+ iomd_writeb(0, IOMD_IRQMASKA);
+ iomd_writeb(0, IOMD_IRQMASKB);
+ iomd_writeb(0, IOMD_FIQMASK);
+ iomd_writeb(0, IOMD_DMAMASK);
+
+ set_fiq_handler(&rpc_default_fiq_start,
+ &rpc_default_fiq_end - &rpc_default_fiq_start);
+
+ for (irq = 0; irq < NR_IRQS; irq++) {
+ flags = IRQF_VALID;
+
+ if (irq <= 6 || (irq >= 9 && irq <= 15))
+ flags |= IRQF_PROBE;
+
+ if (irq == 21 || (irq >= 16 && irq <= 19) ||
+ irq == IRQ_KEYBOARDTX)
+ flags |= IRQF_NOAUTOEN;
+
+ switch (irq) {
+ case 0 ... 7:
+ irq_set_chip_and_handler(irq, &iomd_a_chip,
+ handle_level_irq);
+ set_irq_flags(irq, flags);
+ break;
+
+ case 8 ... 15:
+ irq_set_chip_and_handler(irq, &iomd_b_chip,
+ handle_level_irq);
+ set_irq_flags(irq, flags);
+ break;
+
+ case 16 ... 21:
+ irq_set_chip_and_handler(irq, &iomd_dma_chip,
+ handle_level_irq);
+ set_irq_flags(irq, flags);
+ break;
+
+ case 64 ... 71:
+ irq_set_chip(irq, &iomd_fiq_chip);
+ set_irq_flags(irq, IRQF_VALID);
+ break;
+ }
+ }
+
+ init_FIQ(FIQ_START);
+}
+