diff options
| author |   Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
| commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
| tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/mach-pxa/include | |
| parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) | |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/mach-pxa/include')
76 files changed, 8626 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-pxa/include/mach/addr-map.h b/kernel/arch/arm/mach-pxa/include/mach/addr-map.h new file mode 100644 index 000000000..d28fe2912 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/addr-map.h @@ -0,0 +1,53 @@ +#ifndef __ASM_MACH_ADDR_MAP_H +#define __ASM_MACH_ADDR_MAP_H + +/* + * Chip Selects + */ +#define PXA_CS0_PHYS 0x00000000 +#define PXA_CS1_PHYS 0x04000000 +#define PXA_CS2_PHYS 0x08000000 +#define PXA_CS3_PHYS 0x0C000000 +#define PXA_CS4_PHYS 0x10000000 +#define PXA_CS5_PHYS 0x14000000 + +#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ +#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ +#define PXA3xx_CS2_PHYS 0x10000000 +#define PXA3xx_CS3_PHYS 0x14000000 + +/* + * Peripheral Bus + */ +#define PERIPH_PHYS 0x40000000 +#define PERIPH_VIRT IOMEM(0xf2000000) +#define PERIPH_SIZE 0x02000000 + +/* + * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) + */ +#define PXA2XX_SMEMC_PHYS 0x48000000 +#define PXA3XX_SMEMC_PHYS 0x4a000000 +#define SMEMC_VIRT IOMEM(0xf6000000) +#define SMEMC_SIZE 0x00100000 + +/* + * Dynamic Memory Controller (only on PXA3xx) + */ +#define DMEMC_PHYS 0x48100000 +#define DMEMC_VIRT IOMEM(0xf6100000) +#define DMEMC_SIZE 0x00100000 + +/* + * Reserved space for low level debug virtual addresses within + * 0xf6200000..0xf6201000 + */ + +/* + * Internal Memory Controller (PXA27x and later) + */ +#define IMEMC_PHYS 0x58000000 +#define IMEMC_VIRT IOMEM(0xfe000000) +#define IMEMC_SIZE 0x00100000 + +#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/audio.h b/kernel/arch/arm/mach-pxa/include/mach/audio.h new file mode 100644 index 000000000..a3449e35a --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/audio.h @@ -0,0 +1,30 @@ +#ifndef __ASM_ARCH_AUDIO_H__ +#define __ASM_ARCH_AUDIO_H__ + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/ac97_codec.h> + +/* + * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95) + * a -1 value means no gpio will be used for reset + * @codec_pdata: AC97 codec platform_data + + * reset_gpio should only be specified for pxa27x CPUs where a silicon + * bug prevents correct operation of the reset line. If not specified, + * the default behaviour on these CPUs is to consider gpio 113 as the + * AC97 reset line, which is the default on most boards. + */ +typedef struct { + int (*startup)(struct snd_pcm_substream *, void *); + void (*shutdown)(struct snd_pcm_substream *, void *); + void (*suspend)(void *); + void (*resume)(void *); + void *priv; + int reset_gpio; + void *codec_pdata[AC97_BUS_MAX_DEVICES]; +} pxa2xx_audio_ops_t; + +extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/balloon3.h b/kernel/arch/arm/mach-pxa/include/mach/balloon3.h new file mode 100644 index 000000000..1b0825911 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/balloon3.h @@ -0,0 +1,184 @@ +/* + * linux/include/asm-arm/arch-pxa/balloon3.h + * + * Authors: Nick Bane and Wookey + * Created: Oct, 2005 + * Copyright: Toby Churchill Ltd + * Cribbed from mainstone.c, by Nicholas Pitre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ASM_ARCH_BALLOON3_H +#define ASM_ARCH_BALLOON3_H + +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + +enum balloon3_features { + BALLOON3_FEATURE_OHCI, + BALLOON3_FEATURE_MMC, + BALLOON3_FEATURE_CF, + BALLOON3_FEATURE_AUDIO, + BALLOON3_FEATURE_TOPPOLY, +}; + +#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS +#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ +#define BALLOON3_FPGA_LENGTH 0x01000000 + +#define BALLOON3_FPGA_SETnCLR (0x1000) + +/* FPGA / CPLD registers for CF socket */ +#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +/* FPGA / CPLD version register */ +#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c) +/* FPGA / CPLD registers for NAND flash */ +#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) +#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) +#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) +#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) +#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) + +/* fpga/cpld interrupt control register */ +#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C) +#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c) + +#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000) +#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004) +#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c) + +/* CF Status Register bits (read-only) bits */ +#define BALLOON3_CF_nIRQ (1 << 0) +#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1) + +/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */ +#define BALLOON3_CF_RESET (1 << 0) +#define BALLOON3_CF_ENABLE (1 << 1) +#define BALLOON3_CF_ADD_ENABLE (1 << 2) + +/* CF Interrupt sources */ +#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) +#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) + +/* NAND Control register */ +#define BALLOON3_NAND_CONTROL_FLWP (1 << 7) +#define BALLOON3_NAND_CONTROL_FLSE (1 << 6) +#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5) +#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4) +#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3) +#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2) +#define BALLOON3_NAND_CONTROL_FLALE (1 << 1) +#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0) + +/* NAND Status register */ +#define BALLOON3_NAND_STAT_RNB (1 << 0) + +/* NAND Control2 register */ +#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0) + +/* GPIOs for irqs */ +#define BALLOON3_GPIO_AUX_NIRQ (94) +#define BALLOON3_GPIO_CODEC_IRQ (95) + +/* Timer and Idle LED locations */ +#define BALLOON3_GPIO_LED_NAND (9) +#define BALLOON3_GPIO_LED_IDLE (10) + +/* backlight control */ +#define BALLOON3_GPIO_RUN_BACKLIGHT (99) + +#define BALLOON3_GPIO_S0_CD (105) + +/* NAND */ +#define BALLOON3_GPIO_RUN_NAND (102) + +/* PCF8574A Leds */ +#define BALLOON3_PCF_GPIO_BASE 160 +#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0) +#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1) +#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2) +#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3) +#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4) +#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5) +#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6) +#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7) + +/* FPGA Interrupt Mask/Acknowledge Register */ +#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */ +#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */ + +/* CPLD (and FPGA) interface definitions */ +#define CPLD_LCD0_DATA_SET 0x00 +#define CPLD_LCD0_DATA_CLR 0x10 +#define CPLD_LCD0_COMMAND_SET 0x01 +#define CPLD_LCD0_COMMAND_CLR 0x11 +#define CPLD_LCD1_DATA_SET 0x02 +#define CPLD_LCD1_DATA_CLR 0x12 +#define CPLD_LCD1_COMMAND_SET 0x03 +#define CPLD_LCD1_COMMAND_CLR 0x13 + +#define CPLD_MISC_SET 0x07 +#define CPLD_MISC_CLR 0x17 +#define CPLD_MISC_LOON_NRESET_BIT 0 +#define CPLD_MISC_LOON_UNSUSP_BIT 1 +#define CPLD_MISC_RUN_5V_BIT 2 +#define CPLD_MISC_CHG_D0_BIT 3 +#define CPLD_MISC_CHG_D1_BIT 4 +#define CPLD_MISC_DAC_NCS_BIT 5 + +#define CPLD_LCD_SET 0x08 +#define CPLD_LCD_CLR 0x18 +#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0 +#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1 +#define CPLD_LCD_LED_RED_BIT 4 +#define CPLD_LCD_LED_GREEN_BIT 5 +#define CPLD_LCD_NRESET_BIT 7 + +#define CPLD_LCD_RO_SET 0x09 +#define CPLD_LCD_RO_CLR 0x19 +#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0 +#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1 + +#define CPLD_SERIAL_SET 0x0a +#define CPLD_SERIAL_CLR 0x1a +#define CPLD_SERIAL_GSM_RI_BIT 0 +#define CPLD_SERIAL_GSM_CTS_BIT 1 +#define CPLD_SERIAL_GSM_DTR_BIT 2 +#define CPLD_SERIAL_LPR_CTS_BIT 3 +#define CPLD_SERIAL_TC232_CTS_BIT 4 +#define CPLD_SERIAL_TC232_DSR_BIT 5 + +#define CPLD_SROUTING_SET 0x0b +#define CPLD_SROUTING_CLR 0x1b +#define CPLD_SROUTING_MSP430_LPR 0 +#define CPLD_SROUTING_MSP430_TC232 1 +#define CPLD_SROUTING_MSP430_GSM 2 +#define CPLD_SROUTING_LOON_LPR (0 << 4) +#define CPLD_SROUTING_LOON_TC232 (1 << 4) +#define CPLD_SROUTING_LOON_GSM (2 << 4) + +#define CPLD_AROUTING_SET 0x0c +#define CPLD_AROUTING_CLR 0x1c +#define CPLD_AROUTING_MIC2PHONE_BIT 0 +#define CPLD_AROUTING_PHONE2INT_BIT 1 +#define CPLD_AROUTING_PHONE2EXT_BIT 2 +#define CPLD_AROUTING_LOONL2INT_BIT 3 +#define CPLD_AROUTING_LOONL2EXT_BIT 4 +#define CPLD_AROUTING_LOONR2PHONE_BIT 5 +#define CPLD_AROUTING_LOONR2INT_BIT 6 +#define CPLD_AROUTING_LOONR2EXT_BIT 7 + +/* Balloon3 Interrupts */ +#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) + +#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) + +#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) + +extern int balloon3_has(enum balloon3_features feature); + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/bitfield.h b/kernel/arch/arm/mach-pxa/include/mach/bitfield.h new file mode 100644 index 000000000..f1f0e3387 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/bitfield.h @@ -0,0 +1,113 @@ +/* + * FILE bitfield.h + * + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) + * Language C or ARM Assembly + * Purpose Definition of macros to operate on bit fields. + */ + + + +#ifndef __BITFIELD_H +#define __BITFIELD_H + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long) (Data)) +#else +#define UData(Data) (Data) +#endif + + +/* + * MACRO: Fld + * + * Purpose + * The macro "Fld" encodes a bit field, given its size and its shift value + * with respect to bit 0. + * + * Note + * A more intuitive way to encode bit fields would have been to use their + * mask. However, extracting size and shift value information from a bit + * field's mask is cumbersome and might break the assembler (255-character + * line-size limit). + * + * Input + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. + * + * Output + * Fld Encoded bit field. + */ + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + + +/* + * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit + * + * Purpose + * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return + * the size, shift value, mask, aligned mask, and first bit of a + * bit field. + * + * Input + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. + */ + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) +#define F1stBit(Field) (UData (1) << FShft (Field)) + + +/* + * MACRO: FInsrt + * + * Purpose + * The macro "FInsrt" inserts a value into a bit field by shifting the + * former appropriately. + * + * Input + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FInsrt Bit-field value positioned appropriately. + */ + +#define FInsrt(Value, Field) \ + (UData (Value) << FShft (Field)) + + +/* + * MACRO: FExtr + * + * Purpose + * The macro "FExtr" extracts the value of a bit field by masking and + * shifting it appropriately. + * + * Input + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). + * + * Output + * FExtr Bit-field value. + */ + +#define FExtr(Data, Field) \ + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + + +#endif /* __BITFIELD_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/colibri.h b/kernel/arch/arm/mach-pxa/include/mach/colibri.h new file mode 100644 index 000000000..cb4236e98 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/colibri.h @@ -0,0 +1,69 @@ +#ifndef _COLIBRI_H_ +#define _COLIBRI_H_ + +#include <net/ax88796.h> +#include <mach/mfp.h> + +/* + * base board glue for PXA270 module + */ + +enum { + COLIBRI_EVALBOARD = 0, + COLIBRI_PXA270_INCOME, +}; + +#if defined(CONFIG_MACH_COLIBRI_EVALBOARD) +extern void colibri_evalboard_init(void); +#else +static inline void colibri_evalboard_init(void) {} +#endif + +#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) +extern void colibri_pxa270_income_boardinit(void); +#else +static inline void colibri_pxa270_income_boardinit(void) {} +#endif + +/* + * common settings for all modules + */ + +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin); +#else +static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) {} +#endif + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +extern void colibri_pxa3xx_init_lcd(int bl_pin); +#else +static inline void colibri_pxa3xx_init_lcd(int bl_pin) {} +#endif + +#if defined(CONFIG_AX88796) +extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data); +#endif + +#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) +extern void colibri_pxa3xx_init_nand(void); +#else +static inline void colibri_pxa3xx_init_nand(void) {} +#endif + +/* physical memory regions */ +#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ + +/* GPIO definitions for Colibri PXA270 */ +#define GPIO114_COLIBRI_PXA270_ETH_IRQ 114 +#define GPIO0_COLIBRI_PXA270_SD_DETECT 0 +#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 + +/* GPIO definitions for Colibri PXA300/310 */ +#define GPIO13_COLIBRI_PXA300_SD_DETECT 13 + +/* GPIO definitions for Colibri PXA320 */ +#define GPIO28_COLIBRI_PXA320_SD_DETECT 28 + +#endif /* _COLIBRI_H_ */ + diff --git a/kernel/arch/arm/mach-pxa/include/mach/corgi.h b/kernel/arch/arm/mach-pxa/include/mach/corgi.h new file mode 100644 index 000000000..c030d955b --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/corgi.h @@ -0,0 +1,114 @@ +/* + * Hardware specific definitions for SL-C7xx series of PDAs + * + * Copyright (c) 2004-2005 Richard Purdie + * + * Based on Sharp's 2.4 kernel patches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __ASM_ARCH_CORGI_H +#define __ASM_ARCH_CORGI_H 1 + +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + +/* + * Corgi (Non Standard) GPIO Definitions + */ +#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */ +#define CORGI_GPIO_AC_IN (1) /* Charger Detection */ +#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */ +#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */ +#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */ +#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */ +#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */ +#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */ +#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */ +#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */ +#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */ +#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */ +#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */ +#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */ +#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ +#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ +#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ +#define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */ +#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ +#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ +#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ +#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */ +#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */ +#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */ +#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */ + + +/* + * Corgi Keyboard Definitions + */ +#define CORGI_KEY_STROBE_NUM (12) +#define CORGI_KEY_SENSE_NUM (8) +#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) +#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) +#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) +#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) +#define CORGI_GPIO_LOW_SENSE_LSHIFT (6) +#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) +#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) +#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) +#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) +#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) +#define CORGI_GPIO_KEY_SENSE(a) (58+(a)) +#define CORGI_GPIO_KEY_STROBE(a) (66+(a)) + + +/* + * Corgi Interrupts + */ +#define CORGI_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(0) +#define CORGI_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define CORGI_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(3) +#define CORGI_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(4) +#define CORGI_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define CORGI_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define CORGI_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(10) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(11) +#define CORGI_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define CORGI_IRQ_GPIO_CHRG_FULL PXA_GPIO_TO_IRQ(16) /* Battery fully charged */ +#define CORGI_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define CORGI_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */ + + +/* + * Corgi SCOOP GPIOs and Config + */ +#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11 +#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */ +#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */ +#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14 +#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15 +#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16 +#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17 +#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18 +#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19 + +#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ + CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ + CORGI_SCP_MIC_BIAS ) +#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) + +#define CORGI_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0) +#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */ +#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */ +#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3) +#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4) +#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5) +#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6) +#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7) +#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8) + +#endif /* __ASM_ARCH_CORGI_H */ + diff --git a/kernel/arch/arm/mach-pxa/include/mach/csb726.h b/kernel/arch/arm/mach-pxa/include/mach/csb726.h new file mode 100644 index 000000000..00cfbbbf7 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/csb726.h @@ -0,0 +1,28 @@ +/* + * Support for Cogent CSB726 + * + * Copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef CSB726_H +#define CSB726_H + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +#define CSB726_GPIO_IRQ_LAN 52 +#define CSB726_GPIO_IRQ_SM501 53 +#define CSB726_GPIO_MMC_DETECT 100 +#define CSB726_GPIO_MMC_RO 101 + +#define CSB726_FLASH_SIZE (64 * 1024 * 1024) +#define CSB726_FLASH_uMON (8 * 1024 * 1024) + +#define CSB726_IRQ_LAN PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN) +#define CSB726_IRQ_SM501 PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501) + +#endif + diff --git a/kernel/arch/arm/mach-pxa/include/mach/dma.h b/kernel/arch/arm/mach-pxa/include/mach/dma.h new file mode 100644 index 000000000..5bd55894a --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/dma.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-pxa/include/mach/dma.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#include <mach/hardware.h> + +/* DMA Controller Registers Definitions */ +#define DMAC_REGS_VIRT io_p2v(0x40000000) + +#include <plat/dma.h> +#endif /* _ASM_ARCH_DMA_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/kernel/arch/arm/mach-pxa/include/mach/eseries-gpio.h new file mode 100644 index 000000000..f3e550982 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/eseries-gpio.h @@ -0,0 +1,67 @@ +/* + * eseries-gpio.h + * + * Copyright (C) Ian Molton <spyro@f2s.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* e-series power button */ +#define GPIO_ESERIES_POWERBTN 0 + +/* UDC GPIO definitions */ +#define GPIO_E7XX_USB_DISC 13 +#define GPIO_E7XX_USB_PULLUP 3 + +#define GPIO_E800_USB_DISC 4 +#define GPIO_E800_USB_PULLUP 84 + +/* e740 PCMCIA GPIO definitions */ +/* Note: PWR1 seems to be inverted */ +#define GPIO_E740_PCMCIA_CD0 8 +#define GPIO_E740_PCMCIA_CD1 44 +#define GPIO_E740_PCMCIA_RDY0 11 +#define GPIO_E740_PCMCIA_RDY1 6 +#define GPIO_E740_PCMCIA_RST0 27 +#define GPIO_E740_PCMCIA_RST1 24 +#define GPIO_E740_PCMCIA_PWR0 20 +#define GPIO_E740_PCMCIA_PWR1 23 + +/* e750 PCMCIA GPIO definitions */ +#define GPIO_E750_PCMCIA_CD0 8 +#define GPIO_E750_PCMCIA_RDY0 12 +#define GPIO_E750_PCMCIA_RST0 27 +#define GPIO_E750_PCMCIA_PWR0 20 + +/* e800 PCMCIA GPIO definitions */ +#define GPIO_E800_PCMCIA_RST0 69 +#define GPIO_E800_PCMCIA_RST1 72 +#define GPIO_E800_PCMCIA_PWR0 20 +#define GPIO_E800_PCMCIA_PWR1 73 + +/* e7xx IrDA power control */ +#define GPIO_E7XX_IR_OFF 38 + +/* e740 audio control GPIOs */ +#define GPIO_E740_WM9705_nAVDD2 16 +#define GPIO_E740_MIC_ON 40 +#define GPIO_E740_AMP_ON 41 + +/* e750 audio control GPIOs */ +#define GPIO_E750_HP_AMP_OFF 4 +#define GPIO_E750_SPK_AMP_OFF 7 +#define GPIO_E750_HP_DETECT 37 + +/* e800 audio control GPIOs */ +#define GPIO_E800_HP_DETECT 81 +#define GPIO_E800_HP_AMP_OFF 82 +#define GPIO_E800_SPK_AMP_ON 83 + +/* ASIC related GPIOs */ +#define GPIO_ESERIES_TMIO_IRQ 5 +#define GPIO_ESERIES_TMIO_PCLR 19 +#define GPIO_ESERIES_TMIO_SUSPEND 45 +#define GPIO_E800_ANGELX_IRQ 8 diff --git a/kernel/arch/arm/mach-pxa/include/mach/eseries-irq.h b/kernel/arch/arm/mach-pxa/include/mach/eseries-irq.h new file mode 100644 index 000000000..de292b269 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/eseries-irq.h @@ -0,0 +1,28 @@ +/* + * eseries-irq.h + * + * Copyright (C) Ian Molton <spyro@f2s.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8) +#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n)) + +#define ANGELX_RDY0_IRQ IRQ_ANGELX(0) +#define ANGELX_ST0_IRQ IRQ_ANGELX(1) +#define ANGELX_CD0_IRQ IRQ_ANGELX(2) +#define ANGELX_RDY1_IRQ IRQ_ANGELX(3) +#define ANGELX_ST1_IRQ IRQ_ANGELX(4) +#define ANGELX_CD1_IRQ IRQ_ANGELX(5) + +#define TMIO_IRQ_BASE (IRQ_BOARD_START+0) +#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n)) + +#define TMIO_SD_IRQ IRQ_TMIO(1) +#define TMIO_USB_IRQ IRQ_TMIO(2) + +#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16) diff --git a/kernel/arch/arm/mach-pxa/include/mach/generic.h b/kernel/arch/arm/mach-pxa/include/mach/generic.h new file mode 100644 index 000000000..665542e0c --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/generic.h @@ -0,0 +1 @@ +#include "../../generic.h" diff --git a/kernel/arch/arm/mach-pxa/include/mach/gumstix.h b/kernel/arch/arm/mach-pxa/include/mach/gumstix.h new file mode 100644 index 000000000..f7df27bbb --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/gumstix.h @@ -0,0 +1,92 @@ +/* + * arch/arm/mach-pxa/include/mach/gumstix.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/* BTRESET - Reset line to Bluetooth module, active low signal. */ +#define GPIO_GUMSTIX_BTRESET 7 +#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT) + + +/* +GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean +interrupt signal for determining cable presence. On the gumstix F, +this moves to GPIO17 and GPIO37. */ + +/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn +has detected a cable insertion; driven low otherwise. */ + +#define GPIO_GUMSTIX_USB_GPIOn 35 +#define GPIO_GUMSTIX_USB_GPIOx 41 + +/* usb state change */ +#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn) + +#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) +#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) +#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) + +/* + * SD/MMC definitions + */ +#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ +#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ +#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT) + +/* + * SMC Ethernet definitions + * ETH_RST provides a hardware reset line to the ethernet chip + * ETH is the IRQ line in from the ethernet chip to the PXA + */ +#define GPIO_GUMSTIX_ETH0_RST 80 +#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT) +#define GPIO_GUMSTIX_ETH1_RST 52 +#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT) + +#define GPIO_GUMSTIX_ETH0 36 +#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) +#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0) +#define GPIO_GUMSTIX_ETH1 27 +#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) +#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1) + + +/* CF reset line */ +#define GPIO8_RESET 8 + +/* CF slot 0 */ +#define GPIO4_nBVD1 4 +#define GPIO4_nSTSCHG GPIO4_nBVD1 +#define GPIO11_nCD 11 +#define GPIO26_PRDY_nBSY 26 +#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG) +#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD) +#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY) + +/* CF slot 1 */ +#define GPIO18_nBVD1 18 +#define GPIO18_nSTSCHG GPIO18_nBVD1 +#define GPIO36_nCD 36 +#define GPIO27_PRDY_nBSY 27 +#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG) +#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD) +#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY) + +/* CF GPIO line modes */ +#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) +#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT) +#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN) +#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN) +#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) +#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) +#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) + +/* for expansion boards that can't be programatically detected */ +extern int am200_init(void); +extern int am300_init(void); + diff --git a/kernel/arch/arm/mach-pxa/include/mach/h5000.h b/kernel/arch/arm/mach-pxa/include/mach/h5000.h new file mode 100644 index 000000000..2a5ae3802 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/h5000.h @@ -0,0 +1,113 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright(20)02 Hewlett-Packard Company. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks + */ + +#ifndef __ASM_ARCH_H5000_H +#define __ASM_ARCH_H5000_H + +#include <mach/mfp-pxa25x.h> + +/* + * CPU GPIOs + */ + +#define H5000_GPIO_POWER_BUTTON (0) +#define H5000_GPIO_RESET_BUTTON_N (1) +#define H5000_GPIO_OPT_INT (2) +#define H5000_GPIO_BACKUP_POWER (3) +#define H5000_GPIO_ACTION_BUTTON (4) +#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ +/* 6 not connected */ +#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ +/* 8 not connected */ +#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ +#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ +#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ +/*(12) not connected */ +#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ +#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ +/*(15) is CS1# */ +/*(16) not connected */ +/*(17) not connected */ +/*(18) is pcmcia ready */ +/*(19) is dreq1 */ +/*(20) is dreq0 */ +#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ +/*(22) is not connected */ +#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ +/*(27) not connected */ +#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ +/*(33) is CS5# */ +#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ + +#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ + +#define H5000_GPIO_IRDA_RXD (46) +#define H5000_GPIO_IRDA_TXD (47) + +#define H5000_GPIO_POE_N (48) /* used for pcmcia */ +#define H5000_GPIO_PWE_N (49) /* used for pcmcia */ +#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ +#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ +#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ +#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ +#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ +#define H5000_GPIO_PREG_N (55) /* used for pcmcia */ +#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ +#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ + +#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ +/*(59) not connected */ +#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ +#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ +#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ +/*(63) is not connected */ +#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ +#define H5000_GPIO_CHG_EN (65) /* to sc801 en */ +#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ +#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ +#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ +/*(69) is not connected */ +#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ +#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) +#define H5000_GPIO_BT_M_RESET (72) +#define H5000_GPIO_STD_CHG_RATE (73) +#define H5000_GPIO_SD_WP_N (74) +#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ +#define H5000_GPIO_HEADPHONE_DETECT (76) +#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ +/*(78) is CS2# */ +/*(79) is CS3# */ +/*(80) is CS4# */ + +#endif /* __ASM_ARCH_H5000_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/hardware.h b/kernel/arch/arm/mach-pxa/include/mach/hardware.h new file mode 100644 index 000000000..8d63c211b --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/hardware.h @@ -0,0 +1,310 @@ +/* + * arch/arm/mach-pxa/include/mach/hardware.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <mach/addr-map.h> + +/* + * Workarounds for at least 2 errata so far require this. + * The mapping is set in mach-pxa/generic.c. + */ +#define UNCACHED_PHYS_0 0xfe000000 +#define UNCACHED_PHYS_0_SIZE 0x00100000 + +/* + * Intel PXA2xx internal register mapping: + * + * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff + * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff + * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff + * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff + * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff + * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff + * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff + * + * Note that not all PXA2xx chips implement all those addresses, and the + * kernel only maps the minimum needed range of this mapping. + */ +#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) +#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) + +#ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) + +/* With indexed regs we don't want to feed the index through io_p2v() + especially if it is a variable, otherwise horrible code will result. */ +# define __REG2(x,y) \ + (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) + +# define __PREG(x) (io_v2p((u32)&(x))) + +#else + +# define __REG(x) io_p2v(x) +# define __PREG(x) io_v2p(x) + +#endif + +#ifndef __ASSEMBLY__ + +#include <asm/cputype.h> + +/* + * CPU Stepping CPU_ID JTAG_ID + * + * PXA210 B0 0x69052922 0x2926C013 + * PXA210 B1 0x69052923 0x3926C013 + * PXA210 B2 0x69052924 0x4926C013 + * PXA210 C0 0x69052D25 0x5926C013 + * + * PXA250 A0 0x69052100 0x09264013 + * PXA250 A1 0x69052101 0x19264013 + * PXA250 B0 0x69052902 0x29264013 + * PXA250 B1 0x69052903 0x39264013 + * PXA250 B2 0x69052904 0x49264013 + * PXA250 C0 0x69052D05 0x59264013 + * + * PXA255 A0 0x69052D06 0x69264013 + * + * PXA26x A0 0x69052903 0x39264013 + * PXA26x B0 0x69052D05 0x59264013 + * + * PXA27x A0 0x69054110 0x09265013 + * PXA27x A1 0x69054111 0x19265013 + * PXA27x B0 0x69054112 0x29265013 + * PXA27x B1 0x69054113 0x39265013 + * PXA27x C0 0x69054114 0x49265013 + * PXA27x C5 0x69054117 0x79265013 + * + * PXA30x A0 0x69056880 0x0E648013 + * PXA30x A1 0x69056881 0x1E648013 + * PXA31x A0 0x69056890 0x0E649013 + * PXA31x A1 0x69056891 0x1E649013 + * PXA31x A2 0x69056892 0x2E649013 + * PXA32x B1 0x69056825 0x5E642013 + * PXA32x B2 0x69056826 0x6E642013 + * + * PXA930 B0 0x69056835 0x5E643013 + * PXA930 B1 0x69056837 0x7E643013 + * PXA930 B2 0x69056838 0x8E643013 + * + * PXA935 A0 0x56056931 0x1E653013 + * PXA935 B0 0x56056936 0x6E653013 + * PXA935 B1 0x56056938 0x8E653013 + */ +#ifdef CONFIG_PXA25x +#define __cpu_is_pxa210(id) \ + ({ \ + unsigned int _id = (id) & 0xf3f0; \ + _id == 0x2120; \ + }) + +#define __cpu_is_pxa250(id) \ + ({ \ + unsigned int _id = (id) & 0xf3ff; \ + _id <= 0x2105; \ + }) + +#define __cpu_is_pxa255(id) \ + ({ \ + unsigned int _id = (id) & 0xffff; \ + _id == 0x2d06; \ + }) + +#define __cpu_is_pxa25x(id) \ + ({ \ + unsigned int _id = (id) & 0xf300; \ + _id == 0x2100; \ + }) +#else +#define __cpu_is_pxa210(id) (0) +#define __cpu_is_pxa250(id) (0) +#define __cpu_is_pxa255(id) (0) +#define __cpu_is_pxa25x(id) (0) +#endif + +#ifdef CONFIG_PXA27x +#define __cpu_is_pxa27x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x411; \ + }) +#else +#define __cpu_is_pxa27x(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA300 +#define __cpu_is_pxa300(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x688; \ + }) +#else +#define __cpu_is_pxa300(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA310 +#define __cpu_is_pxa310(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x689; \ + }) +#else +#define __cpu_is_pxa310(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA320 +#define __cpu_is_pxa320(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x603 || _id == 0x682; \ + }) +#else +#define __cpu_is_pxa320(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA930 +#define __cpu_is_pxa930(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x683; \ + }) +#else +#define __cpu_is_pxa930(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA935 +#define __cpu_is_pxa935(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x693; \ + }) +#else +#define __cpu_is_pxa935(id) (0) +#endif + +#define cpu_is_pxa210() \ + ({ \ + __cpu_is_pxa210(read_cpuid_id()); \ + }) + +#define cpu_is_pxa250() \ + ({ \ + __cpu_is_pxa250(read_cpuid_id()); \ + }) + +#define cpu_is_pxa255() \ + ({ \ + __cpu_is_pxa255(read_cpuid_id()); \ + }) + +#define cpu_is_pxa25x() \ + ({ \ + __cpu_is_pxa25x(read_cpuid_id()); \ + }) + +#define cpu_is_pxa27x() \ + ({ \ + __cpu_is_pxa27x(read_cpuid_id()); \ + }) + +#define cpu_is_pxa300() \ + ({ \ + __cpu_is_pxa300(read_cpuid_id()); \ + }) + +#define cpu_is_pxa310() \ + ({ \ + __cpu_is_pxa310(read_cpuid_id()); \ + }) + +#define cpu_is_pxa320() \ + ({ \ + __cpu_is_pxa320(read_cpuid_id()); \ + }) + +#define cpu_is_pxa930() \ + ({ \ + __cpu_is_pxa930(read_cpuid_id()); \ + }) + +#define cpu_is_pxa935() \ + ({ \ + __cpu_is_pxa935(read_cpuid_id()); \ + }) + + + +/* + * CPUID Core Generation Bit + * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x + */ +#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) +#define __cpu_is_pxa2xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id <= 0x2; \ + }) +#else +#define __cpu_is_pxa2xx(id) (0) +#endif + +#ifdef CONFIG_PXA3xx +#define __cpu_is_pxa3xx(id) \ + ({ \ + __cpu_is_pxa300(id) \ + || __cpu_is_pxa310(id) \ + || __cpu_is_pxa320(id) \ + || __cpu_is_pxa93x(id); \ + }) +#else +#define __cpu_is_pxa3xx(id) (0) +#endif + +#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) +#define __cpu_is_pxa93x(id) \ + ({ \ + __cpu_is_pxa930(id) \ + || __cpu_is_pxa935(id); \ + }) +#else +#define __cpu_is_pxa93x(id) (0) +#endif + +#define cpu_is_pxa2xx() \ + ({ \ + __cpu_is_pxa2xx(read_cpuid_id()); \ + }) + +#define cpu_is_pxa3xx() \ + ({ \ + __cpu_is_pxa3xx(read_cpuid_id()); \ + }) + +#define cpu_is_pxa93x() \ + ({ \ + __cpu_is_pxa93x(read_cpuid_id()); \ + }) + + +/* + * return current memory and LCD clock frequency in units of 10kHz + */ +extern unsigned int get_memclk_frequency_10khz(void); + +/* return the clock tick rate of the OS timer */ +extern unsigned long get_clock_tick_rate(void); +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/hx4700.h b/kernel/arch/arm/mach-pxa/include/mach/hx4700.h new file mode 100644 index 000000000..0e1bb4626 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/hx4700.h @@ -0,0 +1,133 @@ +/* + * GPIO and IRQ definitions for HP iPAQ hx4700 + * + * Copyright (c) 2008 Philipp Zabel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _HX4700_H_ +#define _HX4700_H_ + +#include <linux/gpio.h> +#include <linux/mfd/asic3.h> +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + +#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO +#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) +#define HX4700_NR_IRQS (IRQ_BOARD_START + 70) + +/* + * PXA GPIOs + */ + +#define GPIO0_HX4700_nKEY_POWER 0 +#define GPIO12_HX4700_ASIC3_IRQ 12 +#define GPIO13_HX4700_W3220_IRQ 13 +#define GPIO14_HX4700_nWLAN_IRQ 14 +#define GPIO18_HX4700_RDY 18 +#define GPIO22_HX4700_LCD_RL 22 +#define GPIO27_HX4700_CODEC_ON 27 +#define GPIO32_HX4700_RS232_ON 32 +#define GPIO52_HX4700_CPU_nBATT_FAULT 52 +#define GPIO58_HX4700_TSC2046_nPENIRQ 58 +#define GPIO59_HX4700_LCD_PC1 59 +#define GPIO60_HX4700_CF_RNB 60 +#define GPIO61_HX4700_W3220_nRESET 61 +#define GPIO62_HX4700_LCD_nRESET 62 +#define GPIO63_HX4700_CPU_SS_nRESET 63 +#define GPIO65_HX4700_TSC2046_PEN_PU 65 +#define GPIO66_HX4700_ASIC3_nSDIO_IRQ 66 +#define GPIO67_HX4700_EUART_PS 67 +#define GPIO70_HX4700_LCD_SLIN1 70 +#define GPIO71_HX4700_ASIC3_nRESET 71 +#define GPIO72_HX4700_BQ24022_nCHARGE_EN 72 +#define GPIO73_HX4700_LCD_UD_1 73 +#define GPIO75_HX4700_EARPHONE_nDET 75 +#define GPIO76_HX4700_USBC_PUEN 76 +#define GPIO81_HX4700_CPU_GP_nRESET 81 +#define GPIO82_HX4700_EUART_RESET 82 +#define GPIO83_HX4700_WLAN_nRESET 83 +#define GPIO84_HX4700_LCD_SQN 84 +#define GPIO85_HX4700_nPCE1 85 +#define GPIO88_HX4700_TSC2046_CS 88 +#define GPIO91_HX4700_FLASH_VPEN 91 +#define GPIO92_HX4700_HP_DRIVER 92 +#define GPIO93_HX4700_EUART_INT 93 +#define GPIO94_HX4700_KEY_MAIL 94 +#define GPIO95_HX4700_BATT_OFF 95 +#define GPIO96_HX4700_BQ24022_ISET2 96 +#define GPIO97_HX4700_nBL_DETECT 97 +#define GPIO99_HX4700_KEY_CONTACTS 99 +#define GPIO100_HX4700_AUTO_SENSE 100 /* BL auto brightness */ +#define GPIO102_HX4700_SYNAPTICS_POWER_ON 102 +#define GPIO103_HX4700_SYNAPTICS_INT 103 +#define GPIO105_HX4700_nIR_ON 105 +#define GPIO106_HX4700_CPU_BT_nRESET 106 +#define GPIO107_HX4700_SPK_nSD 107 +#define GPIO109_HX4700_CODEC_nPDN 109 +#define GPIO110_HX4700_LCD_LVDD_3V3_ON 110 +#define GPIO111_HX4700_LCD_AVDD_3V3_ON 111 +#define GPIO112_HX4700_LCD_N2V7_7V3_ON 112 +#define GPIO114_HX4700_CF_RESET 114 +#define GPIO116_HX4700_CPU_HW_nRESET 116 + +/* + * ASIC3 GPIOs + */ + +#define GPIOC_BASE (HX4700_ASIC3_GPIO_BASE + 32) +#define GPIOD_BASE (HX4700_ASIC3_GPIO_BASE + 48) + +#define GPIOC0_LED_RED (GPIOC_BASE + 0) +#define GPIOC1_LED_GREEN (GPIOC_BASE + 1) +#define GPIOC2_LED_BLUE (GPIOC_BASE + 2) +#define GPIOC3_nSD_CS (GPIOC_BASE + 3) +#define GPIOC4_CF_nCD (GPIOC_BASE + 4) /* Input */ +#define GPIOC5_nCIOW (GPIOC_BASE + 5) /* Output, to CF */ +#define GPIOC6_nCIOR (GPIOC_BASE + 6) /* Output, to CF */ +#define GPIOC7_nPCE1 (GPIOC_BASE + 7) /* Input, from CPU */ +#define GPIOC8_nPCE2 (GPIOC_BASE + 8) /* Input, from CPU */ +#define GPIOC9_nPOE (GPIOC_BASE + 9) /* Input, from CPU */ +#define GPIOC10_CF_nPWE (GPIOC_BASE + 10) /* Input */ +#define GPIOC11_PSKTSEL (GPIOC_BASE + 11) /* Input, from CPU */ +#define GPIOC12_nPREG (GPIOC_BASE + 12) /* Input, from CPU */ +#define GPIOC13_nPWAIT (GPIOC_BASE + 13) /* Output, to CPU */ +#define GPIOC14_nPIOIS16 (GPIOC_BASE + 14) /* Output, to CPU */ +#define GPIOC15_nPIOR (GPIOC_BASE + 15) /* Input, from CPU */ + +#define GPIOD0_CPU_SS_INT (GPIOD_BASE + 0) /* Input */ +#define GPIOD1_nKEY_CALENDAR (GPIOD_BASE + 1) +#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2) +#define GPIOD3_nKEY_HOME (GPIOD_BASE + 3) +#define GPIOD4_CF_nCD (GPIOD_BASE + 4) /* Input, from CF */ +#define GPIOD5_nPIO (GPIOD_BASE + 5) /* Input */ +#define GPIOD6_nKEY_RECORD (GPIOD_BASE + 6) +#define GPIOD7_nSDIO_DETECT (GPIOD_BASE + 7) +#define GPIOD8_COM_DCD (GPIOD_BASE + 8) /* Input */ +#define GPIOD9_nAC_IN (GPIOD_BASE + 9) +#define GPIOD10_nSDIO_IRQ (GPIOD_BASE + 10) /* Input */ +#define GPIOD11_nCIOIS16 (GPIOD_BASE + 11) /* Input, from CF */ +#define GPIOD12_nCWAIT (GPIOD_BASE + 12) /* Input, from CF */ +#define GPIOD13_CF_RNB (GPIOD_BASE + 13) /* Input */ +#define GPIOD14_nUSBC_DETECT (GPIOD_BASE + 14) +#define GPIOD15_nPIOW (GPIOD_BASE + 15) /* Input, from CPU */ + +/* + * EGPIOs + */ + +#define EGPIO0_VCC_3V3_EN (HX4700_EGPIO_BASE + 0) /* WLAN support chip */ +#define EGPIO1_WL_VREG_EN (HX4700_EGPIO_BASE + 1) /* WLAN power */ +#define EGPIO2_VCC_2V1_WL_EN (HX4700_EGPIO_BASE + 2) /* unused */ +#define EGPIO3_SS_PWR_ON (HX4700_EGPIO_BASE + 3) /* smart slot power */ +#define EGPIO4_CF_3V3_ON (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */ +#define EGPIO5_BT_3V3_ON (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */ +#define EGPIO6_WL1V8_EN (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */ +#define EGPIO7_VCC_3V3_WL_EN (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */ +#define EGPIO8_USB_3V3_ON (HX4700_EGPIO_BASE + 8) /* unused */ + +#endif /* _HX4700_H_ */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/idp.h b/kernel/arch/arm/mach-pxa/include/mach/idp.h new file mode 100644 index 000000000..7e63f4680 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/idp.h @@ -0,0 +1,198 @@ +/* + * arch/arm/mach-pxa/include/mach/idp.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. + * + * 2001-09-13: Cliff Brake <cbrake@accelent.com> + * Initial code + * + * 2005-02-15: Cliff Brake <cliff.brake@gmail.com> + * <http://www.vibren.com> <http://bec-systems.com> + * Changes for 2.6 kernel. + */ + + +/* + * Note: this file must be safe to include in assembly files + * + * Support for the Vibren PXA255 IDP requires rev04 or later + * IDP hardware. + */ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +#define IDP_FLASH_PHYS (PXA_CS0_PHYS) +#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) +#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) +#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) +#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) +#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) +#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) + + +/* + * virtual memory map + */ + +#define IDP_COREVOLT_VIRT (0xf0000000) +#define IDP_COREVOLT_SIZE (1*1024*1024) + +#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE) +#define IDP_CPLD_SIZE (1*1024*1024) + +#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000 +#error Your custom IO space is getting a bit large !! +#endif + +#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT) +#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS) + +#ifndef __ASSEMBLY__ +# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) +#else +# define __CPLD_REG(x) CPLD_P2V(x) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_VIRT) */ + +#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) +#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) +#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) +#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) +#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) +#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) +#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) +#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) +#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) +#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) +#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) +#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) +#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) +#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) + +#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) +#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) +#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) +#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) + +/* FPGA register virtual addresses */ + +#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) +#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) +#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) +#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) +#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) +#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) +#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) +#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) +#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) +#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) +#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) +#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) +#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) +#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) + +#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) +#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) +#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) +#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) + + +/* + * Bit masks for various registers + */ + +// IDP_CPLD_PCCARD_PWR +#define PCC0_PWR0 (1 << 0) +#define PCC0_PWR1 (1 << 1) +#define PCC0_PWR2 (1 << 2) +#define PCC0_PWR3 (1 << 3) +#define PCC1_PWR0 (1 << 4) +#define PCC1_PWR1 (1 << 5) +#define PCC1_PWR2 (1 << 6) +#define PCC1_PWR3 (1 << 7) + +// IDP_CPLD_PCCARD_EN +#define PCC0_RESET (1 << 6) +#define PCC1_RESET (1 << 7) +#define PCC0_ENABLE (1 << 0) +#define PCC1_ENABLE (1 << 1) + +// IDP_CPLD_PCCARDx_STATUS +#define _PCC_WRPROT (1 << 7) // 7-4 read as low true +#define _PCC_RESET (1 << 6) +#define _PCC_IRQ (1 << 5) +#define _PCC_INPACK (1 << 4) +#define PCC_BVD2 (1 << 3) +#define PCC_BVD1 (1 << 2) +#define PCC_VS2 (1 << 1) +#define PCC_VS1 (1 << 0) + +/* A listing of interrupts used by external hardware devices */ + +#define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5) +#define IDE_IRQ PXA_GPIO_TO_IRQ(21) + +#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING + +#define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4) +#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +#define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7) +#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH + +#define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8) +#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH + +#define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19) +#define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22) + + +/* + * Macros for LED Driver + */ + +/* leds 0 = ON */ +#define IDP_HB_LED (1<<5) +#define IDP_BUSY_LED (1<<6) + +#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) + +/* + * macros for MTD driver + */ + +#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) +#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) + +/* + * macros for matrix keyboard driver + */ + +#define KEYBD_MATRIX_NUMBER_INPUTS 7 +#define KEYBD_MATRIX_NUMBER_OUTPUTS 14 + +#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE +#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE + +#define KEYBD_MATRIX_SETTLING_TIME_US 100 +#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 + +#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ +{\ + IDP_CPLD_KB_COL_LOW = outputs;\ + IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ +} + +#define KEYBD_MATRIX_GET_INPUTS(inputs) \ +{\ + inputs = (IDP_CPLD_KB_ROW & 0x7f);\ +} + + diff --git a/kernel/arch/arm/mach-pxa/include/mach/io.h b/kernel/arch/arm/mach-pxa/include/mach/io.h new file mode 100644 index 000000000..cd78b7fe3 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/io.h @@ -0,0 +1,17 @@ +/* + * arch/arm/mach-pxa/include/mach/io.h + * + * Copied from asm/arch/sa1100/io.h + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) __typesafe_io(a) + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/irqs.h b/kernel/arch/arm/mach-pxa/include/mach/irqs.h new file mode 100644 index 000000000..7e3ea351f --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/irqs.h @@ -0,0 +1,112 @@ +/* + * arch/arm/mach-pxa/include/mach/irqs.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#include <asm/irq.h> + +#define PXA_ISA_IRQ(x) (x) +#define PXA_IRQ(x) (NR_IRQS_LEGACY + (x)) + +#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ +#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ +#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ +#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ +#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ +#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ +#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ +#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ +#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ +#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ +#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ +#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ +#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ +#define IRQ_USB PXA_IRQ(11) /* USB Service */ +#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ +#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ +#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ +#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ +#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ +#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ +#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ +#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ +#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ +#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ +#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ +#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ +#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ +#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ +#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ +#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ +#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ +#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ +#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ +#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ +#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ +#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ +#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ +#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ + +#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ +#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ +#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ +#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ +#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ +#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ +#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ +#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ +#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ +#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ +#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ +#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ +#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ +#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ +#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ +#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ +#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ +#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ + +#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ +#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ +#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ +#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ +#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ +#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ + +#define PXA_GPIO_IRQ_BASE PXA_IRQ(96) +#define PXA_NR_BUILTIN_GPIO (192) +#define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) + +/* + * The following interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. + * By default, no board IRQ is reserved. It should be finished in + * custom board since sparse IRQ is already enabled. + */ +#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) + +#define PXA_NR_IRQS (IRQ_BOARD_START) + +#ifndef __ASSEMBLY__ +struct irq_data; +struct pt_regs; + +void pxa_mask_irq(struct irq_data *); +void pxa_unmask_irq(struct irq_data *); +void icip_handle_irq(struct pt_regs *); +void ichp_handle_irq(struct pt_regs *); + +void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); +#endif + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/littleton.h b/kernel/arch/arm/mach-pxa/include/mach/littleton.h new file mode 100644 index 000000000..8066be54e --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/littleton.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARCH_LITTLETON_H +#define __ASM_ARCH_LITTLETON_H + +#define LITTLETON_ETH_PHYS 0x30000000 + +#define LITTLETON_GPIO_LCD_CS (17) + +#define EXT0_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) + +#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8) + +#endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/lpd270.h b/kernel/arch/arm/mach-pxa/include/mach/lpd270.h new file mode 100644 index 000000000..4edc712a2 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/lpd270.h @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-pxa/include/mach/lpd270.h + * + * Author: Lennert Buytenhek + * Created: Feb 10, 2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_LPD270_H +#define __ASM_ARCH_LPD270_H + +#define LPD270_CPLD_PHYS PXA_CS2_PHYS +#define LPD270_CPLD_VIRT IOMEM(0xf0000000) +#define LPD270_CPLD_SIZE 0x00100000 + +#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) + +/* CPLD registers */ +#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x)) +#define LPD270_CONTROL LPD270_CPLD_REG(0x00) +#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) +#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) +#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14) +#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20) +#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24) +#define LPD270_EGPIO LPD270_CPLD_REG(0x30) +#define LPD270_INT_MASK LPD270_CPLD_REG(0x40) +#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50) + +#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ +#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ +#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ + +#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) +#define LPD270_USBC_IRQ LPD270_IRQ(2) +#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) +#define LPD270_AC97_IRQ LPD270_IRQ(4) +#define LPD270_NR_IRQS (IRQ_BOARD_START + 5) + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/lubbock.h b/kernel/arch/arm/mach-pxa/include/mach/lubbock.h new file mode 100644 index 000000000..1eecf794a --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/lubbock.h @@ -0,0 +1,56 @@ +/* + * arch/arm/mach-pxa/include/mach/lubbock.h + * + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/irqs.h> + +#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS + +#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS +#define LUBBOCK_FPGA_VIRT (0xf0000000) +#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) +#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) +#else +# define __LUB_REG(x) LUB_P2V(x) +#endif + +/* FPGA register virtual addresses */ +#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) +#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) +#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) +#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) +#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) +#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090) +#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0) +#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) +#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) + +/* Board specific IRQs */ +#define LUBBOCK_NR_IRQS IRQ_BOARD_START + +#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x)) +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) +#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ +#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) + +#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32) + +#ifndef __ASSEMBLY__ +extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/magician.h b/kernel/arch/arm/mach-pxa/include/mach/magician.h new file mode 100644 index 000000000..ba6a6e1d2 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/magician.h @@ -0,0 +1,120 @@ +/* + * GPIO and IRQ definitions for HTC Magician PDA phones + * + * Copyright (c) 2007 Philipp Zabel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _MAGICIAN_H_ +#define _MAGICIAN_H_ + +#include <linux/gpio.h> +#include <mach/irqs.h> + +/* + * PXA GPIOs + */ + +#define GPIO0_MAGICIAN_KEY_POWER 0 +#define GPIO9_MAGICIAN_UNKNOWN 9 +#define GPIO10_MAGICIAN_GSM_IRQ 10 +#define GPIO11_MAGICIAN_GSM_OUT1 11 +#define GPIO13_MAGICIAN_CPLD_IRQ 13 +#define GPIO18_MAGICIAN_UNKNOWN 18 +#define GPIO22_MAGICIAN_VIBRA_EN 22 +#define GPIO26_MAGICIAN_GSM_POWER 26 +#define GPIO27_MAGICIAN_USBC_PUEN 27 +#define GPIO30_MAGICIAN_BQ24022_nCHARGE_EN 30 +#define GPIO37_MAGICIAN_KEY_HANGUP 37 +#define GPIO38_MAGICIAN_KEY_CONTACTS 38 +#define GPIO40_MAGICIAN_GSM_OUT2 40 +#define GPIO48_MAGICIAN_UNKNOWN 48 +#define GPIO56_MAGICIAN_UNKNOWN 56 +#define GPIO57_MAGICIAN_CAM_RESET 57 +#define GPIO75_MAGICIAN_SAMSUNG_POWER 75 +#define GPIO83_MAGICIAN_nIR_EN 83 +#define GPIO86_MAGICIAN_GSM_RESET 86 +#define GPIO87_MAGICIAN_GSM_SELECT 87 +#define GPIO90_MAGICIAN_KEY_CALENDAR 90 +#define GPIO91_MAGICIAN_KEY_CAMERA 91 +#define GPIO93_MAGICIAN_KEY_UP 93 +#define GPIO94_MAGICIAN_KEY_DOWN 94 +#define GPIO95_MAGICIAN_KEY_LEFT 95 +#define GPIO96_MAGICIAN_KEY_RIGHT 96 +#define GPIO97_MAGICIAN_KEY_ENTER 97 +#define GPIO98_MAGICIAN_KEY_RECORD 98 +#define GPIO99_MAGICIAN_HEADPHONE_IN 99 +#define GPIO100_MAGICIAN_KEY_VOL_UP 100 +#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101 +#define GPIO102_MAGICIAN_KEY_PHONE 102 +#define GPIO103_MAGICIAN_LED_KP 103 +#define GPIO104_MAGICIAN_LCD_POWER_1 104 +#define GPIO105_MAGICIAN_LCD_POWER_2 105 +#define GPIO106_MAGICIAN_LCD_POWER_3 106 +#define GPIO107_MAGICIAN_DS1WM_IRQ 107 +#define GPIO108_MAGICIAN_GSM_READY 108 +#define GPIO114_MAGICIAN_UNKNOWN 114 +#define GPIO115_MAGICIAN_nPEN_IRQ 115 +#define GPIO116_MAGICIAN_nCAM_EN 116 +#define GPIO119_MAGICIAN_UNKNOWN 119 +#define GPIO120_MAGICIAN_UNKNOWN 120 + +/* + * CPLD IRQs + */ + +#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) +#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) +#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) +#define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) + +#define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8) + +/* + * CPLD EGPIOs + */ + +#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO +#define MAGICIAN_EGPIO(reg,bit) \ + (MAGICIAN_EGPIO_BASE + 8*reg + bit) + +/* output */ + +#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2) +#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5) +#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6) +#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7) +#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0) +#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1) +#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2) +#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3) +#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4) +#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5) +#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6) +#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7) +#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0) +#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1) +#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2) +#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3) +#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4) +#define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5) +#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7) + +/* input */ + +#define EGPIO_MAGICIAN_CABLE_STATE_AC MAGICIAN_EGPIO(4, 0) +#define EGPIO_MAGICIAN_CABLE_STATE_USB MAGICIAN_EGPIO(4, 1) + +#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0) +#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1) +#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2) +#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3) +#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4) + +#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1) + +#endif /* _MAGICIAN_H_ */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mainstone.h b/kernel/arch/arm/mach-pxa/include/mach/mainstone.h new file mode 100644 index 000000000..e82a7d311 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mainstone.h @@ -0,0 +1,141 @@ +/* + * arch/arm/mach-pxa/include/mach/mainstone.h + * + * Author: Nicolas Pitre + * Created: Nov 14, 2002 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ASM_ARCH_MAINSTONE_H +#define ASM_ARCH_MAINSTONE_H + +#include <mach/irqs.h> + +#define MST_ETH_PHYS PXA_CS4_PHYS + +#define MST_FPGA_PHYS PXA_CS2_PHYS +#define MST_FPGA_VIRT (0xf0000000) +#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) +#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) + +#ifndef __ASSEMBLY__ +# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) +#else +# define __MST_REG(x) MST_P2V(x) +#endif + +/* board level registers in the FPGA */ + +#define MST_LEDDAT1 __MST_REG(0x08000010) +#define MST_LEDDAT2 __MST_REG(0x08000014) +#define MST_LEDCTRL __MST_REG(0x08000040) +#define MST_GPSWR __MST_REG(0x08000060) +#define MST_MSCWR1 __MST_REG(0x08000080) +#define MST_MSCWR2 __MST_REG(0x08000084) +#define MST_MSCWR3 __MST_REG(0x08000088) +#define MST_MSCRD __MST_REG(0x08000090) +#define MST_INTMSKENA __MST_REG(0x080000c0) +#define MST_INTSETCLR __MST_REG(0x080000d0) +#define MST_PCMCIA0 __MST_REG(0x080000e0) +#define MST_PCMCIA1 __MST_REG(0x080000e4) + +#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ +#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ +#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ +#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ +#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ +#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ +#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ +#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ +#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ + +#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ +#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ +#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ +#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ +#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ + +#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ +#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ +#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ +#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ +#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ + +#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ +#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ +#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ +#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ +#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ +#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ +#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ + +#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ +#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ +#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ + +#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ +#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ +#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ +#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ +#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ +#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ +#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ +#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ +#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ +#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ + +#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ +#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ +#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ +#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ +#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ +#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ +#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ +#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ +#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ +#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ +#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ +#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ +#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ +#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ + +#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ +#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ +#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ +#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ +#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ +#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ +#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ +#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ + +#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ +#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ +#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ +#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ +#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ +#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ + +/* board specific IRQs */ +#define MAINSTONE_NR_IRQS IRQ_BOARD_START + +#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x)) +#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) +#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) +#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) +#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) +#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) +#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) +#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) +#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) +#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) +#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) +#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) +#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) +#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) +#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h new file mode 100644 index 000000000..cafadc33d --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h @@ -0,0 +1,225 @@ +#ifndef __ASM_ARCH_MFP_PXA25X_H +#define __ASM_ARCH_MFP_PXA25X_H + +#include <mach/mfp-pxa2xx.h> + +/* GPIO */ +#define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0) + +#define GPIO1_RST MFP_CFG_IN(GPIO1, AF1) + +/* Crystal and Clock Signals */ +#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) +#define GPIO70_RTCCLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) +#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) +#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) +#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) +#define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) +#define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW) + +/* SDRAM and Static Memory I/O Signals */ +#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) +#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) +#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) +#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) +#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) + +/* Miscellaneous I/O and DMA Signals */ +#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) +#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) +#define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1) + +/* Alternate Bus Master Mode I/O Signals */ +#define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW) +#define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW) +#define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1) +#define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1) + +/* PC CARD */ +#define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH) +#define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH) +#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) +#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) +#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) +#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) +#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) +#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) +#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) +#define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) + +/* FFUART */ +#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) +#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) +#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) +#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) +#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) +#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) +#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) +#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) + +/* BTUART */ +#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) +#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) +#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) +#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) + +/* STUART */ +#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) +#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) + +/* HWUART */ +#define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3) +#define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH) +#define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3) +#define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH) +#define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH) +#define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1) +#define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1) +#define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH) + +/* FICP */ +#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) +#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) + +/* PWM 0/1 */ +#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) +#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) + +/* AC97 */ +#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) +#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) +#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) +#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) +#define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1) + +/* I2S */ +#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) +#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) +#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) +#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) +#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) +#define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) + +/* SSP 1 */ +#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) +#define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW) +#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) +#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) +#define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1) + +/* SSP 2 - NSSP */ +#define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) +#define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1) +#define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW) +#define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1) +#define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW) +#define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2) +#define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW) +#define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2) + +/* MMC */ +#define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW) +#define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW) +#define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) +#define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW) +#define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) +#define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) +#define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW) +#define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW) +#define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW) +#define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW) + +/* LCD */ +#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) +#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) +#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) +#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) +#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) +#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) +#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) +#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) +#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) +#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) +#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) +#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) +#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) +#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) +#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) +#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) +#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) +#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) +#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) +#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) + +#ifdef CONFIG_CPU_PXA26x +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) + +/* SDRAM */ +#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) +#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) +#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) + +/* USB */ +#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) +#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) +#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) +#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) +#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) + +/* ASSP */ +#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) +#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) +#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) +#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) +#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) + +/* AC97 */ +#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) +#endif /* CONFIG_CPU_PXA26x */ + +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_DSTN_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + +#endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h new file mode 100644 index 000000000..b6132aa95 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -0,0 +1,471 @@ +#ifndef __ASM_ARCH_MFP_PXA27X_H +#define __ASM_ARCH_MFP_PXA27X_H + +/* + * NOTE: for those special-function bidirectional GPIOs, as described + * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input + * alternative is preserved, the direction is actually selected by the + * specific controller, and this should work in most cases. + */ + +#include <mach/mfp-pxa2xx.h> + +/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN + * bit is set, regardless of the GPIO configuration + */ +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) + +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) + +/* Crystal and Clock Signals */ +#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) +#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) +#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) +#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) +#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) + +/* OS Timer Signals */ +#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) +#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) +#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) +#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) +#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) +#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) + +/* SDRAM and Static Memory I/O Signals */ +#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) +#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) +#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) +#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) +#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) +#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) +#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) + +/* Miscellaneous I/O and DMA Signals */ +#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) +#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) +#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) +#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) +#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) +#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) +#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) +#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) +#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) +#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) +#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) + +/* Alternate Bus Master Mode I/O Signals */ +#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) +#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) +#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) +#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) +#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) +#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) +#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) +#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) + +/* PC CARD */ +#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) +#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) +#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) +#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) +#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) +#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) +#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) +#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) +#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) +#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) +#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) +#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) +#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) +#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) +#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) +#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) + +/* I2C */ +#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) +#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) + +/* FFUART */ +#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) +#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) +#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) +#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) +#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) +#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) +#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) +#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) +#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) +#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) +#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) +#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) +#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) +#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) +#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) +#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) +#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) +#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) +#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) +#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) +#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) +#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) +#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) +#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) +#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) +#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) +#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) +#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) +#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) + +/* BTUART */ +#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) +#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) +#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) +#define GPIO45_BTUART_RTS_LPM_LOW MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW) +#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) +#define GPIO43_BTUART_TXD_LPM_LOW MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW) + +/* STUART */ +#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) +#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) + +/* FICP */ +#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) +#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) +#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) +#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) + +/* PWM 0/1/2/3 */ +#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) +#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) +#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) +#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) +#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) +#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) +#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) +#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) +#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) +#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) + +/* AC97 */ +#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) +#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) +#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) +#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) +#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) +#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) +#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) +#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) +#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) +#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) +#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) +#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) +#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) + +/* I2S */ +#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) +#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) +#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) +#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) +#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) +#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) + +/* SSP 1 */ +#define GPIO23_SSP1_SCLK_IN MFP_CFG_IN(GPIO23, AF2) +#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) +#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) +#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) +#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) +#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) +#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) +#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) +#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) +#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) +#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) + +/* SSP 2 */ +#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) +#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) +#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) +#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) +#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) +#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) +#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) +#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) +#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) +#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) +#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) +#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) +#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) +#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) +#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) +#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) +#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) +#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) +#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) +#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) +#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) +#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) +#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) + +/* SSP 3 */ +#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) +#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) +#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) +#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) +#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) +#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) +#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) +#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) +#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) +#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) +#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) +#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) +#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) +#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) + +/* MMC */ +#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) +#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) +#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) +#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) +#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) +#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) + +/* LCD */ +#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) +#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) +#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) +#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) +#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) +#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) +#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) +#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) +#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) +#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) +#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) +#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) +#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) +#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) +#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) +#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) +#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) +#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) +#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) +#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) +#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) +#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) +#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) +#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) + +/* Keypad */ +#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) +#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) +#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) +#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) +#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) +#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) +#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) +#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) +#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) +#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) +#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) +#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) +#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) +#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) +#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) +#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) +#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) +#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) +#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) +#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) +#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) +#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) +#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) +#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) +#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) +#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) +#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) +#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) +#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) +#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) +#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) +#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) +#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) +#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) + +/* USB P3 */ +#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) +#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) +#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) +#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) +#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) +#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) +#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) +#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) + +/* USB P2 */ +#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) +#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) +#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) +#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) +#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) +#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) +#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) +#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) +#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) + +/* USB Host Port 1/2 */ +#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) +#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) +#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) + +/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ +#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) +#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) +#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) +#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) +#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) +#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) +#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) +#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) +#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) +#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) +#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) +#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) +#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) +#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) +#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) +#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) +#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) +#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) +#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) +#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) +#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) +#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) +#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) +#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) +#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) +#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) +#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) +#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) +#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) +#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) +#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) +#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) +#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) +#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) +#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) +#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) +#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) +#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) +#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) + +/* Universal Subscriber ID Interface */ +#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) +#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) +#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) +#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) +#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) +#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) +#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) +#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) +#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) +#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) + +/* Mobile Scalable Link (MSL) Interface */ +#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) +#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) +#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) +#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) +#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) +#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) +#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) +#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) +#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) +#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) +#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) +#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) +#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) +#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) + +/* Memory Stick Host Controller */ +#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) +#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) +#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) +#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) + +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + +/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */ +#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT) +#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT) + +extern int keypad_set_wake(unsigned int on); +#endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h new file mode 100644 index 000000000..cbf51ae81 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -0,0 +1,142 @@ +#ifndef __ASM_ARCH_MFP_PXA2XX_H +#define __ASM_ARCH_MFP_PXA2XX_H + +#include <plat/mfp.h> + +/* + * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: + * + * MFP_PIN(x) + * MFP_AFx + * MFP_LPM_DRIVE_{LOW, HIGH} + * MFP_LPM_EDGE_x + * + * other MFP_x bit definitions will be ignored + * + * and adds the below two bits specifically for pxa2xx: + * + * bit 23 - Input/Output (PXA2xx specific) + * bit 24 - Wakeup Enable(PXA2xx specific) + * bit 25 - Keep Output (PXA2xx specific) + */ + +#define MFP_DIR_IN (0x0 << 23) +#define MFP_DIR_OUT (0x1 << 23) +#define MFP_DIR_MASK (0x1 << 23) +#define MFP_DIR(x) (((x) >> 23) & 0x1) + +#define MFP_LPM_CAN_WAKEUP (0x1 << 24) + +/* + * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to + * retain their last output level (low or high). + * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. + */ +#define MFP_LPM_KEEP_OUTPUT (0x1 << 25) + +#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) +#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) +#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) + +/* specifically for enabling wakeup on keypad GPIOs */ +#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) + +#define MFP_CFG_IN(pin, af) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) + +/* NOTE: pins configured as output _must_ provide a low power state, + * and this state should help to minimize the power dissipation. + */ +#define MFP_CFG_OUT(pin, af, state) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) + +/* Common configurations for pxa25x and pxa27x + * + * Note: pins configured as GPIO are always initialized to input + * so not to cause any side effect + */ +#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) +#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) +#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) +#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) +#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) +#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) +#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) +#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) +#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) +#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) + +extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); +extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); +extern int gpio_set_wake(unsigned int gpio, unsigned int on); +#endif /* __ASM_ARCH_MFP_PXA2XX_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa300.h new file mode 100644 index 000000000..4e1287070 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa300.h @@ -0,0 +1,575 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp-pxa300.h + * + * PXA300/PXA310 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao <eric.miao@marvell.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA300_H +#define __ASM_ARCH_MFP_PXA300_H + +#include <mach/mfp-pxa3xx.h> + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#ifdef CONFIG_CPU_PXA310 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#endif + +/* Chip Select */ +#define GPIO1_nCS2 MFP_CFG(GPIO1, AF1) +#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) + +/* AC97 */ +#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) +#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) +#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) +#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) +#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) +#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) +#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) +#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) +#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) + +/* I2C */ +#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) +#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) +#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) +#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) +#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) +#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) +#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) +#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) +#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) +#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) +#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) +#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) +#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) +#define GPIO51_CI_HSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) +#define GPIO52_CI_VSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) + +/* KEYPAD */ +#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) +#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) +#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) +#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) +#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) +#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) +#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) +#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) +#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) +#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) +#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) +#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) +#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) +#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) + +#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) +#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) +#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) +#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) +#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) +#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) +#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) +#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) +#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) +#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) +#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) + +#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) +#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) +#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) +#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) +#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) +#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) +#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) +#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) +#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) +#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) +#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) +#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) +#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) +#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) +#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) +#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) +#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) +#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) +#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) +#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS02X) +#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) +#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) + +#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) +#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) +#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) + +/* Mini-LCD */ +#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) +#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) +#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) +#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) +#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) +#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) +#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) +#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) +#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) +#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) + +/* MMC1 */ +#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) +#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) +#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) +#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) + +/* MMC2 */ +#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) +#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) +#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) +#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) +#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) +#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) +#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) +#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) +#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) + +/* SSP1 */ +#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) +#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) +#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) +#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) +#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) +#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) +#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) +#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) +#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) +#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) +#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) +#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) +#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) +#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) +#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) +#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) +#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) +#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) +#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) + +/* SSP2 */ +#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) +#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) +#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) +#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) +#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) +#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) +#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) +#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) +#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) +#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) +#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) +#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) +#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) +#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) +#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) +#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) +#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) +#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) +#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) +#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) +#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) +#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) +#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) +#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) + +/* SSP3 */ +#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) +#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) +#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) +#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) +#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) +#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) +#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) +#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + +/* SSP4 */ +#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) +#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) +#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) +#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) + +/* UART1 */ +#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) +#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) +#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) + +#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) +#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) +#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) +#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) +#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) + +#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) +#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) + +#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) +#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) + +#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) +#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) + +#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) +#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) +#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) +#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) +#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) +#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) + +#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) +#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) +#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) + +/* UART2 */ +#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) +#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) +#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) + +#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) +#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) +#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) +#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) +#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) +#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) + +#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) +#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) +#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) + +/* UART3 */ +#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) + +#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) + +#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) +#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) +#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) +#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) +#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) + +#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) +#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) +#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) +#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) +#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) + +/* USB Host */ +#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) +#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) + +/* USB P3 */ +#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) +#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) +#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) + +/* PWM */ +#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) +#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) +#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) +#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) + +/* CIR */ +#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) +#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) + +#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) +#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) + +#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) +#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) +#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) +#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) +#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) +#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) +#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) +#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) +#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) +#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) + +#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) + +#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) +#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) +#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) +#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) + +#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) +#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) +#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) + +/* + * PXA300 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA300 +#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) +#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) +#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) +#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) +#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) +#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) +#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) +#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) +#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) +#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) +#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) + +/* U2D UTMI */ +#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) +#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) +#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) +#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) +#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) +#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) +#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) +#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) +#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) +#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) +#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) +#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) +#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) +#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) +#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) +#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) +#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) +#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) +#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) +#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) +#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) +#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) +#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) +#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) +#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) +#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) +#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) +#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) +#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) +#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) +#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) +#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) +#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) +#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) +#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) +#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) +#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) +#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) +#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) +#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) +#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) +#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) +#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) +#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) +#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) +#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) +#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) +#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) +#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) +#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) +#endif /* CONFIG_CPU_PXA300 */ + +/* + * PXA310 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA310 +/* USB P2 */ +#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) +#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) +#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) +#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) +#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) +#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) + +/* MMC1 */ +#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) +#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) + +/* MMC3 */ +#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) +#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) +#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) +#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) +#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) +#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) +#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) +#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) + +/* ULPI */ +#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) +#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) +#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) + +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, AF0, DS01X) +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, AF0, DS01X) +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, AF0, DS01X) +#endif /* CONFIG_CPU_PXA310 */ + +#endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa320.h new file mode 100644 index 000000000..3ce4682ea --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa320.h @@ -0,0 +1,461 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp-pxa320.h + * + * PXA320 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao <eric.miao@marvell.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA320_H +#define __ASM_ARCH_MFP_PXA320_H + +#include <mach/mfp-pxa3xx.h> + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) + +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) +#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) +#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) +#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) +#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) + +/* Chip Select */ +#define GPIO3_nCS2 MFP_CFG(GPIO3, AF1) +#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) + +/* AC97 */ +#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) +#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) +#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) +#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) +#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) +#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) +#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) +#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) +#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) +#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) +#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) + +/* I2C */ +#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) +#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) +#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) +#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) +#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) +#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) +#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) +#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) +#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) +#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) +#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) +#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) +#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) +#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) +#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) + +#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) + +#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) +#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) +#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) +#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) +#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) +#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) +#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) +#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) + +#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) + +#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) +#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) +#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) + +#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) + +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) +#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) + +#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) + +#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) +#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) +#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) + +#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) +#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) + +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) +#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) +#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) +#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) +#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) +#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) +#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) +#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) +#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) +#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) +#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) +#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) +#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) +#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) +#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) +#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) +#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) + +#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) +#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) +#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) +#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) +#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) +#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) +#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) +#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) +#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) +#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) +#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) +#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) +#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) +#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) + +/* MMC1 */ +#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) +#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) +#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) +#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) +#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) +#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) +#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) +#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) +#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) + +#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) +#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) +#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) +#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) +#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) + +#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) +#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) +#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) +#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) +#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) +#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) +#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) +#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) +#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) + +/* 1-Wire */ +#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) +#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) + +/* SSP1 */ +#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) +#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) +#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) +#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) +#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) +#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) +#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) + +/* SSP2 */ +#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) +#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) +#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) +#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) +#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) +#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) +#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) +#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) +#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) + +#define GPIO69_SSP3_SCLK MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT) +#define GPIO70_SSP3_FRM MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO89_SSP3_SCLK MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT) +#define GPIO90_SSP3_FRM MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) +#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) +#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) +#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) +#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) +#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) + +#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) +#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) +#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) +#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) +#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) + +/* UART1 */ +#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) +#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO75_UART1_RXD MFP_CFG_LPM(GPIO75, AF1, FLOAT) +#define GPIO76_UART1_RXD MFP_CFG_LPM(GPIO76, AF3, FLOAT) +#define GPIO76_UART1_TXD MFP_CFG_LPM(GPIO76, AF1, FLOAT) +#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) +#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) +#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) +#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) +#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) +#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) +#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) +#define GPIO77_UART1_CTS MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO82_UART1_RTS MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO82_UART1_CTS MFP_CFG_LPM(GPIO82, AF3, FLOAT) +#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) +#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) +#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) +#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) +#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) +#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) +#define GPIO79_UART1_DSR MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO78_UART1_DCD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) +#define GPIO80_UART1_RI MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +/* UART2 */ +#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) +#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) +#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +/* UART3 */ +#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) +#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) +#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) +#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) +#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) +#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) +#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) +#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) +#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) +#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) +#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) +#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) + + +/* USB 2.0 UTMI */ +#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) +#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) +#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) +#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) +#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) +#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) +#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) +#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) +#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) +#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) +#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) +#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) +#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) +#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) +#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) +#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) +#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) +#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) + +#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) +#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) +#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) +#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) +#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) +#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) +#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) +#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) + +#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) +#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) +#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) +#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) +#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) +#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) +#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) +#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) + +#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) +#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) +#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) + +#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) +#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) +#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) +#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) + +#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) +#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) +#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) + +#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) +#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) +#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) + +#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) +#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) +#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) + +#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) +#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) +#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) + +#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) +#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) +#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) + +/* USB Host 1.1 */ +#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) +#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) + +/* USB P2 */ +#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) +#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) +#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) +#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) +#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) +#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) +#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) +#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) +#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) + +/* USB P3 */ +#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) +#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) +#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) + +#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) +#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) + +#define GPIO2_RDY MFP_CFG(GPIO2, AF1) +#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) +#define GPIO6_NPIOW MFP_CFG(GPIO6, AF3) +#define GPIO7_NPIOS16 MFP_CFG(GPIO7, AF3) +#define GPIO8_NPWAIT MFP_CFG(GPIO8, AF3) + +#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) +#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) +#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) +#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) + +#endif /* __ASM_ARCH_MFP_PXA320_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h new file mode 100644 index 000000000..d375195d9 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h @@ -0,0 +1,158 @@ +#ifndef __ASM_ARCH_MFP_PXA3XX_H +#define __ASM_ARCH_MFP_PXA3XX_H + +#include <plat/mfp.h> + +#define MFPR_BASE (0x40e10000) + +/* PXA3xx common MFP configurations - processor specific ones defined + * in mfp-pxa300.h and mfp-pxa320.h + */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) + +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) + +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) + +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) + +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) + +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) + +/* NOTE: usage of these two functions is not recommended, + * use pxa3xx_mfp_config() instead. + */ +static inline unsigned long pxa3xx_mfp_read(int mfp) +{ + return mfp_read(mfp); +} + +static inline void pxa3xx_mfp_write(int mfp, unsigned long val) +{ + mfp_write(mfp, val); +} + +static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) +{ + mfp_config(mfp_cfg, num); +} +#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa930.h new file mode 100644 index 000000000..04f7c9704 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp-pxa930.h @@ -0,0 +1,498 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp-pxa930.h + * + * PXA930 specific MFP configuration definitions + * + * Copyright (C) 2007-2008 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA9xx_H +#define __ASM_ARCH_MFP_PXA9xx_H + +#include <mach/mfp-pxa3xx.h> + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0) +#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0) +#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0) +#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0) + +#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0) +#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0) +#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0) +#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0) +#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0) +#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0) +#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0) +#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0) +#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0) +#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0) +#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0) +#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0) +#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0) +#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0) +#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0) +#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0) +#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0) +#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0) +#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0) +#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0) +#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0) +#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0) +#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0) +#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0) +#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0) + +#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0) +#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0) +#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0) +#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0) +#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0) +#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0) +#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0) +#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) +#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) +#define RDY_GPIO_62 MFP_CFG(RDY, AF0) +#define PMIC_INT_GPIO83 MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH) + +/* Chip Select */ +#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) +#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH) + +/* AC97 */ +#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3) +#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3) +#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3) +#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3) +#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3) +#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3) + +/* I2C */ +#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH) +#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH) + +#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH) +#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH) + +#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) +#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) + +#define GPIO73_CI2C_SCL MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH) +#define GPIO74_CI2C_SDA MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH) + +#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) +#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) + +#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH) +#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH) + +#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) + +#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH) +#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH) + +/* QCI */ +#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW) +#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW) +#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW) +#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW) +#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW) +#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW) +#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW) +#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW) +#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW) +#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW) +#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW) +#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW) +#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW) +#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW) + +/* KEYPAD */ +#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT) +#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT) +#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT) +#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT) +#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT) +#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT) + +#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT) +#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT) +#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT) +#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT) + +#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT) + +#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT) +#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT) +#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT) +#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT) +#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT) +#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT) +#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT) +#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1) +#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4) + +#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH) +#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH) +#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH) +#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH) +#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH) +#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH) + +/* LCD */ +#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1) +#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1) +#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1) +#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1) +#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1) +#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2) +#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1) +#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1) +#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1) +#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1) +#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1) +#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1) +#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1) +#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1) +#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1) +#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1) +#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1) +#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1) +#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1) +#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1) +#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1) +#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1) +#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1) +#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1) +#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1) +#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3) +#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3) +#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1) + +/* Mini-LCD */ +#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3) +#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3) +#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3) +#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3) +#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3) +#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3) +#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3) +#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3) +#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3) +#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3) +#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3) +#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3) +#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3) +#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3) +#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3) +#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3) +#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3) +#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3) +#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3) +#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3) +#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5) + +/* MMC1 */ +#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4) +#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4) +#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4) +#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4) +#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4) +#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4) +#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3) +#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3) +#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3) +#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3) +#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3) +#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3) + +#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2) +#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2) +#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2) +#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3) +#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2) + +/* MMC2 */ +#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7) +#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7) +#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7) +#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7) +#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7) +#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7) + +#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1) +#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1) +#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1) +#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1) +#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1) +#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1) + +#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3) +#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3) +#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3) +#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3) +#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3) +#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3) + +/* BSSP1 */ +#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3) +#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3) +#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3) +#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3) +#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5) +#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5) + +/* BSSP2 */ +#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1) +#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1) +#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1) +#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1) +#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4) + +/* BSSP3 */ +#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1) +#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1) +#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1) +#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1) +#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1) + +/* BSSP4 */ +#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4) +#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4) +#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4) +#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4) + +#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4) +#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4) +#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4) +#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4) + +/* GSSP1 */ +#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2) +#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2) +#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2) +#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2) +#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2) + +#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4) +#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4) +#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4) +#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4) + +/* GSSP2 */ +#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4) +#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4) +#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4) +#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4) + +#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4) +#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4) +#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4) +#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4) + +#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2) +#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2) +#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2) +#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2) +#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2) +#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5) + +#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2) +#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2) +#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2) +#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2) + +/* UART1 - FFUART */ +#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1) +#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1) +#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1) +#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1) +#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1) +#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1) +#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1) +#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1) + +#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2) +#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2) +#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2) +#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2) +#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2) +#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2) +#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) +#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) + +#define GPIO53_UART1_TXD MFP_CFG(GPIO53, AF2) +#define GPIO54_UART1_RXD MFP_CFG(GPIO54, AF2) + +/* UART2 - BTUART */ +#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) +#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) +#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1) +#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1) + +/* UART3 - STUART */ +#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3) +#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3) +#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3) +#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3) + +#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5) +#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5) +#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5) +#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5) + +/* DFI */ +#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2) +#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2) +#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2) +#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2) +#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2) +#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2) +#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2) +#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2) +#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2) +#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2) +#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2) +#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2) +#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2) +#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2) +#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2) +#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2) +#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2) +#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2) +#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2) +#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2) +#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2) +#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2) + +/* DFI - NAND */ +#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH) +#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW) +#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW) +#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW) +#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW) +#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW) +#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW) +#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW) +#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW) +#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW) +#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW) +#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW) +#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW) +#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW) +#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW) +#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW) +#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW) +#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW) +#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH) +#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH) +#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH) +#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH) +#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH) +#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH) +#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH) + +/* PWM */ +#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW) +#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW) +#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW) +#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) +#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) +#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) +#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW) + +/* CIR */ +#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) +#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3) + +/* USB P2 */ +#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3) +#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5) +#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2) +#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7) +#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6) +#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3) + +#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2) +#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT) +#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2) +#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2) +#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2) +#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2) +#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2) +#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2) + +#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3) +#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3) +#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3) +#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3) +#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3) +#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3) +#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3) +#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3) + +/* ULPI */ +#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4) +#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7) +#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5) +#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5) +#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5) +#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5) +#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5) +#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5) +#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4) +#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4) +#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4) +#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4) + +#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3) +#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7) +#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5) +#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4) +#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3) +#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3) + +#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5) +#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7) +#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5) +#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4) + +#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3) +#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7) +#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3) +#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5) +#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4) +#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3) + +/* 1 wire */ +#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5) + +#endif /* __ASM_ARCH_MFP_PXA9xx_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mfp.h b/kernel/arch/arm/mach-pxa/include/mach/mfp.h new file mode 100644 index 000000000..271e249ae --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mfp.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp.h + * + * Multi-Function Pin Definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * 2007-8-21: eric miao <eric.miao@marvell.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_H +#define __ASM_ARCH_MFP_H + +#include <plat/mfp.h> + +#endif /* __ASM_ARCH_MFP_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mioa701.h b/kernel/arch/arm/mach-pxa/include/mach/mioa701.h new file mode 100644 index 000000000..e57f5c724 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mioa701.h @@ -0,0 +1,75 @@ +#ifndef _MIOA701_H_ +#define _MIOA701_H_ + +#define MIO_CFG_IN(pin, af) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ + (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN)) + +#define MIO_CFG_OUT(pin, af, state) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) + +/* Global GPIOs */ +#define GPIO9_CHARGE_EN 9 +#define GPIO18_POWEROFF 18 +#define GPIO87_LCD_POWER 87 +#define GPIO96_AC_DETECT 96 +#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ + +/* USB */ +#define GPIO13_nUSB_DETECT 13 +#define GPIO22_USB_ENABLE 22 + +/* SDIO bits */ +#define GPIO78_SDIO_RO 78 +#define GPIO15_SDIO_INSERT 15 +#define GPIO91_SDIO_EN 91 + +/* Bluetooth */ +#define GPIO14_BT_nACTIVITY 14 +#define GPIO83_BT_ON 83 +#define GPIO77_BT_UNKNOWN1 77 +#define GPIO86_BT_MAYBE_nRESET 86 + +/* GPS */ +#define GPIO23_GPS_UNKNOWN1 23 +#define GPIO26_GPS_ON 26 +#define GPIO27_GPS_RESET 27 +#define GPIO106_GPS_UNKNOWN2 106 +#define GPIO107_GPS_UNKNOWN3 107 + +/* GSM */ +#define GPIO24_GSM_MOD_RESET_CMD 24 +#define GPIO88_GSM_nMOD_ON_CMD 88 +#define GPIO90_GSM_nMOD_OFF_CMD 90 +#define GPIO114_GSM_nMOD_DTE_UART_STATE 114 +#define GPIO25_GSM_MOD_ON_STATE 25 +#define GPIO113_GSM_EVENT 113 + +/* SOUND */ +#define GPIO12_HPJACK_INSERT 12 + +/* LEDS */ +#define GPIO10_LED_nCharging 10 +#define GPIO97_LED_nBlue 97 +#define GPIO98_LED_nOrange 98 +#define GPIO82_LED_nVibra 82 +#define GPIO115_LED_nKeyboard 115 + +/* Keyboard */ +#define GPIO0_KEY_POWER 0 +#define GPIO93_KEY_VOLUME_UP 93 +#define GPIO94_KEY_VOLUME_DOWN 94 + +/* Camera */ +#define GPIO56_MT9M111_nOE 56 + +extern struct input_dev *mioa701_evdev; +extern void mioa701_gpio_lpm_set(unsigned long mfp_pin); + +/* Assembler externals mioa701_bootresume.S */ +extern u32 mioa701_bootstrap; +extern u32 mioa701_jumpaddr; +extern u32 mioa701_bootstrap_lg; + +#endif /* _MIOA701_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mtd-xip.h b/kernel/arch/arm/mach-pxa/include/mach/mtd-xip.h new file mode 100644 index 000000000..990d2bf2f --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mtd-xip.h @@ -0,0 +1,35 @@ +/* + * MTD primitives for XIP support. Architecture specific functions + * + * Do not include this file directly. It's included from linux/mtd/xip.h + * + * Author: Nicolas Pitre + * Created: Nov 2, 2004 + * Copyright: (C) 2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_PXA_MTD_XIP_H__ +#define __ARCH_PXA_MTD_XIP_H__ + +#include <mach/regs-ost.h> + +#define xip_irqpending() (ICIP & ICMR) + +/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ +#define xip_currtime() (OSCR) +#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) + +/* + * xip_cpu_idle() is used when waiting for a delay equal or larger than + * the system timer tick period. This should put the CPU into idle mode + * to save power and to be woken up only when some interrupts are pending. + * As above, this should not rely upon standard kernel code. + */ + +#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1)) + +#endif /* __ARCH_PXA_MTD_XIP_H__ */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/mxm8x10.h b/kernel/arch/arm/mach-pxa/include/mach/mxm8x10.h new file mode 100644 index 000000000..ffa15665a --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/mxm8x10.h @@ -0,0 +1,21 @@ +#ifndef __MACH_MXM_8X10_H +#define __MACH_MXM_8X10_H + +#define MXM_8X10_ETH_PHYS 0x13000000 + +#if defined(CONFIG_MMC) + +#define MXM_8X10_SD_nCD (72) +#define MXM_8X10_SD_WP (84) + +extern void mxm_8x10_mmc_init(void); +#else +static inline void mxm_8x10_mmc_init(void) {} +#endif + +extern void mxm_8x10_usb_host_init(void); +extern void mxm_8x10_ac97_init(void); + +extern void mxm_8x10_barebones_init(void); + +#endif /* __MACH_MXM_8X10_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/palm27x.h b/kernel/arch/arm/mach-pxa/include/mach/palm27x.h new file mode 100644 index 000000000..d4eac3d6f --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palm27x.h @@ -0,0 +1,81 @@ +/* + * Common functions for Palm LD, T5, TX, Z72 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __INCLUDE_MACH_PALM27X__ +#define __INCLUDE_MACH_PALM27X__ + +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +extern void __init palm27x_mmc_init(int detect, int ro, int power, + int power_inverted); +#else +static inline void palm27x_mmc_init(int detect, int ro, int power, + int power_inverted) +{} +#endif + +#if defined(CONFIG_SUSPEND) +extern void __init palm27x_pm_init(unsigned long str_base); +#else +static inline void palm27x_pm_init(unsigned long str_base) {} +#endif + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +extern struct pxafb_mode_info palm_320x480_lcd_mode; +extern struct pxafb_mode_info palm_320x320_lcd_mode; +extern struct pxafb_mode_info palm_320x320_new_lcd_mode; +extern void __init palm27x_lcd_init(int power, + struct pxafb_mode_info *mode); +#else +#define palm27x_lcd_init(power, mode) do {} while (0) +#endif + +#if defined(CONFIG_USB_PXA27X) || \ + defined(CONFIG_USB_PXA27X_MODULE) +extern void __init palm27x_udc_init(int vbus, int pullup, + int vbus_inverted); +#else +static inline void palm27x_udc_init(int vbus, int pullup, int vbus_inverted) {} +#endif + +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) +extern void __init palm27x_irda_init(int pwdn); +#else +static inline void palm27x_irda_init(int pwdn) {} +#endif + +#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \ + defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE) +extern void __init palm27x_ac97_init(int minv, int maxv, int jack, + int reset); +#else +static inline void palm27x_ac97_init(int minv, int maxv, int jack, int reset) {} +#endif + +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +extern void __init palm27x_pwm_init(int bl, int lcd); +#else +static inline void palm27x_pwm_init(int bl, int lcd) {} +#endif + +#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE) +extern void __init palm27x_power_init(int ac, int usb); +#else +static inline void palm27x_power_init(int ac, int usb) {} +#endif + +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +extern void __init palm27x_pmic_init(void); +#else +static inline void palm27x_pmic_init(void) {} +#endif + +#endif /* __INCLUDE_MACH_PALM27X__ */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmld.h b/kernel/arch/arm/mach-pxa/include/mach/palmld.h new file mode 100644 index 000000000..b184f2960 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmld.h @@ -0,0 +1,111 @@ +/* + * GPIOs and interrupts for Palm LifeDrive Handheld Computer + * + * Authors: Alex Osborne <ato@meshy.org> + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMLD_H_ +#define _INCLUDE_PALMLD_H_ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMLD_GPIO_RESET 1 +#define GPIO_NR_PALMLD_POWER_DETECT 4 +#define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMLD_POWER_SWITCH 12 +#define GPIO_NR_PALMLD_EARPHONE_DETECT 13 +#define GPIO_NR_PALMLD_LOCK_SWITCH 15 + +/* SD/MMC */ +#define GPIO_NR_PALMLD_SD_DETECT_N 14 +#define GPIO_NR_PALMLD_SD_POWER 114 +#define GPIO_NR_PALMLD_SD_READONLY 116 + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMLD_WM9712_IRQ 27 + +/* IRDA */ +#define GPIO_NR_PALMLD_IR_DISABLE 108 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMLD_BL_POWER 19 +#define GPIO_NR_PALMLD_LCD_POWER 96 + +/* LCD BORDER */ +#define GPIO_NR_PALMLD_BORDER_SWITCH 21 +#define GPIO_NR_PALMLD_BORDER_SELECT 22 + +/* BLUETOOTH */ +#define GPIO_NR_PALMLD_BT_POWER 17 +#define GPIO_NR_PALMLD_BT_RESET 83 + +/* PCMCIA (WiFi) */ +#define GPIO_NR_PALMLD_PCMCIA_READY 38 +#define GPIO_NR_PALMLD_PCMCIA_POWER 36 +#define GPIO_NR_PALMLD_PCMCIA_RESET 81 + +/* LEDs */ +#define GPIO_NR_PALMLD_LED_GREEN 52 +#define GPIO_NR_PALMLD_LED_AMBER 94 + +/* IDE */ +#define GPIO_NR_PALMLD_IDE_RESET 98 +#define GPIO_NR_PALMLD_IDE_PWEN 115 + +/* USB */ +#define GPIO_NR_PALMLD_USB_DETECT_N 3 +#define GPIO_NR_PALMLD_USB_READY 86 +#define GPIO_NR_PALMLD_USB_RESET 88 +#define GPIO_NR_PALMLD_USB_INT 106 +#define GPIO_NR_PALMLD_USB_POWER 118 +/* 20, 53 and 86 are usb related too */ + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMLD_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET) +#define IRQ_GPIO_PALMLD_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N) +#define IRQ_GPIO_PALMLD_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ) +#define IRQ_GPIO_PALMLD_IDE_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ) + + +/** HERE ARE INIT VALUES **/ + +/* IO mappings */ +#define PALMLD_USB_PHYS PXA_CS2_PHYS +#define PALMLD_USB_VIRT 0xf0000000 +#define PALMLD_USB_SIZE 0x00100000 + +#define PALMLD_IDE_PHYS 0x20000000 +#define PALMLD_IDE_VIRT 0xf1000000 +#define PALMLD_IDE_SIZE 0x00100000 + +#define PALMLD_PHYS_IO_START 0x40000000 +#define PALMLD_STR_BASE 0xa0200000 + +/* BATTERY */ +#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ +#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ +#define PALMLD_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */ + +#define PALMLD_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMLD_MAX_INTENSITY 0xFE +#define PALMLD_DEFAULT_INTENSITY 0x7E +#define PALMLD_LIMIT_MASK 0x7F +#define PALMLD_PRESCALER 0x3F +#define PALMLD_PERIOD_NS 3500 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmt5.h b/kernel/arch/arm/mach-pxa/include/mach/palmt5.h new file mode 100644 index 000000000..e342c5921 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmt5.h @@ -0,0 +1,86 @@ +/* + * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer + * + * Authors: Ales Snuparek <snuparek@atlas.cz> + * Marek Vasut <marek.vasut@gmail.com> + * Justin Kendrick <twilightsentry@gmail.com> + * RichardT5 <richard_t5@users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMT5_H_ +#define _INCLUDE_PALMT5_H_ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMT5_GPIO_RESET 1 + +#define GPIO_NR_PALMT5_POWER_DETECT 90 +#define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMT5_EARPHONE_DETECT 107 + +/* SD/MMC */ +#define GPIO_NR_PALMT5_SD_DETECT_N 14 +#define GPIO_NR_PALMT5_SD_POWER 114 +#define GPIO_NR_PALMT5_SD_READONLY 115 + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMT5_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMT5_IR_DISABLE 40 + +/* USB */ +#define GPIO_NR_PALMT5_USB_DETECT_N 15 +#define GPIO_NR_PALMT5_USB_PULLUP 93 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMT5_BL_POWER 84 +#define GPIO_NR_PALMT5_LCD_POWER 96 + +/* BLUETOOTH */ +#define GPIO_NR_PALMT5_BT_POWER 17 +#define GPIO_NR_PALMT5_BT_RESET 83 + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMT5_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N) +#define IRQ_GPIO_PALMT5_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ) +#define IRQ_GPIO_PALMT5_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT) +#define IRQ_GPIO_PALMT5_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET) + +/** HERE ARE INIT VALUES **/ + +/* Various addresses */ +#define PALMT5_PHYS_RAM_START 0xa0000000 +#define PALMT5_PHYS_IO_START 0x40000000 +#define PALMT5_STR_BASE 0xa0200000 + +/* TOUCHSCREEN */ +#define AC97_LINK_FRAME 21 + +/* BATTERY */ +#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#define PALMT5_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMT5_MAX_INTENSITY 0xFE +#define PALMT5_DEFAULT_INTENSITY 0x7E +#define PALMT5_LIMIT_MASK 0x7F +#define PALMT5_PRESCALER 0x3F +#define PALMT5_PERIOD_NS 3500 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmtc.h b/kernel/arch/arm/mach-pxa/include/mach/palmtc.h new file mode 100644 index 000000000..81c727b3c --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmtc.h @@ -0,0 +1,88 @@ +/* + * linux/include/asm-arm/arch-pxa/palmtc-gpio.h + * + * GPIOs and interrupts for Palm Tungsten|C Handheld Computer + * + * Authors: Alex Osborne <bobofdoom@gmail.com> + * Marek Vasut <marek.vasut@gmail.com> + * Holger Bocklet <bitz.email@gmx.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMTC_H_ +#define _INCLUDE_PALMTC_H_ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTC_EARPHONE_DETECT 2 +#define GPIO_NR_PALMTC_CRADLE_DETECT 5 +#define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7 + +/* SD/MMC */ +#define GPIO_NR_PALMTC_SD_DETECT_N 12 +#define GPIO_NR_PALMTC_SD_POWER 32 +#define GPIO_NR_PALMTC_SD_READONLY 54 + +/* WLAN */ +#define GPIO_NR_PALMTC_PCMCIA_READY 13 +#define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14 +#define GPIO_NR_PALMTC_PCMCIA_POWER1 15 +#define GPIO_NR_PALMTC_PCMCIA_POWER2 33 +#define GPIO_NR_PALMTC_PCMCIA_POWER3 55 +#define GPIO_NR_PALMTC_PCMCIA_RESET 78 + +/* UDC */ +#define GPIO_NR_PALMTC_USB_DETECT_N 4 +#define GPIO_NR_PALMTC_USB_POWER 36 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTC_BL_POWER 16 +#define GPIO_NR_PALMTC_LCD_POWER 44 +#define GPIO_NR_PALMTC_LCD_BLANK 38 + +/* UART */ +#define GPIO_NR_PALMTC_RS232_POWER 37 + +/* IRDA */ +#define GPIO_NR_PALMTC_IR_DISABLE 45 + +/* IRQs */ +#define IRQ_GPIO_PALMTC_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N) +#define IRQ_GPIO_PALMTC_WLAN_READY PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY) + +/* UCB1400 GPIOs */ +#define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00) +#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01) +#define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03) +#define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05) +#define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07) + +/** HERE ARE INIT VALUES **/ +#define PALMTC_UCB1400_GPIO_OFFSET 0x80 + +/* BATTERY */ +#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ +#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ +#define PALMTC_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */ + +#define PALMTC_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMTC_MAX_INTENSITY 0xFE +#define PALMTC_DEFAULT_INTENSITY 0x7E +#define PALMTC_LIMIT_MASK 0x7F +#define PALMTC_PRESCALER 0x3F +#define PALMTC_PERIOD_NS 3500 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmte2.h b/kernel/arch/arm/mach-pxa/include/mach/palmte2.h new file mode 100644 index 000000000..f89e989a7 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmte2.h @@ -0,0 +1,68 @@ +/* + * GPIOs and interrupts for Palm Tungsten|E2 Handheld Computer + * + * Author: + * Carlos Eduardo Medaglia Dyonisio <cadu@nerdfeliz.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMTE2_H_ +#define _INCLUDE_PALMTE2_H_ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTE2_POWER_DETECT 9 +#define GPIO_NR_PALMTE2_HOTSYNC_BUTTON_N 4 +#define GPIO_NR_PALMTE2_EARPHONE_DETECT 15 + +/* SD/MMC */ +#define GPIO_NR_PALMTE2_SD_DETECT_N 10 +#define GPIO_NR_PALMTE2_SD_POWER 55 +#define GPIO_NR_PALMTE2_SD_READONLY 51 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMTE2_IR_DISABLE 48 + +/* USB */ +#define GPIO_NR_PALMTE2_USB_DETECT_N 35 +#define GPIO_NR_PALMTE2_USB_PULLUP 53 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTE2_BL_POWER 56 +#define GPIO_NR_PALMTE2_LCD_POWER 37 + +/* KEYS */ +#define GPIO_NR_PALMTE2_KEY_NOTES 5 +#define GPIO_NR_PALMTE2_KEY_TASKS 7 +#define GPIO_NR_PALMTE2_KEY_CALENDAR 11 +#define GPIO_NR_PALMTE2_KEY_CONTACTS 13 +#define GPIO_NR_PALMTE2_KEY_CENTER 14 +#define GPIO_NR_PALMTE2_KEY_LEFT 19 +#define GPIO_NR_PALMTE2_KEY_RIGHT 20 +#define GPIO_NR_PALMTE2_KEY_DOWN 21 +#define GPIO_NR_PALMTE2_KEY_UP 22 + +/** HERE ARE INIT VALUES **/ + +/* BACKLIGHT */ +#define PALMTE2_MAX_INTENSITY 0xFE +#define PALMTE2_DEFAULT_INTENSITY 0x7E +#define PALMTE2_LIMIT_MASK 0x7F +#define PALMTE2_PRESCALER 0x3F +#define PALMTE2_PERIOD_NS 3500 + +/* BATTERY */ +#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTE2_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmtreo.h b/kernel/arch/arm/mach-pxa/include/mach/palmtreo.h new file mode 100644 index 000000000..714b65743 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmtreo.h @@ -0,0 +1,68 @@ +/* + * GPIOs and interrupts for Palm Treo smartphones + * + * currently supported: + * Palm Treo 680 (GSM) + * Palm Centro 685 (GSM) + * + * Author: Tomas Cech <sleep_walker@suse.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * find more info at www.hackndev.com + * + */ + +#ifndef _INCLUDE_TREO_H_ +#define _INCLUDE_TREO_H_ + +/* GPIOs */ +#define GPIO_NR_TREO_POWER_DETECT 0 +#define GPIO_NR_TREO_AMP_EN 27 +#define GPIO_NR_TREO_GREEN_LED 20 +#define GPIO_NR_TREO_RED_LED 79 +#define GPIO_NR_TREO_SD_DETECT_N 113 +#define GPIO_NR_TREO_EP_DETECT_N 116 +#define GPIO_NR_TREO_USB_DETECT 1 +#define GPIO_NR_TREO_USB_PULLUP 114 +#define GPIO_NR_TREO_GSM_POWER 40 +#define GPIO_NR_TREO_GSM_RESET 87 +#define GPIO_NR_TREO_GSM_WAKE 57 +#define GPIO_NR_TREO_GSM_HOST_WAKE 14 +#define GPIO_NR_TREO_GSM_TRIGGER 10 +#define GPIO_NR_TREO_IR_EN 115 +#define GPIO_NR_TREO_IR_TXD 47 +#define GPIO_NR_TREO_BL_POWER 38 +#define GPIO_NR_TREO_LCD_POWER 25 + +/* Treo680 specific GPIOs */ +#define GPIO_NR_TREO680_SD_READONLY 33 +#define GPIO_NR_TREO680_SD_POWER 42 +#define GPIO_NR_TREO680_VIBRATE_EN 44 +#define GPIO_NR_TREO680_KEYB_BL 24 +#define GPIO_NR_TREO680_BT_EN 43 +#define GPIO_NR_TREO680_LCD_POWER 77 +#define GPIO_NR_TREO680_LCD_EN 86 +#define GPIO_NR_TREO680_LCD_EN_N 25 + +/* Centro685 specific GPIOs */ +#define GPIO_NR_CENTRO_SD_POWER 21 +#define GPIO_NR_CENTRO_VIBRATE_EN 22 +#define GPIO_NR_CENTRO_KEYB_BL 33 +#define GPIO_NR_CENTRO_BT_EN 80 + +/* Various addresses */ +#define TREO_PHYS_RAM_START 0xa0000000 +#define TREO_PHYS_IO_START 0x40000000 +#define TREO_STR_BASE 0xa2000000 + +/* BACKLIGHT */ +#define TREO_MAX_INTENSITY 254 +#define TREO_DEFAULT_INTENSITY 160 +#define TREO_LIMIT_MASK 0x7F +#define TREO_PRESCALER 63 +#define TREO_PERIOD_NS 3500 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmtx.h b/kernel/arch/arm/mach-pxa/include/mach/palmtx.h new file mode 100644 index 000000000..92bc1f053 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmtx.h @@ -0,0 +1,114 @@ +/* + * GPIOs and interrupts for Palm T|X Handheld Computer + * + * Based on palmld-gpio.h by Alex Osborne + * + * Authors: Marek Vasut <marek.vasut@gmail.com> + * Cristiano P. <cristianop@users.sourceforge.net> + * Jan Herman <2hp@seznam.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMTX_H_ +#define _INCLUDE_PALMTX_H_ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTX_GPIO_RESET 1 + +#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ +#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMTX_EARPHONE_DETECT 107 + +/* SD/MMC */ +#define GPIO_NR_PALMTX_SD_DETECT_N 14 +#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ +#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMTX_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMTX_IR_DISABLE 40 + +/* USB */ +#define GPIO_NR_PALMTX_USB_DETECT_N 13 +#define GPIO_NR_PALMTX_USB_PULLUP 93 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTX_BL_POWER 84 +#define GPIO_NR_PALMTX_LCD_POWER 96 + +/* LCD BORDER */ +#define GPIO_NR_PALMTX_BORDER_SWITCH 98 +#define GPIO_NR_PALMTX_BORDER_SELECT 22 + +/* BLUETOOTH */ +#define GPIO_NR_PALMTX_BT_POWER 17 +#define GPIO_NR_PALMTX_BT_RESET 83 + +/* PCMCIA (WiFi) */ +#define GPIO_NR_PALMTX_PCMCIA_POWER1 94 +#define GPIO_NR_PALMTX_PCMCIA_POWER2 108 +#define GPIO_NR_PALMTX_PCMCIA_RESET 79 +#define GPIO_NR_PALMTX_PCMCIA_READY 116 + +/* NAND Flash ... this GPIO may be incorrect! */ +#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMTX_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET) + +/** HERE ARE INIT VALUES **/ + +/* Various addresses */ +#define PALMTX_PCMCIA_PHYS 0x28000000 +#define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) +#define PALMTX_PCMCIA_SIZE 0x100000 + +#define PALMTX_PHYS_RAM_START 0xa0000000 +#define PALMTX_PHYS_IO_START 0x40000000 + +#define PALMTX_STR_BASE 0xa0200000 + +#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ +#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ + +#define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24)) +#define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25)) +#define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) +#define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) + +/* TOUCHSCREEN */ +#define AC97_LINK_FRAME 21 + + +/* BATTERY */ +#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMTX_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#define PALMTX_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMTX_MAX_INTENSITY 0xFE +#define PALMTX_DEFAULT_INTENSITY 0x7E +#define PALMTX_LIMIT_MASK 0x7F +#define PALMTX_PRESCALER 0x3F +#define PALMTX_PERIOD_NS 3500 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/palmz72.h b/kernel/arch/arm/mach-pxa/include/mach/palmz72.h new file mode 100644 index 000000000..0d4700a79 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/palmz72.h @@ -0,0 +1,84 @@ +/* + * GPIOs and interrupts for Palm Zire72 Handheld Computer + * + * Authors: Alex Osborne <bobofdoom@gmail.com> + * Jan Herman <2hp@seznam.cz> + * Sergey Lapin <slapin@ossfans.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMZ72_H_ +#define _INCLUDE_PALMZ72_H_ + +/* Power and control */ +#define GPIO_NR_PALMZ72_GPIO_RESET 1 +#define GPIO_NR_PALMZ72_POWER_DETECT 0 + +/* SD/MMC */ +#define GPIO_NR_PALMZ72_SD_DETECT_N 14 +#define GPIO_NR_PALMZ72_SD_POWER_N 98 +#define GPIO_NR_PALMZ72_SD_RO 115 + +/* Touchscreen */ +#define GPIO_NR_PALMZ72_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMZ72_IR_DISABLE 49 + +/* USB */ +#define GPIO_NR_PALMZ72_USB_DETECT_N 15 +#define GPIO_NR_PALMZ72_USB_PULLUP 95 + +/* LCD/Backlight */ +#define GPIO_NR_PALMZ72_BL_POWER 20 +#define GPIO_NR_PALMZ72_LCD_POWER 96 + +/* LED */ +#define GPIO_NR_PALMZ72_LED_GREEN 88 + +/* Bluetooth */ +#define GPIO_NR_PALMZ72_BT_POWER 17 +#define GPIO_NR_PALMZ72_BT_RESET 83 + +/* Camera */ +#define GPIO_NR_PALMZ72_CAM_PWDN 56 +#define GPIO_NR_PALMZ72_CAM_RESET 57 +#define GPIO_NR_PALMZ72_CAM_POWER 91 + +/** Initial values **/ + +/* Battery */ +#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */ + +/* Backlight */ +#define PALMZ72_MAX_INTENSITY 0xFE +#define PALMZ72_DEFAULT_INTENSITY 0x7E +#define PALMZ72_LIMIT_MASK 0x7F +#define PALMZ72_PRESCALER 0x3F +#define PALMZ72_PERIOD_NS 3500 + +#ifdef CONFIG_PM +struct palmz72_resume_info { + u32 magic0; /* 0x0 */ + u32 magic1; /* 0x4 */ + u32 resume_addr; /* 0x8 */ + u32 pad[11]; /* 0xc..0x37 */ + u32 arm_control; /* 0x38 */ + u32 aux_control; /* 0x3c */ + u32 ttb; /* 0x40 */ + u32 domain_access; /* 0x44 */ + u32 process_id; /* 0x48 */ +}; +#endif +#endif + diff --git a/kernel/arch/arm/mach-pxa/include/mach/pcm027.h b/kernel/arch/arm/mach-pxa/include/mach/pcm027.h new file mode 100644 index 000000000..86ebd7b6c --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pcm027.h @@ -0,0 +1,86 @@ +/* + * arch/arm/mach-pxa/include/mach/pcm027.h + * + * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> + * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Definitions of CPU card resources only + */ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/* phyCORE-PXA270 (PCM027) Interrupts */ +#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) +#define PCM027_BTDET_IRQ PCM027_IRQ(0) +#define PCM027_FF_RI_IRQ PCM027_IRQ(1) +#define PCM027_MMCDET_IRQ PCM027_IRQ(2) +#define PCM027_PM_5V_IRQ PCM027_IRQ(3) + +#define PCM027_NR_IRQS (IRQ_BOARD_START + 32) + +/* I2C RTC */ +#define PCM027_RTC_IRQ_GPIO 0 +#define PCM027_RTC_IRQ PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO) +#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING +#define ADR_PCM027_RTC 0x51 /* I2C address */ + +/* I2C EEPROM */ +#define ADR_PCM027_EEPROM 0x54 /* I2C address */ + +/* Ethernet chip (SMSC91C111) */ +#define PCM027_ETH_IRQ_GPIO 52 +#define PCM027_ETH_IRQ PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO) +#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING +#define PCM027_ETH_PHYS PXA_CS5_PHYS +#define PCM027_ETH_SIZE (1*1024*1024) + +/* CAN controller SJA1000 (unsupported yet) */ +#define PCM027_CAN_IRQ_GPIO 114 +#define PCM027_CAN_IRQ PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO) +#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING +#define PCM027_CAN_PHYS 0x22000000 +#define PCM027_CAN_SIZE 0x100 + +/* SPI GPIO expander (unsupported yet) */ +#define PCM027_EGPIO_IRQ_GPIO 27 +#define PCM027_EGPIO_IRQ PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO) +#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING +#define PCM027_EGPIO_CS 24 +/* + * TODO: Switch this pin from dedicated usage to GPIO if + * more than the MAX7301 device is connected to this SPI bus + */ +#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD + +/* Flash memory */ +#define PCM027_FLASH_PHYS 0x00000000 +#define PCM027_FLASH_SIZE 0x02000000 + +/* onboard LEDs connected to GPIO */ +#define PCM027_LED_CPU 90 +#define PCM027_LED_HEARD_BEAT 91 + +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls baseboard's init function. + * TODO: Add your own basebaord init function and call it from + * inside pcm027_init(). This example here is for the developmen board. + * Refer pcm990-baseboard.c + */ +extern void pcm990_baseboard_init(void); diff --git a/kernel/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/kernel/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h new file mode 100644 index 000000000..7e544c149 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h @@ -0,0 +1,212 @@ +/* + * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h + * + * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> + * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <mach/pcm027.h> +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/* + * definitions relevant only when the PCM-990 + * development base board is in use + */ + +/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ +#define PCM990_CTRL_INT_IRQ_GPIO 9 +#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) +#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING +#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ +#define PCM990_CTRL_SIZE (1*1024*1024) + +#define PCM990_CTRL_PWR_IRQ_GPIO 14 +#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) +#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +/* visible CPLD (U7) registers */ +#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ +#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ +#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ +#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ + +#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ +#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ +#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ +#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ + +#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ +#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ +#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ +#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ + +#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ +#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ +#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ +#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ +#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ + +#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ +#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ + +#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ +#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ +#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ +#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ +#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ + +#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */ +#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ +#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ +#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ +#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ + +#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */ +#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ +#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ +#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ +#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ + +#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ +#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ +#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ +#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ +#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ + +#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ +#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ +#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ +#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ + +#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ +#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ +#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ + +#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ +#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ +#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ +#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ +#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ + +/* + * IDE + */ +#define PCM990_IDE_IRQ_GPIO 13 +#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) +#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING +#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ +#define PCM990_IDE_PLD_BASE 0xee000000 +#define PCM990_IDE_PLD_SIZE (1*1024*1024) + +/* visible CPLD (U6) registers */ +#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ +#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ +#define PCM990_IDE_STBY 0x0008 /* R System StandBy */ + +#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ +#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ +#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ +#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ + +#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ +#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ +#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ +#define PCM990_IDE_RDY 0x0008 /* RDY */ + +#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ +#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ +#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ +#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ + +#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ +#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ +#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ +#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ + +#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) +#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) + +/* + * Compact Flash + */ +#define PCM990_CF_IRQ_GPIO 11 +#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) +#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +#define PCM990_CF_CD_GPIO 12 +#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) +#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING + +#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ + +/* visible CPLD (U6) registers */ +#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ +#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ +#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ +#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ +#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ + +#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ +#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ +#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ + +#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ +#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ +#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ +#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ + +#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ +#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ +#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ +#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ +#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ + +#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ +#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ +#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ +#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ +#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ + +#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ +#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ +#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ +#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ +#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ + +#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ +#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ +#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ + +/* + * Wolfson AC97 Touch + */ +#define PCM990_AC97_IRQ_GPIO 10 +#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) +#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +/* + * MMC phyCORE + */ +#define PCM990_MMC0_IRQ_GPIO 9 +#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) +#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING + +/* + * USB phyCore + */ +#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) +#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) diff --git a/kernel/arch/arm/mach-pxa/include/mach/pm.h b/kernel/arch/arm/mach-pxa/include/mach/pm.h new file mode 100644 index 000000000..51558bcee --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pm.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/suspend.h> + +struct pxa_cpu_pm_fns { + int save_count; + void (*save)(unsigned long *); + void (*restore)(unsigned long *); + int (*valid)(suspend_state_t state); + void (*enter)(suspend_state_t state); + int (*prepare)(void); + void (*finish)(void); +}; + +extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; + +/* sleep.S */ +extern int pxa25x_finish_suspend(unsigned long); +extern int pxa27x_finish_suspend(unsigned long); + +extern int pxa_pm_enter(suspend_state_t state); +extern int pxa_pm_prepare(void); +extern void pxa_pm_finish(void); + +/* NOTE: this is for PM debugging on Lubbock, it's really a big + * ugly, but let's keep the crap minimum here, instead of direct + * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c + */ +#ifdef CONFIG_ARCH_LUBBOCK +extern void lubbock_set_hexled(uint32_t value); +#else +#define lubbock_set_hexled(x) +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/poodle.h b/kernel/arch/arm/mach-pxa/include/mach/poodle.h new file mode 100644 index 000000000..b56b19351 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/poodle.h @@ -0,0 +1,94 @@ +/* + * arch/arm/mach-pxa/include/mach/poodle.h + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Based on: + * arch/arm/mach-sa1100/include/mach/collie.h + * + * ChangeLog: + * 04-06-2001 Lineo Japan, Inc. + * 04-16-2001 SHARP Corporation + * Update to 2.6 John Lenz + */ +#ifndef __ASM_ARCH_POODLE_H +#define __ASM_ARCH_POODLE_H 1 + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/* + * GPIOs + */ +/* PXA GPIOs */ +#define POODLE_GPIO_ON_KEY (0) +#define POODLE_GPIO_AC_IN (1) +#define POODLE_GPIO_CO 16 +#define POODLE_GPIO_TP_INT (5) +#define POODLE_GPIO_TP_CS (24) +#define POODLE_GPIO_WAKEUP (11) /* change battery */ +#define POODLE_GPIO_GA_INT (10) +#define POODLE_GPIO_IR_ON (22) +#define POODLE_GPIO_HP_IN (4) +#define POODLE_GPIO_CF_IRQ (17) +#define POODLE_GPIO_CF_CD (14) +#define POODLE_GPIO_CF_STSCHG (14) +#define POODLE_GPIO_SD_PWR (33) +#define POODLE_GPIO_SD_PWR1 (3) +#define POODLE_GPIO_nSD_CLK (6) +#define POODLE_GPIO_nSD_WP (7) +#define POODLE_GPIO_nSD_INT (8) +#define POODLE_GPIO_nSD_DETECT (9) +#define POODLE_GPIO_MAIN_BAT_LOW (13) +#define POODLE_GPIO_BAT_COVER (13) +#define POODLE_GPIO_USB_PULLUP (20) +#define POODLE_GPIO_ADC_TEMP_ON (21) +#define POODLE_GPIO_BYPASS_ON (36) +#define POODLE_GPIO_CHRG_ON (38) +#define POODLE_GPIO_CHRG_FULL (16) +#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ + +/* PXA GPIOs */ +#define POODLE_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(0) +#define POODLE_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(1) +#define POODLE_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(4) +#define POODLE_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(16) +#define POODLE_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(5) +#define POODLE_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(11) +#define POODLE_IRQ_GPIO_GA_INT PXA_GPIO_TO_IRQ(10) +#define POODLE_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(17) +#define POODLE_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(14) +#define POODLE_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(8) +#define POODLE_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(9) +#define POODLE_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(13) + +/* SCOOP GPIOs */ +#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 +#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13 +#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18 +#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20 +#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21 +#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22 + +#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) +#define POODLE_SCOOP_IO_OUT ( 0 ) + +#define POODLE_SCOOP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0) +#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2) +#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7) +#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9) +#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10) +#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11) + +#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8) +#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10) +#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11) +#define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) +#define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) + +#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */ + +extern struct platform_device poodle_locomo_device; + +#endif /* __ASM_ARCH_POODLE_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa25x-udc.h b/kernel/arch/arm/mach-pxa/include/mach/pxa25x-udc.h new file mode 100644 index 000000000..1b80a4805 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa25x-udc.h @@ -0,0 +1,163 @@ +#ifndef _ASM_ARCH_PXA25X_UDC_H +#define _ASM_ARCH_PXA25X_UDC_H + +#ifdef _ASM_ARCH_PXA27X_UDC_H +#error "You can't include both PXA25x and PXA27x UDC support" +#endif + +#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ +#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ +#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ + +#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR_UDE (1 << 0) /* UDC enable */ +#define UDCCR_UDA (1 << 1) /* UDC active */ +#define UDCCR_RSM (1 << 2) /* Device resume */ +#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ +#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ +#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ +#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ +#define UDCCR_REM (1 << 7) /* Reset interrupt mask */ + +#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ +#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ +#define UDCCS0_IPR (1 << 1) /* IN packet ready */ +#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ +#define UDCCS0_SST (1 << 4) /* Sent stall */ +#define UDCCS0_FST (1 << 5) /* Force stall */ +#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ +#define UDCCS0_SA (1 << 7) /* Setup active */ + +/* Bulk IN - Endpoint 1,6,11 */ +#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ +#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ +#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ + +#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ +#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ +#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ +#define UDCCS_BI_SST (1 << 4) /* Sent stall */ +#define UDCCS_BI_FST (1 << 5) /* Force stall */ +#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ + +/* Bulk OUT - Endpoint 2,7,12 */ +#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ +#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ +#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ + +#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ +#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ +#define UDCCS_BO_DME (1 << 3) /* DMA enable */ +#define UDCCS_BO_SST (1 << 4) /* Sent stall */ +#define UDCCS_BO_FST (1 << 5) /* Force stall */ +#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ +#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ + +/* Isochronous IN - Endpoint 3,8,13 */ +#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ +#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ +#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ + +#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ +#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ +#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ +#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ + +/* Isochronous OUT - Endpoint 4,9,14 */ +#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ +#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ +#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ + +#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ +#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ +#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ +#define UDCCS_IO_DME (1 << 3) /* DMA enable */ +#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ +#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ + +/* Interrupt IN - Endpoint 5,10,15 */ +#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ +#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ +#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ + +#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ +#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ +#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ +#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ +#define UDCCS_INT_SST (1 << 4) /* Sent stall */ +#define UDCCS_INT_FST (1 << 5) /* Force stall */ +#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ + +#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ +#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ +#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ +#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ +#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ +#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ +#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ +#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ +#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ +#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ +#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ +#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ +#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ +#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ +#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ +#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ +#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ +#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ +#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ +#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ +#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ +#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ +#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ +#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ + +#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ + +#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ +#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ +#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ +#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ +#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ +#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ +#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ +#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ + +#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ + +#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ +#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ +#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ +#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ +#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ +#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ +#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ +#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ + +#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ + +#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ +#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ +#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ +#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ +#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ +#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ +#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ +#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ + +#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ + +#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ +#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ +#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ +#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ +#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ +#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ +#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ +#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa25x.h b/kernel/arch/arm/mach-pxa/include/mach/pxa25x.h new file mode 100644 index 000000000..5a341752e --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa25x.h @@ -0,0 +1,9 @@ +#ifndef __MACH_PXA25x_H +#define __MACH_PXA25x_H + +#include <mach/hardware.h> +#include <mach/pxa2xx-regs.h> +#include <mach/mfp-pxa25x.h> +#include <mach/irqs.h> + +#endif /* __MACH_PXA25x_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa27x-udc.h b/kernel/arch/arm/mach-pxa/include/mach/pxa27x-udc.h new file mode 100644 index 000000000..4cf28f670 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa27x-udc.h @@ -0,0 +1,257 @@ +#ifndef _ASM_ARCH_PXA27X_UDC_H +#define _ASM_ARCH_PXA27X_UDC_H + +#ifdef _ASM_ARCH_PXA25X_UDC_H +#error You cannot include both PXA25x and PXA27x UDC support +#endif + +#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ +#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation + Protocol Port Support */ +#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol + Support */ +#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol + Enable */ +#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ +#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ +#define UDCCR_ACN_S 11 +#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ +#define UDCCR_AIN_S 8 +#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface + Setting Number */ +#define UDCCR_AAISN_S 5 +#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active + Configuration */ +#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration + Error */ +#define UDCCR_UDR (1 << 2) /* UDC Resume */ +#define UDCCR_UDA (1 << 1) /* UDC Active */ +#define UDCCR_UDE (1 << 0) /* UDC Enable */ + +#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ +#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ +#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ +#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ + +#define UDC_INT_FIFOERROR (0x2) +#define UDC_INT_PACKETCMP (0x1) + +#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ +#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ +#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ +#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ +#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ + +#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ +#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ +#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ +#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ +#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ + +#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ +#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ +#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ +#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt + Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt + Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising + Edge Interrupt Enable */ +#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling + Edge Interrupt Enable */ +#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge + Interrupt Enable */ + +#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ +#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ + +#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ +#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ +#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ +#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ +#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ +#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ +#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ +#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ +#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ +#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ +#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ +#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ +#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ +#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ + +#define UDCCSN(x) __REG2(0x40600100, (x) << 2) +#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ +#define UDCCSR0_SA (1 << 7) /* Setup Active */ +#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define UDCCSR0_FST (1 << 5) /* Force Stall */ +#define UDCCSR0_SST (1 << 4) /* Sent Stall */ +#define UDCCSR0_DME (1 << 3) /* DMA Enable */ +#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ +#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ +#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ +#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ +#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ +#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ +#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ +#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ +#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ +#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ +#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ +#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ +#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ +#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ +#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ +#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ +#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ +#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ +#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ +#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ +#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ +#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ +#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ + +#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ +#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ +#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ +#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ +#define UDCCSR_FST (1 << 5) /* Force STALL */ +#define UDCCSR_SST (1 << 4) /* Sent STALL */ +#define UDCCSR_DME (1 << 3) /* DMA Enable */ +#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ +#define UDCCSR_PC (1 << 1) /* Packet Complete */ +#define UDCCSR_FS (1 << 0) /* FIFO needs service */ + +#define UDCBCN(x) __REG2(0x40600200, (x)<<2) +#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ +#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ +#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ +#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ +#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ +#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ +#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ +#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ +#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ +#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ +#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ +#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ +#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ +#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ +#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ +#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ +#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ +#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ +#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ +#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ +#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ +#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ +#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ +#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ + +#define UDCDN(x) __REG2(0x40600300, (x)<<2) +#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) +#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) +#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ +#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ +#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ +#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ +#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ +#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ +#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ +#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ +#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ +#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ +#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ +#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ +#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ +#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ +#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ +#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ +#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ +#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ +#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ +#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ +#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ +#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ +#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ +#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ + +#define UDCCN(x) __REG2(0x40600400, (x)<<2) +#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ +#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ +#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ +#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ +#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ +#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ +#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ +#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ +#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ +#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ +#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ +#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ +#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ +#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ +#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ +#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ +#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ +#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ +#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ +#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ +#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ +#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ +#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ + +#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ +#define UDCCONR_CN_S (25) +#define UDCCONR_IN (0x07 << 22) /* Interface Number */ +#define UDCCONR_IN_S (22) +#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ +#define UDCCONR_AISN_S (19) +#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ +#define UDCCONR_EN_S (15) +#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ +#define UDCCONR_ET_S (13) +#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ +#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ +#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ +#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ +#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ +#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ +#define UDCCONR_MPS_S (2) +#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ +#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ + + +#define UDC_INT_FIFOERROR (0x2) +#define UDC_INT_PACKETCMP (0x1) + +#define UDC_FNR_MASK (0x7ff) + +#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) +#define UDC_BCR_MASK (0x3ff) + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa27x.h b/kernel/arch/arm/mach-pxa/include/mach/pxa27x.h new file mode 100644 index 000000000..599b925a6 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa27x.h @@ -0,0 +1,25 @@ +#ifndef __MACH_PXA27x_H +#define __MACH_PXA27x_H + +#include <linux/suspend.h> +#include <mach/hardware.h> +#include <mach/pxa2xx-regs.h> +#include <mach/mfp-pxa27x.h> +#include <mach/irqs.h> + +#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ + +#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ +#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ +#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ +#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ +#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ +#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ +#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ +#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ +#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ + +extern int __init pxa27x_set_pwrmode(unsigned int mode); +extern void pxa27x_cpu_pm_enter(suspend_state_t state); + +#endif /* __MACH_PXA27x_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/kernel/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h new file mode 100644 index 000000000..f1dd62946 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -0,0 +1,197 @@ +/* + * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h + * + * Taken from pxa-regs.h by Russell King + * + * Author: Nicolas Pitre + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PXA2XX_REGS_H +#define __PXA2XX_REGS_H + +#include <mach/hardware.h> + +/* + * Power Manager + */ + +#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ +#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ +#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ +#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ +#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ +#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ + +#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ +#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ +#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ +#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ +#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ +#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ +#define PCMD(x) __REG2(0x40F00080, (x)<<2) +#define PCMD0 __REG(0x40F00080 + 0 * 4) +#define PCMD1 __REG(0x40F00080 + 1 * 4) +#define PCMD2 __REG(0x40F00080 + 2 * 4) +#define PCMD3 __REG(0x40F00080 + 3 * 4) +#define PCMD4 __REG(0x40F00080 + 4 * 4) +#define PCMD5 __REG(0x40F00080 + 5 * 4) +#define PCMD6 __REG(0x40F00080 + 6 * 4) +#define PCMD7 __REG(0x40F00080 + 7 * 4) +#define PCMD8 __REG(0x40F00080 + 8 * 4) +#define PCMD9 __REG(0x40F00080 + 9 * 4) +#define PCMD10 __REG(0x40F00080 + 10 * 4) +#define PCMD11 __REG(0x40F00080 + 11 * 4) +#define PCMD12 __REG(0x40F00080 + 12 * 4) +#define PCMD13 __REG(0x40F00080 + 13 * 4) +#define PCMD14 __REG(0x40F00080 + 14 * 4) +#define PCMD15 __REG(0x40F00080 + 15 * 4) +#define PCMD16 __REG(0x40F00080 + 16 * 4) +#define PCMD17 __REG(0x40F00080 + 17 * 4) +#define PCMD18 __REG(0x40F00080 + 18 * 4) +#define PCMD19 __REG(0x40F00080 + 19 * 4) +#define PCMD20 __REG(0x40F00080 + 20 * 4) +#define PCMD21 __REG(0x40F00080 + 21 * 4) +#define PCMD22 __REG(0x40F00080 + 22 * 4) +#define PCMD23 __REG(0x40F00080 + 23 * 4) +#define PCMD24 __REG(0x40F00080 + 24 * 4) +#define PCMD25 __REG(0x40F00080 + 25 * 4) +#define PCMD26 __REG(0x40F00080 + 26 * 4) +#define PCMD27 __REG(0x40F00080 + 27 * 4) +#define PCMD28 __REG(0x40F00080 + 28 * 4) +#define PCMD29 __REG(0x40F00080 + 29 * 4) +#define PCMD30 __REG(0x40F00080 + 30 * 4) +#define PCMD31 __REG(0x40F00080 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +/* FIXME: PCMD_SQC need be checked. */ +#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, + bit 9 should be 0 all day. */ +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +#define PCFR_PI2C_EN (0x1 << 6) + +#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ +#define PSSR_RDH (1 << 5) /* Read Disable Hold */ +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ +#define PSSR_STS (1 << 3) /* Standby Mode Status */ +#define PSSR_VFS (1 << 2) /* VDD Fault Status */ +#define PSSR_BFS (1 << 1) /* Battery Fault Status */ +#define PSSR_SSS (1 << 0) /* Software Sleep Status */ + +#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ + +#define PCFR_RO (1 << 15) /* RDH Override */ +#define PCFR_PO (1 << 14) /* PH Override */ +#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ +#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ +#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ +#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ +#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ +#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ + +#define RCSR_GPR (1 << 3) /* GPIO Reset */ +#define RCSR_SMR (1 << 2) /* Sleep Mode */ +#define RCSR_WDR (1 << 1) /* Watchdog Reset */ +#define RCSR_HWR (1 << 0) /* Hardware Reset */ + +#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ + +/* + * PXA2xx specific Core clock definitions + */ +#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ +#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ +#define CKEN __REG(0x41300004) /* Clock Enable Register */ +#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + +#define CCCR_CPDIS_BIT (31) +#define CCCR_PPDIS_BIT (30) +#define CCCR_LCD_26_BIT (27) +#define CCCR_A_BIT (25) + +#define CCSR_N2_MASK CCCR_N_MASK +#define CCSR_M_MASK CCCR_M_MASK +#define CCSR_L_MASK CCCR_L_MASK +#define CCSR_N2_SHIFT 7 + +#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ +#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ +#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ +#define CKEN_MEMC (22) /* Memory Controller Clock Enable */ +#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ +#define CKEN_IM (20) /* Internal Memory Clock Enable */ +#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ +#define CKEN_USIM (18) /* USIM Unit Clock Enable */ +#define CKEN_MSL (17) /* MSL Unit Clock Enable */ +#define CKEN_LCD (16) /* LCD Unit Clock Enable */ +#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ +#define CKEN_I2C (14) /* I2C Unit Clock Enable */ +#define CKEN_FICP (13) /* FICP Unit Clock Enable */ +#define CKEN_MMC (12) /* MMC Unit Clock Enable */ +#define CKEN_USB (11) /* USB Unit Clock Enable */ +#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ +#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ +#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ +#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ +#define CKEN_I2S (8) /* I2S Unit Clock Enable */ +#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ +#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ +#define CKEN_STUART (5) /* STUART Unit Clock Enable */ +#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ +#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ +#define CKEN_SSP (3) /* SSP Unit Clock Enable */ +#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ +#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ +#define CKEN_PWM1 (1) /* PWM1 Clock Enable */ +#define CKEN_PWM0 (0) /* PWM0 Clock Enable */ + +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + +/* PWRMODE register M field values */ + +#define PWRMODE_IDLE 0x1 +#define PWRMODE_STANDBY 0x2 +#define PWRMODE_SLEEP 0x3 +#define PWRMODE_DEEPSLEEP 0x7 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa300.h b/kernel/arch/arm/mach-pxa/include/mach/pxa300.h new file mode 100644 index 000000000..733b6412c --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa300.h @@ -0,0 +1,7 @@ +#ifndef __MACH_PXA300_H +#define __MACH_PXA300_H + +#include <mach/pxa3xx.h> +#include <mach/mfp-pxa300.h> + +#endif /* __MACH_PXA300_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa320.h b/kernel/arch/arm/mach-pxa/include/mach/pxa320.h new file mode 100644 index 000000000..b6204e470 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa320.h @@ -0,0 +1,8 @@ +#ifndef __MACH_PXA320_H +#define __MACH_PXA320_H + +#include <mach/pxa3xx.h> +#include <mach/mfp-pxa320.h> + +#endif /* __MACH_PXA320_H */ + diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/kernel/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h new file mode 100644 index 000000000..f4d48d207 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -0,0 +1,206 @@ +/* + * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h + * + * PXA3xx specific register definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_PXA3XX_REGS_H +#define __ASM_ARCH_PXA3XX_REGS_H + +#include <mach/hardware.h> + +/* + * Oscillator Configuration Register (OSCC) + */ +#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ + +#define OSCC_PEN (1 << 11) /* 13MHz POUT */ + + +/* + * Service Power Management Unit (MPMU) + */ +#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ +#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) + +/* + * Slave Power Management Unit + */ +#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ +#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ +#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ +#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ +#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ +#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ +#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ +#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ +#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ +#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ +#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ +#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ +#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ +#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ + +/* + * Application Subsystem Configuration bits. + */ +#define ASCR_RDH (1 << 31) +#define ASCR_D1S (1 << 2) +#define ASCR_D2S (1 << 1) +#define ASCR_D3S (1 << 0) + +/* + * Application Reset Status bits. + */ +#define ARSR_GPR (1 << 3) +#define ARSR_LPMR (1 << 2) +#define ARSR_WDT (1 << 1) +#define ARSR_HWR (1 << 0) + +/* + * Application Subsystem Wake-Up bits. + */ +#define ADXER_WRTC (1 << 31) /* RTC */ +#define ADXER_WOST (1 << 30) /* OS Timer */ +#define ADXER_WTSI (1 << 29) /* Touchscreen */ +#define ADXER_WUSBH (1 << 28) /* USB host */ +#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ +#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ +#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ +#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ +#define ADXER_WKP (1 << 21) /* Keypad */ +#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ +#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ +#define ADXER_WOTG (1 << 16) /* USBOTG input */ +#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ +#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ +#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ +#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ +#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ +#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ +#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ +#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ +#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ +#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ +#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ +#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ +#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ +#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ +#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ +#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ + +/* + * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. + */ +#define ADXR_L2 (1 << 8) +#define ADXR_R5 (1 << 5) +#define ADXR_R4 (1 << 4) +#define ADXR_R3 (1 << 3) +#define ADXR_R2 (1 << 2) +#define ADXR_R1 (1 << 1) +#define ADXR_R0 (1 << 0) + +/* + * Values for PWRMODE CP15 register + */ +#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ +#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ +#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ +#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ +#define PXA3xx_PM_S0D0C1 0x01 + +/* + * Application Subsystem Clock + */ +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define CKENC __REG(0x41340024) /* C Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ +#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ +#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ +#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ +#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ + +#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ +#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ +#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ +#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ +#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ +#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ +#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ + +#define ACCR_SMCFS(x) (((x) & 0x7) << 23) +#define ACCR_SFLFS(x) (((x) & 0x3) << 18) +#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) +#define ACCR_HSS(x) (((x) & 0x3) << 14) +#define ACCR_DMCFS(x) (((x) & 0x3) << 12) +#define ACCR_XN(x) (((x) & 0x7) << 8) +#define ACCR_XL(x) ((x) & 0x1f) + +/* + * Clock Enable Bit + */ +#define CKEN_LCD 1 /* < LCD Clock Enable */ +#define CKEN_USBH 2 /* < USB host clock enable */ +#define CKEN_CAMERA 3 /* < Camera interface clock enable */ +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ +#define CKEN_BOOT 11 /* < Boot rom clock enable */ +#define CKEN_MMC1 12 /* < MMC1 Clock enable */ +#define CKEN_MMC2 13 /* < MMC2 clock enable */ +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ +#define CKEN_TPM 19 /* < TPM clock enable */ +#define CKEN_UDC 20 /* < UDC clock enable */ +#define CKEN_BTUART 21 /* < BTUART clock enable */ +#define CKEN_FFUART 22 /* < FFUART clock enable */ +#define CKEN_STUART 23 /* < STUART clock enable */ +#define CKEN_AC97 24 /* < AC97 clock enable */ +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ +#define CKEN_SSP1 26 /* < SSP1 clock enable */ +#define CKEN_SSP2 27 /* < SSP2 clock enable */ +#define CKEN_SSP3 28 /* < SSP3 clock enable */ +#define CKEN_SSP4 29 /* < SSP4 clock enable */ +#define CKEN_MSL0 30 /* < MSL0 clock enable */ +#define CKEN_PWM0 32 /* < PWM[0] clock enable */ +#define CKEN_PWM1 33 /* < PWM[1] clock enable */ +#define CKEN_I2C 36 /* < I2C clock enable */ +#define CKEN_INTC 38 /* < Interrupt controller clock enable */ +#define CKEN_GPIO 39 /* < GPIO clock enable */ +#define CKEN_1WIRE 40 /* < 1-wire clock enable */ +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ +#define CKEN_MINI_IM 48 /* < Mini-IM */ +#define CKEN_MINI_LCD 49 /* < Mini LCD */ + +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ +#define CKEN_MVED 43 /* < MVED clock enable */ + +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ +#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ +#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ + +#endif /* __ASM_ARCH_PXA3XX_REGS_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa3xx.h b/kernel/arch/arm/mach-pxa/include/mach/pxa3xx.h new file mode 100644 index 000000000..b4143fb66 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa3xx.h @@ -0,0 +1,8 @@ +#ifndef __MACH_PXA3XX_H +#define __MACH_PXA3XX_H + +#include <mach/hardware.h> +#include <mach/pxa3xx-regs.h> +#include <mach/irqs.h> + +#endif /* __MACH_PXA3XX_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/pxa930.h b/kernel/arch/arm/mach-pxa/include/mach/pxa930.h new file mode 100644 index 000000000..190363b98 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/pxa930.h @@ -0,0 +1,7 @@ +#ifndef __MACH_PXA930_H +#define __MACH_PXA930_H + +#include <mach/pxa3xx.h> +#include <mach/mfp-pxa930.h> + +#endif /* __MACH_PXA930_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/regs-ac97.h b/kernel/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 000000000..b8d14bd9a --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/regs-ac97.h @@ -0,0 +1,101 @@ +#ifndef __ASM_ARCH_REGS_AC97_H +#define __ASM_ARCH_REGS_AC97_H + +#include <mach/hardware.h> + +/* + * AC97 Controller registers + */ + +#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define GCR __REG(0x4050000C) /* Global Control Register */ +#ifdef CONFIG_PXA3xx +#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ +#endif +#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ + +#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR_FIFOE (1 << 4) /* FIFO error */ +#define POSR_FSR (1 << 2) /* FIFO Service Request */ + +#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR_FIFOE (1 << 4) /* FIFO error */ +#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define PISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR_FIFOE (1 << 4) /* FIFO error */ +#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MCSR_FSR (1 << 2) /* FIFO Service Request */ + +#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR_CDONE (1 << 19) /* Command Done */ +#define GSR_SDONE (1 << 18) /* Status Done */ +#define GSR_RDCS (1 << 15) /* Read Completion Status */ +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ +#define GSR_PCR (1 << 8) /* Primary Codec Ready */ +#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ +#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ + +#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ + +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ + +#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR_FEIE (1 << 3) /* FIFO Error */ +#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR_FEIE (1 << 3) /* FIFO Error */ +#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR_FIFOE (1 << 4) /* FIFO error */ +#define MOSR_FSR (1 << 2) /* FIFO Service Request */ + +#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR_FIFOE (1 << 4) /* FIFO error */ +#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ + +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + +#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/regs-lcd.h b/kernel/arch/arm/mach-pxa/include/mach/regs-lcd.h new file mode 100644 index 000000000..f82dcea79 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/regs-lcd.h @@ -0,0 +1,197 @@ +#ifndef __ASM_ARCH_REGS_LCD_H +#define __ASM_ARCH_REGS_LCD_H + +#include <mach/bitfield.h> + +/* + * LCD Controller Registers and Bits Definitions + */ +#define LCCR0 (0x000) /* LCD Controller Control Register 0 */ +#define LCCR1 (0x004) /* LCD Controller Control Register 1 */ +#define LCCR2 (0x008) /* LCD Controller Control Register 2 */ +#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ +#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ +#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ +#define LCSR (0x038) /* LCD Controller Status Register 0 */ +#define LCSR1 (0x034) /* LCD Controller Status Register 1 */ +#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ +#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ +#define TMEDCR (0x044) /* TMED Control Register */ + +#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ +#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ +#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ +#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ +#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ +#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ +#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ + +#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ +#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ +#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ +#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ + +#define CMDCR (0x100) /* Command Control Register */ +#define PRSR (0x104) /* Panel Read Status Register */ + +#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) + +#define LCCR3_PDFOR_0 (0 << 30) +#define LCCR3_PDFOR_1 (1 << 30) +#define LCCR3_PDFOR_2 (2 << 30) +#define LCCR3_PDFOR_3 (3 << 30) + +#define LCCR4_PAL_FOR_0 (0 << 15) +#define LCCR4_PAL_FOR_1 (1 << 15) +#define LCCR4_PAL_FOR_2 (2 << 15) +#define LCCR4_PAL_FOR_3 (3 << 15) +#define LCCR4_PAL_FOR_MASK (3 << 15) + +#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ +#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ +#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ +#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ +#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ +#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ +#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ + +#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ +#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ +#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ +#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ +#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ +#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ +#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ + +#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ +#define LCCR0_SFM (1 << 4) /* Start of frame mask */ +#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ +#define LCCR0_EFM (1 << 6) /* End of Frame mask */ +#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ +#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ +#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ +#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ +#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ +#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ +#define LCCR0_DIS (1 << 10) /* LCD Disable */ +#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ +#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ +#define LCCR0_PDD_S 12 +#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ +#define LCCR0_LCDT (1 << 22) /* LCD panel type */ +#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ +#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ +#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ +#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ + +#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ +#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) + +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ +#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) + +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ +#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) + +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ +#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) + +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) + +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ +#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) + +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ +#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) + +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ +#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) + +#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ +#define LCCR3_API_S 16 +#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ +#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ +#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ +#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ +#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ + +#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ +#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ +#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ + +#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ +#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) + +#define LCCR3_ACB Fld (8, 8) /* AC Bias */ +#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) + +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ + +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ + +#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ +#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ +#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ +#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ + +#define LCSR_LDD (1 << 0) /* LCD Disable Done */ +#define LCSR_SOF (1 << 1) /* Start of frame */ +#define LCSR_BER (1 << 2) /* Bus error */ +#define LCSR_ABC (1 << 3) /* AC Bias count */ +#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ +#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ +#define LCSR_OU (1 << 6) /* output FIFO underrun */ +#define LCSR_QD (1 << 7) /* quick disable */ +#define LCSR_EOF (1 << 8) /* end of frame */ +#define LCSR_BS (1 << 9) /* branch status */ +#define LCSR_SINT (1 << 10) /* subsequent interrupt */ +#define LCSR_RD_ST (1 << 11) /* read status */ +#define LCSR_CMD_INT (1 << 12) /* command interrupt */ + +#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ +#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ +#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ +#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ + +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ + +/* overlay control registers */ +#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ +#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ +#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ +#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ +#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ +#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ +#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ + +/* smartpanel related */ +#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ +#define PRSR_A0 (1 << 8) /* Read Data Source */ +#define PRSR_ST_OK (1 << 9) /* Status OK */ +#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ + +#define SMART_CMD_A0 (0x1 << 8) +#define SMART_CMD_READ_STATUS_REG (0x0 << 9) +#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) +#define SMART_CMD_WRITE_COMMAND (0x1 << 9) +#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) +#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) +#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) +#define SMART_CMD_NOOP (0x4 << 9) +#define SMART_CMD_INTERRUPT (0x5 << 9) + +#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) +#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) + +/* SMART_DELAY() is introduced for software controlled delay primitive which + * can be inserted between command sequences, unused command 0x6 is used here + * and delay ranges from 0ms ~ 255ms + */ +#define SMART_CMD_DELAY (0x6 << 9) +#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) +#endif /* __ASM_ARCH_REGS_LCD_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/regs-ost.h b/kernel/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 000000000..628819995 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/regs-ost.h @@ -0,0 +1,34 @@ +#ifndef __ASM_MACH_REGS_OST_H +#define __ASM_MACH_REGS_OST_H + +#include <mach/hardware.h> + +/* + * OS Timer & Match Registers + */ + +#define OSMR0 io_p2v(0x40A00000) /* */ +#define OSMR1 io_p2v(0x40A00004) /* */ +#define OSMR2 io_p2v(0x40A00008) /* */ +#define OSMR3 io_p2v(0x40A0000C) /* */ +#define OSMR4 io_p2v(0x40A00080) /* */ +#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ +#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 io_p2v(0x40A000C0) /* */ +#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ +#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ + +#define OSSR_M3 (1 << 3) /* Match status channel 3 */ +#define OSSR_M2 (1 << 2) /* Match status channel 2 */ +#define OSSR_M1 (1 << 1) /* Match status channel 1 */ +#define OSSR_M0 (1 << 0) /* Match status channel 0 */ + +#define OWER_WME (1 << 0) /* Watchdog Match Enable */ + +#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ +#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ +#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ +#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ + +#endif /* __ASM_MACH_REGS_OST_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/regs-rtc.h b/kernel/arch/arm/mach-pxa/include/mach/regs-rtc.h new file mode 100644 index 000000000..f0e4a589b --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/regs-rtc.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_REGS_RTC_H +#define __ASM_MACH_REGS_RTC_H + +#include <mach/hardware.h> + +/* + * Real Time Clock + */ + +#define RCNR __REG(0x40900000) /* RTC Count Register */ +#define RTAR __REG(0x40900004) /* RTC Alarm Register */ +#define RTSR __REG(0x40900008) /* RTC Status Register */ +#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ +#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ + +#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ +#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ +#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ +#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ +#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ +#define RTSR_AL (1 << 0) /* RTC alarm detected */ + +#endif /* __ASM_MACH_REGS_RTC_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/regs-u2d.h b/kernel/arch/arm/mach-pxa/include/mach/regs-u2d.h new file mode 100644 index 000000000..c15c0c57d --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/regs-u2d.h @@ -0,0 +1,200 @@ +#ifndef __ASM_ARCH_PXA3xx_U2D_H +#define __ASM_ARCH_PXA3xx_U2D_H + +#include <mach/bitfield.h> + +/* + * USB2 device controller registers and bits definitions + */ +#define U2DCR (0x0000) /* U2D Control Register */ +#define U2DCR_NDC (1 << 31) /* NAK During Config */ +#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */ +#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */ +#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */ +#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ +#define U2DCR_ABP (1 << 21) /* Application Bus Power */ +#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ +#define U2DCR_CC (1 << 19) /* Configuration Change */ +#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ +#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */ +#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ +#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ +#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ +#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ +#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ +#define U2DCR_UDR (1 << 2) /* U2D Resume */ +#define U2DCR_UDA (1 << 1) /* U2D Active */ +#define U2DCR_UDE (1 << 0) /* U2D Enable */ + +#define U2DICR (0x0004) /* U2D Interrupt Control Register */ +#define U2DISR (0x000C) /* U2D Interrupt Status Register */ +#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ +#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ +#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ +#define U2DINT_RU (1 << 28) /* Interrupt - Resume */ +#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ +#define U2DINT_RS (1 << 26) /* Interrupt - Reset */ +#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ +#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ +#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ +#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ + +#define U2DFNR (0x0014) /* U2D Frame Number Register */ + +#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) +#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */ +#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */ + +#define U2DOTGCR (0x0020) /* U2D OTG Control Register */ +#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */ +#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */ +#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */ +#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */ + +#ifdef CONFIG_CPU_PXA930 +#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */ +#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */ +#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */ +#endif + +#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */ +#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */ +#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */ +#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */ +#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */ +#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */ + +#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */ +#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */ + +#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */ +#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */ +#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */ +#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */ +#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */ +#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */ +#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */ +#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */ +#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */ +#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */ +#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */ +#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */ +#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */ +#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */ +#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */ +#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */ + +#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */ +#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */ +#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */ +#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */ +#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */ +#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */ +#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */ +#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */ +#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */ +#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */ +#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */ +#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */ + +#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */ +#define U2DOTGUCR_RUN (1 << 25) /* RUN */ +#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */ +#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */ +#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */ +#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */ + +#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */ +#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */ +#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */ +#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */ +#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */ + +#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */ +#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ +#define U2DCSR0_SA (1 << 7) /* SETUP Active */ +#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define U2DCSR0_FST (1 << 5) /* Force Stall */ +#define U2DCSR0_SST (1 << 4) /* Send Stall */ +#define U2DCSR0_DME (1 << 3) /* DMA Enable */ +#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */ +#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */ +#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ +#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ +#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ +#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ +#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ +#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ +#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ +#define U2DCSR_DME (1 << 3) /* DMA Enable */ +#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ +#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ +#define U2DCSR_FS (1 << 0) /* FIFO needs Service */ + +#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */ +#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */ + +#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */ + +#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */ +#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */ +#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ + +#define U2DSCA (0x0500) /* U2D Setup Command Address */ +#define U2DSCA_VALUE (0x0120) + +#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */ +#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */ + +/* U2DMA registers */ +#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */ +#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */ +#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ +#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ +#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ +#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ +#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ +#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ +#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ +#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ +#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ +#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ +#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */ +#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ +#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ +#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ +#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ + +#define U2DMACR (0x1080) /* U2DMA Control Register */ +#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */ + +#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */ +#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */ + +#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */ +#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */ + +#define U2DMADADR_STOP (1U << 0) + +#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */ +#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */ +#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */ +#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */ + +#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */ +#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */ + +#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */ +#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */ +#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */ + +#endif /* __ASM_ARCH_PXA3xx_U2D_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/regs-uart.h b/kernel/arch/arm/mach-pxa/include/mach/regs-uart.h new file mode 100644 index 000000000..55aeb7fb7 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/regs-uart.h @@ -0,0 +1,143 @@ +#ifndef __ASM_ARCH_REGS_UART_H +#define __ASM_ARCH_REGS_UART_H + +/* + * UARTs + */ + +/* Full Function UART (FFUART) */ +#define FFUART FFRBR +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Bluetooth UART (BTUART) */ +#define BTUART BTRBR +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Standard UART (STUART) */ +#define STUART STRBR +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ +#define STMSR __REG(0x40700018) /* Reserved */ +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Hardware UART (HWUART) */ +#define HWUART HWRBR +#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ +#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ +#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ +#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ +#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ +#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ +#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ +#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ +#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ +#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ +#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ +#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ +#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ +#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ +#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + +/* + * IrSR (Infrared Selection Register) + */ +#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ +#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ +#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ +#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ +#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ + +#endif /* __ASM_ARCH_REGS_UART_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/reset.h b/kernel/arch/arm/mach-pxa/include/mach/reset.h new file mode 100644 index 000000000..b6c10556f --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/reset.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARCH_RESET_H +#define __ASM_ARCH_RESET_H + +#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ +#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ +#define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */ +#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ +#define RESET_STATUS_ALL (0xf) + +extern unsigned int reset_status; +extern void clear_reset_status(unsigned int mask); + +/** + * init_gpio_reset() - register GPIO as reset generator + * @gpio: gpio nr + * @output: set gpio as output instead of input during normal work + * @level: output level + */ +extern int init_gpio_reset(int gpio, int output, int level); + +#endif /* __ASM_ARCH_RESET_H */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/sharpsl_pm.h b/kernel/arch/arm/mach-pxa/include/mach/sharpsl_pm.h new file mode 100644 index 000000000..905be6755 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/sharpsl_pm.h @@ -0,0 +1,113 @@ +/* + * SharpSL Battery/PM Driver + * + * Copyright (c) 2004-2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _MACH_SHARPSL_PM +#define _MACH_SHARPSL_PM + +struct sharpsl_charger_machinfo { + void (*init)(void); + void (*exit)(void); + int gpio_acin; + int gpio_batfull; + int batfull_irq; + int gpio_batlock; + int gpio_fatal; + void (*discharge)(int); + void (*discharge1)(int); + void (*charge)(int); + void (*measure_temp)(int); + void (*presuspend)(void); + void (*postsuspend)(void); + void (*earlyresume)(void); + unsigned long (*read_devdata)(int); +#define SHARPSL_BATT_VOLT 1 +#define SHARPSL_BATT_TEMP 2 +#define SHARPSL_ACIN_VOLT 3 +#define SHARPSL_STATUS_ACIN 4 +#define SHARPSL_STATUS_LOCK 5 +#define SHARPSL_STATUS_CHRGFULL 6 +#define SHARPSL_STATUS_FATAL 7 + unsigned long (*charger_wakeup)(void); + int (*should_wakeup)(unsigned int resume_on_alarm); + void (*backlight_limit)(int); + int (*backlight_get_status) (void); + int charge_on_volt; + int charge_on_temp; + int charge_acin_high; + int charge_acin_low; + int fatal_acin_volt; + int fatal_noacin_volt; + int bat_levels; + struct battery_thresh *bat_levels_noac; + struct battery_thresh *bat_levels_acin; + struct battery_thresh *bat_levels_noac_bl; + struct battery_thresh *bat_levels_acin_bl; + int status_high_acin; + int status_low_acin; + int status_high_noac; + int status_low_noac; +}; + +struct battery_thresh { + int voltage; + int percentage; +}; + +struct battery_stat { + int ac_status; /* APM AC Present/Not Present */ + int mainbat_status; /* APM Main Battery Status */ + int mainbat_percent; /* Main Battery Percentage Charge */ + int mainbat_voltage; /* Main Battery Voltage */ +}; + +struct sharpsl_pm_status { + struct device *dev; + struct timer_list ac_timer; + struct timer_list chrg_full_timer; + + int charge_mode; +#define CHRG_ERROR (-1) +#define CHRG_OFF (0) +#define CHRG_ON (1) +#define CHRG_DONE (2) + + unsigned int flags; +#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */ +#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */ +#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */ +#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */ +#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */ + + int full_count; + unsigned long charge_start_time; + struct sharpsl_charger_machinfo *machinfo; + struct battery_stat battstat; +}; + +extern struct sharpsl_pm_status sharpsl_pm; + +extern struct battery_thresh sharpsl_battery_levels_acin[]; +extern struct battery_thresh sharpsl_battery_levels_noac[]; + +#define SHARPSL_LED_ERROR 2 +#define SHARPSL_LED_ON 1 +#define SHARPSL_LED_OFF 0 + +void sharpsl_battery_kick(void); +void sharpsl_pm_led(int val); + +/* MAX1111 Channel Definitions */ +#define MAX1111_BATT_VOLT 4u +#define MAX1111_BATT_TEMP 2u +#define MAX1111_ACIN_VOLT 6u +int sharpsl_pm_pxa_read_max1111(int channel); + +void corgi_lcd_limit_intensity(int limit); +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/smemc.h b/kernel/arch/arm/mach-pxa/include/mach/smemc.h new file mode 100644 index 000000000..b802f285f --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/smemc.h @@ -0,0 +1,75 @@ +/* + * Static memory controller register definitions for PXA CPUs + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SMEMC_REGS_H +#define __SMEMC_REGS_H + +#define PXA2XX_SMEMC_BASE 0x48000000 +#define PXA3XX_SMEMC_BASE 0x4a000000 +#define SMEMC_VIRT IOMEM(0xf6000000) + +#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ +#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ +#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ +#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ +#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */ +#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */ +#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */ +#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ +#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */ +#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */ +#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ +#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ +#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ +#define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */ + +/* + * More handy macros for PCMCIA + * + * Arg is socket number + */ +#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */ +#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */ +#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */ + +/* MECR register defines */ +#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ +#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ + +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/spitz.h b/kernel/arch/arm/mach-pxa/include/mach/spitz.h new file mode 100644 index 000000000..25c9f62e4 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/spitz.h @@ -0,0 +1,189 @@ +/* + * Hardware specific definitions for SL-Cx000 series of PDAs + * + * Copyright (c) 2005 Alexander Wykes + * Copyright (c) 2005 Richard Purdie + * + * Based on Sharp's 2.4 kernel patches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __ASM_ARCH_SPITZ_H +#define __ASM_ARCH_SPITZ_H 1 +#endif + +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */ +#include <linux/fb.h> + +/* Spitz/Akita GPIOs */ + +#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */ +#define SPITZ_GPIO_RESET (1) +#define SPITZ_GPIO_nSD_DETECT (9) +#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */ +#define SPITZ_GPIO_AK_INT (13) /* Remote Control */ +#define SPITZ_GPIO_ADS7846_CS (14) +#define SPITZ_GPIO_SYNC (16) +#define SPITZ_GPIO_MAX1111_CS (20) +#define SPITZ_GPIO_FATAL_BAT (21) +#define SPITZ_GPIO_HSYNC (22) +#define SPITZ_GPIO_nSD_CLK (32) +#define SPITZ_GPIO_USB_DEVICE (35) +#define SPITZ_GPIO_USB_HOST (37) +#define SPITZ_GPIO_USB_CONNECT (41) +#define SPITZ_GPIO_LCDCON_CS (53) +#define SPITZ_GPIO_nPCE (54) +#define SPITZ_GPIO_nSD_WP (81) +#define SPITZ_GPIO_ON_RESET (89) +#define SPITZ_GPIO_BAT_COVER (90) +#define SPITZ_GPIO_CF_CD (94) +#define SPITZ_GPIO_ON_KEY (95) +#define SPITZ_GPIO_SWA (97) +#define SPITZ_GPIO_SWB (96) +#define SPITZ_GPIO_CHRG_FULL (101) +#define SPITZ_GPIO_CO (101) +#define SPITZ_GPIO_CF_IRQ (105) +#define SPITZ_GPIO_AC_IN (115) +#define SPITZ_GPIO_HP_IN (116) + +/* Spitz Only GPIOs */ + +#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */ +#define SPITZ_GPIO_CF2_CD (93) + + +/* Spitz/Akita Keyboard Definitions */ + +#define SPITZ_KEY_STROBE_NUM (11) +#define SPITZ_KEY_SENSE_NUM (7) +#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000 +#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000 +#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000 +#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880 +#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000 +#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4 +#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000 +#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000 + +#define SPITZ_GPIO_KEY_STROBE0 88 +#define SPITZ_GPIO_KEY_STROBE1 23 +#define SPITZ_GPIO_KEY_STROBE2 24 +#define SPITZ_GPIO_KEY_STROBE3 25 +#define SPITZ_GPIO_KEY_STROBE4 26 +#define SPITZ_GPIO_KEY_STROBE5 27 +#define SPITZ_GPIO_KEY_STROBE6 52 +#define SPITZ_GPIO_KEY_STROBE7 103 +#define SPITZ_GPIO_KEY_STROBE8 107 +#define SPITZ_GPIO_KEY_STROBE9 108 +#define SPITZ_GPIO_KEY_STROBE10 114 + +#define SPITZ_GPIO_KEY_SENSE0 12 +#define SPITZ_GPIO_KEY_SENSE1 17 +#define SPITZ_GPIO_KEY_SENSE2 91 +#define SPITZ_GPIO_KEY_SENSE3 34 +#define SPITZ_GPIO_KEY_SENSE4 36 +#define SPITZ_GPIO_KEY_SENSE5 38 +#define SPITZ_GPIO_KEY_SENSE6 39 + + +/* Spitz Scoop Device (No. 1) GPIOs */ +/* Suspend States in comments */ +#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */ +#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */ +#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */ +#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */ +#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */ +#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */ +#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */ +#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ +#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ + +#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ + SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \ + SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) +#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) +#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) +#define SPITZ_SCP_SUS_SET 0 + +#define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0) +#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1) +#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2) +#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3) +#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4) +#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5) +#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6) +#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7) +#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8) + +/* Spitz Scoop Device (No. 2) GPIOs */ +/* Suspend States in comments */ +#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ +#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */ +#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */ +#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */ +#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */ +#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */ +#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */ +#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ +#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ + +#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ + SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ + SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) + +#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) +#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ + SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) +#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) + +#define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) +#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0) +#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1) +#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2) +#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3) +#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4) +#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5) +#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6) +#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7) +#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8) + +/* Akita IO Expander GPIOs */ +#define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) +#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0) +#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1) +#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2) +#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3) +#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4) +#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5) +#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6) +#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7) + +/* Spitz IRQ Definitions */ + +#define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT) +#define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN) +#define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT) +#define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN) +#define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT) +#define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC) +#define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY) +#define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA) +#define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB) +#define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER) +#define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT) +#define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO) +#define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ) +#define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD) +#define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ) +#define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT) +#define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT) + +/* + * Shared data structures + */ +extern struct platform_device spitzssp_device; +extern struct sharpsl_charger_machinfo spitz_pm_machinfo; diff --git a/kernel/arch/arm/mach-pxa/include/mach/tosa.h b/kernel/arch/arm/mach-pxa/include/mach/tosa.h new file mode 100644 index 000000000..0497d95ce --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/tosa.h @@ -0,0 +1,202 @@ +/* + * Hardware specific definitions for Sharp SL-C6000x series of PDAs + * + * Copyright (c) 2005 Dirk Opfer + * + * Based on Sharp's 2.4 kernel patches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _ASM_ARCH_TOSA_H_ +#define _ASM_ARCH_TOSA_H_ 1 + +#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + +/* TOSA Chip selects */ +#define TOSA_LCDC_PHYS PXA_CS4_PHYS +/* Internel Scoop */ +#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000) +/* Jacket Scoop */ +#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) + +#define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS) +/* + * SCOOP2 internal GPIOs + */ +#define TOSA_SCOOP_GPIO_BASE PXA_NR_BUILTIN_GPIO +#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 +#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) +#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) +#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) +#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) +#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 +#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6) +#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7) +#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 + +/* GPIO Direction 1 : output mode / 0:input mode */ +#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \ + TOSA_SCOOP_AUD_PWR_ON) + +/* + * SCOOP2 jacket GPIOs + */ +#define TOSA_SCOOP_JC_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) +#define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0) +#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) +#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) +#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) +#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4) +#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5) +#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 +#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) +#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 + +/* GPIO Direction 1 : output mode / 0:input mode */ +#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL) + +/* + * TC6393XB GPIOs + */ +#define TOSA_TC6393XB_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 2 * 12) + +#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) +#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) +#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3) +#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4) +#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6) +#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7) +#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9) +#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10) +#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11) +#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12) +#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14) +#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15) + +/* + * Timing Generator + */ +#define TG_PNLCTL 0x00 +#define TG_TPOSCTL 0x01 +#define TG_DUTYCTL 0x02 +#define TG_GPOSR 0x03 +#define TG_GPODR1 0x04 +#define TG_GPODR2 0x05 +#define TG_PINICTL 0x06 +#define TG_HPOSCTL 0x07 + +/* + * PXA GPIOs + */ +#define TOSA_GPIO_POWERON (0) +#define TOSA_GPIO_RESET (1) +#define TOSA_GPIO_AC_IN (2) +#define TOSA_GPIO_RECORD_BTN (3) +#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */ +#define TOSA_GPIO_USB_IN (5) +#define TOSA_GPIO_JACKET_DETECT (7) +#define TOSA_GPIO_nSD_DETECT (9) +#define TOSA_GPIO_nSD_INT (10) +#define TOSA_GPIO_TC6393XB_CLK (11) +#define TOSA_GPIO_BAT1_CRG (12) +#define TOSA_GPIO_CF_CD (13) +#define TOSA_GPIO_BAT0_CRG (14) +#define TOSA_GPIO_TC6393XB_INT (15) +#define TOSA_GPIO_BAT0_LOW (17) +#define TOSA_GPIO_TC6393XB_RDY (18) +#define TOSA_GPIO_ON_RESET (19) +#define TOSA_GPIO_EAR_IN (20) +#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ +#define TOSA_GPIO_ON_KEY (22) +#define TOSA_GPIO_VGA_LINE (27) +#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ +#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ +#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ +#define TOSA_GPIO_IRDA_TX (47) +#define TOSA_GPIO_TG_SPI_SCLK (81) +#define TOSA_GPIO_TG_SPI_CS (82) +#define TOSA_GPIO_TG_SPI_MOSI (83) +#define TOSA_GPIO_BAT1_LOW (84) + +#define TOSA_GPIO_HP_IN GPIO_EAR_IN + +#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW + +#define TOSA_KEY_STROBE_NUM (11) +#define TOSA_KEY_SENSE_NUM (7) + +#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000) +#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f) +#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0) +#define TOSA_GPIO_ALL_SENSE_RSHIFT (5) +#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a)) +#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a)) +#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000) +#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff) +#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00) +#define TOSA_GPIO_KEY_SENSE(a) (69+(a)) +#define TOSA_GPIO_KEY_STROBE(a) (58+(a)) + +/* + * Interrupts + */ +#define TOSA_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP) +#define TOSA_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN) +#define TOSA_IRQ_GPIO_RECORD_BTN PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN) +#define TOSA_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC) +#define TOSA_IRQ_GPIO_USB_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN) +#define TOSA_IRQ_GPIO_JACKET_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT) +#define TOSA_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT) +#define TOSA_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT) +#define TOSA_IRQ_GPIO_BAT1_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG) +#define TOSA_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD) +#define TOSA_IRQ_GPIO_BAT0_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG) +#define TOSA_IRQ_GPIO_TC6393XB_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT) +#define TOSA_IRQ_GPIO_BAT0_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW) +#define TOSA_IRQ_GPIO_EAR_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN) +#define TOSA_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ) +#define TOSA_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY) +#define TOSA_IRQ_GPIO_VGA_LINE PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE) +#define TOSA_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT) +#define TOSA_IRQ_GPIO_JC_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ) +#define TOSA_IRQ_GPIO_BAT_LOCKED PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED) +#define TOSA_IRQ_GPIO_BAT1_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW) +#define TOSA_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(69+(a)) + +#define TOSA_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW) + +#define TOSA_KEY_SYNC KEY_102ND /* ??? */ + +#ifndef CONFIG_TOSA_USE_EXT_KEYCODES +#define TOSA_KEY_RECORD KEY_YEN +#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA +#define TOSA_KEY_CANCEL KEY_ESC +#define TOSA_KEY_CENTER KEY_HIRAGANA +#define TOSA_KEY_OK KEY_HENKAN +#define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA +#define TOSA_KEY_HOMEPAGE KEY_HANGEUL +#define TOSA_KEY_LIGHT KEY_MUHENKAN +#define TOSA_KEY_MENU KEY_HANJA +#define TOSA_KEY_FN KEY_RIGHTALT +#define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU +#else +#define TOSA_KEY_RECORD KEY_RECORD +#define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK +#define TOSA_KEY_CANCEL KEY_CANCEL +#define TOSA_KEY_CENTER KEY_SELECT /* ??? */ +#define TOSA_KEY_OK KEY_OK +#define TOSA_KEY_CALENDAR KEY_CALENDAR +#define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE +#define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE +#define TOSA_KEY_MENU KEY_MENU +#define TOSA_KEY_FN KEY_FN +#define TOSA_KEY_MAIL KEY_MAIL +#endif + +struct spi_device; +extern int tosa_bl_enable(struct spi_device *spi, int enable); + +#endif /* _ASM_ARCH_TOSA_H_ */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/tosa_bt.h b/kernel/arch/arm/mach-pxa/include/mach/tosa_bt.h new file mode 100644 index 000000000..efc3c3d3b --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/tosa_bt.h @@ -0,0 +1,22 @@ +/* + * Tosa bluetooth built-in chip control. + * + * Later it may be shared with some other platforms. + * + * Copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef TOSA_BT_H +#define TOSA_BT_H + +struct tosa_bt_data { + int gpio_pwr; + int gpio_reset; +}; + +#endif + diff --git a/kernel/arch/arm/mach-pxa/include/mach/trizeps4.h b/kernel/arch/arm/mach-pxa/include/mach/trizeps4.h new file mode 100644 index 000000000..ae3ca013a --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/trizeps4.h @@ -0,0 +1,164 @@ +/************************************************************************ + * Include file for TRIZEPS4 SoM and ConXS eval-board + * Copyright (c) Jürgen Schindele + * 2006 + ************************************************************************/ + +/* + * Includes/Defines + */ +#ifndef _TRIPEPS4_H_ +#define _TRIPEPS4_H_ + +#include "irqs.h" /* PXA_GPIO_TO_IRQ */ + +/* physical memory regions */ +#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ +#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ +#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ +#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ +#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ + + /* Logic on ConXS-board CSFR register*/ +#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) + /* Logic on ConXS-board BOCR register*/ +#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) + /* Logic on ConXS-board IRCR register*/ +#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) + /* Logic on ConXS-board UPSR register*/ +#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) + /* Logic on ConXS-board DICR register*/ +#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) + +/* virtual memory regions */ +#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ + +#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ +#define TRIZEPS4_CFSR_VIRT 0xF0100000 +#define TRIZEPS4_BOCR_VIRT 0xF0200000 +#define TRIZEPS4_DICR_VIRT 0xF0300000 +#define TRIZEPS4_IRCR_VIRT 0xF0400000 +#define TRIZEPS4_UPSR_VIRT 0xF0500000 + +/* size of flash */ +#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ + +/* Ethernet Controller Davicom DM9000 */ +#define GPIO_DM9000 101 +#define TRIZEPS4_ETH_IRQ PXA_GPIO_TO_IRQ(GPIO_DM9000) + +/* UCB1400 audio / TS-controller */ +#define GPIO_UCB1400 1 +#define TRIZEPS4_UCB1400_IRQ PXA_GPIO_TO_IRQ(GPIO_UCB1400) + +/* PCMCIA socket Compact Flash */ +#define GPIO_PCD 11 /* PCMCIA Card Detect */ +#define TRIZEPS4_CD_IRQ PXA_GPIO_TO_IRQ(GPIO_PCD) +#define GPIO_PRDY 13 /* READY / nINT */ +#define TRIZEPS4_READY_NINT PXA_GPIO_TO_IRQ(GPIO_PRDY) + +/* MMC socket */ +#define GPIO_MMC_DET 12 +#define TRIZEPS4_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO_MMC_DET) + +/* DOC NAND chip */ +#define GPIO_DOC_LOCK 94 +#define GPIO_DOC_IRQ 93 +#define TRIZEPS4_DOC_IRQ PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ) + +/* SPI interface */ +#define GPIO_SPI 53 +#define TRIZEPS4_SPI_IRQ PXA_GPIO_TO_IRQ(GPIO_SPI) + +/* LEDS using tx2 / rx2 */ +#define GPIO_SYS_BUSY_LED 46 +#define GPIO_HEARTBEAT_LED 47 + +/* Off-module PIC on ConXS board */ +#define GPIO_PIC 0 +#define TRIZEPS4_PIC_IRQ PXA_GPIO_TO_IRQ(GPIO_PIC) + +#ifdef CONFIG_MACH_TRIZEPS_CONXS +/* for CONXS base board define these registers */ +#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) +#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) + +#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) +#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) + +#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) +#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) + +#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT) +#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS) + +#ifndef __ASSEMBLY__ +static inline unsigned short CFSR_readw(void) +{ + /* [Compact Flash Status Register] is read only */ + return *((unsigned short *)CFSR_P2V(0x0C000000)); +} +static inline void BCR_writew(unsigned short value) +{ + /* [Board Control Regsiter] is write only */ + *((unsigned short *)BCR_P2V(0x0E000000)) = value; +} +static inline void DCR_writew(unsigned short value) +{ + /* [Display Control Register] is write only */ + *((unsigned short *)DCR_P2V(0x0E000000)) = value; +} +static inline void IRCR_writew(unsigned short value) +{ + /* [InfraRed data Control Register] is write only */ + *((unsigned short *)IRCR_P2V(0x0E000000)) = value; +} +#else +#define ConXS_CFSR CFSR_P2V(0x0C000000) +#define ConXS_BCR BCR_P2V(0x0E000000) +#define ConXS_DCR DCR_P2V(0x0F800000) +#define ConXS_IRCR IRCR_P2V(0x0F800000) +#endif +#else +/* for whatever baseboard define function registers */ +static inline unsigned short CFSR_readw(void) +{ + return 0; +} +static inline void BCR_writew(unsigned short value) +{ + ; +} +static inline void DCR_writew(unsigned short value) +{ + ; +} +static inline void IRCR_writew(unsigned short value) +{ + ; +} +#endif /* CONFIG_MACH_TRIZEPS_CONXS */ + +#define ConXS_CFSR_BVD_MASK 0x0003 +#define ConXS_CFSR_BVD1 (1 << 0) +#define ConXS_CFSR_BVD2 (1 << 1) +#define ConXS_CFSR_VS_MASK 0x000C +#define ConXS_CFSR_VS1 (1 << 2) +#define ConXS_CFSR_VS2 (1 << 3) +#define ConXS_CFSR_VS_5V (0x3 << 2) +#define ConXS_CFSR_VS_3V3 0x0 + +#define ConXS_BCR_S0_POW_EN0 (1 << 0) +#define ConXS_BCR_S0_POW_EN1 (1 << 1) +#define ConXS_BCR_L_DISP (1 << 4) +#define ConXS_BCR_CF_BUF_EN (1 << 5) +#define ConXS_BCR_CF_RESET (1 << 7) +#define ConXS_BCR_S0_VCC_3V3 0x1 +#define ConXS_BCR_S0_VCC_5V0 0x2 +#define ConXS_BCR_S0_VPP_12V 0x4 +#define ConXS_BCR_S0_VPP_3V3 0x8 + +#define ConXS_IRCR_MODE (1 << 0) +#define ConXS_IRCR_SD (1 << 1) + +#endif /* _TRIPEPS4_H_ */ diff --git a/kernel/arch/arm/mach-pxa/include/mach/udc.h b/kernel/arch/arm/mach-pxa/include/mach/udc.h new file mode 100644 index 000000000..9a827e32d --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/udc.h @@ -0,0 +1,8 @@ +/* + * arch/arm/mach-pxa/include/mach/udc.h + * + */ +#include <linux/platform_data/pxa2xx_udc.h> + +extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); + diff --git a/kernel/arch/arm/mach-pxa/include/mach/uncompress.h b/kernel/arch/arm/mach-pxa/include/mach/uncompress.h new file mode 100644 index 000000000..8c27757e6 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/uncompress.h @@ -0,0 +1,74 @@ +/* + * arch/arm/mach-pxa/include/mach/uncompress.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/serial_reg.h> +#include <asm/mach-types.h> + +#define FFUART_BASE (0x40100000) +#define BTUART_BASE (0x40200000) +#define STUART_BASE (0x40700000) + +unsigned long uart_base; +unsigned int uart_shift; +unsigned int uart_is_pxa; + +static inline unsigned char uart_read(int offset) +{ + return *(volatile unsigned char *)(uart_base + (offset << uart_shift)); +} + +static inline void uart_write(unsigned char val, int offset) +{ + *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val; +} + +static inline int uart_is_enabled(void) +{ + /* assume enabled by default for non-PXA uarts */ + return uart_is_pxa ? uart_read(UART_IER) & UART_IER_UUE : 1; +} + +static inline void putc(char c) +{ + if (!uart_is_enabled()) + return; + + while (!(uart_read(UART_LSR) & UART_LSR_THRE)) + barrier(); + + uart_write(c, UART_TX); +} + +/* + * This does not append a newline + */ +static inline void flush(void) +{ +} + +static inline void arch_decomp_setup(void) +{ + /* initialize to default */ + uart_base = FFUART_BASE; + uart_shift = 2; + uart_is_pxa = 1; + + if (machine_is_littleton() || machine_is_intelmote2() + || machine_is_csb726() || machine_is_stargate2() + || machine_is_cm_x300() || machine_is_balloon3()) + uart_base = STUART_BASE; + + if (machine_is_arcom_zeus()) { + uart_base = 0x10000000; /* nCS4 */ + uart_shift = 1; + uart_is_pxa = 0; + } +} diff --git a/kernel/arch/arm/mach-pxa/include/mach/viper.h b/kernel/arch/arm/mach-pxa/include/mach/viper.h new file mode 100644 index 000000000..5f5fbf1f6 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/viper.h @@ -0,0 +1,94 @@ +/* + * arch/arm/mach-pxa/include/mach/viper.h + * + * Author: Ian Campbell + * Created: Feb 03, 2003 + * Copyright: Arcom Control Systems. + * + * Maintained by Marc Zyngier <maz@misterjones.org> + * <marc.zyngier@altran.com> + * + * Created based on lubbock.h: + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ARCH_VIPER_H +#define ARCH_VIPER_H + +#define VIPER_BOOT_PHYS PXA_CS0_PHYS +#define VIPER_FLASH_PHYS PXA_CS1_PHYS +#define VIPER_ETH_PHYS PXA_CS2_PHYS +#define VIPER_USB_PHYS PXA_CS3_PHYS +#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS +#define VIPER_CPLD_PHYS PXA_CS5_PHYS + +#define VIPER_CPLD_BASE (0xf0000000) +#define VIPER_PC104IO_BASE (0xf1000000) +#define VIPER_USB_BASE (0xf1800000) + +#define VIPER_ETH_GPIO (0) +#define VIPER_CPLD_GPIO (1) +#define VIPER_USB_GPIO (2) +#define VIPER_UARTA_GPIO (4) +#define VIPER_UARTB_GPIO (3) +#define VIPER_CF_CD_GPIO (32) +#define VIPER_CF_RDY_GPIO (8) +#define VIPER_BCKLIGHT_EN_GPIO (9) +#define VIPER_LCD_EN_GPIO (10) +#define VIPER_PSU_DATA_GPIO (6) +#define VIPER_PSU_CLK_GPIO (11) +#define VIPER_UART_SHDN_GPIO (12) +#define VIPER_BRIGHTNESS_GPIO (16) +#define VIPER_PSU_nCS_LD_GPIO (19) +#define VIPER_UPS_GPIO (20) +#define VIPER_CF_POWER_GPIO (82) +#define VIPER_TPM_I2C_SDA_GPIO (26) +#define VIPER_TPM_I2C_SCL_GPIO (27) +#define VIPER_RTC_I2C_SDA_GPIO (83) +#define VIPER_RTC_I2C_SCL_GPIO (84) + +#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE) +#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS) + +#ifndef __ASSEMBLY__ +# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x))) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */ + +/* ... Physical addresses */ +#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000) +#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002) +#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004) +#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006) +#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010) +#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000) +#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000) + +/* ... Virtual addresses */ +#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS) +#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS) +#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS) +#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS) + +/* Decode VIPER_VERSION register */ +#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7) +#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3) +#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7) + +/* Interrupt and Configuration Register (VIPER_ICR) */ +/* This is a write only register. Only CF_RST is used under Linux */ + +#define VIPER_ICR_RETRIG (1 << 0) +#define VIPER_ICR_AUTO_CLR (1 << 1) +#define VIPER_ICR_R_DIS (1 << 2) +#define VIPER_ICR_CF_RST (1 << 3) + +#endif + diff --git a/kernel/arch/arm/mach-pxa/include/mach/vpac270.h b/kernel/arch/arm/mach-pxa/include/mach/vpac270.h new file mode 100644 index 000000000..7bfa3dd0f --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/vpac270.h @@ -0,0 +1,42 @@ +/* + * GPIOs and interrupts for Voipac PXA270 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_VPAC270_H_ +#define _INCLUDE_VPAC270_H_ + +#define GPIO1_VPAC270_USER_BTN 1 + +#define GPIO15_VPAC270_LED_ORANGE 15 + +#define GPIO81_VPAC270_BKL_ON 81 +#define GPIO83_VPAC270_NL_ON 83 + +#define GPIO52_VPAC270_SD_READONLY 52 +#define GPIO53_VPAC270_SD_DETECT_N 53 + +#define GPIO84_VPAC270_PCMCIA_CD 84 +#define GPIO35_VPAC270_PCMCIA_RDY 35 +#define GPIO107_VPAC270_PCMCIA_PPEN 107 +#define GPIO11_VPAC270_PCMCIA_RESET 11 +#define GPIO17_VPAC270_CF_CD 17 +#define GPIO12_VPAC270_CF_RDY 12 +#define GPIO16_VPAC270_CF_RESET 16 + +#define GPIO41_VPAC270_UDC_DETECT 41 + +#define GPIO114_VPAC270_ETH_IRQ 114 + +#define GPIO36_VPAC270_IDE_IRQ 36 + +#define GPIO113_VPAC270_TS_IRQ 113 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/z2.h b/kernel/arch/arm/mach-pxa/include/mach/z2.h new file mode 100644 index 000000000..7b0f71ef3 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/z2.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-pxa/include/mach/z2.h + * + * Author: Ken McGuire + * Created: Feb 6, 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ASM_ARCH_ZIPIT2_H +#define ASM_ARCH_ZIPIT2_H + +/* LEDs */ +#define GPIO10_ZIPITZ2_LED_WIFI 10 +#define GPIO85_ZIPITZ2_LED_CHARGED 85 +#define GPIO83_ZIPITZ2_LED_CHARGING 83 + +/* SD/MMC */ +#define GPIO96_ZIPITZ2_SD_DETECT 96 + +/* GPIO Buttons */ +#define GPIO1_ZIPITZ2_POWER_BUTTON 1 +#define GPIO98_ZIPITZ2_LID_BUTTON 98 + +/* Libertas GSPI8686 WiFi */ +#define GPIO14_ZIPITZ2_WIFI_POWER 14 +#define GPIO24_ZIPITZ2_WIFI_CS 24 +#define GPIO36_ZIPITZ2_WIFI_IRQ 36 + +/* LCD */ +#define GPIO19_ZIPITZ2_LCD_RESET 19 +#define GPIO88_ZIPITZ2_LCD_CS 88 + +/* MISC GPIOs */ +#define GPIO0_ZIPITZ2_AC_DETECT 0 +#define GPIO37_ZIPITZ2_HEADSET_DETECT 37 + +#endif diff --git a/kernel/arch/arm/mach-pxa/include/mach/zeus.h b/kernel/arch/arm/mach-pxa/include/mach/zeus.h new file mode 100644 index 000000000..56024f81d --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/zeus.h @@ -0,0 +1,85 @@ +/* + * arch/arm/mach-pxa/include/mach/zeus.h + * + * Author: David Vrabel + * Created: Sept 28, 2005 + * Copyright: Arcom Control Systems Ltd. + * + * Maintained by: Marc Zyngier <maz@misterjones.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MACH_ZEUS_H +#define _MACH_ZEUS_H + +#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) + +/* Physical addresses */ +#define ZEUS_FLASH_PHYS PXA_CS0_PHYS +#define ZEUS_ETH0_PHYS PXA_CS1_PHYS +#define ZEUS_ETH1_PHYS PXA_CS2_PHYS +#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) +#define ZEUS_SRAM_PHYS PXA_CS5_PHYS +#define ZEUS_PC104IO_PHYS (0x30000000) + +#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) +#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) +#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) +#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) + +/* GPIOs */ +#define ZEUS_AC97_GPIO 0 +#define ZEUS_WAKEUP_GPIO 1 +#define ZEUS_UARTA_GPIO 9 +#define ZEUS_UARTB_GPIO 10 +#define ZEUS_UARTC_GPIO 12 +#define ZEUS_UARTD_GPIO 11 +#define ZEUS_ETH0_GPIO 14 +#define ZEUS_ISA_GPIO 17 +#define ZEUS_BKLEN_GPIO 19 +#define ZEUS_USB2_PWREN_GPIO 22 +#define ZEUS_PTT_GPIO 27 +#define ZEUS_CF_CD_GPIO 35 +#define ZEUS_MMC_WP_GPIO 52 +#define ZEUS_MMC_CD_GPIO 53 +#define ZEUS_EXTGPIO_GPIO 91 +#define ZEUS_CF_PWEN_GPIO 97 +#define ZEUS_CF_RDY_GPIO 99 +#define ZEUS_LCD_EN_GPIO 101 +#define ZEUS_ETH1_GPIO 113 +#define ZEUS_CAN_GPIO 116 + +#define ZEUS_EXT0_GPIO_BASE 128 +#define ZEUS_EXT1_GPIO_BASE 160 +#define ZEUS_USER_GPIO_BASE 192 + +#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) +#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) +#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) + +#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) + +/* + * CPLD registers: + * Only 4 registers, but spread over a 32MB address space. + * Be gentle, and remap that over 32kB... + */ + +#define ZEUS_CPLD IOMEM(0xf0000000) +#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) +#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) +#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) + +/* CPLD register bits */ +#define ZEUS_CPLD_CONTROL_CF_RST 0x01 + +#define ZEUS_PC104IO IOMEM(0xf1000000) + +#define ZEUS_SRAM_SIZE (256 * 1024) + +#endif + + diff --git a/kernel/arch/arm/mach-pxa/include/mach/zylonite.h b/kernel/arch/arm/mach-pxa/include/mach/zylonite.h new file mode 100644 index 000000000..ecca976f0 --- /dev/null +++ b/kernel/arch/arm/mach-pxa/include/mach/zylonite.h @@ -0,0 +1,42 @@ +#ifndef __ASM_ARCH_ZYLONITE_H +#define __ASM_ARCH_ZYLONITE_H + +#define ZYLONITE_ETH_PHYS 0x14000000 + +#define EXT_GPIO(x) (128 + (x)) + +#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32) + +/* the following variables are processor specific and initialized + * by the corresponding zylonite_pxa3xx_init() + */ +extern int gpio_eth_irq; +extern int gpio_debug_led1; +extern int gpio_debug_led2; + +extern int wm9713_irq; + +extern int lcd_id; +extern int lcd_orientation; + +#ifdef CONFIG_MACH_ZYLONITE300 +extern void zylonite_pxa300_init(void); +#else +static inline void zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) + panic("%s: PXA300/PXA310 not supported\n", __func__); +} +#endif + +#ifdef CONFIG_MACH_ZYLONITE320 +extern void zylonite_pxa320_init(void); +#else +static inline void zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) + panic("%s: PXA320 not supported\n", __func__); +} +#endif + +#endif /* __ASM_ARCH_ZYLONITE_H */ |