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author | 2015-08-04 12:17:53 -0700 | |
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committer | 2015-08-04 15:44:42 -0700 | |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/mach-iop32x/irq.c | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/mach-iop32x/irq.c')
-rw-r--r-- | kernel/arch/arm/mach-iop32x/irq.c | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-iop32x/irq.c b/kernel/arch/arm/mach-iop32x/irq.c new file mode 100644 index 000000000..d7ee2789d --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/irq.c @@ -0,0 +1,74 @@ +/* + * arch/arm/mach-iop32x/irq.c + * + * Generic IOP32X IRQ handling functionality + * + * Author: Rory Bolt <rorybolt@pacbell.net> + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <asm/mach/irq.h> +#include <asm/irq.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +static u32 iop32x_mask; + +static void intctl_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); +} + +static void intstr_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); +} + +static void +iop32x_irq_mask(struct irq_data *d) +{ + iop32x_mask &= ~(1 << d->irq); + intctl_write(iop32x_mask); +} + +static void +iop32x_irq_unmask(struct irq_data *d) +{ + iop32x_mask |= 1 << d->irq; + intctl_write(iop32x_mask); +} + +struct irq_chip ext_chip = { + .name = "IOP32x", + .irq_ack = iop32x_irq_mask, + .irq_mask = iop32x_irq_mask, + .irq_unmask = iop32x_irq_unmask, +}; + +void __init iop32x_init_irq(void) +{ + int i; + + iop_init_cp6_handler(); + + intctl_write(0); + intstr_write(0); + if (machine_is_glantank() || + machine_is_iq80321() || + machine_is_iq31244() || + machine_is_n2100() || + machine_is_em7210()) + *IOP3XX_PCIIRSR = 0x0f; + + for (i = 0; i < NR_IRQS; i++) { + irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } +} |