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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/mach-dove/include/mach
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/mach-dove/include/mach')
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/bridge-regs.h57
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/dove.h190
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/entry-macro.S33
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/hardware.h19
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/irqs.h96
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/pm.h72
-rw-r--r--kernel/arch/arm/mach-dove/include/mach/uncompress.h36
7 files changed, 503 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-dove/include/mach/bridge-regs.h b/kernel/arch/arm/mach-dove/include/mach/bridge-regs.h
new file mode 100644
index 000000000..f4a5b3448
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-dove/include/mach/bridge-regs.h
+ *
+ * Mbus-L to Mbus Bridge Registers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/dove.h>
+
+#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
+
+#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
+#define CPU_CTRL_PCIE0_LINK 0x00000001
+#define CPU_RESET 0x00000002
+#define CPU_CTRL_PCIE1_LINK 0x00000008
+
+#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
+#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
+#define SOFT_RESET_OUT_EN 0x00000004
+
+#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
+#define SOFT_RESET 0x00000001
+
+#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
+#define BRIDGE_INT_TIMER1_CLR (~0x0004)
+
+#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
+#define IRQ_CAUSE_LOW_OFF 0x0000
+#define IRQ_MASK_LOW_OFF 0x0004
+#define FIQ_MASK_LOW_OFF 0x0008
+#define ENDPOINT_MASK_LOW_OFF 0x000c
+#define IRQ_CAUSE_HIGH_OFF 0x0010
+#define IRQ_MASK_HIGH_OFF 0x0014
+#define FIQ_MASK_HIGH_OFF 0x0018
+#define ENDPOINT_MASK_HIGH_OFF 0x001c
+#define PCIE_INTERRUPT_MASK_OFF 0x0020
+
+#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
+#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
+#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
+#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
+#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
+#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
+#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
+
+#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
+
+#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
+
+#endif
diff --git a/kernel/arch/arm/mach-dove/include/mach/dove.h b/kernel/arch/arm/mach-dove/include/mach/dove.h
new file mode 100644
index 000000000..0c4b35f4e
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/dove.h
@@ -0,0 +1,190 @@
+/*
+ * arch/arm/mach-dove/include/mach/dove.h
+ *
+ * Generic definitions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_DOVE_H
+#define __ASM_ARCH_DOVE_H
+
+/*
+ * Marvell Dove address maps.
+ *
+ * phys virt size
+ * c8000000 fdb00000 1M Cryptographic SRAM
+ * e0000000 @runtime 128M PCIe-0 Memory space
+ * e8000000 @runtime 128M PCIe-1 Memory space
+ * f1000000 fde00000 8M on-chip south-bridge registers
+ * f1800000 fe600000 8M on-chip north-bridge registers
+ * f2000000 fee00000 1M PCIe-0 I/O space
+ * f2100000 fef00000 1M PCIe-1 I/O space
+ */
+
+#define DOVE_CESA_PHYS_BASE 0xc8000000
+#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
+#define DOVE_CESA_SIZE SZ_1M
+
+#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
+#define DOVE_PCIE0_MEM_SIZE SZ_128M
+
+#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
+#define DOVE_PCIE1_MEM_SIZE SZ_128M
+
+#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
+#define DOVE_BOOTROM_SIZE SZ_128M
+
+#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
+#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
+#define DOVE_SCRATCHPAD_SIZE SZ_1M
+
+#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
+#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
+#define DOVE_SB_REGS_SIZE SZ_8M
+
+#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
+#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
+#define DOVE_NB_REGS_SIZE SZ_8M
+
+#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
+#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
+#define DOVE_PCIE0_IO_SIZE SZ_64K
+
+#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
+#define DOVE_PCIE1_IO_BUS_BASE 0x00010000
+#define DOVE_PCIE1_IO_SIZE SZ_64K
+
+/*
+ * Dove Core Registers Map
+ */
+
+/* SPI, I2C, UART */
+#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
+#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
+#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
+#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
+#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
+#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
+#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
+#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
+#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
+#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
+#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
+
+/* North-South Bridge */
+#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
+#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
+#define BRIDGE_WINS_SZ (0x80)
+
+/* Cryptographic Engine */
+#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
+
+/* PCIe 0 */
+#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
+
+/* USB */
+#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
+#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
+
+/* XOR 0 Engine */
+#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
+#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
+#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
+
+/* XOR 1 Engine */
+#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
+#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
+#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
+
+/* Gigabit Ethernet */
+#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
+
+/* PCIe 1 */
+#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
+
+/* CAFE */
+#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
+#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
+#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
+
+/* SATA */
+#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
+
+/* I2S/SPDIF */
+#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
+#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
+
+/* NAND Flash Controller */
+#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
+
+/* MPP, GPIO, Reset Sampling */
+#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
+#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
+#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
+#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
+#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
+#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
+#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
+#define DOVE_NAND_GPIO_EN (1 << 0)
+#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define DOVE_SPI_GPIO_SEL (1 << 5)
+#define DOVE_UART1_GPIO_SEL (1 << 4)
+#define DOVE_AU1_GPIO_SEL (1 << 3)
+#define DOVE_CAM_GPIO_SEL (1 << 2)
+#define DOVE_SD1_GPIO_SEL (1 << 1)
+#define DOVE_SD0_GPIO_SEL (1 << 0)
+
+/* Power Management */
+#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
+#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
+
+/* Real Time Clock */
+#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
+
+/* AC97 */
+#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
+#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
+
+/* Peripheral DMA */
+#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
+#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
+
+#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
+#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
+#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
+#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
+#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
+#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
+#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
+#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
+#define DOVE_SSP_ON_AU1 (1 << 0)
+#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
+#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
+/* Memory Controller */
+#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000)
+#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100)
+#define DOVE_MC_WINS_SZ (0x8)
+#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
+
+/* LCD Controller */
+#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
+#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
+
+/* Graphic Engine */
+#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
+
+/* Video Engine */
+#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
+
+#endif
diff --git a/kernel/arch/arm/mach-dove/include/mach/entry-macro.S b/kernel/arch/arm/mach-dove/include/mach/entry-macro.S
new file mode 100644
index 000000000..72d622baa
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-dove/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Dove platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/bridge-regs.h>
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =IRQ_VIRT_BASE
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ @ check low interrupts
+ ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+ ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
+ mov \irqnr, #31
+ ands \irqstat, \irqstat, \tmp
+
+ @ if no low interrupts set, check high interrupts
+ ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+ ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+ moveq \irqnr, #63
+ andeqs \irqstat, \irqstat, \tmp
+
+ @ find first active interrupt source
+ clzne \irqstat, \irqstat
+ subne \irqnr, \irqnr, \irqstat
+ .endm
diff --git a/kernel/arch/arm/mach-dove/include/mach/hardware.h b/kernel/arch/arm/mach-dove/include/mach/hardware.h
new file mode 100644
index 000000000..f1368b9a8
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/hardware.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-dove/include/mach/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "dove.h"
+
+/* Macros below are required for compatibility with PXA AC'97 driver. */
+#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
+ DOVE_SB_REGS_VIRT_BASE)))
+#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
+ DOVE_SB_REGS_PHYS_BASE)
+#endif
diff --git a/kernel/arch/arm/mach-dove/include/mach/irqs.h b/kernel/arch/arm/mach-dove/include/mach/irqs.h
new file mode 100644
index 000000000..03d401d20
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/irqs.h
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-dove/include/mach/irqs.h
+ *
+ * IRQ definitions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+/*
+ * Dove Low Interrupt Controller
+ */
+#define IRQ_DOVE_BRIDGE 0
+#define IRQ_DOVE_H2C 1
+#define IRQ_DOVE_C2H 2
+#define IRQ_DOVE_NAND 3
+#define IRQ_DOVE_PDMA 4
+#define IRQ_DOVE_SPI1 5
+#define IRQ_DOVE_SPI0 6
+#define IRQ_DOVE_UART_0 7
+#define IRQ_DOVE_UART_1 8
+#define IRQ_DOVE_UART_2 9
+#define IRQ_DOVE_UART_3 10
+#define IRQ_DOVE_I2C 11
+#define IRQ_DOVE_GPIO_0_7 12
+#define IRQ_DOVE_GPIO_8_15 13
+#define IRQ_DOVE_GPIO_16_23 14
+#define IRQ_DOVE_PCIE0_ERR 15
+#define IRQ_DOVE_PCIE0 16
+#define IRQ_DOVE_PCIE1_ERR 17
+#define IRQ_DOVE_PCIE1 18
+#define IRQ_DOVE_I2S0 19
+#define IRQ_DOVE_I2S0_ERR 20
+#define IRQ_DOVE_I2S1 21
+#define IRQ_DOVE_I2S1_ERR 22
+#define IRQ_DOVE_USB_ERR 23
+#define IRQ_DOVE_USB0 24
+#define IRQ_DOVE_USB1 25
+#define IRQ_DOVE_GE00_RX 26
+#define IRQ_DOVE_GE00_TX 27
+#define IRQ_DOVE_GE00_MISC 28
+#define IRQ_DOVE_GE00_SUM 29
+#define IRQ_DOVE_GE00_ERR 30
+#define IRQ_DOVE_CRYPTO 31
+
+/*
+ * Dove High Interrupt Controller
+ */
+#define IRQ_DOVE_AC97 32
+#define IRQ_DOVE_PMU 33
+#define IRQ_DOVE_CAM 34
+#define IRQ_DOVE_SDIO0 35
+#define IRQ_DOVE_SDIO1 36
+#define IRQ_DOVE_SDIO0_WAKEUP 37
+#define IRQ_DOVE_SDIO1_WAKEUP 38
+#define IRQ_DOVE_XOR_00 39
+#define IRQ_DOVE_XOR_01 40
+#define IRQ_DOVE_XOR0_ERR 41
+#define IRQ_DOVE_XOR_10 42
+#define IRQ_DOVE_XOR_11 43
+#define IRQ_DOVE_XOR1_ERR 44
+#define IRQ_DOVE_LCD_DCON 45
+#define IRQ_DOVE_LCD1 46
+#define IRQ_DOVE_LCD0 47
+#define IRQ_DOVE_GPU 48
+#define IRQ_DOVE_PERFORM_MNTR 49
+#define IRQ_DOVE_VPRO_DMA1 51
+#define IRQ_DOVE_SSP_TIMER 54
+#define IRQ_DOVE_SSP 55
+#define IRQ_DOVE_MC_L2_ERR 56
+#define IRQ_DOVE_CRYPTO_ERR 59
+#define IRQ_DOVE_GPIO_24_31 60
+#define IRQ_DOVE_HIGH_GPIO 61
+#define IRQ_DOVE_SATA 62
+
+/*
+ * DOVE General Purpose Pins
+ */
+#define IRQ_DOVE_GPIO_START 64
+#define NR_GPIO_IRQS 64
+
+/*
+ * PMU interrupts
+ */
+#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
+#define NR_PMU_IRQS 7
+#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
+
+#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
+
+
+#endif
diff --git a/kernel/arch/arm/mach-dove/include/mach/pm.h b/kernel/arch/arm/mach-dove/include/mach/pm.h
new file mode 100644
index 000000000..b47f75038
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/pm.h
@@ -0,0 +1,72 @@
+/*
+ * arch/arm/mach-dove/include/mach/pm.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_PM_H
+#define __ASM_ARCH_PM_H
+
+#include <asm/errno.h>
+#include <mach/irqs.h>
+
+#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
+#define CLOCK_GATING_BIT_USB0 0
+#define CLOCK_GATING_BIT_USB1 1
+#define CLOCK_GATING_BIT_GBE 2
+#define CLOCK_GATING_BIT_SATA 3
+#define CLOCK_GATING_BIT_PCIE0 4
+#define CLOCK_GATING_BIT_PCIE1 5
+#define CLOCK_GATING_BIT_SDIO0 8
+#define CLOCK_GATING_BIT_SDIO1 9
+#define CLOCK_GATING_BIT_NAND 10
+#define CLOCK_GATING_BIT_CAMERA 11
+#define CLOCK_GATING_BIT_I2S0 12
+#define CLOCK_GATING_BIT_I2S1 13
+#define CLOCK_GATING_BIT_CRYPTO 15
+#define CLOCK_GATING_BIT_AC97 21
+#define CLOCK_GATING_BIT_PDMA 22
+#define CLOCK_GATING_BIT_XOR0 23
+#define CLOCK_GATING_BIT_XOR1 24
+#define CLOCK_GATING_BIT_GIGA_PHY 30
+#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
+#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
+#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
+#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
+#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
+#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
+#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
+#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
+#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
+#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
+#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
+#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
+#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
+#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
+#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
+#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
+#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
+#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
+
+#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
+#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
+
+static inline int pmu_to_irq(int pin)
+{
+ if (pin < NR_PMU_IRQS)
+ return pin + IRQ_DOVE_PMU_START;
+
+ return -EINVAL;
+}
+
+static inline int irq_to_pmu(int irq)
+{
+ if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS)
+ return irq - IRQ_DOVE_PMU_START;
+
+ return -EINVAL;
+}
+
+#endif
diff --git a/kernel/arch/arm/mach-dove/include/mach/uncompress.h b/kernel/arch/arm/mach-dove/include/mach/uncompress.h
new file mode 100644
index 000000000..5c8ae9b9d
--- /dev/null
+++ b/kernel/arch/arm/mach-dove/include/mach/uncompress.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-dove/include/mach/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/dove.h>
+
+#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
+#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
+
+#define LSR_THRE 0x20
+
+static void putc(const char c)
+{
+ int i;
+
+ for (i = 0; i < 0x1000; i++) {
+ /* Transmit fifo not full? */
+ if (*UART_LSR & LSR_THRE)
+ break;
+ }
+
+ *UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()