diff options
author | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
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committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/boot/dts/stih41x.dtsi | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/boot/dts/stih41x.dtsi')
-rw-r--r-- | kernel/arch/arm/boot/dts/stih41x.dtsi | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/kernel/arch/arm/boot/dts/stih41x.dtsi b/kernel/arch/arm/boot/dts/stih41x.dtsi new file mode 100644 index 000000000..5cb0e6337 --- /dev/null +++ b/kernel/arch/arm/boot/dts/stih41x.dtsi @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + intc: interrupt-controller@fffe1000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffe1000 0x1000>, + <0xfffe0100 0x100>; + }; + + scu@fffe0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffe0000 0x1000>; + }; + + timer@fffe0200 { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-global-timer"; + reg = <0xfffe0200 0x100>; + interrupts = <1 11 0x04>; + clocks = <&arm_periph_clk>; + }; +}; |