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authorJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-04-11 10:41:07 +0300
committerJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-04-13 08:17:18 +0300
commite09b41010ba33a20a87472ee821fa407a5b8da36 (patch)
treed10dc367189862e7ca5c592f033dc3726e1df4e3 /kernel/Documentation/devicetree/bindings/gpu
parentf93b97fd65072de626c074dbe099a1fff05ce060 (diff)
These changes are the raw update to linux-4.4.6-rt14. Kernel sources
are taken from kernel.org, and rt patch from the rt wiki download page. During the rebasing, the following patch collided: Force tick interrupt and get rid of softirq magic(I70131fb85). Collisions have been removed because its logic was found on the source already. Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769 Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'kernel/Documentation/devicetree/bindings/gpu')
-rw-r--r--kernel/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt378
-rw-r--r--kernel/Documentation/devicetree/bindings/gpu/st,stih4xx.txt243
2 files changed, 0 insertions, 621 deletions
diff --git a/kernel/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/kernel/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
deleted file mode 100644
index 009f4bfa1..000000000
--- a/kernel/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ /dev/null
@@ -1,378 +0,0 @@
-NVIDIA Tegra host1x
-
-Required properties:
-- compatible: "nvidia,tegra<chip>-host1x"
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The interrupt outputs from the controller.
-- #address-cells: The number of cells used to represent physical base addresses
- in the host1x address space. Should be 1.
-- #size-cells: The number of cells used to represent the size of an address
- range in the host1x address space. Should be 1.
-- ranges: The mapping of the host1x address space to the CPU address space.
-- clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - host1x
-
-The host1x top-level node defines a number of children, each representing one
-of the following host1x client modules:
-
-- mpe: video encoder
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-mpe"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - mpe
-
-- vi: video input
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-vi"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - vi
-
-- epp: encoder pre-processor
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-epp"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - epp
-
-- isp: image signal processor
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-isp"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - isp
-
-- gr2d: 2D graphics engine
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-gr2d"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - 2d
-
-- gr3d: 3D graphics engine
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-gr3d"
- - reg: Physical base address and length of the controller's registers.
- - clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: Must include the following entries:
- (This property may be omitted if the only clock in the list is "3d")
- - 3d
- This MUST be the first entry.
- - 3d2 (Only required on SoCs with two 3D clocks)
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - 3d
- - 3d2 (Only required on SoCs with two 3D clocks)
-
-- dc: display controller
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-dc"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: Must include the following entries:
- - dc
- This MUST be the first entry.
- - parent
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - dc
- - nvidia,head: The number of the display controller head. This is used to
- setup the various types of output to receive video data from the given
- head.
-
- Each display controller node has a child node, named "rgb", that represents
- the RGB output associated with the controller. It can take the following
- optional properties:
- - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- - nvidia,edid: supplies a binary EDID blob
- - nvidia,panel: phandle of a display panel
-
-- hdmi: High Definition Multimedia Interface
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-hdmi"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - hdmi-supply: supply for the +5V HDMI connector pin
- - vdd-supply: regulator for supply voltage
- - pll-supply: regulator for PLL
- - clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: Must include the following entries:
- - hdmi
- This MUST be the first entry.
- - parent
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - hdmi
-
- Optional properties:
- - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- - nvidia,edid: supplies a binary EDID blob
- - nvidia,panel: phandle of a display panel
-
-- tvo: TV encoder output
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-tvo"
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
-
-- dsi: display serial interface
-
- Required properties:
- - compatible: "nvidia,tegra<chip>-dsi"
- - reg: Physical base address and length of the controller's registers.
- - clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: Must include the following entries:
- - dsi
- This MUST be the first entry.
- - lp
- - parent
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - dsi
- - avdd-dsi-supply: phandle of a supply that powers the DSI controller
- - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
- which pads are used by this DSI output and need to be calibrated. See also
- ../mipi/nvidia,tegra114-mipi.txt.
-
- Optional properties:
- - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- - nvidia,edid: supplies a binary EDID blob
- - nvidia,panel: phandle of a display panel
- - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
- up with in order to support up to 8 data lanes
-
-- sor: serial output resource
-
- Required properties:
- - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
- must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
- is tegra132.
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: Must include the following entries:
- - sor: clock input for the SOR hardware
- - parent: input for the pixel clock
- - dp: reference clock for the SOR clock
- - safe: safe reference for the SOR clock during power up
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - sor
-
- Optional properties:
- - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- - nvidia,edid: supplies a binary EDID blob
- - nvidia,panel: phandle of a display panel
-
- Optional properties when driving an eDP output:
- - nvidia,dpaux: phandle to a DispayPort AUX interface
-
-- dpaux: DisplayPort AUX interface
- - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
- must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
- <chip> is tegra132.
- - reg: Physical base address and length of the controller's registers.
- - interrupts: The interrupt outputs from the controller.
- - clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: Must include the following entries:
- - dpaux: clock input for the DPAUX hardware
- - parent: reference clock
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - dpaux
- - vdd-supply: phandle of a supply that powers the DisplayPort link
-
-Example:
-
-/ {
- ...
-
- host1x {
- compatible = "nvidia,tegra20-host1x", "simple-bus";
- reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
- clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
- resets = <&tegra_car 28>;
- reset-names = "host1x";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0x54000000 0x54000000 0x04000000>;
-
- mpe {
- compatible = "nvidia,tegra20-mpe";
- reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_MPE>;
- resets = <&tegra_car 60>;
- reset-names = "mpe";
- };
-
- vi {
- compatible = "nvidia,tegra20-vi";
- reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_VI>;
- resets = <&tegra_car 100>;
- reset-names = "vi";
- };
-
- epp {
- compatible = "nvidia,tegra20-epp";
- reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_EPP>;
- resets = <&tegra_car 19>;
- reset-names = "epp";
- };
-
- isp {
- compatible = "nvidia,tegra20-isp";
- reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_ISP>;
- resets = <&tegra_car 23>;
- reset-names = "isp";
- };
-
- gr2d {
- compatible = "nvidia,tegra20-gr2d";
- reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_GR2D>;
- resets = <&tegra_car 21>;
- reset-names = "2d";
- };
-
- gr3d {
- compatible = "nvidia,tegra20-gr3d";
- reg = <0x54180000 0x00040000>;
- clocks = <&tegra_car TEGRA20_CLK_GR3D>;
- resets = <&tegra_car 24>;
- reset-names = "3d";
- };
-
- dc@54200000 {
- compatible = "nvidia,tegra20-dc";
- reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_DISP1>,
- <&tegra_car TEGRA20_CLK_PLL_P>;
- clock-names = "dc", "parent";
- resets = <&tegra_car 27>;
- reset-names = "dc";
-
- rgb {
- status = "disabled";
- };
- };
-
- dc@54240000 {
- compatible = "nvidia,tegra20-dc";
- reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_DISP2>,
- <&tegra_car TEGRA20_CLK_PLL_P>;
- clock-names = "dc", "parent";
- resets = <&tegra_car 26>;
- reset-names = "dc";
-
- rgb {
- status = "disabled";
- };
- };
-
- hdmi {
- compatible = "nvidia,tegra20-hdmi";
- reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_HDMI>,
- <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
- clock-names = "hdmi", "parent";
- resets = <&tegra_car 51>;
- reset-names = "hdmi";
- status = "disabled";
- };
-
- tvo {
- compatible = "nvidia,tegra20-tvo";
- reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_TVO>;
- status = "disabled";
- };
-
- dsi {
- compatible = "nvidia,tegra20-dsi";
- reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car TEGRA20_CLK_DSI>,
- <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
- clock-names = "dsi", "parent";
- resets = <&tegra_car 48>;
- reset-names = "dsi";
- status = "disabled";
- };
- };
-
- ...
-};
diff --git a/kernel/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/kernel/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
deleted file mode 100644
index 6b1d75f1a..000000000
--- a/kernel/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
+++ /dev/null
@@ -1,243 +0,0 @@
-STMicroelectronics stih4xx platforms
-
-- sti-vtg: video timing generator
- Required properties:
- - compatible: "st,vtg"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- Optional properties:
- - interrupts : VTG interrupt number to the CPU.
- - st,slave: phandle on a slave vtg
-
-- sti-vtac: video timing advanced inter dye communication Rx and TX
- Required properties:
- - compatible: "st,vtac-main" or "st,vtac-aux"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - clocks: from common clock binding: handle hardware IP needed clocks, the
- number of clocks may depend of the SoC type.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: names of the clocks listed in clocks property in the same
- order.
-
-- sti-display-subsystem: Master device for DRM sub-components
- This device must be the parent of all the sub-components and is responsible
- of bind them.
- Required properties:
- - compatible: "st,sti-display-subsystem"
- - ranges: to allow probing of subdevices
-
-- sti-compositor: frame compositor engine
- must be a child of sti-display-subsystem
- Required properties:
- - compatible: "st,stih<chip>-compositor"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - clocks: from common clock binding: handle hardware IP needed clocks, the
- number of clocks may depend of the SoC type.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: names of the clocks listed in clocks property in the same
- order.
- - resets: resets to be used by the device
- See ../reset/reset.txt for details.
- - reset-names: names of the resets listed in resets property in the same
- order.
- - st,vtg: phandle(s) on vtg device (main and aux) nodes.
-
-- sti-tvout: video out hardware block
- must be a child of sti-display-subsystem
- Required properties:
- - compatible: "st,stih<chip>-tvout"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - reg-names: names of the mapped memory regions listed in regs property in
- the same order.
- - resets: resets to be used by the device
- See ../reset/reset.txt for details.
- - reset-names: names of the resets listed in resets property in the same
- order.
- - ranges: to allow probing of subdevices
-
-- sti-hdmi: hdmi output block
- must be a child of sti-tvout
- Required properties:
- - compatible: "st,stih<chip>-hdmi";
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - reg-names: names of the mapped memory regions listed in regs property in
- the same order.
- - interrupts : HDMI interrupt number to the CPU.
- - interrupt-names: name of the interrupts listed in interrupts property in
- the same order
- - clocks: from common clock binding: handle hardware IP needed clocks, the
- number of clocks may depend of the SoC type.
- - clock-names: names of the clocks listed in clocks property in the same
- order.
- - ddc: phandle of an I2C controller used for DDC EDID probing
-
-sti-hda:
- Required properties:
- must be a child of sti-tvout
- - compatible: "st,stih<chip>-hda"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - reg-names: names of the mapped memory regions listed in regs property in
- the same order.
- - clocks: from common clock binding: handle hardware IP needed clocks, the
- number of clocks may depend of the SoC type.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: names of the clocks listed in clocks property in the same
- order.
-
-sti-dvo:
- Required properties:
- must be a child of sti-tvout
- - compatible: "st,stih<chip>-dvo"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - reg-names: names of the mapped memory regions listed in regs property in
- the same order.
- - clocks: from common clock binding: handle hardware IP needed clocks, the
- number of clocks may depend of the SoC type.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: names of the clocks listed in clocks property in the same
- order.
- - pinctrl-0: pin control handle
- - pinctrl-name: names of the pin control to use
- - sti,panel: phandle of the panel connected to the DVO output
-
-sti-hqvdp:
- must be a child of sti-display-subsystem
- Required properties:
- - compatible: "st,stih<chip>-hqvdp"
- - reg: Physical base address of the IP registers and length of memory mapped region.
- - clocks: from common clock binding: handle hardware IP needed clocks, the
- number of clocks may depend of the SoC type.
- See ../clocks/clock-bindings.txt for details.
- - clock-names: names of the clocks listed in clocks property in the same
- order.
- - resets: resets to be used by the device
- See ../reset/reset.txt for details.
- - reset-names: names of the resets listed in resets property in the same
- order.
- - st,vtg: phandle on vtg main device node.
-
-Example:
-
-/ {
- ...
-
- vtg_main_slave: sti-vtg-main-slave@fe85A800 {
- compatible = "st,vtg";
- reg = <0xfe85A800 0x300>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
- };
-
- vtg_main: sti-vtg-main-master@fd348000 {
- compatible = "st,vtg";
- reg = <0xfd348000 0x400>;
- st,slave = <&vtg_main_slave>;
- };
-
- vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
- compatible = "st,vtg";
- reg = <0xfe858200 0x300>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
- };
-
- vtg_aux: sti-vtg-aux-master@fd348400 {
- compatible = "st,vtg";
- reg = <0xfd348400 0x400>;
- st,slave = <&vtg_aux_slave>;
- };
-
-
- sti-vtac-rx-main@fee82800 {
- compatible = "st,vtac-main";
- reg = <0xfee82800 0x200>;
- clock-names = "vtac";
- clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
- };
-
- sti-vtac-rx-aux@fee82a00 {
- compatible = "st,vtac-aux";
- reg = <0xfee82a00 0x200>;
- clock-names = "vtac";
- clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
- };
-
- sti-vtac-tx-main@fd349000 {
- compatible = "st,vtac-main";
- reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
- clock-names = "vtac";
- clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
- };
-
- sti-vtac-tx-aux@fd349200 {
- compatible = "st,vtac-aux";
- reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
- clock-names = "vtac";
- clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
- };
-
- sti-display-subsystem {
- compatible = "st,sti-display-subsystem";
- ranges;
-
- sti-compositor@fd340000 {
- compatible = "st,stih416-compositor";
- reg = <0xfd340000 0x1000>;
- clock-names = "compo_main", "compo_aux",
- "pix_main", "pix_aux";
- clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
- <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
- reset-names = "compo-main", "compo-aux";
- resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
- st,vtg = <&vtg_main>, <&vtg_aux>;
- };
-
- sti-tvout@fe000000 {
- compatible = "st,stih416-tvout";
- reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
- reg-names = "tvout-reg", "hda-reg", "syscfg";
- reset-names = "tvout";
- resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
- ranges;
-
- sti-hdmi@fe85c000 {
- compatible = "st,stih416-hdmi";
- reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
- reg-names = "hdmi-reg", "syscfg";
- interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
- interrupt-names = "irq";
- clock-names = "pix", "tmds", "phy", "audio";
- clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
- };
-
- sti-hda@fe85a000 {
- compatible = "st,stih416-hda";
- reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
- reg-names = "hda-reg", "video-dacs-ctrl";
- clock-names = "pix", "hddac";
- clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
- };
-
- sti-dvo@8d00400 {
- compatible = "st,stih407-dvo";
- reg = <0x8d00400 0x200>;
- reg-names = "dvo-reg";
- clock-names = "dvo_pix", "dvo",
- "main_parent", "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
- <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dvo>;
- sti,panel = <&panel_dvo>;
- };
- };
-
- sti-hqvdp@9c000000 {
- compatible = "st,stih407-hqvdp";
- reg = <0x9C00000 0x100000>;
- clock-names = "hqvdp", "pix_main";
- clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
- reset-names = "hqvdp";
- resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
- st,vtg = <&vtg_main>;
- };
- };
- ...
-};