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<!doctype html>
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		<title>OPNFV presentation</title>

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				<section data-background="../../../img/title-bg-berlin.png" data-background-transition="none">
                     <br><br><br><br><br>
                     <h1>Conversation with the Testing Community</h1>
                     <br><br>
					 <h4>OPNFV testing community</h4>
					 <h5>OPNFV Design Summit, 20/6/2016, Berlin</h5>
					 <br>

				</section>

				<section data-markdown>
						>“You make experiments and I make theories. Do you know the difference? A theory is something nobody believes, except the person who made it. An experiment is something everybody believes, except the person who made it." A.Einstein
				</section>

				<section data-markdown>
					# Agenda
					* Who are we?
					* Upstream, Upstream, Upstream
					* Towards Telco Cloud KPI
				</section>

				<section data-markdown>
					# Who are we?
					![team](../../../img/OPNFV_testing_group.png)
					This is a representation...not a governance!
				</section>
                <section>
					<section>
						<h3>The test projects</h3>
						<table>
							<thead>
								<tr>
									<th>Test case</th>
									<th>Description</th>
								</tr>
							</thead>
							<tbody>
								<tr>
									<td>Functest</td>
									<td>Umbrella project for Functional testing</td>
								</tr>
								<tr>
									<td>Yardstick</td>
									<td>Umbrella project for performance/qualification testing</td>
								</tr>
								<tr>
									<td>CPerf</td>
									<td>SDN controller performance testing</td>
								</tr>
								<tr>
									<td>StorPerf</td>
									<td>Storage performance testing</td>
								</tr>
								<tr>
									<td>VSPerf</td>
									<td>VSwitch qualification</td>
								</tr>
								<tr>
									<td>Bottlenecks</td>
									<td>Detect possible bottlenecks</td>
								</tr>
								<tr>
									<td>QTIP</td>
									<td>Benchmark to boost performance</td>
								</tr>
							</tbody>
						</table>
					</section>

						<section data-markdown>
							# Functest
							* Functional testing to validate scenarios
							* Contributors (raise your hands)
							* Functest presentation (here...1h ago :))
							* breakout sessions
							  * Today 3.10PM-3.40PM (vIMS evolution) 4PM (feature project integration), 5PM (Colorado status)
							  * tomorrow 11AM (API, test collection), 1PM (work Upstream), 3.15PM (D Release)(to be confirmed...)
						</section>
						<section data-markdown>
							# Yardstick
							* Performance testing framework and NFVI Validation
							* [Contributors](https://wiki.opnfv.org/display/yardstick/People)
							* Yardstick presentation
							  * How to Do a Pre-deployment NFVI Validation Quickly and Efficiently? Wednesday, June 22, 4:00 PM - 4:30 PM
							  * Yardstick: A Pre-deployment NFVI Validation Tool. Thursday, June 23, 3:10 PM - 3:30 PM
							* breakout sessions
							  * Tomorrow 2PM (Yardstick in C)
						</section>
						<section data-markdown>
							# CPerf
							* SDN Controller Performance Testing
							* Upstream test experts + standards/metrics experts
							* Goal: Cross-controller perf tests in CI against realistic deployments
						</section>
						<section data-markdown>
							# StorPerf
							* Cinder Volume Performance Testing
							* Based on SNIA's SSD Test Specification
							* Presentation
							  * StorPerf: Cinder Storage Performance Measurement.
							    Wednesday, June 22, 3:40 PM - 3:55 PM
							* Breakout Session
							  * Tomorrow 10:15 (StorPerf Test Results Working Session)
						</section>
						<section data-markdown>
							# VSPerf
						</section>
						<section data-markdown>
							# Bottlenecks
						</section>
						<section data-markdown>
							# QTIP

							## OPNFV Platform Benchmark

							- Bottom up
								- testing baremetal components first
							- More than result
								- comparing against reference
							- Setup-Test-Diagnose-Improve
								- a closed loop to boost platform performance

							## Breakout session

							- 14:30~15:45, June 21st/Tuesday
							- Room Tegel
						</section>
				</section>
				<section>
				    <section data-markdown>
				    # Upstream, upstream, upstream..
				    </section>
				    <section data-markdown>
				    ## We are on the shoulders of the giants
				    * Rally (OpenStack)
				    * ODL, ONOS, ...
				    * RobotFramework, Teston
				    * .....
				    </section>
				    <section data-markdown>
				    ## Time to give back
				    ### How to improve work with testing upstream community
				    </section>

				</section>

				<section>

				    <section data-markdown>
				    # Towards Telco Cloud KPI?
				    </section>

				    <section data-markdown>
				    # Testing group goals
				    * Define common needs (naming, rules, tools...)
				    * Unify result collection, reporting, dashboarding, documentation
				    * Share best practice: docker, CLI, ..
				    * Identify testing domains
				    * Encourage testing in poorly covered areas
				    </section>

				    <section data-markdown>
				    # The ultimate goal: define Telco Cloud KPIs
				    * Provide methodology and test suites to qualify a Telco Cloud
				    * Provide reference benchs for plugfest/third party integration: compare apple with apple
				    </section>

				</section>

				<section data-markdown>
					# Thank you
				</section>

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"o">- end - virtual end address * * (same as v4wb) */ arm920_dma_clean_range: bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB ret lr /* * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. * * - start - virtual start address * - end - virtual end address */ ENTRY(arm920_dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain WB ret lr /* * dma_map_area(start, size, dir) * - start - kernel virtual start address * - size - size of region * - dir - DMA direction */ ENTRY(arm920_dma_map_area) add r1, r1, r0 cmp r2, #DMA_TO_DEVICE beq arm920_dma_clean_range bcs arm920_dma_inv_range b arm920_dma_flush_range ENDPROC(arm920_dma_map_area) /* * dma_unmap_area(start, size, dir) * - start - kernel virtual start address * - size - size of region * - dir - DMA direction */ ENTRY(arm920_dma_unmap_area) ret lr ENDPROC(arm920_dma_unmap_area) .globl arm920_flush_kern_cache_louis .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm920 #endif ENTRY(cpu_arm920_dcache_clean_area) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE subs r1, r1, #CACHE_DLINESIZE bhi 1b ret lr /* =============================== PageTable ============================== */ /* * cpu_arm920_switch_mm(pgd) * * Set the translation base pointer to be as described by pgd. * * pgd: new page tables */ .align 5 ENTRY(cpu_arm920_switch_mm) #ifdef CONFIG_MMU mov ip, #0 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache #else @ && 'Clean & Invalidate whole DCache' @ && Re-written to use Index Ops. @ && Uses registers r1, r3 and ip mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index subs r3, r3, #1 << 26 bcs 2b @ entries 63 to 0 subs r1, r1, #1 << 5 bcs 1b @ segments 7 to 0 #endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs #endif ret lr /* * cpu_arm920_set_pte(ptep, pte, ext) * * Set a PTE and flush it out */ .align 5 ENTRY(cpu_arm920_set_pte_ext) #ifdef CONFIG_MMU armv3_set_pte_ext mov r0, r0 mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c10, 4 @ drain WB #endif ret lr /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size .equ cpu_arm920_suspend_size, 4 * 3 #ifdef CONFIG_ARM_CPU_SUSPEND ENTRY(cpu_arm920_do_suspend) stmfd sp!, {r4 - r6, lr} mrc p15, 0, r4, c13, c0, 0 @ PID mrc p15, 0, r5, c3, c0, 0 @ Domain ID mrc p15, 0, r6, c1, c0, 0 @ Control register stmia r0, {r4 - r6} ldmfd sp!, {r4 - r6, pc} ENDPROC(cpu_arm920_do_suspend) ENTRY(cpu_arm920_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches ldmia r0, {r4 - r6} mcr p15, 0, r4, c13, c0, 0 @ PID mcr p15, 0, r5, c3, c0, 0 @ Domain ID mcr p15, 0, r1, c2, c0, 0 @ TTB address mov r0, r6 @ control register b cpu_resume_mmu ENDPROC(cpu_arm920_do_resume) #endif .type __arm920_setup, #function __arm920_setup: mov r0, #0 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif adr r5, arm920_crval ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0 @ get control register v4 bic r0, r0, r5 orr r0, r0, r6 ret lr .size __arm920_setup, . - __arm920_setup /* * R * .RVI ZFRS BLDP WCAM * ..11 0001 ..11 0101 * */ .type arm920_crval, #object arm920_crval: crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130 __INITDATA @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1 .section ".rodata" string cpu_arch_name, "armv4t" string cpu_elf_name, "v4" string cpu_arm920_name, "ARM920T" .align .section ".proc.info.init", #alloc .type __arm920_proc_info,#object __arm920_proc_info: .long 0x41009200 .long 0xff00fff0 .long PMD_TYPE_SECT | \ PMD_SECT_BUFFERABLE | \ PMD_SECT_CACHEABLE | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ initfn __arm920_setup, __arm920_proc_info .long cpu_arch_name .long cpu_elf_name .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB .long cpu_arm920_name .long arm920_processor_functions .long v4wbi_tlb_fns .long v4wb_user_fns #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH .long arm920_cache_fns #else .long v4wt_cache_fns #endif .size __arm920_proc_info, . - __arm920_proc_info