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authorAlexandru Avadanii <Alexandru.Avadanii@enea.com>2020-01-03 14:50:33 +0100
committerAlexandru Avadanii <Alexandru.Avadanii@enea.com>2020-01-08 13:17:31 +0000
commitc7c70e890292ec85b05546d91f9dbedbb6df81fb (patch)
treef8731e23518a71b6275e56cafe1a0973f62fd192
parent804cb68bc61126d2e27e8ca9d9abfe2cd0af0cfb (diff)
aarch64: Workaround broken lshw CPU detection
On some aarch64 platforms (e.g. ThunderX), the DMI tables parsed by lshw lead to wrong CPU capabilities detection, breaking our MaaS tag filtering (which used to rely solely on CPU having asimd caps). Extend the tag filtering condition to also include nodes that report `cp15_barrier` platform capability. Note that not all aarch64 systems include this cap explicitly (especially since it's been deprecated in ARM v8), but it is currently reported by the platforms where asimd is not properly detected. This is merely a workaround for the broken lshw version in Ubuntu Bionic (B.02.18). Change-Id: I4a5c0d6af4d863d2ca094d6926a65ee90dee0e07 Signed-off-by: Alexandru Avadanii <Alexandru.Avadanii@enea.com> (cherry picked from commit d2573b60c9daf2c3b6434112d98b733388824b4f)
-rw-r--r--mcp/reclass/classes/cluster/all-mcp-arch-common/infra/maas.yml.j22
1 files changed, 1 insertions, 1 deletions
diff --git a/mcp/reclass/classes/cluster/all-mcp-arch-common/infra/maas.yml.j2 b/mcp/reclass/classes/cluster/all-mcp-arch-common/infra/maas.yml.j2
index b5cb3fece..41871d872 100644
--- a/mcp/reclass/classes/cluster/all-mcp-arch-common/infra/maas.yml.j2
+++ b/mcp/reclass/classes/cluster/all-mcp-arch-common/infra/maas.yml.j2
@@ -29,7 +29,7 @@ parameters:
tags:
aarch64_hugepages_1g:
comment: 'Enable 1G pagesizes on aarch64'
- definition: '//capability[@id="asimd"]'
+ definition: '//capability[@id="asimd"]|//capability[@id="cp15_barrier"]'
kernel_opts: 'default_hugepagesz=1G hugepagesz=1G'
{%- endif %}
timeout: