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path: root/plan-samples/plan-environment-derived-params.yaml
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version: 1.0

name: overcloud
description: >
  Default Deployment plan
template: overcloud.yaml
environments:
  - path: overcloud-resource-registry-puppet.yaml
workflow_parameters:
  tripleo.derive_params.v1.derive_parameters:
    ######### DPDK Parameters #########
    # Specifices the minimum number of CPU threads to be allocated for DPDK
    # PMD threads. The actual allocation will be based on network config, if
    # the a DPDK port is associated with a numa node, then this configuration
    # will be used, else 0.
    number_of_pmd_cpu_threads_per_numa_node: 4
    # Amount of memory to be configured as huge pages in percentage. Ouf the
    # total available memory (excluding the NovaReservedHostMemory), the
    # specified percentage of the remaining is configured as huge pages.
    huge_page_allocation_percentage: 90
    ######### HCI Parameters #########
    hci_profile: default
    hci_profile_config:
      default:
        average_guest_memory_size_in_mb: 2048
        average_guest_cpu_utilization_percentage: 50
      many_small_vms:
        average_guest_memory_size_in_mb: 1024
        average_guest_cpu_utilization_percentage: 20
      few_large_vms:
        average_guest_memory_size_in_mb: 4096
        average_guest_cpu_utilization_percentage: 80
      nfv_default:
        average_guest_memory_size_in_mb: 8192
        average_guest_cpu_utilization_percentage: 90
.h> #include <linux/of_irq.h> #include <linux/spinlock.h> #include <linux/sched_clock.h> #define TIMER_CTRL 0x00 #define TIMER0_EN BIT(0) #define TIMER0_RELOAD_EN BIT(1) #define TIMER1_EN BIT(2) #define TIMER1_RELOAD_EN BIT(3) #define TIMER0_RELOAD 0x10 #define TIMER0_VAL 0x14 #define TIMER1_RELOAD 0x18 #define TIMER1_VAL 0x1c #define ORION_ONESHOT_MIN 1 #define ORION_ONESHOT_MAX 0xfffffffe static void __iomem *timer_base; /* * Free-running clocksource handling. */ static u64 notrace orion_read_sched_clock(void) { return ~readl(timer_base + TIMER0_VAL); } /* * Clockevent handling. */ static u32 ticks_per_jiffy; static int orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) { /* setup and enable one-shot timer */ writel(delta, timer_base + TIMER1_VAL); atomic_io_modify(timer_base + TIMER_CTRL, TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN); return 0; } static int orion_clkevt_shutdown(struct clock_event_device *dev) { /* disable timer */ atomic_io_modify(timer_base + TIMER_CTRL, TIMER1_RELOAD_EN | TIMER1_EN, 0); return 0; } static int orion_clkevt_set_periodic(struct clock_event_device *dev) { /* setup and enable periodic timer at 1/HZ intervals */ writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); atomic_io_modify(timer_base + TIMER_CTRL, TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_RELOAD_EN | TIMER1_EN); return 0; } static struct clock_event_device orion_clkevt = { .name = "orion_event", .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, .shift = 32, .rating = 300, .set_next_event = orion_clkevt_next_event, .set_state_shutdown = orion_clkevt_shutdown, .set_state_periodic = orion_clkevt_set_periodic, .set_state_oneshot = orion_clkevt_shutdown, .tick_resume = orion_clkevt_shutdown, }; static irqreturn_t orion_clkevt_irq_handler(int irq, void *dev_id) { orion_clkevt.event_handler(&orion_clkevt); return IRQ_HANDLED; } static struct irqaction orion_clkevt_irq = { .name = "orion_event", .flags = IRQF_TIMER, .handler = orion_clkevt_irq_handler, }; static void __init orion_timer_init(struct device_node *np) { struct clk *clk; int irq; /* timer registers are shared with watchdog timer */ timer_base = of_iomap(np, 0); if (!timer_base) panic("%s: unable to map resource\n", np->name); clk = of_clk_get(np, 0); if (IS_ERR(clk)) panic("%s: unable to get clk\n", np->name); clk_prepare_enable(clk); /* we are only interested in timer1 irq */ irq = irq_of_parse_and_map(np, 1); if (irq <= 0) panic("%s: unable to parse timer1 irq\n", np->name); /* setup timer0 as free-running clocksource */ writel(~0, timer_base + TIMER0_VAL); writel(~0, timer_base + TIMER0_RELOAD); atomic_io_modify(timer_base + TIMER_CTRL, TIMER0_RELOAD_EN | TIMER0_EN, TIMER0_RELOAD_EN | TIMER0_EN); clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource", clk_get_rate(clk), 300, 32, clocksource_mmio_readl_down); sched_clock_register(orion_read_sched_clock, 32, clk_get_rate(clk)); /* setup timer1 as clockevent timer */ if (setup_irq(irq, &orion_clkevt_irq)) panic("%s: unable to setup irq\n", np->name); ticks_per_jiffy = (clk_get_rate(clk) + HZ/2) / HZ; orion_clkevt.cpumask = cpumask_of(0); orion_clkevt.irq = irq; clockevents_config_and_register(&orion_clkevt, clk_get_rate(clk), ORION_ONESHOT_MIN, ORION_ONESHOT_MAX); } CLOCKSOURCE_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);